JP2006127092A - Clock signal control method and device for synchronous memory, synchronous memory controller and synchronous memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock signal control method and device of a synchronous memory, a synchronous memory controller and a synchronous memory for reducing power consumption with high precision by controlling the supply of a clock signal to the synchronous memory to the minimum. <P>SOLUTION: When a command is issued, the number of clock signals corresponding to the issued command is read from a command mask time corresponding table 2B, and the number of clock signals corresponding to the read number of clock signals are generated by the mask processing release of the clock signals. When the generation of the clock signals ends, the supply of the clock signals to an SDRAM 1 is interrupted by mask processing as long as the next command is not issued. As a result, the clock signals to be supplied to the SDRAM 1 are accurately controlled to the number of clock signals, which is the minimum for executing the issued command. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a clock signal control method and apparatus for a synchronous memory that can reduce power consumption of the synchronous memory by controlling a clock signal supplied to a synchronous memory represented by SDRAM (Synchronous DRAM), The present invention relates to a synchronous memory control device and a synchronous memory.

FIG. 8 is a block diagram showing an outline of an SDRAM 100 to which a conventional synchronous memory clock signal control method is applied and an SDRAM controller 200 for controlling the SDRAM 100. FIG. 7 is a timing chart for explaining problems in a conventional synchronous memory clock signal control method.
The SDRAM controller 200 controls the control signals of the SDRAM 100, for example, RAS, CAS, WE, CS, CKE, A, D signals, etc. by the SDRAM control circuit 300.
A conventional SDRAM has a mask circuit that masks a clock signal based on a clock enable signal, for example, and appropriately controls a CK signal supplied to the SDRAM by the mask circuit to reduce the power consumption of the SDRAM. .
In this way, by controlling the supply of the clock signal, the power consumption can be reduced by controlling the clock enable signal in response to the issuance of access requests such as read / write, refresh, and precharge to the SDRAM. Thus, there is one that can reduce power consumption (see, for example, Patent Document 1).
JP-A-9-180438

However, in the conventional synchronous memory clock signal control method and apparatus, as shown in FIG. 7, the control signal had to be controlled one clock signal before issuing a command. It is necessary to perform the conventional operation after setting the signal to “High” level, and the performance deteriorates by one clock signal.
Also, the control method is such as a control in which the access is not generated such as in the standby mode, and the control is performed after seeing no access for a while, and the period in which the clock signal is supplied even when the SDRAM does not operate. There is room to reduce the supply period of this clock signal. In addition, since the clock signal must always be supplied, there is a problem that the power consumption of the clock signal driver cannot be reduced, and logic for controlling CKE is required on the DRAM controller side.
In addition, when masking a clock signal without using a clock enable signal, if there is a DLL (Delayed Locked Loop) or PLL (Phase Locked Loop) in the SDRAM or SDRAM controller, the frequency can be varied in operation, There was a problem that it was not possible to supply a clock signal for missing teeth.

  The present invention has been made in view of such circumstances, and an object of the present invention is to control the clock signal supplied to the synchronous memory to the minimum necessary, thereby greatly reducing the power consumption of the synchronous memory. To provide a clock signal control method and apparatus for a synchronous memory, a synchronous memory control apparatus, and a synchronous memory.

In order to achieve the above object, a clock signal control method for a synchronous memory according to the present invention is a clock signal control method for a synchronous memory that controls a clock signal supplied to the synchronous memory. A correspondence table storing step for storing a correspondence table in which an issued command and an operation period defining information for defining an operation period of the synchronous memory that operates based on the command are associated; and is issued to the synchronous memory A command interpretation step for inputting the received command, interpreting the input command, and reading the operation period defining information corresponding to the command interpreted in the command interpretation step from the correspondence table, and reading the operation period And a control step for controlling a clock signal supplied to the synchronous memory based on regulation information. .
The synchronous memory clock signal control device of the present invention is a synchronous memory clock signal control device for controlling a clock signal supplied to the synchronous memory, and a command issued to the synchronous memory. Correspondence table storage means for storing a correspondence table in which operation period defining information for defining an operation period of the synchronous memory that operates based on the command is associated, and a command issued to the synchronous memory is input. The command interpreting means for interpreting the input command, and the operation period defining information corresponding to the command interpreted by the command interpreting means are read from the correspondence table stored in the correspondence table storage means and read out. And a control means for controlling a clock signal supplied to the synchronous memory based on the operation period defining information. That.

The synchronous memory control device of the present invention is a synchronous memory control device that controls the operation of the synchronous memory by controlling a clock signal supplied to the synchronous memory, and is issued to the synchronous memory. A correspondence table storage means for storing a correspondence table in which a command to be executed and an operation period defining information for defining an operation period of the synchronous memory that operates based on the command are associated with each other, and is issued to the synchronous memory Command interpretation means for interpreting the input command, and reading the operation period defining information corresponding to the command interpreted by the command interpretation means from the correspondence table stored in the correspondence table storage means Control means for controlling a clock signal supplied to the synchronous memory based on the read operation period defining information. To.
The synchronous memory according to the present invention is a synchronous memory that operates based on an input clock signal, and defines a command issued to the synchronous memory and an operation period that operates based on the command. Correspondence table storage means for storing a correspondence table in association with operation period definition information, command interpretation means for interpreting the input command, and operation period definition information corresponding to the command interpreted by the command interpretation means And a control means for controlling the clock signal input based on the read operation period defining information, from the correspondence table stored in the correspondence table storage means.

According to the synchronous memory clock signal control method and apparatus, the synchronous memory control apparatus, and the synchronous memory of the present invention, a command issued to the synchronous memory and the synchronous type operating based on the command A correspondence table that associates the operation period defining information that defines the operation period of the memory is stored. When a command is issued to the synchronous memory, the issued command is interpreted, the operation period defining information corresponding to the interpreted command is read from the correspondence table, and the read operation period A clock signal supplied to the synchronous memory is controlled based on the regulation information.
Therefore, it is possible to accurately control the minimum clock signal necessary for executing the command issued based on the operation period defining information, and there is an effect that the power consumption of the synchronous memory can be greatly reduced. .

  In order to achieve the above object, a correspondence table in which a command issued to the synchronous memory is associated with the number of clock signals of the synchronous memory that operates based on the command is stored. When a command is issued to the synchronous memory, the issued command is interpreted, the number of clock signals corresponding to the interpreted command is read from the correspondence table, and the number of clock signals read is calculated. The synchronous memory is operated by supplying the synchronous memory. When the supply of the clock signal is completed, the supply of the clock signal is stopped by masking the clock signal.

A clock signal control method and apparatus for a synchronous memory according to a first embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing the structure of an SDRAM (synchronous memory) 1 and an SDRAM controller (synchronous memory controller) 2 to which the synchronous memory clock signal control method of the first embodiment is applied.
The SDRAM controller 2 includes a clock mask circuit 2A, a command mask time correspondence table storage circuit 2B, a clock mask determination circuit 2C, and an SDRAM control circuit 3.
A clock mask determination circuit 2C configured in the SDRAM controller 2 monitors a control signal to the SDRAM 1 and interprets a command to the SDRAM 1 based on a control signal supplied from the SDRAM control circuit 3 or internal information of the SDRAM control. To do. Also, the clock mask determination circuit 2C reads out the number of clock signals corresponding to the command from the command mask time correspondence table 2B. Based on this value, a clock mask signal is generated and transmitted to the clock mask circuit 2A.
The clock mask circuit 2A masks the clock signal while the clock mask signal is valid and does not supply the clock signal to the SDRAM 1, but after the command is issued, the number of the clock signals subtracted from the command mask time correspondence table 2B And invalidate the clock mask signal. As a result, clock signals corresponding to the number of clock signals are generated and output to the SDRAM 1.
By adding a circuit having such a configuration, an operation of supplying only the clock signal required for the issued command to the SDRAM 1 can be realized.

FIG. 2 is a flowchart showing the operation of the clock mask determination circuit 2C. FIG. 3 is a timing chart showing an example of the operation of the clock mask determination circuit 2C of FIG. FIG. 4 is an explanatory diagram showing an example of a command mask time correspondence table 2B for commands and the number of clock signals (counter values).
The clock mask determination circuit 2C determines whether or not to mask the clock signal according to the flowchart shown in FIG. That is, it is determined whether or not a command is generated in step S1, and when a command is generated, the process proceeds to step S2.
In step S2, the generated command, for example, a value (number of clock signals) corresponding to the ACT command is drawn from the command mask time correspondence table 2B shown in FIG. The value subtracted from the command mask time correspondence table 2B is “3” corresponding to the ACT command.
In the following step S3, the value “3” corresponding to the ACT command drawn from the command mask time correspondence table 2B is compared with the counter value CMC held by the clock mask determination circuit 2C. Initially, the counter value CMC is “0”, and the value “3” subtracted from the command mask time correspondence table 2B is larger. Therefore, the process proceeds to step S4, and the counter value CMC is stored in the command mask time correspondence table. Overwrite with the value “3” subtracted from 2B.
In step S5, it is checked whether the counter value CMC is “0”. At this time, since the counter value CMC is “3” instead of “0”, the clock masking process is canceled by disabling the clock mask signal, and the clock signal is converted into one clock signal in step S6. Are generated and output to the SDRAM 1. In the generation of the clock signal, the clock signal mask process is canceled in the clock mask circuit 2A, so that the clock signal CLK supplied to the SDRAM controller 2 is output. In subsequent step S7, the counter value CMC is decreased by "1". This completes one process and holds the counter value CMC.

In the next clock signal, a command of RD (the length of data to be read is 4 clock signals) is detected in step S1. At this time, the counter value CMC in the clock mask determination circuit 2C is “2”. Since the value “7” represented by the command RD (length 4) is larger than the counter value CMC, the process proceeds from step S3 to step S4, the counter value CMC is overwritten with “7”, and the following step In S5 and S6, a clock signal is generated in the same manner as described above, and in step S7, the counter value CMC is decremented by “1”. Then, the processing of step S1, step S5, step S6, step S7, and step S9 is repeated until the counter value CMC becomes “0” in step S5, and the clock signal corresponding to the command RD is set to 7 in step S6. Generate.
Then, in step S5 of the next cycle, it is determined that the counter value CMC is “0”, the process proceeds from step S5 to step S8, and clock signal masking is executed.
As a result, for the command RD, while the counter value CMC is not “0”, that is, seven clock signals are generated.
While no command is issued and the counter value CMC is “0”, the process proceeds from step S1 to step S5 and further to step S8, and the mask process for the clock signal is continued.

  Finally, when a PRE command is detected in step S1, the process proceeds from step S1 to step S2 and further to step S3, and the counter value CMC is overwritten with the clock signal number “3” subtracted from the command mask time correspondence table 2B. Then, the process proceeds from step S5 to step S6, and the processes of step S1, step S5, step S6, step S7, and step S9 are repeated until the counter value CMC becomes “0” in step S5, and in step S6, 3 clocks. Clock signals are generated for the number of signals. In the next cycle, since the counter value CMC is "0", the process proceeds from step S5 to step S8, and a clock signal masking process is executed.

  As described above, according to the first embodiment, the number of clock signals corresponding to the issued command is read from the command mask time correspondence table 2B, and the number of clock signals corresponding to the number of read clock signals is generated. When the generation of the clock signal is completed, the supply of the clock signal to the SDRAM 1 is blocked by mask processing unless the next command is issued. As a result, the clock signal supplied to the SDRAM 1 can be accurately controlled to the minimum number necessary to execute the issued command, and the power consumption can be reduced with high accuracy.

  In the first embodiment, the case where the value drawn from the command mask time correspondence table 2B is the number of clock signals is shown, but the real time and the number of clock signals can also be used. For example, a method in which the value corresponding to the command is the number of clock signals and the specified time is also conceivable. In this case, the clock mask determination circuit manages two values of the real time and the number of clock signals, and masks the clock signal when both conditions are satisfied.

  In addition, if the CPU can read and write the contents of the command mask time correspondence table from the outside and the command, the number of clock signals corresponding to the command, and the designated time can be set, it can be suitably applied to various DRAMs. .

FIG. 5 is a block diagram showing configurations of an SDRAM controller (synchronous memory controller) 102 and an SDRAM (synchronous memory) 11 to which the synchronous memory clock signal control method of the fourth embodiment is applied.
Clock signals are respectively supplied to the SDRAM controller 102 and the SDRAM 11, and the SDRAM 11 includes a clock enable signal terminal CKE.
There is a clock mask judgment circuit (identification means, judgment means, control means) 102A for monitoring a control signal to the SDRAM 11 inside the SDRAM controller 102, based on a control signal supplied from the SDRAM control circuit 3 or internal information of SDRAM control. The command to the SDRAM 11 is interpreted. A command, time information corresponding to the command, and clock signal number information are stored in the command mask time correspondence table (correspondence table) 102B. The clock mask determination circuit 102A draws the time corresponding to the command and the number of clock signals from the command mask time correspondence table 102B. Based on this value, a clock enable signal is generated and supplied to the CKE terminal of the SDRAM 11. In the SDRAM 11, the supplied clock signal is controlled based on the clock enable signal.
By adding a circuit having such a configuration, it is possible to realize an operation in which a clock signal is not supplied for a certain time after a command is issued to the SDRAM 11.
In this case, the timing chart and the algorithm of the clock mask determination circuit also change. The clock signal control method and apparatus of the synchronous memory according to the fourth embodiment is suitable for a case where the clock signal CLK requiring strict timing is not desired to be masked.

  The operation of the clock mask determination circuit 102A of the fourth embodiment is substantially the same as the flowchart shown in FIG. 2 used in the first embodiment, but step S6 in the flowchart of FIG. 2 validates the clock signal supplied to the SDRAM 11. In step S8, the clock enable signal is not generated, and the clock signal supplied to the SDRAM 11 is invalidated.

  As described above, according to the fourth embodiment, the number of clock signals corresponding to the issued command is read from the command mask time correspondence table 2B, a clock enable signal is generated according to the number of read clock signals, and supplied to the SDRAM 11. The clock signal to be controlled is controlled based on the clock enable signal. Unless the next command is issued, the supply of the clock signal to the SDRAM 11 is controlled by the clock enable signal supplied to the clock enable signal terminal CKE. As a result, it is possible to accurately control the supply of the clock signal to the SDRAM including the built-in type to the minimum number required for the issued command based on the number of clock signals corresponding to the issued command. Thus, the power consumption can be greatly reduced.

FIG. 6 is a block diagram showing the configuration of the SDRAM 21 and the SDRAM controller 200 to which the synchronous memory clock signal control method of the fifth embodiment is applied.
In the fifth embodiment, the DRAM controller 200 is the same as the conventional DRAM controller shown in FIG. 8, and has a configuration in which a circuit such as a clock mask is built in an SDRAM (synchronous memory) 21. That is, the SDRAM 21 includes a clock mask circuit 21A, a command mask time correspondence table 21B, a command interpretation circuit / clock mask determination circuit 21C, and an SDRAM core (synchronous memory core) 21D.
A command interpretation circuit / clock mask determination circuit 21C configured in the SDRAM controller 2 monitors a control signal to the SDRAM 21 and also supplies a control signal supplied from the SDRAM control circuit 300 of the SDRAM controller 200 or internal information of the SDRAM control. And the command to the SDRAM 21 is interpreted. Further, the number of clock signals corresponding to the interpreted command is drawn from the command mask time correspondence table 21B. Based on this value, a clock mask signal is generated and transmitted to the clock mask circuit 21A. While the clock mask signal is valid, the clock mask circuit 21A masks the clock signal supplied to the SDRAM core 21D and does not supply the clock signal to the SDRAM core 21D. Are supplied to the SDRAM core 21D.
By adding a circuit having such a configuration, it is possible to realize an operation in which a clock signal is not supplied for a predetermined time after a command is issued to the SDRAM 21.

  In the fifth embodiment, since the command interpretation circuit / clock mask determination circuit 21C can be tuned to a specific SDRAM core, the circuit can be optimized, and a normal controller that does not particularly consider the mask of the clock signal is used on the SDRAM controller 200 side. It can be used, and the clock signal is appropriately masked inside the SDRAM 21, so that power consumption can be easily reduced.

Further, the normal CLK is supplied to the command interpretation circuit / clock mask determination circuit 21C in the SDRAM 21, the CLK mask is determined, and the masked clock signal is supplied into the SDRAM core 21D. In this case, the masked clock signal changes in timing with respect to the conventional SDRAM 100 of FIG.
Further, even when the SDRAM has a DLL (Delayed Locked Loop) or PLL (Phase Locked Loop), it is possible to make the frequency variable or supply a missing clock signal.

In each of the embodiments described above, SDRAM is used as the memory. However, the present invention can also be applied to synchronous DRAM such as DDR-SDRAM and RDRAM and built-in DRAM (eDRAM).

1 is a block diagram showing a configuration of an SDRAM and an SDRAM controller to which a clock signal control method for a synchronous memory according to a first embodiment of the present invention is applied. FIG. 5 is a flowchart showing an operation of a clock mask determination circuit of the SDRAM controller to which the clock signal control method for the synchronous memory according to the first embodiment of the present invention is applied. 3 is a timing chart illustrating an example of an operation of the SDRAM controller to which the clock signal control method for the synchronous memory according to the first embodiment of the present invention is applied. It is explanatory drawing which shows an example of the command mask time corresponding | compatible table of the SDRAM controller to which the clock signal control method of the synchronous memory of Example 1 of this invention is applied. It is a block diagram which shows the structure of the SDRAM controller and SDRAM to which the clock signal control method of the synchronous memory of Example 4 of this invention is applied. It is a block diagram which shows the structure of the SDRAM controller and SDRAM to which the clock signal control method of the synchronous memory of Example 5 of this invention is applied. It is a timing chart for demonstrating the problem in the clock signal control method of the conventional synchronous memory. It is a block diagram which shows the outline | summary of the SDRAM to which the clock signal control method of the conventional synchronous memory is applied, and the SDRAM controller which controls the control signal.

Explanation of symbols

  1, 11, 21, ... SDRAM (synchronous memory), 2, 102, 200 ... SDRAM controller (synchronous memory controller), 2A, 21A ... Clock mask circuit, 2B, 21B, 102B ... Mand mask time correspondence Table storage circuit, 2C, 102A... Clock mask determination circuit, 21C... Command interpretation circuit / clock mask determination circuit, 21D... SDRAM core (synchronous memory core).

Claims (20)

A clock signal control method for a synchronous memory for controlling a clock signal supplied to the synchronous memory,
A correspondence table storing step for storing a correspondence table in which a command issued to the synchronous memory and an operation period defining information defining an operation period of the synchronous memory operating based on the command are associated with each other;
A command interpretation step for inputting a command issued to the synchronous memory and interpreting the input command;
Control for reading the operation period definition information corresponding to the command interpreted in the command interpretation step from the correspondence table and controlling a clock signal supplied to the synchronous memory based on the read operation period definition information Steps,
A method for controlling a clock signal of a synchronous memory, comprising: The operation period defining information is the number of clock signals necessary to execute the command,
2. The method of controlling a clock signal of a synchronous memory according to claim 1, wherein in the control step, the synchronous memory is operated by a clock signal of the number of clock signals.   In the control step, after the synchronous memory is operated by the number of clock signals, the clock signal supplied to the synchronous memory is masked to stop the supply of the clock signal to the synchronous memory. 3. A clock signal control method for a synchronous memory according to claim 2, wherein   3. The control step according to claim 2, wherein the control step controls a clock signal supplied to the synchronous memory by controlling a clock enable signal supplied to the synchronous memory based on the number of clock signals. A clock signal control method for a synchronous memory. The operation period defining information is the number of clock signals and the operation time necessary for executing the command,
2. The clock signal control method for a synchronous memory according to claim 1, wherein the control step controls a clock signal supplied to the synchronous memory based on the number of clock signals and the operation time.   The control step operates the synchronous memory with the number of clock signals of the number of clock signals, and masks a clock signal supplied to the synchronous memory after the operation time has elapsed to clock the synchronous memory 6. The synchronous memory clock signal control method according to claim 5, wherein the supply of the signal is stopped.   The control step controls a clock signal supplied to the synchronous memory by controlling a clock enable signal supplied to the synchronous memory based on the number of clock signals and the operation time. Item 7. A clock signal control method for a synchronous memory according to Item 6. 2. The clock signal control method for a synchronous memory according to claim 1, wherein the correspondence table is rewritable from outside. A clock signal control device for a synchronous memory for controlling a clock signal supplied to the synchronous memory,
Correspondence table storage means for storing a correspondence table in which a command issued to the synchronous memory and an operation period defining information defining an operation period of the synchronous memory that operates based on the command are associated with each other;
Command interpretation means for inputting a command issued to the synchronous memory and interpreting the input command;
The operation period definition information corresponding to the command interpreted by the command interpretation unit is read from the correspondence table stored in the correspondence table storage unit, and is read into the synchronous memory based on the read operation period definition information. Control means for controlling the clock signal supplied;
A clock signal control device for a synchronous memory, comprising: The operation period defining information is the number of clock signals necessary to execute the command,
10. The synchronous memory clock signal control apparatus according to claim 9, wherein the control means operates the synchronous memory in response to the number of clock signals.   The control unit operates the synchronous memory with the number of clock signals, and then masks the clock signal supplied to the synchronous memory and stops the supply of the clock signal to the synchronous memory. 11. The clock signal control device for a synchronous memory according to claim 10, wherein:   11. The control unit according to claim 10, wherein the control unit controls a clock signal supplied to the synchronous memory by controlling a clock enable signal supplied to the synchronous memory based on the number of clock signals. A clock signal control device for a synchronous memory. The operation period defining information is the number of clock signals and the operation time necessary for executing the command,
10. The clock signal control apparatus for a synchronous memory according to claim 9, wherein the control means controls a clock signal supplied to the synchronous memory based on the number of clock signals and the operation time.   The control means operates the synchronous memory with the number of clock signals of the number of clock signals, and after the operation time has elapsed, masks the clock signal supplied to the synchronous memory to clock the synchronous memory 14. The clock signal control device for a synchronous memory according to claim 13, wherein the supply of the signal is stopped.   The control means controls a clock signal supplied to the synchronous memory by controlling a clock enable signal supplied to the synchronous memory based on the number of clock signals and the operation time. Item 14. A clock signal control device for a synchronous memory according to Item 13. 10. The synchronous memory clock signal control device according to claim 9, wherein the correspondence table is rewritable from outside. The correspondence table storage means, the command interpretation means, and the control means are provided in a synchronous memory controller that controls the operation of the synchronous memory,
10. The clock signal control apparatus for a synchronous memory according to claim 9, wherein the clock signal is supplied to the synchronous memory via the control means. The correspondence table storage means, the command interpretation means, and the control means are provided in the synchronous memory,
10. The clock signal control apparatus for a synchronous memory according to claim 9, wherein the clock signal is supplied to the synchronous memory core of the synchronous memory via the control means. A synchronous memory control device for controlling the operation of the synchronous memory by controlling a clock signal supplied to the synchronous memory,
Correspondence table storage means for storing a correspondence table in which a command issued to the synchronous memory and an operation period defining information defining an operation period of the synchronous memory that operates based on the command are associated with each other;
Command interpretation means for inputting a command issued to the synchronous memory and interpreting the input command;
The operation period definition information corresponding to the command interpreted by the command interpretation unit is read from the correspondence table stored in the correspondence table storage unit, and is read into the synchronous memory based on the read operation period definition information. Control means for controlling the clock signal supplied;
A synchronous memory control device comprising: A synchronous memory that operates based on an input clock signal,
Correspondence table storage means for storing a correspondence table in which a command issued to the synchronous memory and an operation period defining information for defining an operation period that operates based on the command are associated with each other;
Command interpreting means for interpreting the input command;
The operation period definition information corresponding to the command interpreted by the command interpretation unit is read from the correspondence table stored in the correspondence table storage unit, and the clock input based on the read operation period definition information Control means for controlling the signal;
A synchronous memory characterized by comprising:

Images