JP2006127080A - Pipeline processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pipeline processor that can prevent degradation of processing efficiency due to cache miss-hit and also the degradation of processing efficiency due to data hazard. <P>SOLUTION: In a fetch stage, which fetches instructions of operation stages to the pipeline processor 3 for executing a plurality of instructions by dividing them into an operation stage of each multi-step, there are arranged an instruction fetch register 119 for storing the instructions and an instruction fetch register control part 109. The instruction fetch register control part 109 detects the cache miss-hit by which the instructions cannot be fetched therein in the fetch stage. Also, when the miss-hit is detected, the instruction fetch register control part 109 successively operates the instruction fetch register 119. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a pipeline processor.

  Currently, there are pipeline processors that execute a plurality of instructions in parallel and perform arithmetic processing in a so-called pipeline system. The pipeline processor executes each of a plurality of instructions in units of stages such as fetch and decode. Some pipeline processors include an external memory that can store a large amount of data, and a cache memory that can be accessed at a higher speed although the data storage capacity is small.

In a pipeline processor having a cache memory, data necessary for execution of instructions is read from the external memory into the cache memory. Then, when the processor accesses the cache memory, retrieves the data and executes the calculation, the calculation process can be executed at a higher speed.
In such a pipeline processor, an error may occur that the pipeline processor accesses an area in the cache memory where necessary information is not written. Such an error is commonly referred to as a cache miss (also referred to herein as a cache miss or simply a miss).

  When a cache miss occurs, the operation of the entire pipeline processor stops until information is read from the external memory. For this reason, it can be said that the occurrence of a cache miss hits the pipeline processor and impedes the processing efficiency. As conventional examples for preventing a decrease in processing efficiency of a pipeline processor due to occurrence of a cache miss hit, for example, there are those described in Patent Document 1 and Patent Document 2.

  The conventional example described in Patent Document 1 provides a shadow register file in addition to a register file. The shadow register file stores information such as a missed address when a cache miss occurs in operand fetch. Then, when the next cache miss hit occurs, an address to be accessed in the future is predicted using the stored address.

In the invention described in Patent Document 2, a first program counter and a second program counter are provided in advance. During normal operation, instruction data indicated by the address of the first program counter is supplied to the CPU. Further, when a cache miss hit occurs, instruction data indicated by the address of the second program counter is supplied to the CPU to prevent the CPU operation from being stopped when the cache miss hit occurs.
JP-A-6-51982 JP 2004-38600 A

  A cache miss hit occurs when the processor fetches instruction data related to an instruction (opcode) of the processor in addition to data related to an operand (operand data) used in the processor. However, many of the prior arts including the above-described prior art have been made in order to avoid a processor stop due to a cache miss hit of operand data. One reason for this is that operand data has a higher cache miss hit rate than instruction data.

  However, cache miss hits of instruction data occur relatively frequently depending on programs and systems, although they are lower than operand data. When an instruction cache miss hit occurs, the pipeline processor must be stopped until the instruction is read from the external memory. Accordingly, the instruction data cache miss hit reduces the processing efficiency of the pipeline processor in the same manner as the operand data cache miss hit.

By the way, as for a plurality of instructions processed by the pipeline processor, an operation result obtained by an instruction that has been processed first (for example, instruction 1) is used as an instruction that has been processed later (for example, instruction 2). It may be used in the calculation of
In such instruction 1 and instruction 2, if writing of the operation result of instruction 1 is not completed at the timing when instruction 2 uses the operation result of instruction 1, a data hazard occurs. When a data hazard occurs, the pipeline processor interlocks and stops processing. Therefore, the stoppage of the interlock due to the occurrence of the data hazard is a cause of lowering the processing efficiency of the pipeline processor as well as the cache miss hit.

Such a data hazard is a cause of reducing the processing efficiency of the pipeline processor along with the occurrence of a cache miss hit in the conventional pipeline processor.
The present invention has been made in view of the above points, and an object thereof is to provide a pipeline processor capable of preventing a decrease in processing efficiency due to a data hazard in addition to a decrease in processing efficiency due to a cache miss hit. To do.

  In order to solve the above problems, a pipeline processor of the present invention is a pipeline processor that executes a plurality of instructions by dividing them into multi-stage operation processes, and takes in instructions in the operation processes. Instruction fetching means for fetching instructions in the process, miss hit detection means for detecting a miss that the instruction fetching means cannot fetch instructions in the fetching operation process, and a miss hit by the miss hit detection means And an operation continuation means for continuously operating the command fetching means even when detected.

According to such an invention, in a pipeline processor that divides and executes a plurality of instructions into multi-stage operation processes, the instruction fetch means fetches instructions in the fetch operation process. Further, in this fetching operation step, the miss-hit detecting means detects a mishit, and the instruction fetching means can be operated even when a mishit is detected.
For this reason, even when a mishit occurs, the processing of other instructions being performed in the pipeline system does not stop by stopping the instruction fetching means, and other instructions preceding the instruction that caused the mishit are not stopped. Instruction processing proceeds. Therefore, it is possible to provide a pipeline processor that can prevent a data hazard from occurring in a program that originally causes a data hazard and can execute pipeline processing more smoothly and efficiently.

In the pipeline processor according to the present invention, the operation continuation unit instructs the instruction fetch unit to not fetch an instruction when a miss is detected by the miss hit detection unit. And operating the insertion means.
According to such an invention, the instruction fetching unit can continue the operation without fetching an invalid instruction input to the pipeline processor when a miss hit is detected. For this reason, the processing of other instructions that are performed in the pipeline system by the stop of the instruction fetching means does not stop, and the processing of the other instructions proceeds prior to the instruction that caused the mishit. Therefore, it is possible to provide a pipeline processor that can prevent a data hazard from occurring in a program that originally causes a data hazard and can execute pipeline processing more smoothly and efficiently.

The pipeline processor according to the present invention is characterized in that the operation continuation means instructs the instruction fetching means not to fetch an instruction by supplying a NOP signal to the instruction fetching means.
According to such an invention, it is possible to avoid the instruction fetching unit from stopping its operation relatively easily.

The pipeline processor according to the present invention further includes hazard detection means for detecting a hazard occurring between the operation steps, and the operation continuation means is configured to detect a miss by the miss-hit detection means, and detect the hazard. When the means does not detect a hazard, a NOP signal is supplied to the instruction fetch means.
According to such an invention, it is possible to supply the NOP signal to the instruction fetching means at the timing when a miss hit has occurred and no hazard has occurred. For this reason, since the NOP signal is efficiently supplied at an appropriate timing, it is possible to prevent the occurrence of a data hazard in a program that originally causes a data hazard, and it is possible to provide a pipeline processor with higher processing efficiency.

  The pipeline processor of the present invention is a pipeline processor that executes a plurality of instructions by dividing them into multi-stage operation steps including a fetch operation step for fetching instructions and a decode operation step for decoding the fetched instructions. An instruction fetching unit that fetches an instruction in the fetching operation step, an instruction decoding unit that decodes an instruction fetched by the instruction fetching unit in the decoding operation step, and the instruction fetching unit fetches an instruction. Miss hit detection means for detecting a miss hit that cannot be performed, interlock detection means for detecting that an interlock has been applied due to the occurrence of a hazard in the decoding operation step, and that a miss has occurred by the miss hit detection means Is detected, and the interlock detection means Other operation continuation means for continuously operating at least a part of the operation steps other than the decoding operation step while stopping the operation of the decoding means until the interlock is canceled when it is detected that the turlock is applied. It is characterized by providing.

  According to such an invention, the instruction is fetched in the fetching operation process among the multi-stage operating processes. Further, the instruction fetching unit detects a miss hit that cannot fetch the instruction, and detects that the interlock has been applied due to the occurrence of a hazard in the decoding operation process. When it is detected that a mis-hit has occurred and an interlock has been detected, at least one of the operation steps other than the decoding operation step is performed while stopping the operation of the decoding means until the interlock is released. The part can be operated continuously.

  According to such an invention, while the progress of the decode stage is stopped in a state where both an interlock and a mishit occur, other operation steps can be continuously executed, and the operation of other instructions is not affected. . For this reason, it is possible to respond to hazards while stopping fetching instructions that caused a miss hit in response to a miss hit, and the total pipeline processor stop time can be handled separately for a miss hit and an interlock. It can be shortened than. Therefore, it is possible to provide a pipeline processor that can execute pipeline processing that is smoother and more efficient.

  Further, according to the present invention, the other operation continuation means detects that a miss has occurred by the miss hit detection means, and the interlock detection means has been interlocked at the same time or immediately before the occurrence of the miss hit. Is detected, the operation of the decoding means is stopped until the interlock is canceled, and at least a part of the operation steps other than the decoding operation step is continuously operated.

According to such an invention, it is possible to execute a process of continuously operating at least a part of the operation steps other than the decoding operation step while stopping the operation of the decoding means at an optimal timing. Therefore, it is possible to provide a pipeline processor that can execute pipeline processing that is smoother and more efficient.
The pipeline processor of the present invention is a pipeline processor that divides and executes a plurality of instructions into multi-stage operation processes, and fetches instructions in the fetch operation process of fetching instructions among the operation processes. An instruction fetching means; a plurality of instruction storing means for storing instructions fetched by the instruction fetching means; and an instruction decoding means for fetching and decoding instructions stored in the instruction storing means; While the hazard is detected by the detecting means and the interlock is applied, each of the instruction storing means sequentially stores the instructions fetched by the instruction fetching means, and after the interlock is resolved, the instruction decoding means Are characterized by sequentially decoding instructions stored in each of the instruction storage means.

  According to such an invention, while the hazard is detected by the hazard detecting means and the interlock is applied, the instructions fetched by the instruction fetching means are sequentially stored in the plurality of instruction storing means, and the interlock is eliminated. After that, the instructions stored in each of the instruction storage means are sequentially decoded. Even after the interlock is released, in order to continue fetching new instructions, new instructions are successively taken into the instruction storage means, and the process proceeds in a state where the instructions exist in the instruction storage means. In the state where the instruction exists in the instruction storing means, when a miss hit occurs, the operation can be continued using the stored instruction. For this reason, for example, the supply of the NOP signal by the operation continuation unit is not required, or the number of times of the NOP signal supply can be suppressed, and a pipeline processor capable of executing smoother and more efficient pipeline processing can be provided.

Embodiments 1 and 2 of a pipeline processor according to the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram of a pipeline processor in Embodiment 1 of the present invention. The illustrated configuration includes an external memory 1 in which instructions to be given to the pipeline processor are stored, an instruction cache 2 used for caching instructions stored in the external memory 1, and a pipeline processor 3.

  The pipeline processor 3 executes a plurality of instructions divided into multi-stage operation processes. In the first embodiment, a plurality of instructions are extracted from the instruction cache 2 and executed. In the first embodiment, the multi-stage operation process for executing each instruction includes a fetch stage for fetching an instruction from the instruction cache, a decode stage for decoding the fetched instruction, an execution stage for executing the instruction, and an execution stage. The four operation stages of the write-back stage for writing the result obtained in step 4 into a register are assumed.

  In order to execute the instruction by dividing the instruction into a plurality of operation stages, the pipeline processor 3 processes the instruction fetch register 119 that fetches the instruction at the fetch stage, the instruction fetch register control unit 109 that controls the instruction fetch stage, and the decode stage. Instruction decode unit 111, an execution unit 113 for executing (calculating) the execution stage, and a register file 115 into which the operation result obtained by the operation by the execution unit 113 is written. The instruction fetch register control unit 109 includes a spare register 121 together with the instruction fetch register 119. Further, an instruction fetch request control unit 105 is provided to make a request for instruction reading to the instruction cache 2. The instruction fetch request control unit 105 outputs an instruction read request signal (denoted as PBUS_RD_EN in the figure) and a read address signal (denoted as PBUS_ADRS in the figure) to the instruction cache 2. This read request and read address are output in the cycle before the fetch stage.

  In the above configuration, an instruction from the instruction cache 2 is fetched into the instruction fetch register 119 by the instruction fetch register control unit 109 at the fetch stage. At this time, if the instruction fetch request control unit 105 makes a read request to an area in the instruction cache 2 where the instruction is not cached, the instruction cannot be immediately fetched. This is generally called a cache miss hit.

The instruction fetch register control unit 109 supplies a NOP (no-operation instruction) signal to the instruction fetch register 119 when a cache miss hit is detected and an interlock described later is not detected. NOP is an instruction that indicates that no processing is to be performed.
For this reason, since the instruction fetch register 119 captures the NOP signal from the instruction fetch register control unit 109 when the instruction cannot be captured due to a miss hit, the instruction fetch register 119 can continue to operate without stopping. Note that “continuous operation” means that the operation is performed in the same manner as when the fetch is normally completed even when an instruction cannot be fetched at the current operation timing (clock cycle). If the instruction fetch register 119 continues to operate even when a cache miss hit occurs, subsequent operation stages such as decoding and execution of operations are also performed continuously.

According to such an operation, an instruction in which a cache miss hit occurs does not affect other instructions, and the other instructions are completed in the same manner as in the case where no cache miss hit has occurred.
Further, the pipeline processor of the first embodiment includes a detection unit 107 for detecting a data hazard or the like. The detection unit 107 is configured to output an interlock signal (indicated as INTERLOCK in the drawing) to the instruction fetch request control unit 105 and the instruction fetch register control unit 109. The interlock signal is a signal having a different value depending on whether or not hazard detection is performed by the detection unit 107.

  Further, the pipeline processor of the first embodiment includes a branch address calculation unit 103 for calculating a branch destination address when a branch instruction is decoded by the instruction decoding unit 111. Further, a program counter 101 that is a source of an instruction read address signal output from the instruction fetch request control unit 105 is provided. The program counter 101 is usually incremented every cycle, but is updated to the branch destination address output from the branch address calculation unit 103 when the branch instruction is decoded. Note that when the instruction read request signal output from the instruction fetch request control unit 105 is disabled, the program counter 101 is controlled not to be updated. Incidentally, the instruction read request signal output from the instruction fetch request control unit 105 of the first embodiment is controlled so as to be disabled in a cycle in which a cache miss hit or an interlock occurs.

  The configuration described above basically operates as follows. That is, the instruction cache 2 shown in FIG. 1 outputs a miss-hit signal (denoted as PBUS_WAIT in the drawing) to the instruction fetch register control unit 109 together with the instruction data. The miss hit signal is a signal whose value is switched depending on whether or not a cache miss hit occurs, and the instruction fetch register control unit 109 detects the occurrence of a cache miss hit based on the value of the miss hit signal.

When a hazard occurs, the detection unit 107 switches the value of the interlock signal and notifies the instruction fetch register control unit 109 that the interlock has been applied.
In the first embodiment, both the miss-hit signal and the interlock signal are digital signals having a value of 1 or 0. For the interlock signal, the value when the interlock is not applied is 0, and the value when the interlock is applied is 1. For the miss-hit signal, the value in a state where no cache miss has occurred is 0, and the value in a state where a cache miss has occurred is 1.

By setting the interlock signal and the miss hit signal in this way, the instruction fetch register control unit 109 according to the first embodiment can recognize four types of states depending on combinations of the values of the interlock signal and the miss hit signal.
Note that the four types of states are states where neither a cache miss hit or an interlock occurs, a state where both a cache miss hit or an interlock occurs, or a state where only a cache miss hit occurs In total, only four interlocks are generated.

  Next, the operation of the pipeline processor described above will be described separately for the case where only a cache miss hit occurs (no occurrence of an interlock) and the case where a cache miss hit and an interlock occur simultaneously. Note that in the first embodiment, prior to the description of the operation of the pipeline processor of the first embodiment, the operation of the conventional configuration is shown in any description and is compared with the first embodiment.

1. When only a cache miss hit occurs (no interlock occurs) First, the operation of the pipeline processor when only a cache miss hit occurs (no interlock occurs) will be described below. This description is made assuming that the pipeline processor executes the program 1 shown below.
Program 1
(INST1)
(INST2)
(INST3) ADD% SR2,% SR0,% SR1
(INST4) ADD% SR4,% SR2,% SR3
(INST5)
(INST6)
In the above-described program 1, INST (INSTruction) 1 to INST6 indicate instruction codes, respectively. INST3 and INST4 are both instruction codes of the ADD instruction. INST3 instructs to add the value taken out from SR0 (register 0) and the value taken out from SR1 and write to SR2. INST4 is an instruction to add the value calculated by the ADD instruction of INST3 and written to SR2 and the value extracted from SR3 and write to SR4. INST1, INST2, INST5, and INST6 may be arbitrary programs.

Such a program 1 cannot be decoded by the INST4 until after the calculation result is written by the INST3. That is, INST4 cannot execute the decode stage until after the write back stage of INST3 is completed.
2 and 3 are timing charts when the above-described program is executed. The timing chart of FIG. 2 is that of a conventional pipeline processor. FIG. 3 is a timing chart when the above-described program is executed by the pipeline processor of the first embodiment. In the timing chart, F represents the fetch stage, D represents the decode stage, E represents the execution stage, and WB represents the write back stage. Further, the cache miss hit signal is indicated as PBUS_WAIT, and the interlock signal is indicated as INTERLOCK.

In both the examples shown in FIGS. 2 and 3, INST 4 generates a miss-hit in clock cycle 4. At this time, in the conventional configuration, the operation stages INST1, INST2, and INST3 do not move to the next operation stage (stop) until clock cycle 6 when the fetch is completed.
In addition, after normal operation is started after clock cycle 6, in the conventional configuration, a data hazard occurs between clocks INST 3 and INST 4 in clock cycle 7. Therefore, INST4 can execute the decode stage after clock cycle 8 in which the write-back stage of INST3 is performed. In the example shown in FIG. 2, the decode stage is executed at clock cycle 9, the execution stage and the write back stage are subsequently executed, and INST4 is completed at clock cycle 11.

  On the other hand, also in the pipeline processor of the first embodiment, INST4 generates a miss-hit in clock cycle 4. At this time, the instruction fetch register control unit 109 receives an active state of a miss signal indicating that a cache miss has occurred. When the active state of the miss-hit signal is input and the disabled state of the interlock signal is input, the instruction fetch register control unit 109 generates a NOP signal and stores it in the instruction fetch register 119.

  The NOP signal is stored, for example, as follows. That is, the instruction fetch register control unit 109 includes a storage device that stores NOP signals in advance. The instruction fetch register control unit 109 detects a cache miss by the miss hit signal and causes the instruction fetch register 119 to output a NOP signal from the storage device when the interlock is not generated. 119 stores this NOP signal.

In FIG. 3, the instruction fetch register 119 stores the NOP signal by the instruction fetch register control unit 109 in clock cycle 4 and clock cycle 5 in which the instruction cannot be fetched. The storage stage of the NOP signal by the instruction fetch register control unit 109 is defined as a hard fetch stage, and is indicated as “hard F” in the drawing.
As described above, the pipeline processor according to the first embodiment executes the hard fetch stage in clock cycle 4 and clock cycle 5. For this reason, the pipeline continues to operate without stopping any stage. Therefore, each operation stage is sequentially executed without stopping in INST1, INST2, and INST3, and the write back stage in INST3 is completed at a timing earlier than the conventional configuration.

  In the example shown in FIG. 3, when the decode stage of INST4 is performed at clock cycle 7, the writing of the calculation result of INST3 is completed. Therefore, the operation result of INST3 can be used by INST4 at clock cycle 7, and the pipeline processor is not stopped by the interlock. The pipeline processor according to the first embodiment can prevent the inherent hazard when a cache miss hit occurs, and can increase the efficiency of pipeline processing.

2. When cache miss hit and interlock occur simultaneously Next, the operation of the pipeline processor when the cache miss hit and interlock occur at the same timing will be described below. This description will be made assuming that the pipeline processor executes the program 2 shown below.
Program 2
(INST1)
(INST2) ADD% SR2,% SR0,% SR1
(INST3) ADD% SR4,% SR2,% SR3
(INST4)
(INST5)
(INST6)
In the program 2 described above, the instruction INST3 cannot decode the instruction until the writing of the operation result by the INST2 is completed. That is, INST3 can only execute the decode stage after the write-back stage of INST2 is completed.

When the cache miss hit and the interlock occur at the same timing, the pipeline processor shown in FIG. 1 serves as an interlock detection unit that detects that the interlock 107 is applied due to the occurrence of a hazard in the decode stage. Function.
In addition, the instruction fetch register control unit 109 detects that a mis-hit has occurred and detects that an interlock has been applied, while stopping the operation of the instruction decode unit 111 until the interlock is released. It functions as another operation continuation means for continuously operating at least a part of the operation stage other than the decode stage.

  In addition, when the occurrence of a miss hit in the first embodiment is detected and the occurrence of an interlock is detected, the occurrence of a miss hit is detected and the occurrence of a simultaneous or miss hit is detected. A case where it is detected that an interlock has been applied immediately before. In the first embodiment, the following description will be given on the assumption that a miss-hit has been detected and at the same time that an interlock has been detected. It is to be noted that the occurrence of a miss hit in the first embodiment is detected and the interlock is simultaneously applied means that the miss hit detection signal and the interlock detection signal are activated in the same cycle. Shall.

  4 and 5 are timing charts for explaining the operation of the pipeline processor when the cache miss hit and the interlock occur at the same timing. The timing chart of FIG. Is. FIG. 5 is a timing chart when the pipeline processor according to the first embodiment copes with a state in which a cache miss hit and an interlock occur at the same timing.

  As shown in the figure, in the timing chart of FIG. 4, an interlock and a miss hit occur simultaneously in clock cycle 4. In such a case, the conventional pipeline processor first stops the operation stages of INST1, INST2, and INST3 in response to the occurrence of a miss hit. After the mishit is resolved, the INST3 decode stage is stopped until the INST2 write-back stage is completed in clock cycle 6 and clock cycle 7 in response to the hazard causing the interlock.

  On the other hand, in the pipeline processor of the first embodiment, when an interlock and a cache miss hit of INST4 occur in clock cycle 4, the decode stage of INST3 is stopped, and INST1 in the write-back stage and INST2 in the execution stage are Let it run continuously. Clock cycle 5 operates in the same manner. In this way, by continuously operating the execution stage and the write back stage, it is possible to deal with the INST4 miss hit as well as dealing with the interlock.

This is because all the operation stages are stopped during a cache miss hit as in the conventional case, so that the stop cycle is shortened compared to the operation for releasing the interlock after the cache miss hit is resolved. Processing efficiency is improved.
Further, the above-described operation stops only the operation of the instruction decoding unit 111 when the instruction fetch register control unit 109 simultaneously detects the occurrence of a cache miss and an interlock in the configuration shown in FIG. That is, it can be realized by operating the execution contents of the execution unit 113 and the like so that the stored contents of the instruction fetch register 119 are not updated.

  FIG. 6 shows a cache miss signal in the first embodiment (in the figure, including the case where only a cache miss hit occurs (no interlock occurs) and the case where a cache miss hit and an interlock occur simultaneously). It is a table showing the transition of the stored contents of the instruction fetch register 119 according to the state of the interlock signal (denoted as INTERLOCK in the figure) and the interlock signal (denoted as PBUS_WAIT). In the table, 1 means active and 0 means disable. Circled numbers in the figure are attached to the state of the pipeline processor, and circle 1 indicates a state in which neither a cache miss hit nor an interlock has occurred. A circle 2 shows a state where only the interlock is generated. A circle 3 indicates a state where only a cache miss hit occurs, and a circle 4 indicates a state where both a cache miss hit and an interlock occur.

In state circle 1, since neither a cache miss hit nor an interlock has occurred, the contents of the instruction fetch register 119 are replaced with the fetched instruction (fetched instruction).
The state circle 3 corresponds to the case where only the cache miss hit (no interlock occurrence) described in the above description occurs. At this time, in the pipeline processor of the first embodiment, the instruction fetch register control unit 109 causes the instruction fetch register 119 to store the NOP instruction. For this reason, the pipeline processor operates as if a cache miss hit has not occurred and does not stop. As a result, conventionally, it is possible to prevent an interlock that would otherwise occur after a stop due to a cache miss hit.

  Further, the state circle 4 corresponds to the case where the cache miss hit and the interlock described in the above description occur simultaneously. In this case, since the interlock has occurred, it is necessary to stop the decode stage. Therefore, the instruction fetch register 119 holds the currently stored instruction even in the next cycle. At this time, since a cache miss hit occurs at the same time in the past, the instructions in the execution stage and the write back stage are also stopped. In the present invention, since the instructions in the execution stage and the write back stage are not stopped, the performance is improved.

  A state circle 2 indicates the state of the pipeline processor in which only the interlock is applied. In this case, since the interlock has occurred, it is necessary to stop the decode stage. Therefore, the instruction fetch register 119 holds the currently stored instruction even in the next cycle. At this time, if there is a newly fetched instruction, it must be held in a separate register. The newly fetched instruction means, for example, an instruction of INST4 fetched in cycle 4 of FIG. 9 which is a timing chart of the first embodiment described later. The spare register 121 shown in FIG. 1 is provided for storing such an instruction.

In the first embodiment, since the interlock signal becomes 1 (active) and the instruction read request signal output from the instruction fetch request control unit 105 is disabled, no further instructions are captured. Therefore, only one spare register 121 in the first embodiment is required.
The pipeline processor of the first embodiment described above does not stop the instruction fetch register 119 when only a cache miss hit occurs (no interlock occurs). For this reason, the pipeline processing is continued, and the processing of the execution stage and the write back stage proceeds. As a result, the first embodiment can prevent inherent hazards and can prevent the pipeline processor from stopping due to the interlock.

  Further, when a cache miss hit and an interlock occur simultaneously, the pipeline processor of the first embodiment stops only the decode stage and operates other operation stages. With such processing, the first embodiment can simultaneously deal with a penalty (processing stagnation) due to the occurrence of a cache miss hit and a penalty due to a hazard. It can be considered that such a countermeasure can conceal the interlock penalty from the penalty of cache miss hit.

Further, Embodiment 1 of the present invention is not limited to the configuration described above. That is, in the first embodiment, only the case where an instruction cache miss hit and an interlock due to a hazard occur simultaneously has been described. However, the operation of the pipeline processor when the cache miss hit and the interlock occur simultaneously in the first embodiment is the same as the cache miss hit penalty and the interlock penalty even when the interlock occurs immediately before the cache miss hit. And processing the pipeline processor more efficiently.
(Embodiment 2)
Next, Embodiment 2 of the present invention will be described. FIG. 7 is a block diagram of a pipeline processor according to the second embodiment of the present invention. Of the configurations shown in FIG. 7, configurations similar to those described in the pipeline processor of the first embodiment are denoted by the same reference numerals, and description thereof is partially omitted.

  The pipeline processor shown in FIG. 7 executes instructions divided into a fetch stage, a decode stage, an execution stage, and a write-back stage in the same manner as the pipeline processor shown in FIG. Therefore, the pipeline processor of the second embodiment also includes an instruction fetch register control unit 709, an instruction decoding unit 111, an execution unit 113, and a register file 115.

The pipeline processor shown in FIG. 7 includes a detection unit 107 and an instruction fetch request control unit 105 for detecting a data hazard or the like.
The instruction fetch register control unit 709 according to the second embodiment is similar to the instruction fetch register control unit according to the first embodiment in that it includes an instruction fetch register 119, but further includes an instruction buffer 0 and an instruction buffer 1 that are a plurality of instruction storage units. ... different from the first embodiment in that an instruction buffer N is provided. In the second embodiment, the instruction buffer 0, the instruction buffer 1,..., The instruction buffer N are referred to as an instruction buffer group 719.

  In the normal operation, in the pipeline processor of the second embodiment, the instruction fetch register 119 fetches an instruction from the instruction cache 2 under the control of the instruction fetch register control unit 709 as in the first embodiment. The fetched instruction is decoded by the instruction decoding unit 111, then executed (calculated) by the execution unit 113, and the result is written in the register file 115 in the write back stage.

  However, the pipeline processor of the second embodiment continues to fetch instructions while the hazard is detected by the detection unit 107 and the interlock is applied, and the instructions fetched into the instruction buffers included in the instruction buffer group 719 are fetched. Store sequentially. In addition, after the interlock is canceled, the instruction stored in each instruction buffer is shifted to the instruction fetch register 119 while being shifted and processed.

Unlike the first embodiment, in order to continue fetching instructions even during the interlock, the instruction fetch request control unit 105 according to the second embodiment performs an instruction read request signal (in the figure, even when the interlock is active). Keep PBUS_RD_EN active).
Next, the operation of the above pipeline processor will be described. In the second embodiment, it is assumed that the pipeline processor executes the program 2 shown in the first embodiment. Also in the second embodiment, prior to the description of the operation of the pipeline processor of the second embodiment, the operation of the conventional configuration is shown and compared with the second embodiment.

8, 9, and 10 are timing charts when the above-described program is executed, and the timing chart of FIG. 8 is that of a conventional pipeline processor. FIGS. 9 and 10 are timing charts when the above-described program is executed by the pipeline processors of the first and second embodiments, respectively.
In the examples shown in FIG. 8, FIG. 9, and FIG. 10, INST3 generates a hazard at clock cycle 4, and interlock is applied until the write back stage of INST2 is completed. Thereafter, a cache miss hit occurs at INST8.

  FIG. 9 is a timing chart showing a state in which the first embodiment described above is applied. In this case, as shown in the figure, the pipeline process is continuously operated by storing the NOP in the instruction fetch register 119 when a miss hit occurs. Therefore, in the conventional operation shown in FIG. 8, an interlock occurs when the operation result of INST8 is INST6 or INST7 is used in clock cycle 14, but in FIG. 9 of the first embodiment, pipeline processing continues to operate. Therefore, in clock cycle 14, the write back stage of INST6 and INST7 is completed, so that no interlock occurs. Therefore, it can be said that the pipeline processor of the first embodiment has higher processing efficiency than the conventional pipeline processor.

  FIG. 10 is a timing chart when the same program 2 is executed by the pipeline processor of the second embodiment. As shown in FIG. 10, the pipeline processor of the second embodiment continues to fetch instruction data even when an interlock is applied. That is, when the interlock occurs, the pipeline processor according to the second embodiment fetches the instruction INST4 into the instruction buffer 0 (denoted as B0 in the drawing) in clock cycle 4. In clock cycle 5, the instruction INST5 is fetched into the instruction buffer 1 (denoted as B1 in the figure).

  After releasing the interlock, the instructions fetched into the instruction buffer by the above processing are processed according to the fetching order. In the example shown in FIG. 10, the instruction INST4 in the instruction buffer 0 (denoted as B0 in the figure) is stored in the instruction fetch register 119 in the clock cycle 6 after the release of the interlock. At this time, the instruction INST5 in the instruction buffer 1 is moved to the instruction buffer 0. At this time, the INST 6 fetched from the instruction cache 2 is stored in the instruction buffer 1.

Similarly, in clock cycle 7, the instruction INST5 in the instruction buffer 0 is moved to the instruction fetch register 119. The instruction INST6 in the instruction buffer 1 is moved to the instruction buffer 0. The INST 8 fetched from the instruction cache 2 is stored in the instruction buffer 1.
As described above, each instruction is sequentially fetched into each instruction buffer of the instruction buffer group 719, and when the instruction is moved to the instruction fetch register 119, execution of each instruction is started.

  In FIG. 9 showing the state of the first embodiment, a cache miss hit of INST8 occurs at clock cycle 10, but in the case of FIG. 10 showing the state of the second embodiment, the interlock is in progress as described above. Since the instruction fetch is continued, a cache miss hit of INST8 occurs at clock cycle 8 which is two cycles earlier. That is, in FIG. 10 of the second embodiment, the processing is advanced two cycles earlier, that is, the processing efficiency of the pipeline processing is improved.

  Moreover, FIG. 9 and FIG. 10 can also be compared as follows. In three cycles during a cache miss hit, FIG. 9 fetches three NOPs, whereas FIG. 10 fetches instructions into the instruction buffer 0 and the instruction buffer 1 in advance, so that one NOP fetch is sufficient. That is, in FIG. 10, the pipeline is operating as if a cache miss hit has occurred for only one cycle. Therefore, the processing efficiency of pipeline processing is improved.

  Also, when a branch instruction such as a branch instruction or jump instruction is decoded in the state where the instruction exists in the instruction buffer, the instruction in the instruction buffer that does not branch is fetched. The program does not work properly. Therefore, the pipeline processor according to the second embodiment operates so as to discard the instruction stored in the instruction buffer when the branch instruction is decoded. Note that the discarding of an instruction here means that the instruction is in the same state as when no instruction is stored in the instruction buffer.

The pipeline processor of the second embodiment can prevent the program from failing due to such an operation. Further, such an operation is similarly performed when a program branches by exception processing or the like.
FIG. 11 is a timing chart for explaining the operation when the pipeline processor of the second embodiment decodes a branch instruction. In FIG. 11, the instruction of INST7 is a branch instruction and is decoded in clock cycle 10. In the second embodiment, control is performed so that the instruction buffer 0 (denoted as B0 in the figure) and the instruction buffer 1 (denoted as B1 in the figure) are invalidated in the clock cycle 11 in the clock cycle 10 in which the branch instruction is decoded. As a result, the instruction stored in the instruction buffer when not branching is discarded. By discarding the instruction, in clock cycle 11, the branch destination instruction is stored in the instruction fetch register 119. In order to realize these operations, a control signal indicating whether or not a branch occurs is output from the instruction decode unit 111 to the instruction fetch register control unit 709.

FIG. 12 shows a cache miss signal (denoted as PBUS_WAIT in the figure), an interlock signal (denoted as INTERLOCK in the figure), and a valid flag (B (0) in the figure) of the instruction buffer 0 in the second embodiment described above. It is a table showing the transition of the stored contents of the instruction fetch register 119 according to _f).
In the table, 1 means active, 0 means disable, and X means Don't Care. The valid flag B (0) _f of the instruction buffer 0 is indicated as valid if an instruction is stored in the instruction buffer 0, and invalid if not stored. The contents stored in the instruction buffer 0 are indicated as B (0). The circled numbers in the table are attached to the state of the pipeline processor.

  Circles 1 and 2 indicate a state in which neither a cache miss hit nor an interlock occurs. At this time, if the instruction buffer 0 is invalid, that is, if no instruction is taken into the instruction buffer 0 (circle 1), the instruction from the instruction cache 2 is stored in the instruction fetch register 119. When the instruction buffer 0 is valid, that is, when an instruction is fetched into the instruction buffer 0 (circle 2), the instruction fetched into the instruction buffer 0 is stored (moved) in the instruction fetch register 119.

A circle 3 indicates a state where only an interlock is generated. At this time, the decode stage is stopped, that is, the instruction fetch register 119 holds the stored instruction in the next cycle.
Circles 4 and 5 show a state in which only a cache miss hit occurs. At this time, if the instruction buffer 0 is invalid (circle 4), the instruction fetch register control unit 709 stores NOP in the instruction fetch register 119. When the instruction buffer 0 is valid (circle 5), the instruction fetched in the instruction buffer 0 is stored (moved) in the instruction fetch register 119.

A circle 6 indicates a state where both a cache miss hit and an interlock have occurred. Since the interlock has occurred, the decode stage stops. That is, the instruction fetch register 119 holds the stored instruction in the next cycle.
FIG. 13 is a table collectively showing the transition of the contents stored in each instruction buffer of the instruction buffer group 719 in the second embodiment. Each instruction buffer has a 1-bit valid flag, the valid flag of the i-th instruction buffer is B (i) _f, and the contents stored in each instruction buffer are shown in the table as B (i). . However, B (i−1) _f when i = 0 means the instruction fetch register 119 and is always valid. In addition, the validity of the valid flag here indicates that there is an instruction in the instruction buffer, and invalid means that there is no instruction.

As shown in FIG. 13, the transition of the valid flag B (i) _f and stored content B (i) of the i-th instruction buffer is a signal indicating the occurrence of a branch, a cache miss signal (denoted as PBUS_WAIT in the figure), It is determined by an interlock signal (indicated as INTERLOCK in the figure), B (i) _f, B (i + 1) _f, and B (i−1) _f.
By controlling the instruction fetch register 119 as shown in FIG. 12, and controlling each instruction buffer of the instruction buffer group 719 as shown in FIG. 11 can operate as in the timing chart shown in FIG. 11 and can operate without failure even when there is a branch of the program, and can realize pipeline processing with high processing efficiency.

The second embodiment of the present embodiment described above includes a plurality of instruction buffers that can store fetched instructions. When an interlock occurs at the decode stage, the instruction is fetched at the fetch stage and sequentially stored in the instruction buffer. Therefore, the instruction can be fetched into the instruction buffer when the interlock occurs.
Further, after the interlock is released, the instructions stored in the instruction buffer are sequentially shifted to the instruction fetch register and decoded. At the same time, fetched instructions are taken into an empty instruction buffer. When a cache miss hit occurs, it is possible to prevent the operation stage from being stopped using an instruction stored in the instruction buffer in preference to dealing with supply of a NOP signal or the like.

  Such a pipeline processor of the second embodiment requires less number of executions such as supply of the NOP signal than the first embodiment, and the processing of the pipeline processor can be made more efficient.

It is a block diagram of the pipeline processor of Embodiment 1 of this invention. 3 is a timing chart of the conventional pipeline processor shown for comparison with the pipeline processor of the first embodiment. 3 is a timing chart of the pipeline processor according to the first embodiment. 4 is a timing chart showing a state in which interlock and mis-hit occur simultaneously in the conventional pipeline processor shown for comparison with the pipeline processor of the first embodiment. 3 is a timing chart illustrating a state in which an interlock and a miss hit occur simultaneously in the pipeline processor of the first embodiment. It is the table | surface which showed the transition of the instruction fetch register in Embodiment 1 of this invention. It is a block diagram of the pipeline processor of Embodiment 2 of this invention. It is a timing chart at the time of executing the program 2 with the conventional pipeline processor. 6 is a timing chart when the program 2 is executed by the pipeline processor of the first embodiment. 10 is a timing chart when the program 2 is executed by the pipeline processor of the second embodiment. 10 is a timing chart for explaining an operation when the pipeline processor of the second exemplary embodiment decodes a branch instruction. It is the table | surface which showed the transition of the instruction fetch register in Embodiment 2 of this invention. It is the table | surface which showed collectively the transition of the content stored in each instruction buffer of the instruction buffer group in Embodiment 2 of this invention.

Explanation of symbols

1 external memory, 2 instruction cache, 3 pipeline processor, 101 program counter, 103 branch address calculation unit, 105 instruction fetch request control unit, 107 detection unit, 109,709 instruction fetch register control unit, 111 instruction decode unit, 113 execution , 115 register file, 119 instruction fetch register, 121 spare register, 719 instruction buffer group

Claims (7)

A pipeline processor that divides a plurality of instructions into multi-stage operation processes and executes the instructions.
Instruction fetching means for fetching instructions in the fetching action process for fetching instructions in the operation process;
In the fetch operation step, a miss detection means for detecting a miss that the instruction fetch means cannot fetch an instruction;
An operation continuation means for continuously operating the instruction fetch means even when a miss hit is detected by the miss hit detection means;
A pipeline processor comprising: The operation continuation means includes
2. The instruction fetching unit according to claim 1, wherein when a miss hit is detected by the miss hit detection unit, the command fetching unit is operated by instructing the command fetching unit not to fetch a command. Pipeline processor.   3. The pipeline processor according to claim 2, wherein the operation continuation unit instructs the instruction fetch unit not to fetch an instruction by supplying a NOP signal to the instruction fetch unit. Further comprising a hazard detection means for detecting a hazard occurring between the operation steps;
The operation continuation means supplies a NOP signal to the instruction fetch means when the miss hit detection means detects a miss and the hazard detection means does not detect a hazard. The pipeline processor according to claim 3. A pipeline processor that divides and executes a plurality of instructions into a multi-stage operation process including a fetch operation process for fetching an instruction and a decode operation process for decoding the fetched instruction,
Command fetching means for fetching commands in the fetching operation step;
Instruction decoding means for decoding the instruction fetched by the instruction fetching means in the decoding operation step;
A miss detection means for detecting a miss that the instruction fetch means cannot fetch an instruction;
Interlock detecting means for detecting that an interlock has been applied due to the occurrence of a hazard in the decoding operation step;
When it is detected by the miss-hit detecting means that a mis-hit has occurred and the interlock detecting means detects that an interlock has been applied, the operation of the decoding means is stopped until the interlock is released. However, other operation continuation means for continuously operating at least a part of the operation steps other than the decoding operation step,
A pipeline processor comprising:   The other operation continuation means, when it is detected that a miss hit has occurred by the miss hit detection means, and when the interlock detection means has detected that an interlock has been applied immediately before the occurrence of a miss hit, 6. The pipeline processor according to claim 5, wherein at least a part of the operation steps other than the decoding operation step are continuously operated while the operation of the decoding means is stopped until the interlock is canceled. A pipeline processor that divides a plurality of instructions into multi-stage operation processes and executes the instructions.
Instruction fetching means for fetching instructions in the fetching action process for fetching instructions in the operation process;
A plurality of instruction storage means for storing instructions fetched by the instruction fetching means;
Instruction decode means for taking out and decoding the instruction stored in the instruction storage means,
While the hazard is detected by the hazard detection means and the interlock is applied, each of the instruction storage means sequentially stores the instructions fetched by the instruction fetch means, and after the interlock is released, the instruction A pipeline processor, wherein the decoding means sequentially decodes instructions stored in each of the instruction storage means.

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