JP2006121443A - Pulse generator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pulse generator for securing the width of an output pulse, and for reducing a mounting area and power consumption than a conventional manner. <P>SOLUTION: This pulse generator is provided with a clock buffer 101 for accepting the input of a clock signal CK, and for outputting a signal IN generated by performing clock skew absorption or impedance conversion or the like, pulse generating circuits 102 and 103 constituted of two input AND elements for accepting the input of a signal IN and a signal IN_B, and for generating a signal OUT generated by operating the logical AND of the two signals and a delay circuit 108 for accepting the input of the signal IN, and for outputting the signal IN_B generated by generating the delay of a predetermined time in the inputted signal IN, and inverting it for outputting to the both pulse generating circuits 102 and 103. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a pulse generation device that generates a clock to be supplied to a latch circuit and the like, and more particularly to a reduction in power consumption of a circuit and a reduction in circuit scale.

  In a semiconductor integrated circuit, a sequential circuit using a flip-flop circuit that takes in and holds data in synchronization with a clock signal has been used for holding an internal state. In order to cope with the accompanying increase in power consumption, a pulse trigger type latch circuit that operates with a low-duty clock pulse has been used (see Patent Document 1).

In the pulse trigger type latch circuit, a pulse generation circuit and one latch are used in place of the conventional typical flip-flop composed of two master slave latches as in the prior art. Since only one device is required, low power consumption by reducing the clock load, high speed by shortening the setup time, and small area by reducing the number of elements are realized.
In particular, in order to reduce power consumption and mounting area due to the addition of the pulse generation circuit, it is general that the plurality of latch circuits are controlled by one pulse generation circuit.

According to the semiconductor integrated circuit using the pulse trigger type latch circuit described in Patent Document 1, the basic clock signal CK of the circuit is buffered by the clock buffer, signal processed by the pulse generation circuit, and supplied to the latch.
The pulse generation circuit includes an inverter train and a two-input AND element, the clock signal input from the clock buffer branches, one branch signal is input to one input terminal of the two-input AND element, and the other The branch signal is input to the inverter train, and after the input clock signal is inverted and delayed in the inverter train, it is input to the other input terminal of the 2-input AND element.

In the 2-input AND element, by taking the logical product of the clock signal output from the clock buffer and the signal inverted and delayed by the inverter row, it rises at the rising edge of the clock signal, and the falling edge of the delayed signal A pulse that sometimes falls is generated, and the pulse is output to the latch circuit.
The pulse width is determined by the signal delay time in the inverter train.
JP-A-11-55081

If the width of the pulse to be output to the latch circuit becomes smaller than the predetermined width due to power supply fluctuation or process fluctuation, data retention in the latch circuit becomes impossible. Therefore, it is necessary to provide a sufficient margin for the pulse width. In order to ensure this, it is necessary to connect a plurality of inverters in series, and there is a problem that the area and power increase due to an increase in the number of elements.
In view of the above problems, an object of the present invention is to provide a pulse generation device that reduces the mounting area and power consumption as compared with the prior art while ensuring the width of an output pulse.

  In order to solve the above-described problem, a pulse generation device that generates a pulse signal having a desired duty ratio using a clock signal, and a plurality of logic operation circuits and one delay shared on the input side of each logic operation circuit Each logic operation circuit generates a pulse signal by performing a logical operation on the clock signal and a delay signal obtained by inputting the clock signal to the delay circuit.

  The pulse generator of the present invention has the above-described configuration, so that a plurality of logic operation circuits share a delay circuit, so that the number of delay circuits can be reduced as compared with the conventional one. Since the number of logic operation circuits to be driven increases compared to the conventional circuit, the delay amount of the output signal from the delay circuit is increased, and the delay required to secure the pulse width of the pulses generated by each logic operation circuit Since the number of circuits can be reduced, it is possible to achieve an excellent effect that the mounting area can be reduced and the power consumption can be reduced while securing the width of the output pulse with a small number of delay circuits.

The plurality of logic operation circuits may obtain the delay signal through a signal line connected to the delay circuit, and the wiring distances from the delay circuit to the two logic operation circuits may be equal to each other.
According to this configuration, since the delay distance of the signal flowing between the delay circuit and each logical operation circuit is equal because the wiring distance of the wiring connection between the delay circuit and each logical operation circuit is equal, each signal is synchronized. Each logic operation circuit can perform a synchronization operation based on a signal from the delay circuit, and can also synchronize pulses output from each logic operation circuit.

The plurality of logic operation circuits may obtain the clock signal via a clock signal line, respectively, and when the clock signal lines run in parallel with each other, they may run in parallel at a predetermined interval or more.
According to this configuration, each logical operation circuit can obtain a clock signal that is not affected by crosstalk.

The plurality of logic operation circuits may obtain the delay signal through a signal line connected to the delay circuit, and wiring distances from the delay circuit to the logic operation circuits may be different from each other.
According to this configuration, since the phases of the signals output from the respective logical operation circuits are shifted from each other, a plurality of pulses that meet the requirements of the receiving side can be provided from one reference clock.

In addition, at least one of the plurality of logic operation circuits may have a drive capability different from the others.
According to this configuration, since at least one of the signals output from each logic operation circuit is out of phase, it is possible to provide a plurality of pulses that meet the requirements of the receiving side from one reference clock.

Each of the plurality of logic operation circuits may generate a logical product of the clock signal and the delay signal.
According to this configuration, the pulse generation device can be configured using an AND circuit that generates a logical product.
The delay circuit may be configured by an inverter.

According to this configuration, a pulse generation device can be configured using an inverter.
The pulse generation device may be realized by a single semiconductor device.
According to this configuration, the pulse generation device can be configured by a single semiconductor device such as an LSI.
The pulse generator further includes a plurality of pulse generators, and each of the pulse generators includes a plurality of logic operation circuits and one delay circuit shared on the input side of each logic operation circuit. And each logical operation circuit generates a pulse signal by performing a logical operation on the clock signal and a delay signal obtained by inputting the clock signal to the delay circuit, and at least one of the plurality of delay circuits is You may have a different driving ability.

  According to this configuration, since at least one of the signals output from the plurality of delay circuits is out of phase, it is possible to provide a plurality of pulses that meet the requirements of the receiving side from one reference clock.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The pulse generator of the present invention generates and outputs a pulse necessary for operation of a transmission type latch circuit outside the apparatus from a clock signal input to the apparatus.
FIG. 1 is a circuit diagram of a basic portion of a counter device using a pulse generator according to an embodiment of the present invention.

The counter device comprises a pulse generator 100 and transmission latch circuits 104-107.
As shown in FIG. 1, each of the transmissive latch circuits 104 to 107 includes a D terminal to which an input data signal is input, a CLK terminal to which a pulse signal is input, and a Q terminal that outputs an output data signal. If the input data signal during the period when the pulse signal is high level is high level, the data corresponding to the value “1” is held, and if the input data signal is low level, the data corresponding to the value “0” is held. The signal indicating the held data is output from the Q terminal.

The pulse input to the CLK terminal is supplied from the pulse generator 100.
Further, the period during which the pulse is at a high level may be about 100 picoseconds.
As shown in FIG. 1, the pulse generation device 100 includes a clock buffer 101, pulse generation circuits 102 and 103, and a delay circuit 108.
The clock buffer 101 is a clock buffer that receives an input of a clock signal CK and outputs a signal IN generated by absorbing clock skew, impedance conversion, and the like.

The delay circuit 108 includes an inverter element, receives an input of the signal IN, generates a delay of a predetermined time for the input signal IN, and outputs a signal IN_B generated by inverting it.
Each of the pulse generation circuits 102 and 103 includes a two-input AND element, and receives a signal IN and a signal IN_B and generates a signal OUT generated by taking a logical product of the two signals.

FIG. 2 is a timing diagram showing waveforms of the signal IN, the signal IN_B, and the signal OUT in the pulse generator 100.
As shown in FIG. 2, the pulse width ΔOUT of a section of the signal OUT that is a positive potential is the same as the signal delay of IN_B with respect to IN.
The signal delay is determined by the specifications of the delay circuit 108, the wiring length from the delay circuit 108 to the pulse generation circuits 102 and 103, the gate delay of the delay circuit 108, the drive capability, and the load on the output side.

The pulse generation circuit 102 supplies the signal OUT to the CLK terminals of the transmissive latch circuits 104 and 105, and the pulse generation circuit 103 supplies the signal OUT to the CLK terminals of the transmissive latch circuits 106 and 107.
Here, by making the wiring length from the delay circuit 108 to the pulse generation circuit 102 equal to the wiring length from the delay circuit 108 to the pulse generation circuit 103, the delay circuit 108 outputs and is input to the pulse generation circuit 102. Since the delay time of the signal between the pulse and the pulse input to the pulse generation circuit 103 becomes equal, and the pulse rises and falls simultaneously, a plurality of circuits can be operated in synchronization.

As described above, since the wiring length between each circuit and each device affects the delay time of the pulse, etc., the layout of each circuit and each device is important. The layout of each circuit block will be described with reference to FIGS.
FIG. 3 is a diagram schematically showing an example of the layout of each circuit block in the pulse generator.

Unlike the circuit diagram showing the connection relationship between each circuit block, the layout diagram schematically shows the layout, that is, the positional relationship in which each circuit block is arranged, and the connection length of the wiring between each circuit block. .
FIG. 4 is a diagram corresponding to a circuit diagram of a memory circuit including the pulse generator shown in FIG.
A square frame in FIG. 3 indicates a circuit block. A line connecting the circuit blocks indicates that a wiring is made, and a length ahead indicates a wiring length.

  As shown in FIG. 3, the pulse generation circuit blocks 203 and 207, and 204 and 206 are arranged at positions corresponding to the vertices of the square, and the clock buffer block 201 is arranged at a position corresponding to the center of the square, A delay circuit block 202 is disposed at an intermediate point between lines connecting the pulse generation circuit blocks 203 and 204, and a delay circuit block 205 is disposed at an intermediate point between lines connecting the pulse generation circuit blocks 206 and 207.

  Here, the wiring length of the wiring connecting the clock buffer block 201 and the pulse generation circuit block 203 is equal to the wiring length of the wiring connecting the clock buffer block 201 and the pulse generation circuit block 204. Indicates that a predetermined interval (for example, 2 millimeters) is open, the wiring length of the wiring connecting the delay circuit 202 and the pulse generation circuit block 203, and the wiring of the wiring connecting the delay circuit 202 and the pulse generation circuit block 204 It shows that the length is equal.

  Specifically, the clock buffer block 201 includes a clock buffer 301, and the pulse generation circuit block 203 specifically includes a pulse generation circuit 303. Similarly, the pulse generation circuit blocks 204, 206, and 207 include: The delay circuit block 202 includes a delay circuit 302, and the delay circuit block 205 includes a delay circuit 305.

Here, the clock buffer 301 is an element equivalent to the clock buffer 101, the pulse generation circuits 310 to 317 are circuits equivalent to the aforementioned pulse generation circuit 103 or 104, and the delay circuits 302 and 303 are the same as those described above. This is an element equivalent to the delay circuit 108.
With the arrangement described above, the wiring structure from the clock buffer to the pulse generation circuit can be made equal, the delay time can be made equal, and the timing of rising and falling of the pulse input to each pulse generation circuit can be accurately set. Can be synchronized.

In addition, since the wiring structure from the delay circuit to the pulse generation circuit is also equal, the delay time of the pulse transmitted from the delay circuit to the pulse generation circuit can be equalized, and the pulse transmitted to each pulse generation circuit It is possible to accurately synchronize the timing of starting and falling.
In addition, since the signal line from the clock buffer to the pulse generation circuit and the wiring from the clock buffer to the delay circuit do not run in parallel, the influence of crosstalk between the respective signals can be eliminated.

In the description of FIG. 3, the case where the H-type wiring structure is used has been described. However, the clock wiring may be configured other than the H-type wiring structure, and in that case, the wiring may be adjacent depending on the position of the delay circuit and the clock buffer. Since crosstalk becomes a problem, layout is performed with a wiring constraint of more than double pitch between the signal from the clock buffer to the pulse generation circuit and the wiring from the clock buffer to the delay circuit. The influence can be eliminated.
<Operation>
FIG. 5 is a diagram illustrating a counter device including a plurality of pulse generators.

As shown in FIG. 5, the counter device operates in response to the input of the basic clock signal CK, and the data held by the transmissive latch circuit 404 is transferred to the transmissive latch circuit 424 via the transmissive latch circuit 414. It communicates to
In the data transmission path of the transmissive latch circuit 404 and the transmissive latch circuit 424, there is a signal path for transmitting the data signal and other signal paths in which a delay of DL1 nanosecond occurs in the data signal, and the data path 450 And a data path 460 in which a delay of DL2 nanoseconds occurs in the data signal.

  The clock buffers 401, 411, 421 are the same elements as the clock buffers 101, 301 described above, and the pulse generation circuits 402, 403, 412, 413, 422, 423 are the pulse generation circuits 102, 103, 303, described above. 304, 306, and 307, and the delay circuits 408, 418, and 428 are elements equivalent to the delay circuits 108, 302, and 305 described above.

Further, the transmissive latch circuits 404, 405, 406, 407, 414, 415, 416, 417, 424, 425, 426, and 427 are respectively the transmissive latch circuit 104 and the other latch circuits 105 to 107, This is a transmissive latch circuit equivalent to 310-317.
Here, the pulse widths or delays of the pulse signals CLK1, CLK2, and CLK3 input to the CLK terminals of the transmissive latch circuits 404, 414, and 424 are adjusted by the following method or a combination thereof.
(Method 1) Changing the drive capability of the delay circuits 408, 418, 428 By changing the drive capability of the delay circuits 408, 418, 428, the pulse widths of CLK1, CLK2, CLK3 can be changed.

  For example, the pulse width of CLK1 and the rising timing of the pulse are output from the delay circuit 408 and reach the pulse generation circuit 402 and the pulse generation circuit 403 by adopting the delay circuit 408 having a higher driving capability. Signal delay until the pulse widths of the pulses generated by the pulse generation circuit 402 and the pulse generation circuit 403 are reduced.

On the contrary, by adopting a delay circuit with a lower drive capability for the delay circuit 408, the signal delay from the output from the delay circuit 408 until reaching the pulse generation circuit 402 and the pulse generation circuit 403 is increased, thereby generating a pulse. The pulse widths of the pulses generated by the circuit 402 and the pulse generation circuit 403 are increased.
Similarly to the pulse width of CLK1, the pulse widths of CLK2 and CLK3 can be changed by changing the drive capabilities of the delay circuit 418 and the delay circuit 428.
(Method 2) Changing the wiring distance from the delay circuits 408, 418, 428 to the connected pulse generation circuit By changing the wiring distance from the delay circuits 408, 418, 428 to the pulse generation circuit to which each delay circuit is connected , CLK1, CLK2, and CLK3 pulse widths can be changed.

  For example, the pulse width of CLK1 is changed so that the wiring distance from the delay circuit 408 to the pulse generation circuits 402 and 403 to be connected is increased, so that the wiring load increases, and the pulse generation circuit 402 is output from the delay circuit 408. The signal delay until reaching the pulse generation circuit 403 is increased, and the pulse width of the pulses generated and output by the pulse generation circuit 402 and the pulse generation circuit 403 is increased.

Conversely, the pulse width of CLK1 is changed so as to shorten the wiring distance from the delay circuit 408 to the pulse generation circuits 402 and 403 connected thereto, thereby reducing the wiring load and being output from the delay circuit 408. The signal delay until reaching 402 and the pulse generation circuit 403 is reduced, and the pulse width of the pulses generated and output by the pulse generation circuit 402 and the pulse generation circuit 403 is reduced.
(Method 3) Change the wiring length between the pulse generation circuit and the transmissive latch circuit Reduce the wiring length between the pulse generation circuit and the transmissive latch circuit to reduce the wiring load of the wiring itself As a result, the clock rises faster, and conversely, by increasing the wiring length between the pulse generation circuit and the transmissive latch circuit, the wiring load of the wiring itself increases and the clock rise is delayed.
(Method 4) Change the drive capability of the pulse generator circuit By increasing the drive capability of the pulse generator circuit, the clock rises faster, and conversely, by reducing the drive capability of the pulse generator circuit than the others. The clock rise is slow.

By using any one of the above (Method 1), (Method 2), (Method 3), (Method 4) or a combination of the above methods, it is possible to increase the speed of the clock used in the entire counter device.
Hereinafter, after the signal D1_OUT of the transmissive latch circuit 404 passes through the data path 450 and is input to the transmissive latch circuit 414 as D2_IN, the output signal D2_OUT of the transmissive latch circuit 414 passes through the data path 460 and is transmitted as D3_IN. The route until entering the type latch circuit 424 will be described, but the description other than the above-described route will be omitted because it is redundant.

For DL1 and DL2, there are two examples: (1) DL1 is 11 ns and DL2 is 9 ns; (2) DL1 is 9 ns and DL2 is 11 ns. Although the operation will be described, the delay amounts of DL1 and DL2 are values that vary depending on the design contents of the data path 460 and the data path 470, and are not limited to 11 nanoseconds and 9 nanoseconds as described above.
(1) When DL1 is 11 ns and DL2 is 9 ns Here, it is assumed that the delay circuit 418 has a characteristic of delaying the signal by 1 ns longer than the delay circuits 408 and 428.

When the data paths 450 and 460 are present on the circuit, since DL1 is 11 nanoseconds, it is conceivable to operate the clock signal CK at 11 nanoseconds in order to absorb DL1. The operation is performed by improving the clock to 10 nanoseconds.
FIG. 6 is a diagram showing a timing chart in the circuit shown in FIG. 5 in the case where a clock having a 10 nanosecond cycle and a duty ratio of 0.5 is supplied as the clock signal CK.

CLK1 is an output signal of the pulse generation circuit 402. The pulse generation circuit 402 generates a logical product of a signal directly supplied from the clock buffer 401 and a signal supplied from the clock buffer 401 via the delay circuit 408. The signal has a pulse width corresponding to the delay time by the delay circuit 408.
Similarly, CLK2 is an output signal of the pulse generation circuit 412, and the logic between the signal directly supplied from the clock buffer 411 and the signal supplied from the clock buffer 411 via the delay circuit 418 is the pulse generation circuit 412. The signal generated by the product has a pulse width corresponding to the delay time by the delay circuit 418, CLK3 is an output signal of the pulse generation circuit 422, and the pulse generation circuit 422 is a signal directly supplied from the clock buffer 421. , A signal having a pulse width corresponding to a delay time by the delay circuit 428, generated by a logical product with a signal supplied from the clock buffer 421 via the delay circuit 428.

Specifically, the pulse widths of CLK1 and CLK3 are about 100 picoseconds, and the pulse width of CLK2 is about 1.1 nanoseconds, which is 1 nanosecond longer than the pulse widths of CLK1 and CLK3. Width.
D1_OUT is an output data signal from the transmissive latch circuit 404, D2_IN is a data signal that passes through the data path 450 and is input to the transmissive latch circuit 414, and D2_OUT is output data from the transmissive latch circuit 414. D3_IN is an input data signal to the transmissive latch circuit 424 that has passed through the data path 460.

The horizontal axis of FIG. 6 represents the time axis, and t = t1 is assumed to be t = 0 for convenience of explanation, t = t2 is 10 nanoseconds after t1, and t = t3 is t1 to 10.1 nanoseconds. Later, t = t4 indicates 11 nanoseconds after t1, and t = t5 indicates 20 nanoseconds after t1.
(A) When t = t1 The clock CK rises (not shown), and CLK1, CLK2, and CLK3 rise.

The signal delay of 100 picoseconds by the delay circuits 408 and 428 becomes the pulse width of CLK1 and CLK3, and CLK1 and CLK3 fall after 100 picoseconds from t1.
The signal delay of 1 nanosecond by the delay circuit 418 becomes the pulse width of CLK2, and CLK2 falls 1.1 nanoseconds after t1.
D1_OUT rises upon receiving a signal indicating a value “1” (not shown) at t = t1.

(B) When t = t2 CLK1, CLK2, and CLK3 rise in the same manner as when t = t1.
(C) When t = t3 CLK1 and CLK3 fall.
(D) When t = t4 The rise of D1_OUT at t = t1 is delayed by 11 nanoseconds via the data path 450, and appears at D2_IN at t = t4.

At this time, CLK2 is positive logic, and since both CLK2 and D2_IN are positive logic in the transmissive latch circuit 414, positive data is latched and output to D2_OUT.
(E) When t = t5 The rise of D2_OUT at t = t4 is delayed by 9 nanoseconds via the data path 460, and appears at D2_IN at t = t4.

The transmissive latch circuit 424 latches data indicating the value “1” because both CLK3 and D3_IN are positive logic.
As described above, by applying the pulse generator of the present invention to the target circuit, the falling edge of the clock pulse of the transmissive latch circuit 414 is delayed by 1 ns, so that the transmissive latch can be obtained even if the clock cycle is 10 ns. The circuit 414 can latch data, and can be operated at an operating frequency of 100 MHz where the operating frequency should be 91 MHz.
(2) When DL1 is 9 nanoseconds and DL2 is 11 nanoseconds Here, the drive capability of the pulse generation circuit 412 is larger than the pulse generation circuits 402 and 422 by the amount corresponding to the delay of 1 nanosecond. And

When the data paths 450 and 460 are present on the circuit, since DL2 is 11 nanoseconds, it is conceivable to operate the clock signal CK at 11 nanoseconds in order to absorb DL2. The operation is performed by improving the clock to 10 nanoseconds.
FIG. 7 is a timing chart in the circuit shown in FIG. 5 in the case where a clock having a 10 nanosecond cycle and a duty ratio of 0.5 is supplied as the clock signal CK.

CLK1 is an output signal of the pulse generation circuit 402. The pulse generation circuit 402 generates a logical product of a signal directly supplied from the clock buffer 401 and a signal supplied from the clock buffer 401 via the delay circuit 408. The signal has a pulse width corresponding to the delay time by the delay circuit 408.
Similarly, CLK2 is an output signal of the pulse generation circuit 412, and the logic between the signal directly supplied from the clock buffer 411 and the signal supplied from the clock buffer 411 via the delay circuit 418 is the pulse generation circuit 412. The signal generated by the product has a pulse width corresponding to the delay time by the delay circuit 418, CLK3 is an output signal of the pulse generation circuit 422, and the pulse generation circuit 422 is a signal directly supplied from the clock buffer 421. , A signal having a pulse width corresponding to a delay time by the delay circuit 428, generated by a logical product with a signal supplied from the clock buffer 421 via the delay circuit 428.

Specifically, the pulse widths of CLK1, CLK2, and CLK3 are about 100 picoseconds.
D1_OUT is an output data signal from the transmissive latch circuit 404, D2_IN is a data signal that passes through the data path 450 and is input to the transmissive latch circuit 414, and D2_OUT is output data from the transmissive latch circuit 414. D3_IN is an input data signal to the transmissive latch circuit 424 that has passed through the data path 460.

The horizontal axis of FIG. 7 indicates time, t = t10 is assumed to be t = 0 for convenience of explanation, t = t11 is 9 nanoseconds after t1, t = t12 is 10 nanoseconds after t1, t = T13 indicates 10.1 nanoseconds after t1, t = t14 indicates 19 nanoseconds after t1, and t = t15 indicates 20 nanoseconds after t1.
(A) When t = t10 The clock CK rises (not shown), and CLK1 and CLK3 rise.

The signal delay of 100 picoseconds by the delay circuits 408 and 428 becomes the pulse width of CLK1 and CLK3, and CLK1 and CLK3 fall after 100 picoseconds from t = t10.
D1_OUT rises upon receiving a signal indicating a value “1” (not shown) at t = t10.
(B) When t = t11 The rise of D1_OUT at t = t10 is delayed by 9 nanoseconds via the data path 450, and appears at D2_IN and D2_IN rises at t = t11.

CLK2 rises 1 nanosecond earlier than CLK1 and CLK3.
At this time, CLK2 is positive logic, and since both CLK2 and D2_IN are positive logic in the transmissive latch circuit 414, positive data is latched and output to D2_OUT.
(C) When t = t12 CLK1 and CLK3 rise in the same manner as when t = t1.

(D) When t = t13, CLK1 and CLK3 fall.
(E) When t = t14 CLK2 rises in the same manner as t = 12.
(F) When t = t15, CLK1 and CLK3 rise.

Further, the rising edge of D2_OUT at t = t12 is delayed by 11 nanoseconds through the data path 460, and appears at D3_IN at t = t15.
The transmissive latch circuit 424 latches data indicating the value “1” because both CLK3 and D3_IN are positive logic.
As described above, by applying the pulse generator of the present invention to a target circuit, the rising edge of the clock pulse of the transmissive latch circuit 414 is advanced by 1 ns, so that the transmissive latch circuit even if the clock cycle is 10 ns. 414 can latch data, and can be operated at an operating frequency of 100 MHz where the operating frequency should be 91 MHz.
<Summary>
In the present invention, the delay circuit is shared by a plurality of pulse generation circuits, so that the operation clock of the entire apparatus can be increased, and the number of delay circuits of the pulse generation apparatus is reduced as compared with the prior art. Therefore, the area can be reduced and the power consumption can be reduced.
<Other variations>
Although the present invention has been described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the present invention. Of course.

The following cases are also included in the present invention.
(1) Although the example in which two pulse generation circuits are connected to one delay circuit has been described, three or more pulse generation circuits may be connected to one delay circuit.
(2) The present invention may be the method described above. Further, the present invention may be a computer program that realizes these methods by a computer, or may be a digital signal composed of the computer program.

  The present invention also provides a computer-readable recording medium such as a flexible disk, a hard disk, a CD-ROM (Compact Disc Read Only Memory), a MO (Magneto Optical disc), a DVD (Digital Versatile). (Disc), DVD-ROM (Digital Versatile Disc Read Only Memory), DVD-RAM (Digital Versatile Disc Random Access Memory), BD (Blu-ray Disc), semiconductor memory, etc. Further, the present invention may be the computer program or the digital signal recorded on these recording media.

In the present invention, the computer program or the digital signal may be transmitted via an electric communication line, a wireless or wired communication line, a network represented by the Internet, or the like.
The present invention may be a computer system including a microprocessor and a memory, wherein the memory stores the computer program, and the microprocessor operates according to the computer program.

In addition, the program or the digital signal is recorded on the recording medium and transferred, or the program or the digital signal is transferred via the network or the like, and is executed by another independent computer system. It is good.
(3) The above embodiment and the above modifications may be combined.

  The pulse generator of the present invention is used as a basic technology of a semiconductor device such as an LSI including a counter and a latch circuit, and is produced by a semiconductor device manufacturer or the like.

It is a circuit diagram of the basic part of the counter apparatus using the pulse generator which is one Embodiment of this invention. FIG. 5 is a timing diagram showing waveforms of a signal IN, a signal IN_B, and a signal OUT in the pulse generator. It is a figure which shows typically the example of the layout of each circuit block in a pulse generator. FIG. 4 is a diagram corresponding to a circuit diagram of a memory circuit including the pulse generator shown in FIG. 3. It is a figure which shows a counter apparatus provided with two or more pulse generators. 6 is a timing chart in the circuit shown in FIG. 5 when DL1 is 11 nanoseconds and DL2 is 9 nanoseconds. 6 is a timing chart in the circuit shown in FIG. 5 when DL1 is 9 nanoseconds and DL2 is 11 nanoseconds.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Clock buffer 102, 103 Pulse generation circuit 104-107 Transparent latch circuit 108 Delay circuit 201 Clock buffer 202 Delay circuit 203 Pulse generation circuit block 206 Pulse generation circuit block 302 Delay element 303, 304 Pulse generation circuit 305 Delay element 306, 307 Pulse generation circuit 401 Clock buffer 402 Pulse generation circuit 403 Pulse generation circuit 408 Delay element 411 Clock buffer 412 Pulse generation circuit 414 Transmission type latch circuit 418 Delay element 421 Clock buffer 422 Pulse generation circuit 428 Delay element 450 Data path 460 Data path

Claims (9)

A pulse generation device that generates a pulse signal having a desired duty ratio using a clock signal,
A plurality of logical operation circuits;
One delay circuit shared on the input side of each logic operation circuit,
Each logic operation circuit generates a pulse signal by performing a logical operation on the clock signal and a delay signal obtained by inputting the clock signal to the delay circuit. Each of the plurality of logic operation circuits obtains the delay signal through a signal line connected to the delay circuit,
The pulse generation device according to claim 1, wherein wiring distances from the delay circuit to each logic operation circuit are equal to each other. Each of the plurality of logic operation circuits obtains the clock signal via a clock signal line,
2. The pulse generation device according to claim 1, wherein when the clock signal lines run parallel to each other, the clock signal lines run parallel to each other with a predetermined interval. Each of the plurality of logic operation circuits obtains the delay signal through a signal line connected to the delay circuit,
The pulse generation device according to claim 1, wherein wiring distances from the delay circuit to each logic operation circuit are different from each other. 5. The pulse generation device according to claim 1, wherein at least one of the plurality of logic operation circuits has a drive capability different from the others. The pulse generation device according to claim 3, wherein each of the plurality of logic operation circuits generates a logical product of the clock signal and the delay signal. The pulse generation device according to claim 2, wherein the delay circuit includes an inverter. The pulse generation device according to claim 1, wherein the pulse generation device is realized by a single semiconductor device. The pulse generator further comprises:
Comprising a plurality of pulse generating means;
Each of the pulse generation means includes a plurality of logic operation circuits and one delay circuit shared on the input side of each logic operation circuit, and each of the logic operation circuits delays the clock signal and the clock signal with the delay time. Generate a pulse signal by performing a logical operation on the delay signal obtained by inputting to the circuit,
The pulse generation device according to claim 1, wherein at least one of the plurality of delay circuits has a drive capability different from the others.

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