JP2006121014A - Electrostatic protection circuit and semiconductor integrated circuit employing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrostatic protection circuit including a structure with a protection voltage sufficiently withstanding both surge and latchup and suitably subjected to circuit integration, and to provide a semiconductor integrated circuit employing the same. <P>SOLUTION: The electrostatic protection circuit includes a thyristor 11 whose anode A is connected to a first terminal P1, and whose cathode K is connected to a second terminal P2; and a rectifier circuit 12 comprising a series forward connection of a first rectifier element D1 with a first forward voltage VF1, and a second rectifier element D2 with a second forward voltage VF2 different from the first forward voltage VF1. The anode A1 of the first rectifier element D1 is connected to a second gate G2 of the thyristor 11, and the cathode K2 of the second rectifier element D2 is connected to the cathode K of the thyristor 11. The turn-on voltage of the thyristor 11 is fine-adjusted by the combination of the first and second forward voltages VF1, VF2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electrostatic protection circuit and a semiconductor integrated device using the electrostatic protection circuit, and more particularly to an electrostatic protection circuit having a sufficient protection voltage and having a structure suitable for integration, and a semiconductor integrated circuit using the same. Relates to the device.

  2. Description of the Related Art Conventionally, in a semiconductor device having a semiconductor element, in particular, a CMOS (complementary MOS) transistor, in order to protect the semiconductor element from electrostatic discharge (ESD) due to external static electricity, an electrostatic protection element having an electrostatic protection element is provided. An electric protection circuit is used.

  One of the electrostatic protection elements is a thyristor that keeps a high discharge capability once it is turned on. However, since the turn-on voltage of the thyristor itself is as high as about 40 V, for example, there is a problem that the semiconductor element of the internal circuit is destroyed before the thyristor as the electrostatic protection element is turned on.

  On the other hand, an electrostatic protection circuit that turns on the thyristor with a voltage lower than the turn-on voltage of the thyristor itself is known (see, for example, Non-Patent Document 1).

  The electrostatic protection circuit disclosed in Non-Patent Document 1 includes an anode, a cathode, a first gate, and a second gate, the anode is connected to the first terminal, the cathode is connected to the second terminal, and the first gate is A thyristor connected to the second terminal via a resistor and a plurality of pn junction diodes are connected in series in the forward direction, the anode of the pn junction diode is connected to the second gate of the thyristor, and the cathode of the pn junction diode is the thyristor And a trigger rectifier element connected to the cathode.

The first terminal has a positive electrode larger than the sum of the forward voltage N × VF of the rectifier circuit expressed by the product of the forward voltage VF of the pn junction diode and the number N of series connection stages, and the forward voltage of the anode and second gate of the thyristor. When a positive surge is applied, the rectifier circuit becomes conductive and a forward current flows.
Since this current triggers the thyristor to turn on, the surge applied to the first terminal is discharged from the anode of the thyristor through the cathode to the second terminal.

  That is, a turn-on voltage lower than the turn-on voltage of the thyristor is obtained by appropriately selecting the number of connection stages of pn junction diodes connected in series in the forward direction.

In recent years, semiconductor devices have become more highly integrated and lower in voltage, and the breakdown voltage of the gate oxide film of a MOS transistor, which is a semiconductor element, has decreased. Therefore, the voltage at which the thyristor is turned on needs to be set lower than the breakdown voltage of the oxide film.
On the other hand, the semiconductor device undergoes a so-called burn-in test, which is energized at high temperature and high voltage as a shipping inspection, so the voltage at which the thyristor is turned on is higher than the voltage at which the thyristor is turned on by the high voltage applied during the burn-in test and causes latch-up. It needs to be set high.

  In other words, the voltage at which the thyristor, which is an electrostatic protection element, is turned on must be finely adjusted in accordance with various constraints determined by the specifications of the semiconductor device. ing.

However, the electrostatic protection circuit disclosed in Non-Patent Document 1 has a problem that the turn-on voltage cannot be adjusted to an allowable width because the turn-on voltage is adjusted in steps corresponding to the forward voltage of the pn junction diode. As a result, the semiconductor device may be destroyed.
M. Mergens et al; “Diode Triggered SCR (DTSCR) for RF-ESD Protection of BiCMOS SiGe HBTs and CMOS Ultra-Thin Gate Oxides” International Electron Devices Meeting December 8-10,2003, Technical Digest, P.515-518, Fig.2.

  The present invention provides an electrostatic protection circuit having a sufficient protection voltage against both surge and latch-up and having a structure suitable for integration, and a semiconductor integrated device using the same.

  In order to achieve the above object, in an electrostatic protection circuit of one embodiment of the present invention, a first terminal to which a predetermined potential is applied, a second terminal to which a potential lower than the predetermined potential is provided, an anode, a cathode, A thyristor having first and second gates, an anode connected to the first terminal, and a cathode connected to the second terminal; a first rectifying device having a first forward voltage; and the first A second rectifying element having a second forward voltage different from the forward voltage of the thyristor is connected in series in the forward direction, the anode of one of the rectifying elements is connected to the second gate of the thyristor, and the cathode of the thyristor And a rectifier circuit to which the cathode of the other rectifier element is connected.

  In the semiconductor integrated device of one embodiment of the present invention, a semiconductor substrate, a first terminal formed on a main surface of the semiconductor substrate, to which a predetermined potential is applied, and a second terminal to which a potential lower than the predetermined potential is applied. A terminal, and a p-type first diffusion layer and an n-type second diffusion layer facing and spaced apart from the first diffusion layer in an n-type first well region formed on a main surface of the semiconductor substrate, A p-type third diffusion layer and an n-type fourth diffusion layer facing and spaced apart from the third diffusion layer are formed in a p-type second well region adjacent to one side of the first well region, and the first diffusion A layer is connected to the first terminal, and the third and fourth diffusion layers are respectively formed in a thyristor connected to the second terminal, and a p-type third well region adjacent to the other side of the first well region. The drain and the gate are connected using the second diffusion layer as a drain. A first rectifying element having an n-type MOS transistor, a second rectifying element formed on a main surface of the semiconductor substrate, having an anode connected to a source of the MOS transistor, and a cathode connected to the second terminal; It is characterized by comprising.

  According to the present invention, since the first and second rectifying elements having different forward voltages are connected in series in the forward direction, the turn-on voltage of the thyristor is adjusted by a combination of steps corresponding to the first and second forward voltages. be able to.

Therefore, since the turn-on voltage of the thyristor can be finely set in accordance with the specifications of the semiconductor device, an electrostatic protection circuit having a sufficient protection voltage against both surge and latch-up can be obtained.
As a result, a highly integrated semiconductor device with high integration and low voltage driving can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing an electrostatic protection circuit according to Embodiment 1 of the present invention. The present embodiment is an example of an electrostatic protection circuit that protects an internal circuit from a positive surge that has entered the power supply Vdd line.

  In this specification, in a thyristor having a pnpn junction, the base of an npn transistor that is equivalently formed is referred to as a first gate, and the base of a pnp transistor is referred to as a second gate.

  As shown in FIG. 1, the electrostatic protection circuit 10 of this embodiment includes a thyristor 11 having an anode A, a cathode K, first and second gates G1, G2, and a first forward voltage VF1. A rectifier circuit 12 is provided in which a rectifier element D1 and a second rectifier element D2 having a second forward voltage VF2 different from the first forward voltage VF1 are connected in series in the forward direction.

The anode A of the thyristor 11 is connected to the first terminal P1, the cathode K is connected to the second terminal P2 that is electrically insulated from the first terminal P1, and the first gate G1 is connected to the second terminal P2 via the resistor R1. It is connected to the.
The anode A1 of the first rectifier element D1 of the rectifier circuit 12 is connected to the second gate G2 of the thyristor 11, and the cathode K2 of the second rectifier element D2 is connected to the cathode K of the thyristor 11.

  The first terminal P1 is a terminal connected to, for example, the positive power supply Vdd, and the second terminal P2 is a terminal connected to, for example, the ground GND.

  Since the turn-on voltage Vt of the thyristor 11 is set higher than the power supply voltage Vdd, for example, 1.2 V, both the thyristor 11 and the rectifier circuit 12 are in an off state during normal operation.

When a positive surge enters the first terminal P1 and the voltage of the anode A of the thyristor 11 becomes higher than the turn-on voltage Vt of the thyristor 11, the rectifier circuit 12 is turned on and a forward current flows.
Since this current triggers the thyristor 11 to turn on, the surge applied to the first terminal P1 is discharged from the anode A of the thyristor 11 through the cathode K to the second terminal P2.
When the surge is discharged and the voltage at the anode A of the thyristor 11 becomes lower than the turn-on voltage Vt of the thyristor 11, both the thyristor 11 and the rectifier circuit 12 return to the off state.

  The resistor R1 increases the potential of the first gate G1 by a voltage drop due to the current flowing through the resistor R1 when the current starts to flow through the thyristor 11, so that the thyristor 11 is easily turned on.

As is well known, the thyristor 11 has a pnpn junction, and equivalently, the emitter of the pnp transistor Q1 is connected to the base of the npn transistor Q2, and the collector of the npn transistor Q2 is connected to the base of the pnp transistor Q1. Constitutes a positive feedback loop.
By flowing a gate current into the second gate G2, the thyristor 11 is turned on. When the thyristor 11 is turned on, the transistors Q1 and Q2 supply base currents to each other, so that the turn-on state is maintained.
The first rectifier element D1 includes, for example, an n-type MOS transistor M1 having a gate g1 connected to the drain d1. The threshold voltage Vth of the n-type MOS transistor M1 can be adjusted by changing the impurity concentration of the gate channel, and can be set to about 0.3 to 0.5 V, for example.
Accordingly, the first forward voltage VF1 of the first rectifying element D1 is equal to the threshold voltage Vth of the n-type MOS transistor M1, and can be set to, for example, about 0.3V.

The second rectifier element D2 has, for example, two pn junction diodes 13. The forward voltage of the pn junction diode 13 is about 1V.
Therefore, the second forward voltage VF2 of the second rectifier element D2 is equal to twice the forward voltage of the pn junction diode 13, and can be set to about 2V.

  As a result, the forward voltage VF3 of the rectifier circuit 12 is equal to the sum of the first forward voltage VF1 of the first rectifier element D1 and the second forward voltage VF2 of the second rectifier element D2, and is about 2.3V. Can be set.

  2. The turn-on voltage Vt of the thyristor 11 is equal to the sum of the forward voltage (VF1 + VF2) of the rectifier circuit 12 and the forward voltage VF3 of the pn junction between the anode A of the thyristor 11 and the second gate G2, for example, about 1V. It can be set to about 3V.

  FIG. 2 schematically shows the relationship between the breakdown voltage Vesd of the gate oxide film of the MOS transistor, the burn-in test voltage Vbin, and the turn-on voltage Vt that can be set by the thyristor 11 as compared with the conventional example. The white circle a is according to the present embodiment, and the black circle b is according to the conventional example.

As is apparent from FIG. 2, in this embodiment, since one n-type MOS transistor M1 and two pn junction diodes 13 are combined, the breakdown voltage Vesd of the gate oxide film of the MOS transistor is lower than, for example, 3.5V. Further, a turn-on voltage Vt, for example, 3.3V, higher than the burn-in test voltage Vbin, for example, 3V is obtained.
Therefore, it is possible to finely set the turn-on voltage Vt in accordance with various restrictions determined by the specifications of the semiconductor device.

  On the other hand, since the conventional electrostatic protection circuit is a combination of two pn junction diodes 13, the turn-on voltage Vt is 3 V, for example, which is lower than the breakdown voltage Vesd of the gate oxide film of the MOS transistor and higher than the burn-in test voltage Vbin. The voltage cannot be set.

  FIG. 3 is a cross-sectional view showing a semiconductor integrated device in which the electrostatic protection circuit 10 is integrated on a semiconductor substrate. As shown in FIG. 3, in the semiconductor integrated device 20 of this embodiment, the first element formation region A in which the thyristor 11 is formed and the n-type MOS transistor M1 are formed in the main surface of the p-type silicon substrate 21. A second element formation region B and a third element formation region (not shown) in which a second rectifier element D2 in which two pn junction diodes 13 are connected in series in the forward direction are formed.

  The first element formation region A is in contact with the n-type first well region 22 where the pnp-type transistor Q1 is equivalently formed and the p-type second well region 23 where the npn-type transistor Q2 is equivalently formed. Is formed. A p-type third well region 24 is formed in the second element formation region B.

  The n-type first well region 22 includes a p-type first diffusion layer 25, an n-type second diffusion layer 27 facing the p-type first diffusion layer 25 by Shallow Trench Isolation (hereinafter referred to as STI) 26. Is formed. A part of the n-type second diffusion layer 27 is formed extending to the p-type third well region 24.

  In the p-type second well region 23, a p-type third diffusion layer 28 and an n-type fourth diffusion layer 30 that is spaced apart from the p-type third diffusion layer 28 by the STI 29 are formed. The n-type fourth diffusion layer 30 is opposed to the p-type first diffusion layer 25 by the STI 31.

  As a result, the p-type first diffusion layer 25, the n-type first well 22, and the p-type second well 23 make the pnp-type transistor Q1, the n-type first well 22, the p-type second well 23, and the n-type fourth diffusion. The layer 30 constitutes the npn-type transistor Q2 equivalently, and the thyristor 11 having the p-type first diffusion layer 25 as the anode A and the n-type fourth diffusion layer 30 as the cathode K is formed.

  The p-type first diffusion layer 25 of the anode A is connected to the first terminal P1, and the n-type fourth diffusion layer 30 of the cathode K is connected to the second terminal P2. The p-type second well 23 of the first gate G1 is connected to the n-type fourth diffusion layer 30 of the cathode K via the series resistance R1 of the p-type second well 23.

  The p-type third well region 24 includes an n-type fifth diffusion layer 32 that faces the n-type second diffusion layer 27 while being spaced apart, and a p-type second diffusion layer 32 that faces the n-type fifth diffusion layer 32 by the STI 33. A gate electrode 35 is formed between the sixth diffusion layer 34, the n-type second diffusion layer 27, and the n-type fifth diffusion layer 32.

  Thus, an n-type MOS transistor M1 in which a part of the n-type second diffusion layer 27 is the drain d1, the n-type fifth diffusion layer 32 is the source s1, the gate electrode 35 is the gate g1, and the drain d1 and the gate g1 are connected. And the first rectifying element D1 is formed.

  The n-type fifth diffusion layer 32 is connected to the anode A2 of the second rectifying element D2, and the p-type sixth diffusion layer 34 is connected to the cathode K of the second rectifying element D2.

  FIG. 4 is a block diagram showing a semiconductor device using the electrostatic protection circuit 10, for example, a CMOS inverter device. The internal circuit is formed from the bipolar surge that has entered the power supply Vdd line and the bipolar surge that has entered the input terminal. It is an example of the semiconductor device to protect.

  As shown in FIG. 4, the semiconductor device 40 of this embodiment includes an internal terminal connected to a first terminal P1, for example, a positive power supply Vdd and a second terminal P2, for example, a negative power supply Vss, and a third terminal P3, for example, an input Vin. A circuit 41 is provided, and a parallel circuit of a first electrostatic protection circuit 42 and a third pn junction diode D3 is connected between the first terminal P1 and the second terminal P2.

  Further, a parallel circuit of the second electrostatic protection circuit 43 and the fourth pn junction diode D4 is connected between the first terminal P1 and the third terminal P3, and the third electrostatic protection circuit 44 and the fifth pn junction diode D5 are connected. A parallel circuit is connected between the third terminal P3 and the second terminal P2.

  The turn-on voltage of the first electrostatic protection circuit 42 is set to 3.3V, for example, and the turn-on voltage of the third pn junction diode D3 is set to 3V, for example.

  Thereby, when the surge that has entered the power supply Vdd line is positive, the internal circuit 41 is protected by the first electrostatic protection circuit 42, and when the surge is negative, the internal circuit 41 is protected by the third pn junction diode D3. Is done.

In the burn-in test, since only a positive high voltage is applied, the first electrostatic protection circuit 42 prevents latch-up and the internal circuit 41 is protected.
That is, in the burn-in test, since the third pn junction diode D3 is always reverse-biased with respect to the positive high voltage, it is not necessary to adjust the turn-on voltage.

  The second electrostatic protection circuit 43 and the fourth pn junction diode D4, and the third electrostatic protection circuit 44 and the fifth pn junction diode D5 are set to the same turn-on voltage as, for example, the first electrostatic protection circuit 42 and the third pn junction diode D3. Has been.

Thus, when the surge that has entered the input line is positive with respect to the second terminal P2, the internal circuit 41 is protected by the third electrostatic protection circuit 44, and when the surge is negative, the third pn junction diode D3 is protected. Thus, the internal circuit 41 is protected.
When the first terminal P1 is positive, the internal circuit 41 is protected by the fourth pn junction diode D4, and when the negative terminal is negative, the second electrostatic protection circuit 43 protects the internal circuit 41. .

In the burn-in test, only the positive high voltage with respect to the second terminal P2 is applied to the third terminal P3, so that the third electrostatic protection circuit 44 prevents latch-up and protects the internal circuit 41.
That is, since the third pn junction diode D3 and the fourth pn junction diode D4 are always reverse biased, it is not necessary to adjust the turn-on voltage.

  As described above, according to the first embodiment of the present invention, since the first and second rectifying elements D1 and D2 having different forward voltages are connected in series in the forward direction, the turn-on voltage Vt of the thyristor is set to the first and second rectifiers. It can be adjusted by a combination of steps corresponding to the two forward voltages VF1 and VF2.

  Therefore, since the turn-on voltage of the thyristor can be finely set in accordance with the specifications of the semiconductor device, an electrostatic protection circuit having a sufficient protection voltage against both surge and latch-up can be obtained. As a result, a highly integrated semiconductor device with high integration and low voltage driving can be provided.

  Although the case where the first rectifier element D1 has one n-type MOS transistor M1 and the second rectifier element D2 has two pn junction diodes 13 has been described here, a range in which a predetermined turn-on voltage can be obtained. Thus, the n-type MOS transistor M1 and the pn junction diode 13 may be appropriately provided.

  For example, the first rectifying element D1 may include four n-type MOS transistors M1, and the second rectifying element D2 may be the rectifying circuit 12 including one pn junction diode 13. According to this, 3.2 V is obtained as the turn-on voltage Vt of the thyristor 11.

  In addition, the case where the anode A1 of the first rectifier element D1 is connected to the second gate G2 and the cathode K2 of the second rectifier element D2 is connected to the cathode K of the thyristor 11 has been described, but the first and second diodes D1, The connection order of D2 may be changed.

  That is, the anode A2 of the second rectifying element D2 may be connected to the second gate G2, and the cathode K1 of the first rectifying element D1 may be connected to the cathode K of the thyristor 11.

  Furthermore, although the case where the internal circuit is a CMOS inverter has been described, an internal circuit having any configuration having a MOS transistor may be used. Further, the third terminal P3 may be an output terminal.

  Although the case where the resistor R1 is connected between the first gate G1 and the second terminal P2 has been described, the resistor R1 may not be connected.

  FIG. 5 is a circuit diagram showing an electrostatic protection circuit according to Embodiment 2 of the present invention. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof is omitted, and only different portions are described.

  The present embodiment is different from the first embodiment in that a rectifier circuit is connected between the first terminal and the first gate of the thyristor.

That is, as shown in FIG. 5, in the electrostatic protection circuit 50 of this embodiment, the anode A is connected to the first terminal P1, and the cathode K is connected to the second terminal P2, which is electrically insulated from the first terminal P1. The thyristor 51 connected to the first terminal P1 via the resistor R2 and the anode A2 of the second rectifier element D2 are connected to the first terminal P1, and the cathode K1 of the first rectifier element D1. Has a rectifier circuit 52 connected to the first gate G1 of the thyristor 51.
The first rectifier element D1 includes a p-type MOS transistor M2 having a gate g2 connected to the source s2.

  FIG. 6 is a cross-sectional view showing a semiconductor integrated device in which the electrostatic protection circuit 50 is integrated on a semiconductor substrate. As shown in FIG. 6, in the semiconductor integrated device 60 of the present embodiment, a first element formation region A in which a thyristor 51 is formed and a p-type MOS transistor M2 are formed in the main surface of an n-type silicon substrate 61. An element formation region C and a third element formation region (not shown) are formed in which a second rectifier element D2 in which two pn junction diodes 13 are connected in series in the forward direction is formed.

  An n-type fourth well region 64 is formed in the second element formation region C, and the p-type seventh diffusion layer is opposed to the extended p-type third diffusion layer 28 in the n-type fourth well region 64. 72, an n-type eighth diffusion layer 74 that is opposed to the p-type seventh diffusion layer 72 by the STI 73, and a gate electrode 75 between the p-type third diffusion layer 28 and the p-type seventh diffusion layer 72. Is formed.

  Thus, a part of the p-type third diffusion layer 28 is the drain d2, the p-type seventh diffusion layer 72 is the source s2, the gate electrode 75 is the gate g2, and the p-type MOS transistor M2 is connected to the drain d2 and the gate g2. And the first rectifying element D1 is formed.

  The p-type first diffusion layer 25 and the n-type second diffusion layer 27 are each connected to the first terminal P1, the n-type fourth diffusion layer 30 is connected to the second terminal P2, and the p-type seventh diffusion layer 72 is the first It is connected to the cathode K2 of the two rectifier element D2.

  As described above, according to the second embodiment of the present invention, the turn-on voltage of the thyristor 11 can be finely set in accordance with the specifications of the semiconductor device, and the electrostatic protection of the semiconductor device using the n-type silicon substrate is possible. Suitable as a circuit.

  Here, the case where the anode A2 of the second rectifier element D2 is connected to the anode A of the thyristor 11 and the cathode K1 of the first rectifier element D1 is connected to the first gate G1 of the thyristor 11 has been described. The connection order of the two diodes D1 and D2 may be switched.

  That is, the anode A1 of the first rectifier element D1 may be connected to the anode A of the thyristor 11, and the cathode K2 of the second rectifier element D2 may be connected to the first gate G1 of the thyristor 11.

In the above-described embodiments, the case where the first rectifying element D1 is a diode-connected MOS transistor and the second rectifying element is a pn junction diode has been described. However, the present invention is not limited to this, and a predetermined turn-on voltage is used. May be another rectifying element such as a Schottky diode or a bipolar transistor having a base connected to the collector.
In the case of a Schottky diode, an even lower forward voltage, for example, about 0.2 V can be obtained. Therefore, there is an advantage that the turn-on voltage can be set more finely.

1 is a circuit diagram showing an electrostatic protection circuit according to Embodiment 1 of the present invention. The figure which shows the relationship between the rectifier circuit which concerns on Example 1 of this invention, and the turn-on voltage of a thyristor. Sectional drawing which shows the structure of the semiconductor integrated device which concerns on Example 1 of this invention. 1 is a block diagram showing a configuration of a semiconductor device according to Embodiment 1 of the present invention. The circuit diagram which shows the electrostatic protection circuit which concerns on Example 2 of this invention. Sectional drawing which shows the structure of the semiconductor integrated device which concerns on Example 2 of this invention.

Explanation of symbols

10, 50 Static protection circuit 11, 51 Thyristor 12, 52 Rectifier circuit 13 Pn junction diode 20, 60 Semiconductor integrated device 21 P-type silicon substrate 22 n-type first well region 23 p-type second well region 24 p-type third Well region 25 p-type first diffusion layers 26, 29, 31, 33, 73 STI (shallow Trench Isolation)
27 n-type second diffusion layer 28 p-type third diffusion layer 30 n-type fourth diffusion layer 32 n-type fifth diffusion layer 34 p-type sixth diffusion layers 35 and 75 gate electrode 41 internal circuit 42 first electrostatic protection circuit 43 Second electrostatic protection circuit 44 Third electrostatic protection circuit 61 n-type silicon substrate 64 n-type fourth well region 72 p-type seventh diffusion layer 74 n-type eighth diffusion layer P1 first terminal P2 second terminal P3 second 3 terminal D1 1st rectifier element D2 2nd rectifier element D3 3rd diode D4 4th diode D5 5th diode M1 n-type MOS transistor M2 p-type MOS transistor Q1 pnp-type transistor Q2 npn-type transistors R1, R2 resistance

Claims (5)

A first terminal to which a predetermined potential is applied;
A second terminal to which a potential lower than the predetermined potential is applied;
A thyristor having an anode, a cathode, a first and a second gate, the anode connected to the first terminal, and the cathode connected to the second terminal;
A first rectifier element having a first forward voltage and a second rectifier element having a second forward voltage different from the first forward voltage are connected in series in the forward direction, and the second gate of the thyristor And a rectifier circuit in which the anode of one of the rectifier elements is connected, and the cathode of the other rectifier element is connected to the cathode of the thyristor. A first terminal to which a predetermined potential is applied;
A second terminal to which a potential lower than the predetermined potential is applied;
A thyristor having an anode, a cathode, a first and a second gate, the anode connected to the first terminal, and the cathode connected to the second terminal;
A first rectifier element having a first forward voltage and a second rectifier element having a second forward voltage different from the first forward voltage are connected in series in the forward direction, and the first gate of the thyristor And a rectifier circuit in which the cathode of one of the rectifying elements is connected, and the anode of the other rectifying element is connected to the anode of the thyristor. A semiconductor substrate;
A first terminal formed on a main surface of the semiconductor substrate and applied with a predetermined potential;
A second terminal to which a potential lower than the predetermined potential is applied;
A p-type first diffusion layer and an n-type second diffusion layer facing and spaced apart from the first diffusion layer are formed in an n-type first well region formed on the main surface of the semiconductor substrate, and the first well A p-type third diffusion layer and an n-type fourth diffusion layer facing and spaced apart from the third diffusion layer are formed in a p-type second well region adjacent to one side of the region, and the first diffusion layer is A thyristor connected to the first terminal, wherein the third and fourth diffusion layers are each connected to the second terminal;
A first rectifier element formed in a p-type third well region adjacent to the other side of the first well region, and having an n-type MOS transistor in which the second diffusion layer is a drain and the drain and the gate are connected;
A semiconductor integrated device comprising: a second rectifier element formed on a main surface of the semiconductor substrate, having an anode connected to a source of the MOS transistor, and a cathode connected to the second terminal. A semiconductor substrate;
A first terminal formed on a main surface of the semiconductor substrate and applied with a predetermined potential;
A second terminal to which a potential lower than the predetermined potential is applied;
In the p-type second well region formed in the first element formation region, a p-type third diffusion layer and an n-type fourth diffusion layer spaced apart and opposed to the third diffusion layer are formed, and the second well A p-type first diffusion layer and an n-type second diffusion layer facing and spaced apart from the first diffusion layer are formed in an n-type first well region adjacent to one side of the region, and the fourth diffusion layer is A thyristor connected to a second terminal, wherein the first and second diffusion layers are each connected to the first terminal;
A first rectifying element formed in an n-type fourth well region adjacent to the other side of the second well region and having a p-type MOS transistor having the third diffusion layer as a drain and the drain and gate connected to each other;
A semiconductor integrated device comprising: a second rectifier element formed on a main surface of the semiconductor substrate, having an anode connected to the first terminal and a cathode connected to a source of the MOS transistor.   The second rectifier element includes at least one of a pn junction diode, a Schottky barrier diode, a MOS transistor having a gate connected to a drain, or a bipolar transistor having a base connected to a collector. The semiconductor integrated device according to claim 4.

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