JP2006120706A - Semiconductor device and driving method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is capable of causing a great change in the resistance of a variable resistance layer by a few times of voltage pulse application and shows high working speed, and also provide a driving method for the semiconductor device. <P>SOLUTION: A variable resistance element unit 100 consists of a first electrode 111 and a variable resistance layer 120 which are overlaid in this order on one main surface of the board 10, and a second electrode 112 overlaid on a part of the main surface of the variable resistance layer 120. By applying a voltage pulse to the first and second electrodes 111, 112 sandwiching the variable resistance layer 120 in the variable resistance element unit 100, carriers are injected into the variable resistance layer 120, whose resistance increases in response to the carrier injection by three or more orders of magnitude. The injected carriers have a current density of 10<SP>4</SP>A/cm<SP>2</SP>or higher. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a driving method thereof, and more particularly to a device including an element portion having a variable resistance layer made of a material having a perovskite structure.

  The magnetoresistive effect in which the resistance is changed by applying a magnetic field is often seen in transition metal oxides having a perovskite structure, and the application of these materials to electronic devices has been actively studied. However, many electronic devices have technical barriers such as generation and control of magnetic fields for resistance control and avoidance of mutual magnetic field interference between resistive elements, and the practical use of electronic devices that can overcome these technical problems Is desired.

  On the other hand, many transition metal oxides having a perovskite structure undergo a metal phase-insulation phase transition (Mott transition), and the metal phase-insulation phase transition is caused not only by a magnetic field but also by an electric field, stress, temperature, and the like. For example, an attempt is made to change the resistance by directly applying an electric field to the material (see, for example, Non-Patent Document 1 and Non-Patent Document 2). In the techniques according to these documents, it is considered that a mechanism that makes an orderly d electron omnipresent by applying an electric field in an insulating phase that appears at an extremely low temperature (−150 ° C. or less) is used. However, in the examples according to these documents, since the occurrence of such a resistance change by an electric field is limited to a temperature region extremely lower than room temperature, it can be said that it is a big problem in application to an electronic device.

On the other hand, experiments have been reported in which a voltage pulse is applied to a material having a specific perovskite structure at room temperature to try to change its resistance (see, for example, Non-Patent Document 3, Non-Patent Document 4, and Patent Document 1). ). As materials which have been tried to be used in these documents, there are perovskite oxides containing Mn ions, and there are materials represented by the composition formula of R _(1-X) A _X MnO ₃ . Here, R is a trivalent rare earth ion such as La ³⁺ , Pr ³⁺ , or Nd ³⁺ , and A is a divalent alkaline earth ion such as Ca ²⁺ , Sr ²⁺ , or Ba ^2+. .

  In these specific materials, perovskite materials that are in a low resistance state (metal phase) at room temperature have the characteristic behavior of transitioning to a high resistance state (insulating phase) when a voltage pulse is applied. This causes a phenomenon that is clearly different from the transition to the metal phase due to the electric field of the insulating phase at low temperature. When a variable resistance switching element is to be formed using a material having such a specific perovskite structure, for example, a configuration as shown in FIG. 9 can be employed (Patent Document 1).

As shown in FIG. 9, the variable resistance switch element in the literature has a first electrode 511 and a variable resistance layer 520 stacked in this order on one main surface of a substrate 510, and on the main surface of the variable resistance layer 520. A second electrode 512 is stacked in a partial region. The variable resistance layer 520 is formed with a layer thickness of 600 nm using a material having a perovskite structure, for example, a Pr _0.7 Ca _0.3 MnO ₃ (hereinafter referred to as “PCMO”) material. In addition, a driving circuit capable of applying a voltage pulse is connected to the first electrode 511 and the second electrode 512.

  In this variable resistance type switching element, the resistance value of the variable resistance layer 520 is in a low resistance state of several tens of Ω when no voltage pulse is applied. Here, between the first electrode 511 and the second electrode 512, a voltage of 31 V and a pulse width of 71 nsec. When the voltage pulse is applied a plurality of times, the resistance value of the variable resistance layer 520 is increased about 100 times (two digits) with respect to the low resistance state by applying several tens of pulses. In this way, in the variable resistance switch element, the variable resistance layer 520 shifts to the high resistance state by application of the voltage pulse. Further, in such a variable resistance type switching element, the thickness of the variable resistance layer 520, the amplitude and pulse width of the voltage pulse to be applied, and the number of application times of the voltage pulse are adjusted, so that it can It is possible to obtain a resistance value change of 3 digits to 4 digits. In order to increase the resistance value of the variable resistance layer 520, it is necessary to apply an electric field of at least 105 V / cm.

For example, when the variable resistance type switching element as described above is applied to a memory device, generally, the resistance value between the low resistance state and the high resistance state of one variable resistance type switching element is reduced. The higher the ratio, the better. As an example, when a plurality of variable resistance switch elements are connected to one bit line row, the number of junction points with the bit line is required by the number of variable resistance switch elements, and the number of variable resistance switch elements per bit line is required. As the number of connections increases, junction leakage increases. In order to clearly distinguish between this junction leakage and the current flowing through the selected variable resistance switch element, in the case of a large capacity memory device, the variable resistance switch element has a low resistance state and a high resistance state. It is desirable to set the ratio of resistance values at 3 digits or more.
US Pat. No. 6,204,139 A. Asamitsu et al., Nature 388, p. p. 50-52 (1997) H. Ohno et al., Nature 408, p. p.944-946 (2000) S. Q. Liu et al., Applied Physics Letters 76, p. p.2749-2751 W. W. Zhang et al., IEEE Technical Digest of International Electron Devices Meeting 2002, p. p.193-196

However, in the above prior art, even if an electric field of 10 ⁵ V / cm or more is applied to the variable resistance layer 520, a large resistance change cannot always be caused, but it is induced by application of a single voltage pulse. The resistance change is at most an order of magnitude. Therefore, in the conventional variable resistance switch element, it is necessary to apply a plurality of voltage pulses in order to change the resistance value in the variable resistance layer 520 by three digits or more. Thus, when a semiconductor device such as a large-capacity memory device is configured using a variable resistance switching element that requires the application of a plurality of voltage pulses, the program time of the device is extended and the operating speed is increased. Has the problem of becoming low.

  The present invention has been made to solve such a problem, and it is possible to cause a large resistance value change in the variable resistance layer even by applying a voltage pulse with a small number of times. An object is to provide a fast semiconductor device and a driving method thereof.

In order to solve the above problems, a semiconductor device according to the present invention has the following characteristics.
(1) A semiconductor device according to the present invention is made of a material having a perovskite structure, and includes a variable resistance layer whose electrical characteristics change due to a change in electric field, and a drive unit that causes a change in electrical resistance in the variable resistance layer. The drive unit has carrier injection means for injecting carriers into the variable resistance layer and increasing the resistance of the variable resistance layer.

(2) The semiconductor device according to (1) is characterized in that, when driven, the density of carriers injected into the variable resistance layer by the carrier injection means is 10 ⁴ A / cm ² or more in terms of current density. To do.
(3) The semiconductor device according to (1) or (2) is characterized in that the electrical resistance value of one main surface and its vicinity in the variable resistance layer is changed by carrier injection.

(4) In the semiconductor device according to the above (1) to (3), the variable resistance layer has the first electrode and the second electrode connected to both main surfaces, respectively, and the drive unit includes the variable resistance The carrier is injected by applying a voltage to the layer through the first and second electrodes.
(5) In the semiconductor device according to (4), the driving unit includes carrier extracting means for extracting carriers from the variable resistance layer and reducing the resistance of the variable resistance layer.

(6) In the semiconductor device according to (5), the driving unit performs carrier extraction by applying a voltage having a polarity opposite to that of carrier injection to the variable resistance layer. And
(7) In the semiconductor device according to (4) to (6), the first electrode and the second electrode have different sizes and are connected to the variable resistance layer. .

(8) In the semiconductor device according to (7) above, when carriers are injected into the variable resistance layer, the region near the portion where the smaller size electrode is connected is increased in resistance. And
(9) In the semiconductor device according to the above (4) to (8), the semiconductor device includes a substrate and an insulating layer formed on the substrate, and the first electrode is formed in the thickness direction from the surface of the insulating layer. The variable resistance layer has a connection state with the first electrode and is laminated on the surface of the insulating layer, and the second electrode has a variable resistance. It is characterized by being laminated on the surface of the layer.

  (10) In the semiconductor device according to the above (4) to (9), a unit switch element is formed by a pair of first electrode and second electrode, and a variable resistance layer sandwiched between the two electrodes, One of the first electrode and the second electrode in the switch element is connected to the plate line, the other is connected to the bit line via the selection transistor element section, and the gate electrode of the selection transistor element section is connected to the word line It is characterized by being connected.

(11) In the semiconductor device according to (1) to (11), the variable resistance layer is made of a material represented by a chemical composition formula A _X A ′ _(1-X) B _Y O _Z . Here, in the above chemical composition formula, A, A ′, B, O and X, Y, and Z are defined as follows.
* A: At least one element selected from the group consisting of La, Ce, Bi, Pr, Nd, Pm, Sm, Y, Sc, Yb, Lu, Gd * A ': Mg, Ca , Sr, Ba, Pb, Zn, Cd, at least one element selected from the group consisting of elements * B; Mn, Ce, V, Fe, Co, Nb, Ta, Cr, Mo, W, At least one element selected from the group consisting of Zr, Hf, and Ni * 0 ≦ X ≦ 1
* 0 ≦ Y ≦ 2
* 1 ≦ Z ≦ 7
The method for driving a semiconductor device according to the present invention has the following characteristics.

(12) A driving method of a semiconductor device according to the present invention is a driving method for causing a change in electrical characteristics by a change in an electric field with respect to a variable resistance layer made of a material having a perovskite structure. In order to cause a change in resistance, carriers are injected.
(13) The method for driving a semiconductor device according to (12) is characterized in that the density of carriers injected into the variable resistance layer is 10 ⁴ A / cm ² or more in terms of current density.

(14) The method for driving a semiconductor device according to (12) or (13) is characterized in that the resistance is locally increased by injecting carriers into the variable resistance layer.
(15) In the method for driving a semiconductor device according to (12) to (14), the first and second electrodes are connected to both main surfaces of the variable resistance layer. Carrier injection is performed by applying a voltage via the first and second electrodes, and one of the first and second electrodes in the variable resistance layer is connected by carrier injection. High resistance is achieved in the vicinity of the portion.

(16) In the method for driving a semiconductor device according to (15), by extracting carriers from the variable resistance layer, the resistance of the variable resistance layer in which the resistance is increased can be reduced. It is characterized by.
(17) In the method for driving a semiconductor device according to (16) above, the carrier extraction is performed by applying a voltage having a polarity opposite to that at the time of carrier injection to the first and second electrodes. It is characterized by that.

  The semiconductor device and the driving method thereof according to the present invention are characterized in that the driving unit has carrier injection means as described in the above (1) and (12). The resistance value can be controlled by the injection amount. Therefore, in the semiconductor device according to the present invention, the voltage pulse waveform and the element structure are set so that carriers can be injected into the variable resistance layer at a desired density, so that even a single voltage pulse can be applied. It becomes possible to change the resistance value of the resistance layer by three digits or more.

Therefore, the semiconductor device and the driving method thereof according to the present invention can cause a large change in resistance value in the variable resistance layer even by applying a voltage pulse with a small number of times, and have an advantage of high operating speed. Have. In particular, when the density of injected carriers is 10 ⁴ A / cm ² as the current density as in (2) and (13) above, the resistance value of the variable resistance layer can be obtained by applying a single voltage pulse. Can be changed by three digits or more, which is effective for fulfilling the switching function and can be applied to a memory device or the like.

  Further, in the semiconductor device and the driving method thereof according to the present invention, as shown in the above (3) and (14), the variable resistance layer in the variable resistance layer is set to one main surface and the vicinity thereof to be localized. Thus, it is possible to shorten the time required for changing the resistance value in the variable resistance layer. For this reason, by doing so, the semiconductor device and the driving method thereof according to the present invention have a switching function with a high operating speed.

  As a specific example of carrier injection into the variable resistance layer, as described in (4) and (15) above, the first and second electrodes are connected to the variable resistance layer, and a voltage is applied via this electrode. A configuration and a method of applying a pulse can be employed. By applying voltage pulses and injecting carriers in this way, it is possible to adjust the injected carrier density by controlling the amplitude and time of the applied voltage pulse, and the resistance change at high accuracy and high speed. It becomes possible to make.

  Further, in the semiconductor device and the driving method thereof according to the present invention, as described in the above (5) and (16), the carrier is pulled out from the variable resistance layer that has been brought into the high resistance state by the carrier injection, thereby reducing the speed at a high speed. It becomes possible to change to a resistance state. In particular, in the semiconductor device and the driving method thereof according to the present invention, as described in the above (6) and (17), a voltage pulse having a characteristic opposite to that at the time of carrier injection is applied to the first and second electrodes. Switching operation at a high speed is possible.

In the semiconductor device according to the present invention, as described in (7) and (8) above, the first and second electrodes connected to the variable resistance layer are set so that their connection sizes are different from each other. This is suitable for making the resistance change region local.
Further, as described in (9) above, the semiconductor device according to the present invention has a configuration in which the first electrode is formed by embedding an electrode material in a hole (via hole or contact hole) provided in the insulating layer on the substrate. By adopting it, it is possible to narrow a gap between other circuit element portions, for example, a field effect transistor element portion, and it becomes easy to reduce the size of the device.

  As an application example of the semiconductor device capable of such a high-speed switching operation, there is a memory device constituted by a combination of the selection transistor as described in (10) and the variable resistance element portion.

(Basic principle)
First, the basic principle of the present invention will be described with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing the main configuration of a variable resistance element model 1 for explaining the basic principle of a semiconductor device according to the present invention.
As shown in FIG. 1, in the variable resistance element model 1, a first electrode 11 and a variable resistance layer 20 are sequentially stacked on one main surface of a substrate 10, and are connected to each other on the surface of the variable resistance layer 20. The second electrode 12a, the third electrode 12b, the fourth electrode 12c, and the fifth electrode 12d having different sizes are laminated. The second electrode 12a, the third electrode 12b, the fourth electrode 12c, and the fifth electrode 12d on the main surface of the variable resistance layer 20 are joined to the variable resistance layer 20 with different areas, respectively, They are formed with a gap between them.

  In the above configuration, the first electrode 11 is a layered electrode having a thickness of 200 nm formed from the material Pt using a sputtering method. The variable resistance layer 20 is formed by depositing a PCMO material with a thickness of 100 nm formed on the first electrode 11 using a pulsed laser deposition (PLD) method. In addition, each of the second electrode 12a, the third electrode 12b, the fourth electrode 12c, and the fifth electrode 12d is an electrode having a thickness of 200 nm formed of a material Pt using a sputtering method. The area and shape of each of the electrodes 12a, 12b, 12c, and 12d are defined by a photo resist mask, and are formed and processed using an ion milling method.

  As shown in FIG. 1, the electrodes 12a, 12b, 12c, and 12d on the main surface of the variable resistance layer 20 have four types of dot patterns, φA (= φ120 μm), φB (= φ60 μm), and φC ( = Φ30 μm) and φD (= φ10 μm). Although not shown, a drive circuit for applying a voltage pulse is connected between the first electrode 11, the second electrode 12a, the third electrode 12b, the fourth electrode 12c, and the fifth electrode 12d. Has been.

  Here, between the first electrode 11 and the second electrode 12a, the third electrode 12b, the fourth electrode 12c, and the fifth electrode 12d sandwiching the variable resistance layer 20, the amplitude is 5 V and the pulse width is 50 nsec. FIG. 2 shows a relative change in the resistance value in the variable resistance layer 20 between each electrode pair at that time. In FIG. 2, Rmin represents a resistance value before the voltage pulse is applied, Rmax represents a resistance value after the voltage pulse is applied, and the degree of relative change in the resistance value is indicated by ((Rmax−Rmin) / Rmin). As evaluated.

  As shown in FIG. 2, although the same voltage pulse is applied to each electrode pair, the relative change in the resistance value of the variable resistance layer 20 is caused by the electrodes 12a, 12b, 12c, 12d with respect to the variable resistance layer 20. Depends on the connection size (diameter). When a voltage pulse is applied between the fifth electrode 12d and the first electrode 11 having a diameter φD = 10 μm, the variable resistance layer 20 shows an increase in resistance value of three digits or more. As described below, the electrode size dependency of the change in the resistance value is caused by the reduction in the connection size of the electrodes 12a, 12b, 12c, and 12d on one main surface of the variable resistance layer 20. As a result, the electric field concentration near the electrode connection portion in the variable resistance layer 20 increases. As a result, it can be interpreted that the current density in the vicinity of the connection portion of the electrodes 12a, 12b, 12c, and 12d on the main surface of the variable resistance layer 20 exceeds a certain threshold. This will be described with reference to FIG.

  FIG. 3A shows a variable resistance element model as a comparative example. The first electrode 11 and the second electrode 12e are joined to the variable resistance layer 20 with substantially the same size. The second electrode 12 e is formed with a sufficiently large area with respect to the thickness of the variable resistance layer 20. On the other hand, FIG. 3B shows a variable resistance element model as an example. The first electrode 11 is a flat plate and has an area substantially equal to the main surface of the variable resistance layer 20. This is a model when the electrode 12f is considered as a needle-like point contact electrode having no electrode area.

As shown in FIG. 3A, when the dimension in the surface direction of each of the first electrode 11 and the second electrode 12e is sufficiently larger than the thickness of the variable resistance layer 20, the first electrode 11 and the second electrode 12e The electric field distribution between can ideally be approximated as that between parallel plates. Here, when the voltage applied between the first electrode 11 and the second electrode 12e is V (V) and the thickness of the variable resistance layer 20 is d (cm), the first electrode 11 and the second electrode 12e. It is considered that the electric field E (V / cm) between and V is uniformly V / d everywhere in the variable resistance layer 20. When the thickness of the variable resistance layer 20 is 100 nm, a uniform electric field strength of 10 ⁵ V / cm can be obtained by applying a voltage of 5V. Therefore, when the resistivity of the variable resistance layer 20 in the low resistance state is σ _m (Ω · cm), the current density j between the first electrode 11 and the second electrode 12e is within the variable resistance layer 20 layer. The current density j is uniform in an arbitrary place, and is expressed by the following equation.
(Equation 1) j = E / σ _m (A / cm ² )
On the other hand, in the variable resistance element model according to the embodiment shown in FIG. 3B, a mirror image potential having the first electrode 11 as a mirror surface is formed between the first electrode 11 and the second electrode 12f. At this time, the electric lines of force from the second electrode 12f to the first electrode 11 are isotropic as shown in FIG. 3B, and if the distance from the second electrode 12f to the first electrode 11 is r. The electric field E between the first electrode 11 and the second electrode 12f is defined only by the distance r regardless of the direction. That is, the electric field E at a position separated from the second electrode 12f by the distance r is represented by V / r. Therefore, in the variable resistance element model according to the example, the electric field in the vicinity of the second electrode 12f having a very small distance r is several orders of magnitude stronger than that between the parallel plates in the element model according to the comparative example. sell. As a result, the current density in the vicinity of the second electrode 12f can be several orders of magnitude larger than the variable resistance element model according to the comparative example based on the above equation. This effect is considered to become more prominent as the horizontal dimension of the second electrode 12 f approaches the thickness of the variable resistance layer 20.

  Further, the above experimental results give new important knowledge about the process of resistance change of the variable resistance layer 20. That is, as apparent from the examination using the element model, when a voltage pulse having a constant amplitude and a pulse width is applied between the first electrode 11 and the second electrode 12f sandwiching the variable resistance layer 20, The current density in the vicinity of the second electrode 12f increases remarkably as the junction area of the second electrode 12f with respect to the variable resistance layer 20 decreases, but the current density in the vicinity of the first electrode 11 which is a flat plate is a parallel plate. The current density flowing between the electrode pairs is not exceeded. Therefore, it can be considered that the increase in the resistance value of three digits or more when the fifth electrode 12d having the diameter φ = 10 μm in FIGS. 1 and 2 is used is generated only in the vicinity of the fifth electrode 12d having a high current density. It is reasonable.

  From these matters, in order to make the variable resistance layer 20 of the variable resistance element model transition from the low resistance state to the high resistance state, whichever of the two electrodes that are opposed and connected with the variable resistance layer 20 interposed therebetween is selected. Only the vicinity of one of the connection portions needs to be in a high resistance state. Therefore, in order to investigate the contribution of the current density to the resistance change of the variable resistance layer 20, the inventors of the present application set the connection dimension of the electrode on the main surface of the variable resistance layer 20 as one electrode to be constant at 30 μm. While changing the amplitude in pairs, the pulse width is 50 nsec. When the voltage pulse of 1 was applied once, the relationship between the peak value of the current density flowing between the electrode pair and the relative change in the resistance value was examined. The result is shown in FIG.

As shown in FIG. 4, when the peak value of the current density flowing between the electrode pair exceeds 10 ⁴ A / cm ² , the resistance value increases rapidly, and the maximum value is 2 × 10 ⁴ A / cm ^2. Take. Furthermore, when trying to give a larger current density than that, the variable resistance layer 20 was destroyed. Therefore, it can be seen that in order to induce a resistance change of three orders of magnitude or more in the variable resistance layer 20, a current having a current density of 10 ⁴ A / cm ² or more should flow through the variable resistance layer 20.

The physical process of large resistance change in the variable resistance layer 20 as described above may be considered as follows. For example, when a PCMO material is used to form the variable resistance layer 20, trivalent ionized manganese Mn ³⁺ and tetravalent ionized manganese Mn ⁴⁺ are mixed in a ratio of about 2: 1 in the layer. is doing. In addition, three localized electrons and one conduction electron are coordinated to the d orbital of Mn ³⁺ , and three localized electrons are coordinated to the d orbital of Mn ⁴⁺ . At normal temperature, the conduction electrons of Mn ³⁺ can jump to Mn ⁴⁺ through an oxygen bond, and the manganese atom that has lost the conduction electrons is ionized to Mn ⁴⁺ and the conduction electrons of nearby Mn ³⁺ . Can accept. That is, Mn ⁴⁺ in the variable resistance layer 20 made of PCMO material plays the same role as an acceptor in a semiconductor.

Therefore, the variable resistance layer 20 made of the PCMO material is in a conductive state, that is, a low resistance state at room temperature. At this time, the carriers of the variable resistance layer 20 are conduction electrons associated with Mn ³⁺ . Here, even if a current is passed through the variable resistance layer 20, the variable resistance layer 20 is kept in a low resistance state if the current density is low enough not to exceed the ability to transfer conduction electrons from Mn ³⁺ to Mn ⁴⁺ . Can do. Flowing current through the variable resistance layer 20 may be considered as injecting electrons as carriers from the cathode.

Here, consider the process of injecting electrons at a current density that is high enough to exceed the ability to transfer conduction electrons from Mn ³⁺ to Mn ⁴⁺ . Such a current density is sufficient to make a high resistance state only in the vicinity of one of the two electrodes facing each other across the variable resistance layer 20 of the variable resistance element model. Also, this allows Mn ⁴⁺ in the region filled with high current density to receive all the excess conduction electrons and become all Mn ³⁺ . As a result, the manganese atoms in the region filled with high current density will be in a situation where they are all temporarily filled with Mn ³⁺ . Under this circumstance, the conduction electrons of Mn ³⁺ repel each other due to Coulomb repulsion, lose their itinerant nature and localize to each Mn ³⁺ ion. In this state, conduction electrons are frozen locally, specifically in the vicinity of an electrode having a high current density, and the region filled with such a high current density is transferred to the insulator phase. That is, the variable resistance layer 20 made of the PCMO material is in a high resistance state.

As described above, it is considered that the carrier injection density necessary to cause such a sufficient resistance change is 10 ⁴ A / cm ² or more in terms of current. At this time, since the electrostatic energy of the variable resistance layer 20 is increased by the excess carrier injection, the PCMO material constituting the variable resistance layer 20 spontaneously deforms the crystal in order to suppress this energy increase. There is a possibility. In this case, the high resistance state of the variable resistance layer 20 is relatively stable, and the crystal structure does not return to its original state unless energy exceeding this deformation is given to the system. Therefore, this property can also be used as a nonvolatile memory.

As described above, in order to return the variable resistance layer 20 in the high resistance state to the low resistance state, it is necessary to extract excess carriers localized in the high resistance region, specifically, electrons from this region. That's fine. For that purpose, a potential difference is given to the portion where the resistance is increased, and excess carriers are extracted. The larger this potential difference is, the higher the carrier extraction efficiency is. Therefore, the thinner the region where the resistance is increased, the better. As a result, the ratio of Mn ³⁺ to Mn ⁴⁺ can be returned to approximately 2: 1. As a result, the electrostatic energy due to excess carriers is removed, and the elastic energy is higher when the crystal structure of the PCMO material constituting the variable resistance layer 20 remains deformed. It becomes a resistance state.

In this case, as a means for extracting the carriers injected into the variable resistance layer 20 to the outside of the variable resistance layer 20, the carrier in the variable resistance layer 20 is used for one electrode provided on both main surfaces of the variable resistance layer 20. It is preferable to apply a voltage having a polarity opposite to that at the time of injection.
(Embodiment 1)
Hereinafter, the semiconductor device according to the first embodiment will be described with reference to FIG. 5. FIG. 5 is a schematic cross-sectional view showing the variable resistance element unit 100 in the semiconductor device according to the present embodiment.

  As shown in FIG. 5, in the variable resistance element unit 100 according to the present embodiment, a first electrode 111 and a variable resistance layer 120 are sequentially stacked on one main surface of the substrate 10. A second electrode 112 is laminated and formed in a partial region on the main surface. Among the constituent elements of the variable resistance element unit 100, the first electrode 111 is an electrode layer having a thickness of 200 nm formed from Pt using a sputtering method.

  The variable resistance layer 120, part of which is sandwiched between the first electrode 111 and the second electrode 112, is a 100 nm thick layer formed from a PCMO material using a pulsed laser deposition (PLD) method. . The second electrode 112 on the main surface of the variable resistance layer 120 is a 200 nm-thick electrode layer formed from Pt using a sputtering method in the same manner as the first electrode 111, and its diameter φ is set to 10 to 30 μm. ing.

In the variable resistance element unit 100 according to the present exemplary embodiment, for example, the diameter of the second electrode 112 is 10 μm, and the amplitude is applied to the electrode pair formed by the first electrode 111 and the second electrode 112 sandwiching the variable resistance layer 120. Is 5 V and the pulse width is 50 nsec. When a set voltage pulse is applied, as shown in FIG. 2, an increase in resistance value of three digits or more is realized. For example, the diameter φ of the second electrode 112 is set to 30 μm, and the pulse width is 50 nsec. Between the first electrode 111 and the second electrode 112 sandwiching the variable resistance layer 120. When the voltage pulse of 1 is applied once, the peak value of the current density flowing between the first electrode 111 and the second electrode 112 is set to 10 ⁴ A / cm ² or more, so that the resistance value is 3 digits or more. Increase is realized. The principle of increasing the resistance value is as described above.

  In addition, when a voltage having a polarity opposite to that of injecting carriers into the variable resistance layer 120 is applied between the first electrode 111 and the second electrode 112, the carriers injected into the variable resistance layer 120 are transferred at high speed. Can be pulled out of the variable resistance layer 120, and the variable resistance layer 120 is in a low resistance state. The principle of decreasing the resistance value in this case is also as described above. Therefore, in a semiconductor device including the variable resistance element unit 100 according to the present embodiment, a single voltage pulse waveform and element structure are set so that carriers injected into the variable resistance layer 120 have a desired density. Even with a voltage pulse, the resistance value of the variable resistance layer 120 can be greatly changed, and a switching operation at a high speed can be realized.

  Further, in the variable resistance element unit 100 shown in FIG. 5, the variable resistance layer 120 has a region in which the resistance value changes only in the vicinity of one surface thereof, so that the variable resistance layer 120 has a low resistance state and a high resistance state. The region changing between and is limited to a very small volume. Therefore, in the variable resistance element unit 100 according to the present embodiment, the time required for the variable resistance layer 120 to change between the low resistance state and the high resistance state can be shortened. A switching operation at a high speed can be realized. A specific region in which the resistance change in the variable resistance layer 120 occurs is a junction size (area) when the first electrode 111 and the second electrode 112 have a connection size relationship to the variable resistance layer 120 as shown in FIG. ) Is a portion where the second electrode 112 is connected and a region in the vicinity thereof. This is because electric field concentration occurs in this region.

In the variable resistance element unit 100 according to the present embodiment, the diameter φ of the second electrode 112 is 10 to 30 μm, but the value of the current density flowing between the first electrode 111 and the second electrode 112 is 10 If it can be ⁴ A / cm ² or more, it can be appropriately changed accordingly, and is not limited to the above numerical range.
(Embodiment 2)
Next, a semiconductor device according to the second embodiment will be described with reference to FIGS. FIG. 6 is a cross-sectional view of a main part including a memory element 200 included in the semiconductor device according to the present embodiment, and FIG. 7 is an equivalent circuit diagram thereof.

  As shown in FIG. 6, the memory element 200 according to the present embodiment includes, for example, an insulating layer 230 made of silicon oxide or the like on a main surface of a substrate 210 made of a semiconductor material such as silicon, and a perovskite structure such as a PCMO material. A variable resistance layer 220 made of a transition metal material having a first electrode 211 made of Pt, Ir, or the like is sequentially stacked. In the memory element 200, the source electrode 242 and the drain electrode 243 are formed at two locations from the interface between the substrate 210 and the insulating layer 230 inward in the thickness direction of the substrate 210. Each of the source electrode 242 and the drain electrode 243 is formed by doping an impurity region in a corresponding region on the surface of the substrate 210.

The variable resistance layer 220 uses an organic metal solution as a starting material, spin coating, drying, and firing the organic metal deposition (MOD) method, a sputtering method using a target made of substantially the same material, or a laser ablation method. Can be formed.
A gate electrode 241 made of, for example, a material such as polysilicon is provided at a position located in the middle of the source electrode 242 and the drain electrode 243 in the insulating layer 230. The gate electrode 241, the source electrode 242, the drain electrode 243, and a part of the insulating layer 230 sandwiched therebetween form a field effect type select transistor 240. Of the three electrodes 241, 242, and 243 in the select transistor portion 240, the gate electrode 241 is connected to the word line WL (see FIG. 7), and the drain electrode 243 is connected to the bit line BL (see FIG. 7). (See FIG. 7).

  A second electrode 212 is provided on the insulating layer 230 so as to connect the source electrode 242 of the selection transistor portion 240 and the variable resistance layer 220. The second electrode 212 is formed by providing a contact hole at a corresponding position in the insulating layer 230 and filling the contact hole with an electrode material made of, for example, W or polysilicon. The second electrode 212 connects the source electrode 242 and the variable resistance layer 220 in the selection transistor 240. As described above, in the memory element 200, the variable resistance element portion 250 is formed by the variable resistance layer 220, the first electrode 211, and the second electrode 212.

A diffusion barrier layer for preventing mutual diffusion may be inserted between the second electrode 212 and the variable resistance layer 220 and between the first electrode 211 and the variable resistance layer 220 as necessary.
The memory element 200 having the above configuration has a circuit configuration as shown in FIG. 7, and one of the variable resistance element portions 250 (second electrode 212) is connected to the source electrode 242 of the selection transistor portion 240, and the other (First electrode 211) is connected to plate line PL. Further, as described above, in the selection transistor portion 240, the gate electrode 241 is connected to the word line WL, and the drain electrode 243 is connected to the bit line BL. The memory element 200 is configured by the select transistor unit 240 and the variable resistance element unit 250 thus connected to each other.

It should be noted that in the memory element 200 according to the present embodiment, the junction size (area) of the first electrode 211 that is one electrode joined to the variable resistance layer 220 is the second electrode 212 that is the other electrode. It is set to be larger than that. The junction size of the second electrode 212 with respect to the variable resistance layer 220 is preferably as close as possible to the thickness of the variable resistance layer 220.
By adopting such a configuration, the memory element 200 according to the present embodiment can easily achieve a high current density in the vicinity of the second electrode 212 as in the basic principle of the present invention described above. As shown in FIG. 5, a resistance change region 220a is formed in a portion of the variable resistance layer 220 where the second electrode 212 is connected and in the vicinity thereof.

In the memory element 200 according to the present embodiment, even if a single voltage pulse is applied by setting the waveform of the voltage pulse and the element structure so that carriers injected into the variable resistance layer 220 have a desired density. The resistance value of the variable resistance layer 220 changes greatly (for example, three digits or more), and a switching operation at a high speed is realized.
Further, in the memory element 200 according to the present embodiment, since the variable resistance region 220a in the variable resistance layer 220 is only the portion where the second electrode 212 is joined and the vicinity thereof, the variable resistance layer 220 is in the low resistance state. And the region changing between the high resistance state and the high resistance state are extremely small. Therefore, in the memory element 200 according to the present embodiment, it is possible to shorten the time required for the variable resistance layer 220 to change between the low resistance state and the high resistance state. The switching operation at is realized.

Note that this embodiment is an example used for explaining the characteristics of the present invention, and appropriate modifications can be made except for the essential part of the present invention. For example, the constituent material of the variable resistance layer 220 is a material having a perovskite structure, and any material that can change the electric resistance under the influence of an electric field can be used. Further, the dimensional values of the respective constituent elements can be appropriately changed in consideration of the characteristics of the electronic circuit.
(Embodiment 3)
The configuration of memory device 2000 according to Embodiment 3 will be described with reference to FIG. FIG. 8 is a schematic circuit diagram showing a memory device 2000 in which the memory element 200 according to the second embodiment is configured as a unit memory cell (unit switch element).
1. Configuration of Memory Device 2000 As shown in FIG. 8, in the memory device 2000 according to the present embodiment, the memory elements 200 according to the second embodiment are arranged in a two-dimensional matrix, and these are row decoders that are peripheral circuits. This is a semiconductor device configured by combining an RD, a column decoder CD, a sense amplifier SA, and the like. Specifically, as described above, the 16 memory elements 200 arranged in a matrix of 4 rows × 4 columns are connected to the word lines WL, the plate lines PL, and the bit lines BL. WL is connected to the row decoder RD. The bit line BL and the plate line PL are connected to the column decoder CD. A sense amplifier SA is connected to the end of each bit line BL opposite to the column decoder CD via a switch SW.

Each sense amplifier SA is connected to a reference level input REF and an output terminal DO.
The row decoder RD is configured by a circuit having a function of applying a selection pulse of the memory element 200 to the word line WL, and the column decoder CD has a function of applying a write pulse to the bit line BL and the plate line PL. It is comprised with the circuit which has. Further, the sense amplifier SA is configured by a circuit having a function of reading data from the memory element 1 by detecting the potential of the bit line BL.
2. 2. Driving method of memory device 2000 2-1. Write Operation In the write operation of the memory device 2000, first, a positive pulse is applied from the row decoder RD to the word line WL for word access to be written, and the field effect transistor PT which is a selection switch in the memory element 200 is turned on. To do. Next, when the data is “0”, the column decoder CD sets the bit line BL to the ground potential and applies a write pulse to the plate line PL. Further, when the data is “1”, the column decoder CD applies a write pulse to the bit line BL and sets the plate line PL to the ground potential.

  The variable resistance element portion 250 (see FIGS. 6 and 7) in the memory element 200 is in a low resistance state when the resistance change region 220a in the variable resistance layer 220 is “0” and the data is “1”. In this case, a high resistance state is obtained. That is, the resistance change region 220a of the variable resistance layer 220 made of the PCMO material is obtained when the data is “0” by one or more write pulses applied from the column decoder CD when the data is “1”. The resistance value changes 100 to 1000 times compared to the low resistance state. Here, when the data is “1”, the write pulse applied by the column decoder CD is, for example, a voltage value of 7 V and a pulse width of 100 nsec. Set to

2-2. Read Operation Next, in a read operation of data written in the memory element 200, first, the switch SW is turned on to connect the sense amplifier SA and the bit line BL, and the bit line BL is precharged to a high level. Thereby, the sense amplifier SA is activated. Next, the plate line PL is grounded, and a selection pulse is applied from the row decoder RD to the word line WL. By applying this selection pulse, a current flows from the bit line BL to the plate line PL via the variable resistance element portion 250.

  The memory element 200 shows a difference of 100 to 1000 times in resistance value of the resistance change region 220a depending on whether the recording data is “0” or “1”. As a result, the voltage drop of the bit line BL connected to the memory element 200 whose recording data is “0” has a larger voltage drop than the potential of the bit line BL connected to the memory element 200 whose recording data is “1”. Become. The sense amplifier SA compares the difference between the input potential of the reference level input REF and the potential of the bit line BL, and outputs data to the output terminal DO.

As described above, the memory device 2000 according to the present embodiment includes the memory elements 200 as unit memory cells, and is configured as a device that can be randomly accessed by arranging them in a matrix. The memory device 2000 is a device that operates at a high speed because the memory element 200 can be driven at a high speed as described above.
Further, in the memory device 2000 according to the present embodiment, as described above, the junction size of the second electrode 212 to the variable resistance layer 220 in the memory element 200 is set smaller than the first electrode 211. In some cases, a resistance change region 220a is formed in a portion of the variable resistance layer 220 to which the second electrode 212 is connected and a region in the vicinity thereof, so that current can be effectively concentrated, and driving with low power consumption is possible. Is possible. Further, in the memory device 2000 according to the present embodiment, if a configuration in which the first electrodes 211 of the plurality of memory elements 200 are shared is used, space efficiency can be improved.
(Other matters)
In addition, about the said embodiment, it is an example used in order to demonstrate the structure and effect | action of this invention in an easy-to-understand manner, and this invention is not limited to these. For example, the constituent materials, circuit configurations, and the like used in the above embodiments can be changed as appropriate within the scope having the characteristic portions of the present invention. In the above-described embodiment, as an example of means for injecting carriers into the variable resistance layer, means for applying a voltage pulse through an electrode is used. However, the present invention is not limited to this, and other means are employed. It is also possible to do.

  The present invention can cause a large resistance value change in the variable resistance layer even by applying a voltage pulse with a small number of times, and is effective in realizing a semiconductor device having a high operation speed.

1 is a schematic cross-sectional view showing a configuration of a variable resistance element model 1 used for explaining a basic principle of the present invention. 6 is a characteristic diagram showing a relationship between the size of a second electrode and a relative change in resistance value in the variable resistance element model 1. FIG. (A) is a schematic cross section which shows the electric field distribution in the variable resistance layer 20 in the variable resistance element model which concerns on a comparative example, (b) is the variable resistance layer 20 in the variable resistance element model which concerns on an Example. It is a schematic cross section which shows electric field distribution. It is a characteristic view showing the relationship between the peak value of the current density flowing between the electrode pair in the variable resistance element model and the relative change in the resistance value. 3 is a schematic cross-sectional view showing a configuration of a variable resistance element unit 100 included in the variable resistance device according to Embodiment 1. FIG. FIG. 6 is a main part sectional view showing a configuration of a memory element 200 according to a second embodiment. 3 is an equivalent circuit diagram of the memory element 200. FIG. 2 is a circuit diagram showing a memory device 2000 including a memory element 200. FIG. It is a schematic cross section which shows the structure of the conventional variable resistance element part.

Explanation of symbols

10, 210. Substrate 11, 111, 211. First electrodes 12a, 12e, 12f, 112, 212. Second electrode 12b. Third electrode 12c. Fourth electrode 12d. 5th electrode 20,120,220. Variable resistance layer 200. Memory element 220a. Resistance change region 230. Insulating layer 240. Select transistor 241. Gate electrode 242. Source electrode 243. Drain electrode 250. Variable resistance element 2000. Memory device BL. Bit line CD. Column decoder PL. Plate wire RD. Row decoder SA. Sense amplifier WL. Word line

Claims (17)

A semiconductor device comprising a variable resistance layer made of a material having a perovskite structure, the electrical characteristics of which change due to a change in electric field, and a drive unit that causes a change in electrical resistance in the variable resistance layer,
The drive unit includes carrier injection means for injecting carriers into the variable resistance layer and increasing the resistance of the variable resistance layer. ^2. The semiconductor device according to claim 1, wherein the density of carriers injected into the variable resistance layer by the carrier injection means during driving is 10 ⁴ A / cm ² or more in terms of current density. 3. The semiconductor device according to claim 1, wherein in the variable resistance layer, an electric resistance value of one main surface and a vicinity thereof is changed by the carrier injection. 4. The variable resistance layer has a first electrode and a second electrode connected to both main surfaces,
The said drive part implements the injection | pouring of the said carrier by applying a voltage via the said 1st and 2nd electrode with respect to the said variable resistance layer. Any one of Claim 1 to 3 characterized by the above-mentioned. A semiconductor device according to claim 1. 5. The semiconductor device according to claim 4, wherein the driving unit includes a carrier extracting unit that extracts carriers from the variable resistance layer and reduces resistance of the variable resistance layer. 6. The semiconductor according to claim 5, wherein the drive unit performs the carrier extraction by applying a voltage having a polarity opposite to that of the carrier injection to the variable resistance layer. apparatus. The semiconductor device according to claim 4, wherein the first electrode and the second electrode are connected to the variable resistance layer with different sizes. 8. The semiconductor device according to claim 7, wherein, in the variable resistance layer, when the carrier is injected, the resistance is increased in a region in the vicinity of a portion to which a small-size electrode is connected. A substrate and an insulating layer formed on the substrate;
The first electrode is formed by embedding an electrode material in a hole formed in the thickness direction from the surface of the insulating layer,
The variable resistance layer has a connection state with the first electrode and is laminated on the surface of the insulating layer,
The semiconductor device according to claim 4, wherein the second electrode is stacked on a surface of the variable resistance layer. A unit switch element is formed by the first electrode and the second electrode forming a pair, and the variable resistance layer sandwiched between the two electrodes.
One of the first electrode and the second electrode in the unit switch element is connected to the plate line, and the other is connected to the bit line via the selection transistor element part,
The semiconductor device according to claim 4, wherein a gate electrode of the selection transistor element portion is connected to a word line. The variable resistance layer is made of a material represented by a chemical composition formula A _X A ′ _(1-X) B _Y O _Z
In the above chemical composition formula, A is at least one element selected from the group consisting of La, Ce, Bi, Pr, Nd, Pm, Sm, Y, Sc, Yb, Lu, and Gd. A ′ is at least one element selected from the group consisting of Mg, Ca, Sr, Ba, Pb, Zn, and Cd, and B is Mn, Ce, V, Fe, It is at least one element selected from the group consisting of Co, Nb, Ta, Cr, Mo, W, Zr, Hf, and Ni, and each of X, Y, and Z is 0 ≦ X ≦ The semiconductor device according to claim 1, wherein the semiconductor device has a relationship of 1, 0 ≦ Y ≦ 2, 1 ≦ Z ≦ 7. A method for driving a semiconductor device in which a variable resistance layer made of a material having a perovskite structure causes a change in electrical characteristics due to a change in electric field,
A method for driving a semiconductor device, characterized in that carriers are injected in order to cause a change in electrical resistance of the variable resistance layer. The method for driving a semiconductor device according to claim 12, wherein the density of carriers injected into the variable resistance layer is 10 ⁴ A / cm ² or more in terms of current density. 14. The method of driving a semiconductor device according to claim 12, wherein the resistance is locally increased by injecting the carrier into the variable resistance layer. First and second electrodes are connected to both main surfaces of the variable resistance layer,
Injecting the carrier by applying a voltage to the variable resistance layer via the first and second electrodes,
15. The resistance is increased in the vicinity of a portion where one of the first and second electrodes in the variable resistance layer is connected by the carrier injection. A driving method of the semiconductor device described. 16. The driving of a semiconductor device according to claim 15, wherein the resistance of a portion of the variable resistance layer in which the resistance is increased is reduced by extracting the carrier from the variable resistance layer. Method. 17. The semiconductor device according to claim 16, wherein the carrier is extracted by applying a voltage having a polarity opposite to that of the carrier injection to the first and second electrodes. Driving method.

Images