JP2006120043A - Virtual machine having compiler - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a Java virtual machine generating an instruction scheduled code even in a template JIT (just in time) compiler. <P>SOLUTION: This JIT compiler is provided with a translator 3 to translate a byte code into a native code using a template, a code buffer 6, an FIFO buffer 5, and an evaluator 4. The evaluator 4 outputs a translated latest instruction to the FIFO buffer 5 when there is interference between the latest instruction and the last number instruction of the code buffer 6 or when there is dependency between the translated latest instruction and an instruction stored in the FIFO buffer 5. In addition, the evaluator 4 outputs the translated latest instruction or an instruction of the FIFO buffer 5 to the code buffer 6 when there is no interference between the translated latest instruction or the instruction obtained from the FIFO buffer 5 and the last number instruction of the code buffer 6. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a virtual machine having a JIT compiler, and to a virtual machine having a JIT compiler capable of generating instruction-scheduled code even if the JIT compiler is a template JIT compiler.

In recent years, there have been an increasing number of cases in which JAVA (registered trademark) systems (hereinafter JAVA (registered trademark) is referred to as “Java”) are used in embedded systems such as home appliances and in-vehicle devices. Since the Java program is an interpreter type that executes Java bytecode in a Java virtual machine, the execution efficiency is poor as it is.
Therefore, as a method for speeding up the Java program, there is a method called Just in Time (JIT) compilation in which byte code is compiled into a JITed code (referred to as native code in the present invention) and executed.
JITed code is faster than bytecode execution by (1) improving the execution efficiency of the code itself and (2) increasing the efficiency of method calls.
As described above, the JIT compiler is a means for improving execution efficiency by converting Java bytecode into native code. For example, Patent Document 1 describes a compiler that converts bytecode into machine code at a high speed. Non-Patent Document 1 also describes a compiler in a Java virtual machine.

The template JIT compiler has a one-to-one native code template for bytecode, performs JIT compilation without intermediate code generation, has a short compile time, and does not consume memory for the intermediate code. Suitable for JAVA (registered trademark) system.
On the other hand, a RISC architecture processor can bring out performance by arranging instructions while avoiding register interference and memory interference. This is called instruction scheduling. In an ordinary compiler (for example, C compiler), instruction scheduling is performed by converting a source into intermediate code, converting the intermediate code into DAG (Directed Acyclic Graph), and finally generating code.
JP-A-11-175349 Proceedings of Java (registered trademark) Virtual Machine Research and Technology Symposium, Monterey, California, USA, April 23-24, 2001, Michael Paleczny, Christpher Vick, Cliff Click "The Java (registered trademark) HotSpotServer Compiler" Sun Microsystems [2004 Search October 14], Internet <URL: http: //www.usenix.org/publication/library/prceedings/jvm01/paleczny.html>

A JIT compiler that is not a template requires compile time and memory consumption, such as generating intermediate code for instruction scheduling.
On the other hand, the template JIT compiler does not generate intermediate code, and native code for byte code is generated continuously, so instruction scheduling is difficult.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a Java virtual machine capable of generating instruction-scheduled code even in a template JIT compiler.

In order to solve the above-described problems, in the present invention, a JIT compiler includes a translation unit that translates bytecode into native code using a template, a code buffer that stores an instruction-scheduled instruction, a FIFO buffer, and an evaluation Means are provided.
The evaluation means checks whether there is an interference between the latest translated instruction and the last few instructions output to the code buffer. If there is no interference, the latest instruction is output to the code buffer, and there is an interference. The latest instruction is output to the FIFO buffer.
When there is an instruction in the FIFO buffer, the instruction is taken out from the FIFO buffer, and it is checked whether there is interference between the instruction and the last few instructions in the code buffer. If there is no interference, the instruction taken out from the FIFO buffer is coded. Output to buffer. Also, when there is interference, it is checked whether there is a dependency between the latest instruction translated by the translation means and the FIFO buffer instruction. If there is a dependency, the latest instruction is output to the FIFO buffer, If there is no relationship, the latest instruction and the last few instructions in the code buffer are checked for interference as described above. If there is no interference, the latest instruction is output to the code buffer. The latest instruction is output to the FIFO buffer.

  In the present invention, as described above, the JIT compiler is provided with a translation means for translating bytecode into native code using a template, a code buffer, a FIFO buffer, and an evaluation means, and the latest translated by the evaluation means. Since the instruction scheduling is performed and instruction scheduling is performed, even the template JIT compiler can perform instruction scheduling and improve the execution speed of the program.

FIG. 1 shows the overall configuration of the Java virtual machine of the present invention.
The computer 100 has hardware 20 and an OS 30, and the Java virtual machine 10 is provided on the OS 30.
The Java virtual machine 10 has an interpreter 11 and a JIT compiler 12. The JIT compiler 12 has a template that holds a native code associated with a byte code in a one-to-one relationship, and converts the byte code into a native code using the template. At that time, the translated native code is evaluated, and instruction scheduling is performed based on interference and dependency between native codes.

FIG. 2 is a block diagram showing a functional configuration of the JIT compiler 12 of this embodiment.
As shown in the figure, the JIT compiler 12 includes a template 2, a translator 3, an evaluator 4, a FIFO buffer 5, and a code buffer 6.
The translator 2 translates the byte code 1 into a native code (hereinafter referred to as an instruction) using the template 2. The evaluator 4 evaluates the instruction translated by the translator 2, performs instruction scheduling, and outputs the scheduling result to the code buffer 6.
In other words, the evaluator 4 repeats the following processing using the FIFO buffer and performs instruction scheduling.
(1) When no instruction is held in the FIFO buffer 5.
(i) It is checked whether there is register interference or memory interference between the latest instruction A translated by the translator 2 and the last few instructions B output to the code buffer 6.
(ii) If there is no interference, the instruction A is output to the code buffer 6.
(iii) When there is interference, the instruction A is output to the FIFO buffer 5.
Here, if there is register interference or memory interference (when an instruction to access the same register or the same memory is issued continuously for several instructions), the execution speed becomes slow. Therefore, when there is interference as described above, the instruction A is not immediately output to the code buffer 6 but is held in the FIFO buffer 5 without being exchanged. The “last number of instructions B” refers to instructions that are normally 1 to 4 instructions before output to the code buffer 6, and this number may be determined for each type of instruction.

(2) When an instruction is held in the FIFO buffer.
(i) When an instruction is held in the FIFO buffer 5, one instruction C is taken out from the FIFO buffer 5. Since data is extracted from the FIFO buffer 5 in the order of storage, when a plurality of instructions are stored in the FIFO buffer 5, the first stored data (first instruction) is extracted.
(ii) It is checked whether there is an interference between the instruction C fetched from the FIFO buffer 5 and the last several instructions B in the code buffer 6.
(iii) If there is no interference, the instruction C is output to the code buffer 6.
(iv) If there is interference, it is checked whether there is a command from the translator 3.
Here, when there is no byte code to be translated and no new instruction is output from the translator 3, the instruction C held in the FIFO buffer 5 is output to the code buffer regardless of the presence or absence of interference.

(v) If there is an interference between the instruction C and the last few instructions B and there is the latest instruction from the translator 3, the instruction D is taken out from the translator 3.
(vi) Check whether there is a dependency relationship between the instruction D fetched from the translator 3 and all the instructions stored in the FIFO buffer 5. That is, it is checked whether the instruction fetched from the translator 3 is an instruction that uses the execution result of any instruction stored in the FIFO buffer 5.
(vii) If there is a dependency between the instruction D and the instruction held in the FIFO buffer 5, the instruction D needs to be executed after the instruction held in the FIFO buffer 5 is executed. The instruction D is stored in the FIFO buffer 5. Since the instructions are taken out from the FIFO buffer 5 in the order of storage as described above, the instruction execution order is guaranteed by storing the instruction D in the FIFO buffer 5.
(viii) If there is no dependency between the instruction D and the instruction held in the FIFO buffer 5, the last number output to the instruction D and the code buffer 6 is the same as (1). If there is an interference with the instruction B, the latest translated instruction D is output to the code buffer 6 if there is no interference, and if there is an interference, the latest instruction D is output to the FIFO buffer 5. .

In the present embodiment, as described above, the evaluator 4 and the FIFO buffer are provided, and the instruction scheduling of the native code is performed based on the interference and dependency between instructions. Instruction scheduling can be performed simply by adding a simple configuration.
In the instruction scheduling of the present invention, instruction scheduling as complete as intermediate code generation and instruction scheduling as in the prior art cannot be performed. However, as a template JIT compiler, satisfactory instruction scheduling is possible. The execution speed can be improved as compared with the case where scheduling is not performed.

3 and 4 are flowcharts showing the instruction scheduling process of this embodiment.
First, in FIG. 3, it is checked whether there is an instruction in the FIFO buffer (step S1). If there is no instruction in the FIFO buffer, it is checked whether there is a new instruction from the translator, and if not, the process is terminated (step S2).
If there is an instruction from the translator, one instruction is taken out from the translator (step S3), and it is checked whether there is interference between this instruction and the last few instructions in the code buffer (step S4). If not, the instruction fetched from the translator is output to the code buffer, and the process returns to (A) (step 5). If there is interference, the instruction taken out from the translator is put into the FIFO buffer, and the process returns to (A) (step S6).

On the other hand, if there is an instruction in the FIFO buffer, the process proceeds to step S7 in FIG. 4, where one instruction is extracted from the FIFO buffer, and there is interference between the instruction extracted from the FIFO buffer and the last few instructions in the code buffer. If there is no interference, the instruction is output to the code buffer and the process returns to (A) of FIG. 3 (step S9).
If there is interference between the instruction fetched from the FIFO buffer and the last few instructions in the code buffer, it is checked whether there is an instruction from the translator (step S10).
If there is no instruction from the translator, the instruction is output to the code buffer and the process returns to (A) of FIG. 3 (step S11).
If there is a command from the translator, one command is fetched from the translator (step S12), and it is checked whether there is a dependency between the command fetched from the translator and the command in the FIFO buffer (step S13).

If there is a dependency, it is checked whether the FIFO buffer is full (step S16). If the FIFO buffer is not full, the instruction fetched from the translator is placed in the FIFO buffer (step S18). If the FIFO buffer is full, one instruction in the FIFO buffer is extracted and output to the code buffer (step S17), and then the instruction extracted from the translator is input to the FIFO buffer.
If there is no dependency, it is checked whether there is interference between the instruction fetched from the translator and the last several instructions in the code buffer (step S14). If there is no interference, the instruction is stored in the code buffer. The output is returned to (A) in FIG. 3 (step S15). If there is interference, the instruction fetched from the translator is placed in the FIFO buffer, and the process returns to (A) of FIG. 3 (step S19).

Hereinafter, an example of instruction scheduling processing according to the present embodiment will be described using a specific example.
FIG. 5 shows an example of a Java program that performs an operation of {(a × 3) + (b × 4) + (c × 5)}. FIG. 5 shows byte code before compilation and native code after compilation. The instruction sequence before instruction scheduling is shown.
FIG. 6 shows instructions stored in the code buffer and FIFO buffer during the instruction scheduling process, and (1) to (8) in FIG. 6 are (1) to (8) shown in FIG. Corresponds to the instruction. FIG. 7 shows an instruction sequence stored in the code buffer after instruction scheduling.

Each byte code shown in FIG. 5 is translated into an instruction (native code) shown in the figure by the translator and output from the translator. Each translated instruction performs the following processing.
(1) ldi @ (gr25, 4), g16
The byte code iload_1 is translated into the above instruction (native code). The above instruction is an instruction to load “a” into the register g16 from the memory address pointed by the register (gr25, 4) [gr25 is the register number, 4 is the offset] ([g16] ← “a”).
(2) mul gr16,3, gr17
The byte code iconst_3, imul is translated into the above instruction (native code). The above instruction is an instruction that multiplies “a” held in the register gr16 by a constant “3” and loads it into the register gr17 ([gr17] ← “a × 3”).
Note that if the instructions (1) and (2) are successively executed in this order, the access to the register gr16 occurs continuously, so that the instructions (1) and (2) interfere with each other.
(3) ldi @ (gr25,8), g18
The bytecode iload_2 is translated into the above instruction (native code). The above instruction is an instruction for loading “b” into the register g18 from the memory address pointed by the register (gr25, 8) ([g18] ← “b”).

(4) slli, gr18, 2, gr19
The bytecodes iconst_4, imul are translated into the above instruction (native code). The above instruction is an instruction to shift the register gr18 by two digits (corresponding to 4 times) and load it into the register gr19 ([gr19] ← “b × 4”).
Note that if the instructions (3) and (4) are successively executed in this order, the access to the register gr18 occurs continuously, so that the instructions (3) and (4) interfere with each other.
(5) add gr17, gr19, gr20
The byte code iadd is translated into the above instruction (native code). The above instruction adds the contents of the register gr17 (holding “a × 3”) and the contents of the register gr19 (holding “b × 4”), and loads the result into the register gr20 ( [Gr20] ← “a × 3 + b × 4”).
Since the instruction (5) can be executed only after the instructions (2) and (4) are executed, the instruction (5) is dependent on the instructions (2) and (4).

(6) ldi @ (gr25, 12), g21
The byte code iload — 3 is translated into the above instruction (native code). The above instruction is an instruction to load “c” into the register g21 from the memory address pointed by the register (gr25, 12) ([g21] ← “c”).
(7) mul gr21,5, gr22
The bytecodes iconst_5, imul are translated into the above instructions (native code). The above instruction multiplies “c” held in the register gr21 by a constant “5” and loads it into the register gr22 ([gr22] ← “c × 5”).
Note that if the instructions (6) and (7) are successively executed in this order, the access to the register gr21 occurs continuously, so that the instructions (6) and (7) interfere with each other.
(8) add gr20, gr22, gr23
The byte code iadd is translated into the above instruction (native code). The above instruction adds the contents of the register gr20 (holding “a × 3 + b × 4”) and the contents of the register gr22 (holding “c × 5”), and loads them into the register gr23. Yes ([gr23] ← “a × 3 + b × 4 + c × 5”).
Since the instruction (8) can be executed only after the instructions (5) and (7) are executed, the instruction (8) is dependent on the instructions (5) and (7).

According to this embodiment, the instruction sequence is held in the FIFO buffer 5 as shown in FIG. 6, and the instruction sequence that has been scheduled is output to the code buffer 6.
(i) Command (1) is output from the translator 3. Since no instruction is stored in the code buffer 6, the instruction (1) is output to the code buffer.
(ii) The command (2) is output from the translator 3. There is an instruction (1) in the code buffer 6, and the instruction (1) and the instruction (2) interfere with each other, so that the instruction (2) is put into the FIFO buffer 5.
(iii) The instruction (2) is taken out from the FIFO buffer 5, but since the instruction (2) in the FIFO buffer 5 interferes with the instruction (1) in the code buffer 6, the instruction (3) from the translator 3 is It is taken out. The code buffer 6 contains the instruction (1) but does not interfere with the instruction (3), so the instruction (3) is output to the code buffer 5.
(iv) The instruction (2) is taken out from the FIFO buffer 5, but since the instruction (2) in the FIFO buffer 5 interferes with the instruction (1) in the code buffer 6, the instruction (4) from the translator 3 is It is taken out.
There is an instruction (3) in the code buffer 6, and the instruction (3) and the instruction (4) interfere with each other, so that the instruction (4) is put into the FIFO buffer 5.

(v) The instruction (2) is fetched from the FIFO buffer 5, but since the instruction (2) in the FIFO buffer 5 interferes with the instruction (1) in the code buffer 6, the instruction (5) from the translator 3 is It is taken out.
Since the instruction (5) and the instructions (2) and (4) in the FIFO buffer 5 are in a dependency relationship, the instruction (5) is put into the FIFO buffer 5.
(vi) The instruction (2) is taken out from the FIFO buffer 5. However, since the instruction (2) in the FIFO buffer 5 interferes with the instruction (1) in the code buffer 6, the instruction (6) from the translator 3 is It is taken out.
Since the instruction in the code buffer 6 does not interfere with the instruction (6), the instruction (6) is output to the code buffer 5.
(vii) The instruction (2) is taken out from the FIFO buffer 5. Since the instruction (2) in the FIFO buffer 5 does not interfere with the instruction (1) in the code buffer 6, the instruction (2) is output to the code buffer 6.

(viii) The instruction (4) is taken out from the FIFO buffer 5. Since the instruction (4) in the FIFO buffer 5 does not interfere with the instruction (3) in the code buffer 6, the instruction (4) is output to the code buffer 6.
(ix) The instruction (5) is taken out from the FIFO buffer 5, but since the instruction (5) in the FIFO buffer 5 interferes with the instruction (4) in the code buffer 6, the instruction (7) from the translator 3 is It is taken out.
There is an instruction (6) in the code buffer 6 and the instruction (6) interferes with the instruction (7), so that the instruction (7) is put into the FIFO buffer 5.
(x) The instruction (5) is taken out from the FIFO buffer 5, but since the instruction (5) in the FIFO buffer 5 interferes with the instruction (4) in the code buffer 6, the instruction (8) from the translator 3 is It is taken out.
Since the instruction (8) and the instructions (5) and (7) in the FIFO buffer are in a dependency relationship, the instruction (8) is put into the FIFO buffer 5.

(xi) The instruction (5) is taken out from the FIFO buffer 5. Since there is no instruction from the translator 3, the instruction (5) is output to the code buffer 6.
(xii) The instruction (7) is taken out from the FIFO buffer 5. Since there is no instruction from the translator 3, the instruction (7) is output to the code buffer 6.
(xiii) The instruction (8) is taken out from the FIFO buffer 5. Since there is no instruction from the translator 3, the instruction (8) is output to the code buffer 6.
By performing the above processing, instructions are output to the code buffer 6 in the order of (1) (3) (6) (2) (4) (5) (7) (8).
FIG. 7 shows an instruction sequence after the instruction scheduling. As shown in the figure, the instruction sequence is rearranged so that interference does not occur as much as possible, and the execution speed can be improved as compared with the instruction sequence before scheduling.

It is a figure which shows the whole structure of the Java virtual machine of this invention. It is a block diagram which shows the function structure of the JIT compiler 12 of the Example of this invention. It is a flowchart (1) which shows the command scheduling process of the Example of this invention. It is a flowchart (2) which shows the command scheduling process of the Example of this invention. It is a figure which shows an example of the bytecode and native code in a Java program. It is a figure which shows the instruction | command stored in a code buffer and a FIFO buffer in the case of instruction scheduling processing. It is a figure which shows the native code after instruction scheduling.

Explanation of symbols

1 byte code 2 template 3 translator 4 evaluator 5 FIFO buffer 6 code buffer 10 Java virtual machine

Claims (2)

A virtual machine having a function for compiling bytecode into native code using a template holding native code corresponding to each bytecode one-to-one,
A translation means for translating bytecode into native code using the template,
A FIFO buffer for storing instructions translated by the translation means; a code buffer for storing instructions scheduled for instruction;
An evaluation means for evaluating interference between the instruction translated by the translation means or the instruction stored in the FIFO buffer and the last few instructions stored in the code buffer;
The evaluation means is
There is a dependency between the translated latest instruction and the last few instructions in the code buffer, or between the translated latest instruction and the instruction held in the FIFO buffer. When the latest instruction is output to the FIFO buffer,
When there is no interference between the latest translated instruction or the instruction fetched from the FIFO buffer and the last few instructions in the code buffer, the translated latest instruction or the FIFO buffer instruction is output to the code buffer. A virtual machine characterized by A program executed by a virtual machine having a function of compiling bytecode into native code using a template holding native code corresponding to each bytecode one-to-one,
The program includes a process of translating bytecode into native code using the template,
There is a dependency between the translated latest instruction and the last few instructions in the code buffer, or between the translated latest instruction and the instruction held in the FIFO buffer. When the latest instruction is output to the FIFO buffer,
When there is no interference between the latest translated instruction or the instruction fetched from the FIFO buffer and the last few instructions in the code buffer, the translated latest instruction or the FIFO buffer instruction is output to the code buffer. A program that causes a computer to execute processing to be performed.

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