JP2006114785A - Dram mixed-loading asic and its designing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DRAM mixed-loading ASIC having BIST (Built-in Self Test) with high degree of freedom of layout. <P>SOLUTION: In this DRAM mixed-loading ASIC, a DRAM core 12, and a BIST circuit 15 for inspecting the DRAM core 12 are built into a DRAM macro 2. Owing to this DRAM mixed-loading ASIC, a restriction can be eliminated that a BIST circuit 15 must be arranged near an input terminal 5 and an output terminal 6 of the DRAM macro 2, and the degree of freedom of layout is effectively improved. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an application specific integrated circuit (ASIC), and more particularly, to an ASIC (hereinafter referred to as “DRAM embedded ASIC”) incorporating a DRAM (dynamic random access memory) macro.

  The DRAM-embedded ASIC is suitably used as a signal processing LSI (large scale integrated circuit) that requires high-speed data processing in large quantities. A DRAM-embedded ASIC with a built-in DRAM macro does not require data transfer between the ASIC and an external memory. Therefore, the DRAM-embedded ASIC can realize a high data transfer rate. This is advantageous in performing large-scale and high-speed data processing.

  A DRAM-embedded ASIC is often provided with a built-in self test (BIST) circuit for inspecting a DRAM macro (see Patent Document 1). The BIST circuit supplies a test pattern to the DRAM macro, and further checks whether the DRAM core is operating normally from the output pattern output from the DRAM macro in response to the test pattern.

  One important factor in designing a DRAM-embedded ASIC is that the user has a large degree of freedom in layout. The fact that the user can place a desired circuit at a desired position of the ASIC is effective for suppressing the chip area of the ASIC and optimizing the operation timing.

  One factor that reduces the degree of freedom in layout is the existence of the BIST circuit described above. Since a large number of signals are input to the DRAM macro and a large number of signals are output from the DRAM macro, it is necessary to connect a large number of wirings between the BIST circuit and the DRAM macro. Therefore, in order to reduce the chip area of the ASIC, it is necessary to provide the BIST circuit at a position close to the input terminal and the output terminal of the DRAM core. This imposes significant constraints on the layout of the area around the ASIC DRAM core.

  Another important factor in designing a DRAM-embedded ASIC is that a scan test can reliably confirm that the DRAM macro and other logic circuits are correctly connected by wiring. The scan test is a test for confirming whether a macro and another logic circuit are correctly connected by wiring (see, for example, Patent Document 2 and Patent Document 3). The presence of a portion that is not tested by the scan test in the wiring connecting the DRAM macro and another logic circuit is not preferable in verifying the operation of the DRAM embedded ASIC.

  For example, consider the circuit 100 with DRAM macro 101 shown in FIG. The scan test of the circuit 100 is performed using the scan path 102 and the multiplexer 103. The scan path 102 is connected to a wiring 104 connected to the input of the DRAM macro 101. In the scan test, the scan path 102 is selected by the multiplexer 103, and a scan test signal is passed through the scan path 102. This confirms whether the DRAM macro 101 is correctly connected to other logic circuits.

  However, the circuit 100 shown in FIG. 1 includes a portion that is not tested by the scan test. First, in the scan test of the circuit 100, the connection of the portion of the wiring 104 between the input of the DRAM macro 101 and the node 105 to which the scan path 102 and the wiring 104 are connected is not inspected. Second, the connection between the multiplexer 103 and the output of the DRAM macro 101 is not checked. The presence of a portion that is not tested by the scan test is not preferable in order to improve the reliability of the designed ASIC.

From such a background, it is desired that a DRAM-embedded ASIC with a built-in BIST has a high degree of freedom in layout, and that a connection between a DRAM macro and another logic circuit can be confirmed more reliably in a scan test. .
JP 2000-36200 A JP 2001-235524 A JP 2001-208810 A JP 2003-121509 A

Therefore, an object of the present invention is to provide a BIST built-in DRAM embedded ASIC having a high layout flexibility.
Another object of the present invention is to provide a BIST built-in DRAM embedded ASIC in which a connection between a DRAM macro and another logic circuit can be confirmed more reliably in a scan test.

  In order to achieve the above object, the present invention employs the following means. In the description of technical matters included in the means, in order to clarify the correspondence between the description of [Claims] and the description of [Best Mode for Carrying Out the Invention] Number / symbol used in the best mode for doing this is added. However, the added numbers and symbols shall not be used for the interpretation of the technical scope of the invention described in [Claims].

  In the DRAM-embedded ASIC according to the present invention, a DRAM macro (2) and a BIST circuit (15) for inspecting the DRAM core (12) are incorporated in the DRAM macro (2). According to the DRAM-embedded ASIC, the restriction that the BIST circuit (15) must be arranged in the vicinity of the input terminal (5) and the output terminal (6) of the DRAM macro (2) can be eliminated. The degree of freedom can be improved effectively.

  In a preferred embodiment, the DRAM macro (2) is further supplied from the input terminal (5) to which the macro input signal group (7) is input, the output terminal (6), and the outside of the DRAM macro (2). One of the macro input signal group (7) and the test pattern signal group (16) output from the BIST circuit (15) in response to the control signal (SCAN, BIST) is the DRAM core input signal group (17). In response to the control signal (SCAN, BIST), the input selector circuit (11) that outputs the data, the scan path (13) that transmits the DRAM core input signal group (17), and the transmission via the scan path (13) One of the DRAM core input signal group (17) to be output and the DRAM core output signal group (18) output from the DRAM core (12) is defined as a macro output signal group (8) as an output terminal (6 And an output selector circuit (14) to be output to.

  In a DRAM-embedded ASIC having such a configuration, a signal supplied from an external logic circuit (3) and passing through a scan path (13) is always input to an input terminal (5) and an output terminal (6) during a scan test. Go through both. Therefore, the DRAM-embedded ASIC includes a connection between the input terminal (5) of the DRAM macro (2) and the logic circuit (3), and a connection between the output terminal (6) of the DRAM macro (2) and the logic circuit (3). Can be confirmed more reliably.

  In another preferred embodiment, the DRAM macro (2) further includes an input terminal (5) to which the macro input signal group (7) is input, an output terminal (6), a scan path (13), and a DRAM. One of the macro input signal group (7) and the test pattern signal group (16) output from the BIST circuit (15) in response to control signals (SCAN, BIST) supplied from the outside of the macro (2). And an input selector circuit (11) for outputting a macro input signal group (7) as a scan path signal group (19) in response to a control signal (SCAN, BIST). In response to the scan path (13) transmitting the campus (13) signal group and the control signals (SCAN, BIST), the scan path signal group (19) and the D output from the DRAM core (12) AM and an output selector circuit that outputs to the output terminal (6) one of the core output signal as a macro output signal group (8) (14). Even in such a configuration, the DRAM-embedded ASIC includes the connection between the input terminal (5) of the DRAM macro (2) and the logic circuit (3), and the output terminal (6) and the logic circuit (3) of the DRAM macro (2). Can be reliably confirmed.

  In still another preferred embodiment, the DRAM macro (2) further includes an input terminal (5) to which a macro input signal group (7) composed of a plurality of macro input signal sets is input, and an output terminal (6). ), And a test pattern signal group (16) output from the macro input signal group (7) and the BIST circuit (15) in response to control signals (SCAN, BIST) supplied from the outside of the DRAM macro (2). Is output to the input of the DRAM core (12) as a DRAM core input signal (17), and in response to the control signals (SCAN, BIST), a plurality of macro input signal sets (7a, 7b) An input selector circuit (11) that outputs one of them as a scan path signal group (19), a scan path (13) that transmits the scan path signal group (19), and a control signal (SCAN, B In response to ST), one of the scan path signal group (19) transmitted through the scan path (13) and the DRAM core output signal group (18) output from the DRAM core (12) An output selector circuit (14) for outputting to the output terminal (6) as an output signal group (8).

  The DRAM-embedded ASIC can switch a signal selected from a plurality of macro input signal groups (7a, 7b) constituting the macro input signal group (7) and output to the scan path (13). According to such a configuration, even when the number of signals constituting the macro input signal group (7) is larger than the number of signals that can be output as the macro output signal group (8), the DRAM macro (2) and the input terminal The connection between (5) and the other logic circuit (3) can be reliably confirmed.

  In still another preferred embodiment, the DRAM macro (2) further includes an input terminal (5) to which a macro input signal group (7) is input, an output terminal (6), and an external part of the DRAM macro (2). One of the macro input signal group (7) and the test pattern signal group (16) output from the BIST circuit (15) in response to the control signals (SCAN, BIST) supplied from the plurality of DRAM cores. An input selector circuit (11) for outputting as a DRAM core input signal group (17) composed of input signal sets (17a, 17b), a scan path (13) for transmitting the DRAM core input signal group (17), and a control In response to the signals (SCAN, BIST), a plurality of DRAM core input signal sets (17a, 17b) transmitted through the scan path (13) and the DRAM core (12) output D AM core output signal group one of the (18), and an output selector circuit (14) for outputting to the output terminal (6) as a macro output signal group (8).

  The DRAM-embedded ASIC is selected from a plurality of DRAM core input signal groups (17a, 17b) constituting a DRAM core input signal group (17) transmitted via the scan path (13), and is a macro output signal group. The signal output as (8) can be switched. According to such a configuration, even when the number of signals constituting the macro input signal group (7) is larger than the number of signals that can be output as the macro output signal group (8), the DRAM macro (2) and the input terminal The connection between (5) and the other logic circuit (3) can be reliably confirmed.

  In still another preferred embodiment, the DRAM macro (2) further includes an input terminal (5) to which the macro input signal group (7) is input, an output terminal (6), a scan path (13), Of the macro input signal group (7) and the test pattern signal group (16) output from the BIST circuit (15) in response to control signals (SCAN, BIST) supplied from the outside of the DRAM macro (2) One of them is output as a DRAM core input signal, and in response to the control signals (SCAN, BIST), the macro input signal group (7) is made up of a plurality of scan path signal sets (19a, 19b). In response to the input selector circuit (11) that outputs as the group (19), the scan path (13) that transmits the scan path signal group (19), and the control signals (SCAN, BIST), One of a plurality of scan path signal sets (19a, 19b) transmitted through the canvas (13) and a DRAM core output signal group (18) output from the DRAM core (12) is used as a macro output signal group. (8) includes an output selector circuit (14) for outputting to the output terminal (6).

  The DRAM-embedded ASIC is selected from a plurality of scan path signal groups (19a, 19b) constituting a scan path signal group (19) and a scan path signal group (19) transmitted through the scan path (13). Thus, the signals output as the macro output signal group (8) can be switched. According to such a configuration, even when the number of signals constituting the macro input signal group (7) is larger than the number of signals that can be output as the macro output signal group (8), the DRAM macro (2) and the input terminal The connection between (5) and the other logic circuit (3) can be reliably confirmed.

  The BIST circuit (15) preferably generates a result signal indicating whether or not the DRAM core (12) is defective by compressing the inspection result of the DRAM core (12).

The DRAM-embedded ASIC design method according to the present invention is as follows.
Preparing macro data indicating a layout of a DRAM macro (2) including a DRAM core (12) and a BIST circuit (15) for inspecting the DRAM core (12) in a storage device (33);
A step of incorporating the macro data stored in the storage device (33) and generating layout data (39) of the ASIC including the DRAM macro (2). According to the DRAM-embedded ASIC design method, the restriction that the BIST circuit (15) must be arranged in the vicinity of the input terminal (5) and the output terminal (6) of the DRAM macro (2) can be eliminated. The degree of freedom of layout can be improved effectively.

According to the present invention, it is possible to provide a BIST built-in DRAM mixed ASIC having a high degree of freedom in layout.
In addition, according to the present invention, it is possible to provide a BIST built-in DRAM embedded ASIC in which a connection between a DRAM macro and another logic circuit can be confirmed more reliably in a scan test.

  Embodiments of a DRAM-embedded ASIC according to the present invention will be described below with reference to the drawings. 2 to 8, the same or corresponding elements are referred to by the same or similar reference numerals.

First Embodiment First Embodiment DRAM mixed ASIC configuration:
FIG. 2 is a block diagram showing the configuration of the DRAM-embedded ASIC 1 according to the first embodiment of the present invention. The ASIC 1 includes a DRAM macro 2 and logic circuits 3 and 4. The logic circuit 3 is connected to the input terminal 5 of the DRAM macro 2, and the logic circuit 4 is connected to the output terminal 6 of the DRAM macro 2. The logic circuit 3 is a circuit group that supplies a macro input signal group 7 to the input terminal 5. The macro input signal group 7 includes a plurality of signals, typically an input data signal and an external control signal. However, only two of the macro input signal groups 7 are shown in FIG. Examples of the external control signal include an address signal, a chip enable signal, a row strobe signal, and a column strobe signal. The logic circuit 4 is a circuit group that processes the macro output signal group 8 output from the DRAM macro 2. There are a plurality of macro output signal groups 8 (only two are shown in FIG. 2), and they are typically composed of output data signals.

  The DRAM macro 2 includes an input selector 11, a DRAM core 12, a scan path 13, an output selector 14, and a BIST circuit 15.

  The input selector 11 selects the DRAM core input signal group 17 supplied to the DRAM core 12 from the macro input signal group 7 supplied to the input terminal 5 and the test pattern signal group 16 output from the BIST circuit 15. Circuit. A signal supplied to the DRAM core 12 is selected according to a scan test signal SCAN and a BIST enable signal BIST supplied from the outside of the DRAM macro 2. The scan test signal SCAN is a signal indicating that a scan test is performed, and the BIST enable signal BIST is a signal indicating that the test of the DRAM core 12 by the BIST circuit 15 is performed.

  The DRAM core 12 includes a memory array in which DRAM cells are arranged in a matrix and a peripheral circuit (none of which is shown) that operates the memory array. The input DI of the DRAM core 12 is connected to the output of the input selector 11. The DRAM core 12 outputs a DRAM core output signal group 18 from the output DO in response to the DRAM core input signal group 17 supplied to the input DI.

  The scan path 13 includes signal lines and / or circuits that bypass the DRAM core input signal group 17 output from the input selector 11 to the output selector 14. The scan path 13 is used when a scan test is performed.

  The output selector 14 is a circuit that selects the macro output signal group 8 from the DRAM core input signal group 17 that is bypassed via the scan path 13 and the DRAM core output signal group 18 that is output from the DRAM core 12. is there. The selection of the macro output signal group 8 is performed according to the can test signal SCAN.

  The BIST circuit 15 is a circuit that internally tests the DRAM core 12. The BIST circuit 15 generates a test pattern signal group 16 that is input to the DRAM core 12 during the test. Further, the BIST circuit 15 determines whether or not the DRAM core 12 is operating normally based on a signal output from the DRAM core 12. The test of the DRAM core 12 by the BIST circuit 15 is performed in response to the clock signal CLK and the reset signal RESET. The BIST circuit 15 outputs a result signal TOUT indicating the test result of the DRAM core 12 and a pattern end signal ENDF indicating that the test of the DRAM core 12 is completed.

  The presence of the BIST circuit 15 in the DRAM macro 2 is one of the features of the DRAM-embedded ASIC 1 of the present embodiment. The presence of the BIST circuit 15 in the DRAM macro 2 means that it is not necessary to consider the presence of the BIST circuit in the layout design of the DRAM-embedded ASIC 1. This means that a desired circuit can be arranged near the input terminal and output terminal of the DRAM macro. Thus, the presence of the BIST circuit 15 in the DRAM macro 2 is effective for improving the flexibility of layout.

2. Operation of DRAM-embedded ASIC of this embodiment:
The operation of the DRAM-embedded ASIC 1 varies depending on the operation mode in which the DRAM-embedded ASIC 1 is set. There are three operation modes set in the DRAM-embedded ASIC 1: a normal operation mode, a BIST mode, and a scan test mode. The scan test mode is an operation mode that is set when a scan test is performed on the DRAM-embedded ASIC1, and when the DRAM-embedded ASIC1 is set to the scan test mode, the scan test signal SCAN is activated and the BIST enable signal is set. BIST is deactivated. An activation of a signal typically means that the signal is pulled up to a “High” level, and an inactivation of a signal typically means that the signal This means that it is pulled down to the “Low” level. Those skilled in the art will appreciate that each signal may be either high active or low active. The BIST mode is an operation mode set when the DRAM core 12 is tested by the BIST circuit 15. When the DRAM-embedded ASIC 1 is set to the BIST mode, the scan test signal SCAN is deactivated and the BIST enable signal BIST is activated. The normal operation mode is an operation mode set when the DRAM-embedded ASIC 1 is normally operated. When the DRAM-embedded ASIC 1 is set to the normal operation mode, both the scan test signal SCAN and the BIST enable signal BIST are deactivated.

  When the DRAM-embedded ASIC 1 is set to the normal operation mode (that is, when both the scan test signal SCAN and the BIST enable signal BIST are deactivated), the input selector 11 selects the macro input signal group 7 as the DRAM core input signal. The group 17 is selected, and the output selector 14 selects the DRAM core output signal group 18 as the macro output signal group 8. As a result, the DRAM-embedded ASIC 1 performs a normal operation.

  When the DRAM-embedded ASIC 1 is set in the BIST mode (that is, when the scan test signal SCAN is deactivated and the BIST enable signal BIST is activated), the BIST circuit 15 inspects the DRAM core 12. Specifically, the input selector 11 selects the test pattern signal group 16 as the DRAM core input signal group 17, and the output selector 14 selects the DRAM core output signal group 18 as the macro output signal group 8. In response to the activation of the BIST enable signal BIST, the BIST circuit 15 starts testing the DRAM core 12. The BIST circuit 15 generates a test pattern signal group 16 and supplies it to the DRAM core 12, receives a DRAM core output signal group 18 from the DRAM core 12, and inspects the DRAM core 12 based on the DRAM core output signal group 18. . For example, the BIST circuit 15 writes predetermined data to the DRAM core 12 by the test pattern signal group 16 and determines from the DRAM core output signal group 18 whether the predetermined data is correctly written to the DRAM core 12. When the inspection of the DRAM core 12 is completed, the BIST circuit 15 activates the pattern end signal ENDF, further compresses the inspection result of the DRAM core 12, and outputs a result signal TOUT. The result signal TOUT is a signal indicating whether or not there is a defect in the DRAM core 12. The BIST circuit 15 activates the result signal TOUT when a defect is found in the DRAM core 12. When no defect is found in the DRAM core 12, the result signal TOUT remains inactivated. The pattern end signal ENDF and the result signal TOUT can know from the outside that the inspection of the DRAM core 12 has been completed and whether the DRAM core 12 is defective.

  When the DRAM-embedded ASIC 1 is set to the scan test mode (that is, when the scan test signal SCAN is activated and the BIST enable signal BIST is deactivated), a scan test is performed using the scan path 13. The input selector 11 selects the macro input signal group 7 supplied from the logic circuit 3 as the DRAM core input signal group 17, and the output selector 14 selects the DRAM core input signal group 17 bypassed via the scan path 13 as a macro. The output signal group 8 is selected. In other words, the macro input signal group 7 input to the input terminal 5 by the logic circuit 3 is output as it is from the output terminal 6 via the scan path 13. If the macro input signal group 7 does not reach the logic circuit 4, it indicates that there is a problem in the connection of wiring between the DRAM macro 2 and the logic circuits 3 and 4. By this scan test, the connection between the DRAM macro 2 and the logic circuit 3 and the connection between the DRAM macro 2 and the logic circuit 4 are confirmed.

  In the scan test, a signal is transmitted to the entire wiring connecting the input terminal 5 and the logic circuit 3 of the DRAM macro 2, and a signal is transmitted to the entire wiring connecting the output terminal 6 and the logic circuit 4. is important. The DRAM-embedded ASIC 1 of this embodiment excludes a portion that is not tested by a scan test from the wiring connecting the DRAM macro 2 and the logic circuits 3 and 4. This makes it possible to more reliably verify the operation of the DRAM-embedded ASIC 1.

3. FIG. 3 is a block diagram of a design apparatus 30 used for designing the DRAM-embedded ASIC 1 of this embodiment. FIG. 4 is a procedure for designing the DRAM-embedded ASIC 1 by the design apparatus 30. It is a flowchart which shows. As shown in FIG. 3, the design device 30 is a computer system that includes a CPU 31, an input / output device 32, and an external storage device 33. A logic synthesis tool 34 and a layout tool 35 are installed in the external storage device 33, and a cell library 36 and a macro library 37 are prepared. The cell library 36 stores cell data indicating the layout of cells that can be used in the design, and the macro library 37 stores macro data indicating the layout of usable macros. The macro data prepared in the macro library 37 includes the macro data of the DRAM macro 2 in FIG.

  As shown in FIG. 4, in the design method of the present embodiment, logic synthesis is performed by the logic synthesis tool 34, and a net list 38 describing the connection relationship of the circuits included in the DRAM embedded ASIC 1 is generated (steps). S01). The generated net list 38 is stored in the external storage device 33. Subsequently, macro layout is performed by the layout tool 35 (step S02). The layout tool 35 uses the macro data prepared in the macro library 37 to determine the macro arrangement. Subsequently, power supply wiring is performed (step S03), and automatic placement of cells is performed (step S04). In the automatic cell arrangement, cell data prepared in the cell library 36 is used. Further, schematic wiring (step S05) and detailed wiring (step S06) are performed, and the layout data 39 of the DRAM-embedded ASIC 1 is completed. The layout data 39 incorporates macro data of the DRAM macro 2 of FIG.

  The macro data indicating the layout of the DRAM macro 2 in FIG. 2 is prepared in the macro library 37, so that the degree of freedom of layout is improved and the connection between the DRAM macro and other logic circuits is ensured by the scan test. It is important to make sure. Since the macro data of the DRAM macro 2 including the BIST circuit 15 is prepared, the designer can set the desired data around the input terminal 5 and the output terminal 6 of the DRAM macro 2 without worrying about the position of the BIST circuit. Can be arranged. In addition, if the macro data of the DRAM macro 2 is registered in the macro library 37 after confirming that the connection relation is correct, it is possible to confirm that all wiring connections related to the DRAM macro 2 are correctly connected by a scan test. . This is suitable for guaranteeing the operation of the DRAM macro 2.

  As described above, the DRAM-embedded ASIC design method according to the present embodiment is useful for improving the degree of freedom of layout and for confirming the connection between the DRAM macro and another logic circuit by a scan test. It is.

4). Summary As described above, in the DRAM-embedded ASIC 1 of the present embodiment, the BIST circuit 15 is mounted in the DRAM macro 2. As a result, the degree of freedom in layout is improved.

  In addition, the DRAM-embedded ASIC 1 of the present embodiment has a configuration in which a portion that is not tested by the scan test is excluded from the wiring connecting the DRAM macro 2 and the logic circuits 3 and 4. The DRAM-embedded ASIC 1 of this embodiment can surely confirm the connection between the DRAM macro and another logic circuit in the scan test.

Second Embodiment FIG. 5 is a block diagram showing the configuration of a DRAM-embedded ASIC 1A according to a second embodiment. The configuration of the DRAM-embedded ASIC 1A of the second embodiment is substantially the same as that of the DRAM-embedded ASIC 1 of the first embodiment, but is different in the following points. In the second embodiment, the DRAM-embedded ASIC 1A is configured such that the scan path 13 is separated from the wiring connecting the input selector 11 and the DRAM core 12. Specifically, instead of the input selector 11, an input selector 11A that outputs a scan path signal group 19 to the scan path 13 separately from the DRAM core input signal group 17 is used. In this case, the operation of the DRAM-embedded ASIC 1 is changed as follows.

  When the DRAM-embedded ASIC 1A is set to the normal operation mode, the input selector 11A selects the macro input signal group 7 as the DRAM core input signal group 17, and sets the scan path signal group 19 to a predetermined potential (for example, “High” level or The output selector 14 selects the DRAM core output signal group 18 as the macro output signal group 8. Thereby, the DRAM-embedded ASIC 1A performs a normal operation.

  When the DRAM-embedded ASIC 1A is set to the BIST mode, the input selector 11A selects the test pattern signal group 16 as the DRAM core input signal group 17, and sets the scan path signal group 19 to a predetermined potential (for example, “High” level or “ The output selector 14 selects the DRAM core output signal group 18 as the macro output signal group 8. The BIST circuit 15 generates the test pattern signal group 16 and the DRAM core output signal group 18. And the DRAM core 12 is tested.

  When the DRAM-embedded ASIC 1A is set to the scan test mode, a scan test is performed. The input selector 11 A outputs the macro input signal group 7 supplied from the logic circuit 3 as a scan path signal group 19. The potential of the DRAM core input signal group 17 output from the input selector 11A can be arbitrarily determined. The input selector 11A may output the macro input signal group 7 as the DRAM core input signal group 17, or may fix the DRAM core input signal group 17 to a predetermined potential. The output selector 14 selects the scan path signal group 19 transmitted through the scan path 13 as the macro output signal group 8. In other words, the macro input signal group 7 is output from the output terminal 6 through the scan path 13 as it is. If the macro input signal group 7 does not reach the logic circuit 4, it indicates that there is a problem in the connection of wiring between the DRAM macro 2 and the logic circuits 3 and 4. By such a scan test, the connection between the DRAM macro 2 and the logic circuit 3 and the connection between the DRAM macro 2 and the logic circuit 4 are confirmed.

  The advantage of the DRAM-embedded ASIC 1A according to the second embodiment is that the potential of the scan path signal group 19 is fixed when the DRAM-embedded ASIC 1A is set to the normal operation mode. Fixing the potential of the scan path signal group 19 reduces the crosstalk of the DRAM-embedded ASIC 1A when the normal operation mode is set, and further effectively reduces the power consumption of the DRAM-embedded ASIC 1A.

Third Embodiment Referring to FIG. 2, in DRAM macro 2, in many cases, the number of signals constituting macro input signal group 7 is larger than the number of signals constituting macro output signal group 8. . This is because signals to be supplied to the DRAM macro 2 include data signals and external control signals, whereas signals to be output from the DRAM macro 2 are basically only data signals.

  This can be a problem in the scan test of the DRAM-embedded ASICs 1 and 1A of the first and second embodiments. When the number of macro input signal groups 7 is larger than the number of macro output signal groups 8, all of the macro input signal groups 7 supplied to the DRAM macro 2 cannot be output as the macro output signal groups 8 as they are.

  The DRAM-embedded ASIC 1B of the third embodiment shown in FIG. 6 has a configuration for dealing with such a problem. In the third embodiment, the macro input signal group 7 supplied from the logic circuit 3 to the DRAM macro 2 is divided into a plurality of macro input signal sets. In the present embodiment, the macro input signal group 7 is divided into a first macro input signal group 7a and a second macro input signal group 7b. Further, instead of the input selector 11, an input selector 11B that outputs one of the first macro input signal set 7a and the second macro input signal set 7b as the scan path signal group 19 is used. In addition, the output selector 14B is used.

  In order to select the scan path signal group 19 from the first macro input signal set 7a and the second macro input signal set 7b, scan test signals SCAN1 and SCAN2 are input to the input selector 11B. In order to select the first macro input signal set 7a as the scan path signal group 19, the scan test signal SCAN1 is activated. To select the second macro input signal set 7b as the scan path signal group 19, the scan test signal SCAN1 is activated. Test signal SCAN2 is activated. When the DRAM-embedded ASIC 1B is set to the normal operation mode and the BIST mode, the scan test signals SCAN1 and SCAN2 are both inactivated.

  The scan test signals SCAN1 and SCAN2 are also supplied to the output selector 14B. The output selector 14B selects one of the DRAM core output signal group 18 and the scan path signal group 19 as the macro output signal group 8 in response to the scan test signals SCAN1 and SCAN2.

The operation of the DRAM-embedded ASIC 1B according to the third embodiment will be described below.
When the DRAM-embedded ASIC 1B is set to the normal operation mode, the input selector 11 selects the macro input signal group 7 as the DRAM core input signal group 17, and sets the scan path signal group 19 to a predetermined potential (for example, “High” level or The output selector 14 selects the DRAM core output signal group 18 as the macro output signal group 8. As a result, the DRAM-embedded ASIC 1 performs a normal operation.

  When the DRAM-embedded ASIC 1B is set to the BIST mode, the input selector 11 selects the test pattern signal group 16 as the DRAM core input signal group 17 and sets the scan path signal group 19 to a predetermined potential (for example, “High” level or “ The output selector 14 selects the DRAM core output signal group 18 as the macro output signal group 8. The BIST circuit 15 generates the test pattern signal group 16 and the DRAM core output signal group 18. And the DRAM core 12 is tested.

  When the DRAM-embedded ASIC 1B is set to the scan test mode, a scan test is performed according to the following procedure. First, the scan test signal SCAN1 is activated. In response to the activation of the scan test signal SCAN1, the input selector 11B outputs the first macro input signal set 7a as the scan path signal group 19. On the other hand, the potential of the DRAM core input signal group 17 output from the input selector 11B can be arbitrarily determined. The input selector 11B may output the macro input signal group 7 as the DRAM core input signal group 17, or may fix the DRAM core input signal group 17 to a predetermined potential. The output selector 14 selects the scan path signal group 19 transmitted through the scan path 13 as the macro output signal group 8. In other words, the first macro input signal set 7 a is output as it is from the output terminal 6 via the scan path 13. Thereby, the connection of the wiring corresponding to the first macro input signal set 7a among the wiring connecting the DRAM macro 2 and the logic circuit 3 is confirmed. At the same time, the connection between the DRAM macro 2 and the logic circuit 4 is also confirmed.

  Subsequently, the scan test signal SCAN1 is deactivated and the scan test signal SCAN2 is activated. In response to the activation of the scan test signal SCAN2, the input selector 11B outputs the second macro input signal set 7b as the scan path signal group 19. The output selector 14 selects the scan path signal group 19 transmitted through the scan path 13 as the macro output signal group 8. In other words, the second macro input signal set 7b is set to be output from the output terminal 6 via the scan path 13 as it is. This confirms the connection of the wiring corresponding to the second macro input signal set 7b among the wiring connecting the DRAM macro 2 and the logic circuit 3. Through the above process, connection of all wirings connecting the DRAM macro 2 and the logic circuit 3 is confirmed.

  As described above, the DRAM-embedded ASIC 1B according to the third embodiment has the DRAM macro 2 and the logic circuit 3 even when the number of the macro input signal groups 7 is larger than the number of the macro output signal groups 8. It is possible to confirm the connection of all wirings connecting the two.

Fourth Embodiment Fourth Embodiment FIG. 7 is a block diagram showing a configuration of a DRAM-embedded ASIC 1C according to a fourth embodiment. The DRAM-embedded ASIC 1C according to the fourth embodiment is for coping with a problem caused by the number of macro input signal groups 7 being larger than the number of macro output signal groups 8 as in the third embodiment. is there.

  The configuration of the DRAM-embedded ASIC 1C according to the fourth embodiment is substantially the same as that of the DRAM-embedded ASIC 1 according to the third embodiment, but is different in the following points. In the fourth embodiment, an input selector 11C that operates in response to the scan test signals SCAN1 and SCAN2 is used instead of the input selector 11B. The DRAM core input signal group 17 output from the input selector 11C is divided into a plurality of DRAM core input signal groups. In the present embodiment, the DRAM core input signal group 17 is divided into a first DRAM core input signal set 17a and a second DRAM core input signal set 17b. The first DRAM core input signal set 17a is a signal group corresponding to the first macro input signal set 7a, and the second DRAM core input signal set 17b is a signal group corresponding to the second macro input signal set 7b.

  In the fourth embodiment, an output selector 14C that selectively outputs one of the first and second DRAM core input signal groups 17a and 17b as the macro output signal group 8 is used instead of the output selector 14B. Is done. The output selector 14C selects one of the first and second DRAM core input signal sets 17a and 17b as the macro output signal group 8 in response to the scan test signals SCAN1 and SCAN2. When the scan test signal SCAN1 is activated, the first DRAM core input signal set 17a is selected, and when the scan test signal SCAN2 is activated, the second DRAM core input signal set 17b is selected.

The operation of the DRAM-embedded ASIC 1C according to the fourth embodiment will be described below.
When the DRAM-embedded ASIC 1C is set to the normal operation mode, the input selector 11C selects the macro input signal group 7 as the DRAM core input signal group 17. The output selector 14C selects the DRAM core output signal group 18 as the macro output signal group 8. As a result, the DRAM-embedded ASIC 1C performs a normal operation.

  When the DRAM-embedded ASIC 1C is set to the BIST mode, the input selector 11C selects the test pattern signal group 16 as the DRAM core input signal group 17. The output selector 14C selects the DRAM core output signal group 18 as the macro output signal group 8. The BIST circuit 15 generates a test pattern signal group 16 and further receives a DRAM core output signal group 18 to test the DRAM core 12.

  When the DRAM-embedded ASIC 1C is set to the scan test mode, a scan test is performed according to the following procedure. First, the scan test signal SCAN1 is activated. In response to the activation of the scan test signal SCAN1, the input selector 11C selects the macro input signal group 7 as the DRAM core input signal group 17. On the other hand, the output selector 14C selects the first DRAM core input signal set 17a as the macro output signal group 8 in response to the activation of the scan test signal SCAN1. Since the first DRAM core input signal set 17a corresponds to the first macro input signal set 7a, the first macro input signal set 7a is output from the output terminal 6 through the scan path 13 as it is. Thereby, the connection of the wiring corresponding to the first macro input signal set 7a among the wiring connecting the DRAM macro 2 and the logic circuit 3 is confirmed. At the same time, the connection between the DRAM macro 2 and the logic circuit 4 is also confirmed.

  Subsequently, the scan test signal SCAN1 is deactivated and the scan test signal SCAN2 is activated. In response to the activation of the scan test signal SCAN2, the output selector 14C switches the signal to be output. That is, the output selector 14C selects the second DRAM core input signal set 17b as the macro output signal group 8 instead of the first DRAM core input signal set 17a. Since the second DRAM core input signal set 17b corresponds to the second macro input signal set 7b, the second macro input signal set 7b is output from the output terminal 6 through the scan path 13 as it is. This confirms the connection of the wiring corresponding to the second macro input signal set 7b among the wiring connecting the DRAM macro 2 and the logic circuit 3. Through the above process, connection of all wirings connecting the DRAM macro 2 and the logic circuit 3 is confirmed.

  As described above, the DRAM-embedded ASIC 1C according to the fourth embodiment has the DRAM macro 2 and the logic circuit 3 even when the number of the macro input signal groups 7 is larger than the number of the macro output signal groups 8. It is possible to confirm the connection of all the wirings connecting the two.

Fifth Embodiment Fifth Embodiment FIG. 8 is a block diagram showing a configuration of a DRAM-embedded ASIC 1D according to a fifth embodiment. The DRAM-embedded ASIC 1D according to the fifth embodiment is for coping with the problem caused by the number of macro input signal groups 7 being larger than the number of macro output signal groups 8 as in the third embodiment. is there.

  The configuration of the DRAM-embedded ASIC 1D of the fifth embodiment is substantially the same as that of the DRAM-embedded ASIC 1 of the third embodiment, but differs in the following points. In the DRAM-embedded ASIC 1D of the fifth embodiment, instead of the input selector 11B, an input selector 11D that outputs all of the macro input signal group 7 as the scan path signal group 19 is used; It does not have a function of selectively outputting the second macro input signal sets 7a and 7b. Instead, the scan path signal group 19 output from the input selector 11D is divided into a plurality of scan path signal groups. In the present embodiment, the scan path signal group 19 is divided into a first scan path signal group 19a and a second scan path signal group 19b. The first scan path signal set 19a is a signal group corresponding to the first macro input signal set 7a, and the second scan path signal set 19b is a signal group corresponding to the second macro input signal set 7b.

  Further, an output selector 14D that selectively outputs one of the first and second scan path signal groups 19a and 19b as the macro output signal group 8 is used instead of the output selector 14B. The output selector 14D selects one of the first and second scan path signal groups 19a and 19b as the macro output signal group 8 in response to the scan test signals SCAN1 and SCAN2. When the scan test signal SCAN1 is activated, the first scan path signal set 19a is selected, and when the scan test signal SCAN2 is activated, the second scan path signal set 19b is selected.

  The operation of the DRAM-embedded ASIC 1D according to the fifth embodiment will be described below. When the DRAM-embedded ASIC 1D is set to the normal operation mode, the input selector 11D selects the macro input signal group 7 as the DRAM core input signal group 17, and sets the scan path signal group 19 to a predetermined potential (for example, “High” level or The output selector 14D selects the DRAM core output signal group 18 as the macro output signal group 8. As a result, the DRAM-embedded ASIC 1 performs a normal operation.

  When the DRAM-embedded ASIC 1D is set to the BIST mode, the input selector 11D selects the test pattern signal group 16 as the DRAM core input signal group 17 and sets the scan path signal group 19 to a predetermined potential (for example, “High” level or “ The output selector 14D selects the DRAM core output signal group 18 as the macro output signal group 8. The BIST circuit 15 generates the test pattern signal group 16, and the DRAM core output signal group 18 And the DRAM core 12 is tested.

  When the DRAM-embedded ASIC 1C is set to the scan test mode, a scan test is performed according to the following procedure. First, the scan test signal SCAN1 is activated. In response to the activation of the scan test signal SCAN1, the input selector 11D outputs the macro input signal group 7 as the scan path signal group 19. On the other hand, the potential of the DRAM core input signal group 17 can be arbitrarily determined. The input selector 11D may output the macro input signal group 7 as the DRAM core input signal group 17, or may fix the DRAM core input signal group 17 to a predetermined potential. The output selector 14D selects the first scan path signal set 19a as the macro output signal group 8 in response to the activation of the scan test signal SCAN1. Since the first scan path signal set 19a corresponds to the first macro input signal set 7a, the first macro input signal set 7a is output from the output terminal 6 through the scan path 13 as it is. Thereby, the connection of the wiring corresponding to the first macro input signal set 7a among the wiring connecting the DRAM macro 2 and the logic circuit 3 is confirmed. At the same time, the connection between the DRAM macro 2 and the logic circuit 4 is also confirmed.

  Subsequently, the scan test signal SCAN1 is deactivated and the scan test signal SCAN2 is activated. In response to the activation of the scan test signal SCAN2, the output selector 14D switches the signal to be output. That is, the output selector 14D selects the second scan path signal set 19b as the macro output signal group 8 instead of the first scan path signal set 19a. Since the second scan path signal set 19b corresponds to the second macro input signal set 7b, the second macro input signal set 7b is output from the output terminal 6 via the scan path 13 as it is. This confirms the connection of the wiring corresponding to the second macro input signal set 7b among the wiring connecting the DRAM macro 2 and the logic circuit 3. Through the above process, connection of all wirings connecting the DRAM macro 2 and the logic circuit 3 is confirmed.

  As described above, the DRAM-embedded ASIC 1C according to the fifth embodiment has the DRAM macro 2 and the logic circuit 3 even when the number of the macro input signal groups 7 is larger than the number of the macro output signal groups 8. It is possible to confirm the connection of all the wirings connecting the two.

  It is obvious to those skilled in the art that the DRAM-embedded ASIC according to the second to fifth embodiments can be designed by the same method as the DRAM-embedded ASIC according to the first embodiment. When the DRAM-embedded ASIC according to the second to fifth embodiments is designed, the macro data of the DRAM macro 2 prepared in the macro library 37 is the same as that of the second to fifth embodiments. The DRAM macro 2 is changed so as to correspond to each layout.

FIG. 1 is a block diagram of a typical circuit with a scan path. FIG. 2 is a block diagram showing the configuration of the DRAM-embedded ASIC according to the first embodiment of the present invention. FIG. 3 is a block diagram showing a design apparatus for designing the DRAM-embedded ASIC of the present invention. FIG. 4 is a flowchart showing the DRAM mixed ASIC design method of the present invention. FIG. 5 is a block diagram showing a configuration of a DRAM-embedded ASIC according to the second embodiment of the present invention. FIG. 6 is a block diagram showing a configuration of a DRAM-embedded ASIC according to the third embodiment of the present invention. FIG. 7 is a block diagram showing a configuration of a DRAM embedded ASIC according to the fourth embodiment of the present invention. FIG. 8 is a block diagram showing a configuration of a DRAM embedded ASIC according to the fifth embodiment of the present invention.

Explanation of symbols

1,1A-1D: DRAM-embedded ASIC
2: DRAM macro 3, 4: Logic circuit 5: Input terminal 6: Output terminal 7: Macro input signal group 7a, 7b: Macro input signal group 8: Macro output signal group 11, 11A to 11D: Input selector 12: DRAM core 13: Scan path 14, 14B to 14D: Output selector 15: BIST circuit 16: Test pattern signal group 17: DRAM core input signal group 17a: First DRAM core input signal group 17b: Second DRAM core input signal group 18: DRAM core output Signal group 19: Scan path signal group 19a: First scan path signal group 19b: Second scan path signal group 30: Design device 31: CPU
32: Input / output device 33: External storage device

Claims (12)

A DRAM embedded ASIC comprising a DRAM macro including a DRAM core and a BIST (Built-in Self Test) circuit for inspecting the DRAM core. The DRAM-embedded ASIC according to claim 1,
The DRAM macro further comprises:
An input terminal to which a macro input signal group is input;
An output terminal;
An input selector circuit for outputting one of the macro input signal group and the test pattern signal group output from the BIST circuit as a DRAM core input signal group in response to a control signal supplied from the outside of the DRAM macro; ,
A scan path for transmitting the DRAM core input signal group;
In response to the control signal, one of the DRAM core input signal group transmitted through the scan path and the DRAM core output signal group output from the DRAM core is used as the macro output signal group as the output terminal. A DRAM-embedded ASIC including an output selector circuit for outputting to the DRAM. The DRAM-embedded ASIC according to claim 1,
The DRAM macro further comprises:
An input terminal to which a macro input signal group is input;
An output terminal;
With scan campus,
In response to a control signal supplied from the outside of the DRAM macro, one of the macro input signal group and the test pattern signal group output from the BIST circuit is output as a DRAM core input signal, and the control An input selector circuit for outputting the macro input signal group as a scan path signal group in response to a signal;
A scan path for transmitting the scan path signal group;
In response to the control signal, an output selector circuit that outputs one of the scan path signal group and the DRAM core output signal output from the DRAM core to the output terminal as a macro output signal group ASIC. The DRAM-embedded ASIC according to claim 1,
The DRAM macro further comprises:
An input terminal to which a macro input signal group composed of a plurality of macro input signal sets is input;
An output terminal;
In response to a control signal supplied from the outside of the DRAM macro, one of the macro input signal group and the test pattern signal group output from the BIST circuit is output to the input of the DRAM core as a DRAM core input signal. And an input selector circuit that outputs one of the plurality of macro input signal sets as a scan path signal group in response to the control signal;
A scan path for transmitting the scan path signal group;
In response to the control signal, one of the scan path signal group transmitted through the scan path and the DRAM core output signal group output from the DRAM core is set as a macro output signal group to the output terminal. A DRAM mixed ASIC including an output selector circuit for outputting. The DRAM-embedded ASIC according to claim 1,
The DRAM macro further comprises:
An input terminal to which a macro input signal group is input;
An output terminal;
In response to a control signal supplied from the outside of the DRAM macro, one of the macro input signal group and the test pattern signal group output from the BIST circuit is composed of a plurality of DRAM core input signal sets. An input selector circuit for outputting as a DRAM core input signal group;
A scan path for transmitting the DRAM core input signal group;
One of the plurality of DRAM core input signal sets transmitted through the scan path and the DRAM core output signal group output from the DRAM core in response to the control signal is defined as a macro output signal group. A DRAM-embedded ASIC including an output selector circuit for outputting to the output terminal. The DRAM-embedded ASIC according to claim 1,
The DRAM macro further comprises:
An input terminal to which a macro input signal group is input;
An output terminal;
With scan campus,
In response to a control signal supplied from the outside of the DRAM macro, one of the macro input signal group and the test pattern signal group output from the BIST circuit is output as a DRAM core input signal, and the control An input selector circuit for outputting the macro input signal group as a scan path signal group composed of a plurality of scan path signal sets in response to a signal;
A scan path for transmitting the scan path signal group;
In response to the control signal, one of the plurality of scan path signal sets transmitted through the scan path and the DRAM core output signal group output from the DRAM core is used as the macro output signal group. A DRAM-embedded ASIC including an output selector circuit that outputs to an output terminal. The DRAM-embedded ASIC according to claim 1,
The BIST circuit generates a result signal indicating whether or not the DRAM core is defective by compressing a test result of the DRAM core. Providing macro data indicating a layout of a DRAM macro including a DRAM core and a BIST circuit for inspecting the DRAM core in a storage device;
A method for designing an embedded ASIC with DRAM, comprising the step of generating ASIC layout data including the DRAM macro by incorporating the macro data stored in the storage device. A DRAM-embedded ASIC design method according to claim 8,
The DRAM macro further comprises:
An input terminal to which a macro input signal group is input;
An output terminal;
An input selector circuit for outputting one of the macro input signal group and the test pattern signal group output from the BIST circuit as a DRAM core input signal group in response to a control signal supplied from the outside of the DRAM macro; ,
A scan path for transmitting the DRAM core input signal group;
In response to the control signal, one of the DRAM core input signal group transmitted through the scan path and the DRAM core output signal group output from the DRAM core is used as the macro output signal group as the output terminal. A DRAM-embedded ASIC design method, including an output selector circuit that outputs to a DRAM. A DRAM-embedded ASIC design method according to claim 8,
The DRAM macro further comprises:
An input terminal to which a macro input signal group is input;
An output terminal;
With scan campus,
In response to a control signal supplied from the outside of the DRAM macro, one of the macro input signal group and the test pattern signal group output from the BIST circuit is output as a DRAM core input signal, and the control An input selector circuit for outputting the macro input signal group as a scan path signal group in response to a signal;
A scan path for transmitting the scan path signal group;
In response to the control signal, an output selector circuit that outputs one of the scan path signal group and the DRAM core output signal output from the DRAM core to the output terminal as a macro output signal group ASIC design method. A DRAM-embedded ASIC design method according to claim 8,
The DRAM macro further comprises:
An input terminal to which a macro input signal group composed of a plurality of macro input signal sets is input;
An output terminal;
In response to a control signal supplied from the outside of the DRAM macro, one of the macro input signal group and the test pattern signal group output from the BIST circuit is output to the input of the DRAM core as a DRAM core input signal. And an input selector circuit that outputs one of the plurality of macro input signal sets as a scan path signal group in response to the control signal;
A scan path for transmitting the scan path signal group;
In response to the control signal, one of the scan path signal group transmitted through the scan path and the DRAM core output signal group output from the DRAM core is set as a macro output signal group to the output terminal. A DRAM mixed ASIC design method including an output selector circuit for outputting. The DRAM-embedded ASIC according to claim 8,
The DRAM macro further comprises:
An input terminal to which a macro input signal group is input;
An output terminal;
In response to a control signal supplied from the outside of the DRAM macro, one of the macro input signal group and the test pattern signal group output from the BIST circuit is composed of a plurality of DRAM core input signal sets. An input selector circuit for outputting as a DRAM core input signal group;
A scan path for transmitting the DRAM core input signal group;
One of the plurality of DRAM core input signal sets transmitted through the scan path and the DRAM core output signal group output from the DRAM core in response to the control signal is defined as a macro output signal group. An DRAM ASIC design method including an output selector circuit for outputting to the output terminal.

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