JP2006114212A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance trimming efficiency to an output potential of a voltage step-down circuit. <P>SOLUTION: A semiconductor integrated circuit has the voltage step-down circuit receiving first and second external voltages and generating an internal voltage (VDL), a volatile storing circuit (31DR) connected to the voltage step-down circuit and storing information for adjusting a voltage level of the internal voltage, a central processing unit (10) receiving the internal voltage and the second external voltage and made to operate between the internal voltage and the second external voltage and a nonvolatile memory element storing the information by its threshold value and electrically writable. The information stored in the nonvolatile memory element is read out in response to initialization of the semiconductor integrated circuit and the volatile storing circuit stores the information read out from the nonvolatile memory element in response to the initialization of the semiconductor integrated circuit. Thereby, the internal voltage adjusted by the information is supplied to the central processor unit from the voltage step-down circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention can electrically rewrite volatile memory such as DRAM (dynamic random access memory) and SRAM (static random access memory) and flash memory together with a control processing device such as a central processing unit. The present invention relates to a semiconductor integrated circuit in which a non-volatile memory is mounted on a semiconductor substrate. Technology.

  Today, the increase in scale of semiconductor integrated circuits has led to the trend toward system-on-chip implementations called DRAM-embedded LSIs and system LSIs.

  In a semiconductor integrated circuit, as the scale increases, defects that occur inside the semiconductor integrated circuit cannot be ignored. In particular, memories such as DRAM, SRAM, and flash memory tend to be expected to have a relatively small area and a large storage capacity, and defects are caused by extremely fine processing and accompanying signal miniaturization. It is easy to generate. Therefore, it is important to apply redundant circuit technology in order to enable expected system operation despite the occurrence of some defects.

  When the scale of a semiconductor integrated circuit is increased, it is desired to apply a trimming technique for obtaining desired circuit characteristics. By the trimming technique, an amount that can be regarded as a quasi-analog, such as an analog amount such as an internal voltage or current, or a timing signal timing, is sufficiently close to a desired value regardless of manufacturing variations of the semiconductor integrated circuit.

  Known redundant circuit techniques and trimming techniques for large-scale semiconductor integrated circuits can be referred to. One is an invention in which a memory cell of an electrically rewritable nonvolatile memory such as a flash memory filed by the present applicant is used for a defect repair information program (Japanese Patent Laid-Open No. 7-334999, corresponding US). Patent No. 5561627). In the present invention, relief information for identifying a defective memory cell of a nonvolatile memory is stored in the memory cell of the nonvolatile memory, and the relief information is latched by an internal latch circuit during an initialization operation or the like. The repair information and the access address are compared, and if they match, the access is switched to the access to the redundant memory cell.

  In addition, the other is an invention in which trimming information is stored and used in a part of a storage area of a non-volatile memory such as a flash memory filed by the present applicant (Japanese Patent Laid-Open No. 10-214496, Corresponding US Patent Application No. 09/016300). That is, in the invention, a trimming circuit for finely adjusting the output clamp voltage of the voltage clamp means for providing the operation power supply of the flash memory is provided, and the trimming information for determining the state of the trimming circuit is the memory of the flash memory. Programmed into the cell. The programmed trimming information is read from the flash memory in a reset operation and is internally transferred to a register. The state of the trimming circuit is determined using the transferred trimming information. As a result, the clamp voltage output from the voltage clamp means is trimmed to a suitable value for the operation of the flash memory regardless of manufacturing variations of the semiconductor integrated circuit.

  Examples of documents describing the system LSI include “Electronic materials (issued by the Industrial Research Council in January 1998)” on pages 34-38. FIG. 4 shows an example in which such a volatile memory is mixedly mounted. A technique for forming a nonvolatile memory and a DRAM by the same process is already provided in US Pat. No. 5,057,448. Japanese Laid-Open Patent Publication No. 64-52293 and Japanese Laid-Open Patent Publication No. 10-124381 are known examples of a semiconductor integrated circuit in which a flash memory and a DRAM are mounted on a single semiconductor substrate together with a CPU.

JP 7-334999 A Japanese Patent Laid-Open No. 10-21496

  The above-mentioned previous application by the present applicant intends to use the memory element of the flash memory for defect repair or trimming within a closed range in one flash memory. The present inventor considers a non-volatile memory, which is one circuit module mounted on a large-scale integrated circuit, in relation to another circuit module in view of an increase in the degree of integration represented by a system-on-chip. We examined how to use it efficiently. In this examination process, the present inventor considered that the information stored in the nonvolatile memory is used for defect relief of a volatile memory different from the nonvolatile memory. The present inventor has recognized the following new problem in the examination of such use of the volatile memory.

  That is, in order to give relief information to the nonvolatile memory, a process for reflecting the relief information in the volatile memory is required. Reflection of such information can be realized at high speed even if there is an increase in the amount of relief information corresponding to an increase in defects according to the configuration of the volatile memory or an increase in defects according to an increase in storage capacity. It is desirable to make it.

  In an investigation conducted after this examination, a known technique (Japanese Patent Laid-Open No. 6-131897) using a programmable ROM for repairing a defect in a cache memory was found. However, the known programmable ROM is a dedicated circuit element attached to the redundant memory control circuit in the cache memory, and is only a remedy within a range closed in the cache memory, and is compared as a result. However, it did not give any suggestion to the above-mentioned examination subject by the present inventor.

  An object of the present invention is to improve the change efficiency of coupling change such as defect relief in a circuit having a large-scale logic configuration in which a nonvolatile memory and a volatile memory that are accessible by a control processing device are mounted. An object of the present invention is to provide a semiconductor integrated circuit that can be used.

  Furthermore, an object of the present invention is to realize cost reduction by improving the yield of a semiconductor integrated circuit in which a demand for cost reduction becomes severe due to having a large-scale logic.

  Another object of the present invention is to improve the usability of a memory module in a semiconductor integrated circuit including a volatile memory such as DRAM or SRAM as a memory module by unifying specifications related to defect relief of the memory module. is there.

  Still another object of the present invention is to provide a data storage medium storing design data used when designing a semiconductor integrated circuit using a computer.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  The first semiconductor integrated circuit (1A, 1C) according to the present invention is an electrically rewritable nonvolatile memory that can be accessed by a control processing device (10) such as a central processing unit on one semiconductor substrate. (11) and a volatile memory (12, 13) accessible by the control processing device, and the storage information of the nonvolatile memory is used to change the connection in response to defect repair of the volatile memory. Use. That is, the volatile memory includes a plurality of first volatile memory cells such as normal volatile memory cells and second volatile memory cells such as redundant volatile memory cells. Volatile memory circuits (12AR, 13AR) for holding coupling control information for enabling replacement of the first volatile memory cell by two volatile memory cells. The non-volatile memory has a plurality of non-volatile memory cells, some of which are non-volatile memory cells that store the coupling control information, and coupling control information such as an initialization operation instruction for the semiconductor integrated circuit. The coupling control information is read from the nonvolatile memory cell and output by the read setting operation. The volatile memory circuit captures and stores the coupling control information from the nonvolatile memory by the read setting operation.

  In addition to the above, the second semiconductor integrated circuit (1B) according to the present invention uses the information stored in the nonvolatile memory for defect relief of the nonvolatile memory. That is, the volatile memory holds repair information for repairing a defective normal volatile memory cell by a plurality of normal volatile memory cells, a redundant volatile memory cell, and the redundant volatile memory cell. And volatile memory circuits (12AR, 13AR). The non-volatile memory has a plurality of normal non-volatile memory cells, a redundant non-volatile memory cell, and a volatile memory that stores repair information for relieving a defective normal non-volatile memory cell by the redundant non-volatile memory cell. And a memory memory circuit (11AR). A part of the nonvolatile memory cell is a memory cell that stores relief information of the volatile memory and relief information of the nonvolatile memory. Relief information stored in a part of the nonvolatile memory cell is read from the nonvolatile memory cell by executing a read setting operation such as an initialization operation on the semiconductor integrated circuit, and the volatile in the volatile memory The data is supplied and held in the memory circuit and the volatile memory circuit in the nonvolatile memory, respectively.

  According to the first and second semiconductor integrated circuits, information for coupling control such as defect relief is written in a nonvolatile memory instead of an element such as a fuse element. In such a case, a fuse program circuit which is necessary at the time can be made unnecessary. Accordingly, it is possible to limit the use and process of a manufacturing apparatus that tends to be relatively expensive, such as a laser cutting apparatus for cutting a fuse, and it is possible to reduce the manufacturing cost. When the fuse element is provided, the fuse element is used regardless of the layer that makes laser cutting difficult, such as the aluminum wiring layer considered as the wiring of the semiconductor integrated circuit and the copper wiring expected to further shorten the signal propagation delay time. In order to make it possible to cut the element, it is better to place the fuse element in a relatively upper layer portion on the semiconductor substrate. In order to avoid applying thermal damage due to laser light, it is necessary to provide an opening for laser irradiation in the insulating film and surface protective film on the fuse element. It itself becomes expensive. In addition, when the fuse element is provided, the size reduction of the element itself is restricted due to the convenience of laser light irradiation, and the size of the semiconductor substrate becomes relatively large. If a fuse program circuit is not used, the manufacturing process is simplified. When a non-volatile memory is used to store the coupling control information, it is possible to enjoy the advantage that information can be rewritten at any time and can be performed multiple times. As a result, for example, a coupling change for a defect generated in a relatively later process of manufacturing a semiconductor integrated circuit such as a burn-in process, or a defect generated over time after being mounted on a system or a circuit board. It is possible to fully respond to such coupling changes. As a result, a circuit having a large-scale logic configuration in which a volatile memory is mounted together with a nonvolatile memory can be fully utilized by being able to be changed after manufacturing. Therefore, cost reduction can be realized by improving the yield of a semiconductor integrated circuit having a large-scale logic.

  The data input terminals of the volatile memory circuits (11AR, 12AR, 13AR) are coupled to a data bus (16) to which the data input / output terminals of the nonvolatile memory and the volatile memory are connected in common, The coupling control information output from the nonvolatile memory is transmitted to the corresponding volatile memory circuit via the data bus by the coupling control information read setting operation such as the initialization operation by the control processing device such as the processing device. be able to. As a result, general-purpose usability of the nonvolatile memory can be ensured in terms of access to the nonvolatile memory by the control processing device.

  If a configuration in which a volatile memory circuit in a volatile memory is connected to the data bus is adopted, even if the number of the volatile memories increases, a special wiring for transmitting coupling control information such as relief information is added. There is no need to consider such things.

  If the total number of bits of the combined relief information is less than or equal to the number of bits of the data bus, the data bus signal line is connected to the data input terminal of each volatile memory circuit separately, thereby coupling control to all volatile memory circuits Information can be loaded in parallel.

  When the scale of the semiconductor integrated circuit is large, the frequency of coupling changes such as defects increases accordingly, and the possibility that the coupling control information will increase. When the data bus width, that is, the number of bits of the data bus is small with respect to the increased coupling control information, it is possible to load the coupling control information to each volatile memory circuit in series. That is, in this case, in response to a setting operation instruction such as an initialization instruction for the semiconductor integrated circuit, the coupling control information is read from the nonvolatile memory cell in a plurality of cycles and sequentially output to the data bus. In addition, the coupling control information supplied for each read cycle via the data bus may be taken in and held in the volatile memory circuit in order for each read cycle.

  In particular, in view of the increase in the degree of integration represented by system-on-chip, the following will be apparent. That is, the non-volatile memory is used so that the non-volatile memory that is one circuit module or memory module mounted on the large-scale integrated circuit as described above can be efficiently used in relation to another circuit module or memory module. The stored information is used for coupling control such as defect repair of a volatile memory different from the nonvolatile memory. In this case, the means for transferring the coupling control information via the data bus and the serial internal transfer divided into a plurality of cycles of the coupling control information are subject to coupling control such as a defect according to the large capacity of the volatile memory. When the amount of information increases, it is excellent in that processing for reflecting the information on each volatile memory can be realized at high speed with respect to the increase in the amount of information.

  In order to load the coupling control information to the volatile memory circuit with a simple configuration, the volatile memory circuit is a first that means a reset period instruction of a reset signal (RESET) that instructs the semiconductor integrated circuit to initialize. The coupling control information output from the non-volatile memory in response to the state is held, and the control is performed in response to a change of the reset signal from the first state to the second state which means reset release or termination. The processing device may start the reset exception processing. In this case, the reset signal needs to be maintained in the first state only for a period necessary for loading the coupling control information. In other words, the reset release timing by the reset signal must not be too early.

  The first state (reset period) of the reset signal (RESET) instructing the semiconductor integrated circuit to be initialized so that the loading operation of the coupling control information can be sufficiently performed without substantial restrictions on the reset release timing of the reset signal. A clock control circuit (19, 20) that is initialized in response can be provided. The clock control circuit causes the volatile memory circuit to capture and hold the coupling control information from the nonvolatile memory in response to the change of the reset signal from the first state to the second state, and then Causes the central processing unit to start reset exception handling.

  When the nonvolatile memory is rewritable, there is a risk that the coupling control information written in advance in the nonvolatile memory is erroneously rewritten. In order to eliminate such an inconvenience as much as possible, the nonvolatile memory can be set by the mode bit (MB2) between an operation mode that allows rewrite of the nonvolatile memory cell for storing repair information and an operation mode that inhibits the rewrite information. Good.

  In addition, an operation mode in which rewriting of the nonvolatile memory cell is permitted by a writing device connected to the outside of the semiconductor integrated circuit, and an operation mode in which rewriting of the nonvolatile memory cell is permitted in accordance with instruction execution by the central processing unit. It can also be set by the bit (MB1). In this way, the coupling control information can be written on the mounting board (that is, on board) or in the writing device. It is desirable to support an on-board write mode in order to easily realize a coupling change corresponding to a defect that occurs after the semiconductor integrated circuit is mounted.

  In order to update coupling control information such as a defect repair request by on-board writing, the nonvolatile memory may store a diagnostic program. The diagnostic program detects a defect in the nonvolatile memory and the volatile memory, and writes relief information for relieving a new defective memory cell to a nonvolatile memory cell for storing relief information in the nonvolatile memory. Processing is executed by the central processing unit.

  The third semiconductor integrated circuit (30) according to the present invention is obtained by extending the information stored and used in the nonvolatile memory (11) in addition to the repair information for the defect. That is, a control processing device such as a central processing unit (10) that shares a data bus (16) on a single semiconductor substrate, and a nonvolatile memory that is electrically rewritable and accessible by the control processing device A memory (11) and a volatile memory (12, 13) accessible by the control processing unit. Each of the nonvolatile memory and the volatile memory has register means (11AR, 12AR, 13AR, AR, 31DR, 12DR, and 13DR) whose data input terminals are connected to the data bus, and set to the corresponding register means. A part of each function is determined according to the function control information. The non-volatile memory has a plurality of non-volatile memory cells, some of which are non-volatile memory cells that store initialization data including the function control information. The nonvolatile memory also has an operation mode that allows rewriting of a nonvolatile memory cell for storing initialization data and an operation mode that inhibits the nonvolatile memory cell, and responds to an initialization instruction to the semiconductor integrated circuit. The initialization data is read from the cell and output. The register means fetches and holds initialization data from the nonvolatile memory in response to an initialization instruction for the semiconductor integrated circuit.

  In this third semiconductor integrated circuit, in order to reliably load initialization data having a large amount of data into each register means in response to a reset instruction, a first reset signal for instructing the semiconductor integrated circuit to perform initialization is used. A clock control circuit that is initialized in response to the state may be provided. The clock control circuit outputs a first timing signal of a plurality of phases whose activation timings are shifted in response to a state change such as a change of the reset signal from the first state to the second state. Thereafter, a second timing signal for causing the control processing device to start reset exception processing is output. The nonvolatile memory sequentially reads the initialization data from the nonvolatile memory cell in a plurality of cycles and outputs it to the data bus in response to the activation timing of the first timing signal of the plurality of phases. The register means performs an input setting operation for fetching and holding data on the data bus in order every read cycle of the initialization data from the nonvolatile memory.

  The nonvolatile memory can use the information held by the corresponding register means as repair information for repairing a defective normal nonvolatile memory cell by a redundant nonvolatile memory cell.

  The volatile memory can use the information held by the corresponding register means as repair information for repairing a defective normal volatile memory cell by a redundant volatile memory cell.

  The volatile memory has a dynamic memory cell as a volatile memory cell, and the information for holding the information stored in the register means corresponding to the volatile memory to define the refresh interval of the dynamic memory cell You may make it the structure utilized as information.

  The volatile memory may be configured to use information held by the corresponding register unit as control information for defining the timing of the internal control signal.

  In the third semiconductor integrated circuit, as described above, it is possible to efficiently change the coupling of a circuit having a large-scale logic configuration in which a volatile memory is mounted together with a nonvolatile memory. Therefore, cost reduction can be realized by improving the yield of a semiconductor integrated circuit having a large-scale logic.

  The nonvolatile memory is, for example, a flash memory, and a program executed by the control processing device can be stored in some nonvolatile memory cells. The volatile memory is, for example, a DRAM and can be used as a work memory of the central processing unit. The volatile memory can be a high-speed access memory made of, for example, SRAM.

  In a semiconductor integrated circuit (1A, 1B, 1C) including a volatile memory (12, 13) such as DRAM or SRAM as a memory module, the memory module is a volatile memory for storing remedy information relating to the memory array in a volatile manner. The memory circuit (12AR, 13AR) is included. The volatile memory circuit (12AR, 13AR) includes a plurality of input terminals or input nodes that can be coupled to a data bus to be formed in the semiconductor integrated circuit, and a relief such as an initialization operation of the semiconductor integrated circuit. And a control signal input terminal for receiving a control signal (reset) for an information read setting operation. The memory module includes a plurality of first volatile memory cells such as normal volatile memory cells and a plurality of second volatile memory cells such as redundant volatile memory cells. The memory circuits (12AR, 13AR) can hold relief information for enabling replacement of the first volatile memory cell by the second volatile memory cell.

  As described above, the relief information set in the volatile memory circuit (12AR, 13AR) is supplied from the outside of the memory module to the volatile memory circuit (12AR, 13AR) inside the memory module. Standardize or unify circuits or functional specifications related to defect relief of a memory module built in a semiconductor integrated circuit. Thereby, when selling the memory module as a memory module part, so-called IP (intellectual property) part, the usability of the memory module can be improved.

  Since the semiconductor integrated circuit including the memory module is designed by a design device composed of a computer (electronic computer), layout data, circuit function data, connection data, etc. for determining the configuration of the volatile memory circuit (12AR, 13AR). The design data is data described in a specific computer language that can be understood by the computer. The data is provided as a storage medium such as magnetic tape, MO (Magneto Optical Disk), CD-ROM or floppy disk (registered trademark). Further, the design data of the volatile memory circuits (12AR, 13AR) may be provided by being stored in a data storage medium together with design data of circuit functions of a memory module of a volatile memory such as DRAM or SRAM. Furthermore, the design data of the volatile memory circuits (12AR, 13AR) may be stored in a data storage medium in a state of being incorporated in the design data of a memory module of a volatile memory such as DRAM or SRAM. .

  As described above, the design of the memory module or the design data of the semiconductor integrated circuit including the memory module is stored in the storage medium as the design data described in a specific computer language that can be understood by the computer. The design or design of a semiconductor integrated circuit including the design can be performed efficiently.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the fuse program circuit for changing the connection such as defect relief is not required, the apparatus and process for cutting the fuse can be omitted, and the testing cost can be reduced. The manufacturing process is simplified because it is not necessary to form a laser-cut opening for the fuse. Since it is possible to rewrite the coupling control information for the non-volatile memory, the coupling change such as a defect that occurs later in the manufacturing process such as a burn-in process or a defect that occurs after mounting on a system or circuit board. Can fully meet the demand.

  This makes it possible to efficiently change the coupling of a circuit having a large-scale logic configuration in which a volatile memory is mounted together with a non-volatile memory together with a control processing device such as a central processing unit. Therefore, cost reduction can be realized by improving the yield of a semiconductor integrated circuit having a large-scale logic.

  In particular, in view of the increase in the scale of system-on-chip and the like, in order to efficiently use the nonvolatile memory mounted on the large-scale integrated circuit in relation to another circuit module, the storage information of the nonvolatile memory is concerned. Although it was used for coupling change of volatile memory other than the non-volatile memory, etc., means of transfer of coupling control information via the data bus and serial transfer divided into multiple cycles of coupling control information are as follows: When the chances of coupling change increase according to the large capacity of the volatile memory, the processing to reflect the information on each volatile memory can be realized at high speed with respect to the increase in the amount of control information. Are better.

《First single-chip microcomputer》
FIG. 1 shows a first single-chip microcomputer according to an example of a semiconductor integrated circuit of the present invention. A single-chip microcomputer 1A shown in the figure is formed as a system-on-chip system LSI formed on one semiconductor substrate made of single crystal silicon or the like.

  The single chip microcomputer 1A is a CPU (central processing unit) 10 representatively shown, a flash memory 11 as an example of a nonvolatile memory, a DRAM 12 as an example of a volatile memory, and another example of a volatile memory. An SRAM 13 and an input / output circuit 14 are included. Each of the memories 11, 12 and 13 can be regarded as a memory module. The CPU 10, flash memory 11, DRAM 12, SRAM 13 and input / output circuit 14 share an address bus 15, an N-bit data bus 16 and a control bus 17.

  The input / output circuit 14 is connected to the external address bus 18A, the external data bus 18D, the external control bus 18C, etc., and is connected to the buses 18A, 18D, 18C and the like (not shown). It has an output port, a bus controller for controlling the start of a bus cycle for the external buses 18A, 18D, and 18C, an input / output peripheral circuit represented by a serial interface circuit, and the like.

  The CPU 10 is not particularly limited, but includes a dedicated register such as an arithmetic logic unit (ALU), a program counter (PC), a stack pointer (SP), a status register (SR), and a general-purpose register group used as a work area. An execution unit, a program register stored in the flash memory 11 or an instruction register to which program instructions supplied from the operation system program are sequentially input, and an instruction stored in the instruction register is decoded, And a control unit including an instruction decoder that generates a control signal for the execution unit. The execution unit is coupled to the address bus 15, the data bus 16, and the control bus 17, and outputs a selective address signal to the address bus 15, a selective control signal to the control bus, and data. Controls the input / output of data via the bus. Therefore, the CPU 10 controls the operation of the semiconductor integrated circuit as a whole in accordance with the program data or the operation system program stored in the flash memory 11.

  The DRAM 12 is a relatively large capacity read / write memory that is used as a work memory or main memory of the CPU 10. The DRAM 12 has a large capacity of, for example, several gigabits according to the scale of the system. The memory cell array 12MA of the DRAM 12 has redundant word lines WLdR in addition to the regular word lines WLd_0 to WLd_Nd. A normal dynamic memory cell selection terminal is coupled to normal word lines WLd_0 to WLd_Nd, and a redundant dynamic memory cell selection terminal is coupled to redundant word line WLdR. The difference in the configuration of the memory cell between the regular use and the redundancy use need not be set. Which of the normal word lines WLd_0 to WLd_Nd is to be replaced with the selection of the redundant word line WLdR is determined by the repair information set in the repair address register 12AR. The repair row address information included in the repair information is compared with the row address signal from the address buffer 12AB by the address comparison circuit 12AC. When the comparison result matches, the address comparison circuit 12AC supplies a detection signal 12φ having a logical value “1” to the X decoder 12XD. When the detection signal 12φ is a logical value “1”, the X decoder 12XD suppresses the word line selection operation by the row address from the address buffer 12AB, and selects the redundant word line WLdR instead. Thereby, the memory access related to the defective word line is replaced with the selection operation of the redundant memory cell related to the redundant word line WLdR. Other configurations of the DRAM 12 will be described later.

  The SRAM 13 is used as a high-speed access memory such as a register file or a data buffer memory. The memory cell array 13MA of the SRAM 13 has redundant word lines WLsR in addition to the normal word lines WLs_0 to WLs_Ns. The normal word lines WLs_0 to WLs_Nd are coupled to the selection terminals of normal static memory cells, and the redundant word lines WLsR are coupled to the selection terminals of redundant static memory cells. Which of the normal word lines WLs_0 to WLs_Ns is replaced with the selection of the redundant word line WLsR is determined by the repair information set in the repair address register 13AR. The repair row address information included in the repair information is compared with the row address signal from the address buffer 13AB by the address comparison circuit 13AC. When the comparison result matches, the address comparison circuit 13AC gives the detection signal 13φ having the logical value “1” to the X decoder 13XD. When the detection signal 13φ is the logical value “1”, the X decoder 13XD suppresses the word line selection operation by the row address from the address buffer 13AB, and selects the redundant word line WLsR instead. As a result, the memory access related to the defective word line is replaced with the selection operation of the redundant memory cell related to the redundant word line WLsR. Other configurations of the SRAM 13 will be described later.

  The flash memory 11 has a memory cell array 11MA in which electrically rewritable nonvolatile memory cells having a control gate and a floating gate are arranged in a matrix. The memory cell array 11MA is used as an area for storing the operation program of the CPU 10 and the relief information of the DRAM 12 and SRAM 13. The memory cell array 11MA includes word lines WLf_0 to WLf_Nf coupled to the control gates of the nonvolatile memory cells and bit lines BLf_0 to BLf_Mf coupled to the drains of the nonvolatile memory cells. It should be understood that N sets of word lines WLf_0 to WLf_Nf and bit lines BLf_0 to BLf_Mf are provided in the front and back direction of the sheet of FIG. In this example, N bits of non-volatile memory cells arranged at positions where the word line WLf_0 and the bit line BLf_0 cross each other serve as a storage area for the relief information. The sequence controller 11SQ performs timing control such as erase, write, verify, and read operations of the flash memory 11. The operation instruction is not particularly limited, but is given by a command from the CPU 10 or the like. Although not particularly limited, the flash memory 11 can be erased in units of word lines.

  The CPU 10 fetches and decodes an instruction stored in the flash memory 11 or the like, acquires an operand necessary for executing the instruction from the DRAM 12 or SRAM 13 or the like according to the decoding result, performs an operation on the acquired operand, and outputs the operation result. Is again stored in the DRAM 12 or the SRAM 13, and a series of data processing described in the program is performed. When the reset signal RESET is set to the high level, the CPU 10 aborts all of the processes being executed and initializes a required node of the internal circuit to a predetermined logical value state. In this reset period (high level period of the reset signal RESET), not only the initialization inside the CPU 10 but also the internal registers of peripheral circuits (not shown) are initialized. Further, the relief address registers 12AR and 13AR described below are initialized. The reset signal RESET is changed to a high level in response to any instruction such as a power-on reset or a system reset by turning on the operating power. When the reset signal RESET is negated to a low level, the CPU 10 starts reset exception processing. Initialization in the CPU 10 during the reset period is performed on control registers such as a program counter, a stack pointer, and a status register. In the case of a power-on reset, the operation of the clock generation circuit is stabilized after the power is turned on until the reset is released, and a stable clock signal can be supplied to the CPU 10 and the like after the reset is released. Is done. Although the clock pulse generator is not shown in FIG. 1, the clock pulse generator is actually provided with a vibrator and a frequency dividing circuit, and the clock signal is sent to various internal circuits such as the CPU 10 and the operation reference clock signal. It comes to supply.

  The flash memory 11 performs relief information read operation in response to the reset period of the reset signal RESET. That is, when the sequence controller 11SQ detects the reset period, it activates the sense amplifier 11SA and the output buffer 11OB so that the read operation is possible. The X decoder 11XD and the Y decoder 11YD select the word line WLf_0 and the bit line BLf_0 in response to the reset period indicated by the reset signal RESET. As a result, the storage information of the N-bit memory cell storing the relief information is output to the N-bit data bus 16.

  The relief address registers 12AR and 13AR have static latches for N / 2 bits, for example, for storing relief information. Although not particularly limited, the data input terminal of the static latch constituting the relief address register 12AR is electrically connected to the lower N / 2 bits of the N-bit data bus 16 during the high level (logical value “1”) of the reset signal RESET. The data input during that time can be latched by inverting the reset signal RESET to low level. The data input terminal of the static latch constituting the other relief address register 13AR is made conductive to the upper N / 2 bits of the N-bit data bus 16 during the high level (logical value “1”) of the reset signal RESET. Can be latched by inverting the reset signal RESET to a low level. Therefore, when the reset period ends, the lower side relief information read from the flash memory 10 to the data bus 16 is latched in the relief address register 12AR of the DRAM 12, and the upper side relief information is latched in the relief address register 13AR of the SRAM 13. Is done. Thereafter, in the DRAM 12 and the SRAM 13, if there is an access to the row address specified by the repair information, the repair using the redundant word line is performed.

  FIG. 2 shows a detailed example of relief information. In this example, the relief information is a maximum of N bits in total as described above. In the repair information of the SRAM 13, AS3 to AS0 are repair target row address information, and RE_S is an SRAM repair enable bit indicating the validity of the repair target row address information. This bit RE_S indicates the validity of the row address information AS3 to AS0 by the logical value “1”. The SRAM repair enable bit RE_S loaded in the repair address register 13AR activates the address comparison circuit 13AC when the logical value is “1”, and deactivates the address comparison circuit 13AC when the logical value is “0”. The detection signal 13φ is fixed to the mismatch level “0”. Similarly, in the relief information of the DRAM 12, AD3 to AD0 are relief target row address information, and RE_D is a DRAM relief enable bit indicating the validity of the relief target row address information. The bit RE_D indicates the validity of the row address information AD3 to AD0 by a logical value “1”. The DRAM repair enable bit RE_D loaded in the repair address register 12AR activates the address comparison circuit 12AC when the logic value is “1”, and deactivates the address comparison circuit 12AC when the logic value is “0”. The detection signal 12φ is fixed to the mismatch level “0”.

  FIG. 3 shows the timing of the initial loading process of relief information during the reset period. A reset period is a period in which the reset signal RESET is at a high level due to a power-on reset upon power-on or a system reset. When the supplied power is stabilized, the word line WLf_0 and the Y selector YSf_0 are selected, and the relief information of the DRAM 12 and the SRAM 13 is read in parallel to the data bus 16. The read relief information of the DRAM 12 is loaded into the relief address register 12AR, the relief information of the SRAM 13 is loaded into the relief address register 13AR, and the load data is latched by reset release.

  In FIG. 1, the sequence controller 11SQ of the flash memory 11 has a mode register 11MR, and determines the operation of the flash memory 11 according to the setting contents of the mode register 11MR.

  The mode register 11MR has a write enable bit for instructing a write operation, an erase enable bit for instructing an erase operation, and the like, as in a known flash memory. When a write operation and an erase operation are instructed by the write enable bit and the erase enable bit (not shown), the accessible range in the memory cell array 11MA is determined by the set state of the mode bit MB2. Further, the access subject at that time is determined by the value of the mode bit MB1. That is, the mode register 11MR can be accessed via the data bus 16, but the value of the external terminal P1 of a single chip microcomputer (hereinafter also simply referred to as a microcomputer) 1A is directly assigned to a specific mode bit MB1. It can also be reflected. The mode bit MB1 is a bit for designating an operation mode (EPROM writer mode) that permits rewriting to the flash memory 11 by a writing device such as an EPROM writer connected to the outside of the microcomputer. When the mode bit MB1 is set to the logical value “1”, the microcomputer 1A apparently changes the function of the external input / output circuit 14 so that it has an external interface function equivalent to a semiconductor integrated circuit (bus slave) of a single flash memory. In addition, the operation of the CPU 10 is also stopped. That is, in response to the logical value “1” of the mode bit MB1, the buffer circuit coupled to the address bus 15, the data bus 16, and the control bus 17 of the CPU 10 is set to a high impedance state, and the CPU 10 16 and 17 are electrically disconnected. In this EPROM writer mode, the external input / output circuit 14 inputs an address signal from the outside, supplies it to the address bus 15, and outputs the data on the data bus 16 to the outside in response to a read operation instruction by a read signal from the outside. In addition, data is input and supplied to the data bus 16 in response to a write operation instruction by an external write signal. On the other hand, when the mode bit MB1 is a logical value “0”, the flash memory 11 is made accessible under the control of the CPU 10. That is, the buffer circuit coupled to the buses 15, 16, and 17 of the CPU 10 electrically connects the CPU 10 to the buses 15, 16, and 17 in response to the logical value “0” of the mode bit MB1.

  The mode bit MB2 of the mode register 11MR is a control bit that determines whether or not rewriting to the nonvolatile memory cell for storing repair information that can be selected by the word line WLf_0 and the Y selector YSf_0 is permitted. Relief information can be rewritten by “0”, and renewal of repair information is prevented by a logical value “1”. When the mode bit MB2 is a logical value “1”, the sequence controller 11SQ sets the level of the word line WLf_0 to a voltage that prevents both erasing and writing, for example, 0 V, regardless of the row address signal in the erasing operation and the writing operation. To do. As a result, the erase operation performed in units of word lines and the write operation performed in units of N bits are completely prevented for the memory cells connected to the word line WLf_0. When the mode bit MB2 is a logical value “0”, erasing and writing can be freely performed on the memory cells of the word line WLf_0.

  In the microcomputer 1A in which the operation mode can be set, defect relief for the DRAM 12 and the SRAM 13 is first performed by a chip formed by a wafer process by the manufacturer of the microcomputer 1A as illustrated in FIG. Can be performed on the result of the first probe test (S1) for (S2). In the repair at this time, the microcomputer 1A is set to the EPROM writer mode by the mode bit MB1, the flash memory 11 can be accessed using a dedicated writing device such as a tester or an EPROM writer, and the mode bit MB2 is set to the logical value “0”. Thus, the relief information is written in a predetermined area of the flash memory 11. After that, probe inspection is performed again (S3), packaging (S4), power supply voltage Vdd is made higher than that during normal operation, and burn-in test (S5) is performed to test the reliability. Done. A defective product for which a new defect is discovered due to the influence of burn-in test or the like can be given an opportunity for defect repair (S7). For example, when a defect is revealed in the microcomputer 1A having no defect in step S2 by a burn-in test or the like, the defect can be relieved in the same manner as described above (S7). After the defect relief product is sorted again (S8), the product is shipped (S9). The user who purchased the product mounts the microcomputer on a required circuit board, and the mounted circuit is operated as appropriate (S10). During this operation, the mode bit MB2 is set to the logical value “1” so that the repair information cannot be rewritten by mistake. The microcomputer 1A operated in this on-board state is caused to execute a test program (diagnostic program) for defect diagnosis as necessary to determine the presence / absence of a defect. In this state, defect relief can be performed via the CPU 10 built in the microcomputer 1A (S11). For example, a microcomputer 1A that has no defects at all in the manufacturing process has a defect due to deterioration in characteristics of circuit elements or circuit elements over time, or a new one according to changes in the operating environment such as operating temperature and operating voltage. If a defect occurs, it can be dealt with. Compared with FIG. 4B, which is a defect repair technique using a fuse, the repairable time increases more than three times.

  The diagnostic program for defect relief by on-board writing and the writing program executed at the time of on-board writing can be stored in an area other than the word line WLf_0 of the flash memory 11. The execution of the diagnostic program may be arbitrarily instructed to the CPU 10 by interruption or the like, or may be automatically executed using a timer or the like. The contents of the diagnostic program are not shown in detail here, but a predetermined test pattern is written to the SRAM 12 and the DRAM 13 and then read, and the read data and the expected value data are compared to determine the presence or absence of a defect. For example, a process for checking whether there is a redundant redundant configuration is performed. If there is a redundant configuration that can be relieved, the CPU 10 is caused to execute the write program in order to write relief information for relieving the defect into the nonvolatile memory cell for storing relief information in the flash memory 10. Then, a process for writing relief information to a predetermined memory cell of the flash memory 11 is performed. If there is no redundant configuration that can be relieved, the CPU 10 can set an error status bit and perform an interrupt process (for example, display of a service man call) accordingly.

  In the single-chip microcomputer 1A as the system LSI, a fuse program circuit for defect repair is not required, and a device and a process for cutting a fuse can be omitted, and the testing cost can be reduced. The manufacturing process is simplified because the fuse program circuit is not used even in the case where the process of forming the laser cutting opening of the fuse is complicated, such as a copper wiring system process. For example, as illustrated in FIG. 5, on the lowermost polysilicon wiring layer 102 on the silicon substrate (Si substrate) 100 made of single crystal silicon on which a circuit element such as a MOSFET (not shown) is formed on the surface thereof. Assuming that there are copper wiring layers formed through titanium nitride (TiN) layers 105, 111, 117, etc., from the first layer 106 to the fifth layer (112, 118, 124, 130), respectively, a polycrystal that can be fused by laser fusing. When forming the opening 133 for exposing the silicon fuse through the final passivation film 132, a number of silicon nitride (SiN) layers 131, which are etching stoppers when forming a wiring buried groove for planarizing the wiring layer, Etching 127, 125, 121, 119, 115, 113, 109, 107, 103 at once Since it is difficult to remove, the etching gas for etching the interlayer insulating films (silicon oxide) 128, 126, 122, etc. and the etching gas for the SiN layer must be switched alternately several times, and the number of manufacturing processes is remarkably increased. It will increase. Unless a fuse program circuit is used for defect relief, no problem occurs in the process using copper wiring. That is, the semiconductor integrated circuit 1A of the present invention or the semiconductor integrated circuits 1B and 1C described later have a device structure in which the fuse 102C is omitted from the device cross-sectional view of FIG. As a result, it is possible to provide semiconductor integrated circuits 1A, 1B, and 1C that have low wiring resistance and are capable of high-frequency operation.

  In addition, since the repair information for the flash memory 11 can be rewritten, a defect generated after burn-in can be newly repaired. Can also be remedied.

  As a result, together with the CPU 10, the relief efficiency is improved against a defect in a circuit such as a single-chip microcomputer 1 A having a large-scale logical configuration in which a volatile memory such as a DRAM 12 or an SRAM 13 is mounted together with the flash memory 11. Can do. Therefore, cost reduction can be realized by improving the yield of the semiconductor integrated circuit 1A having a large-scale logic.

  Here, a supplementary description will be given of the configuration of the DRAM 12, SRAM 13, and flash memory 11 that has not been described above.

<< DRAM >>
In the DRAM 12, the memory cell array 12MA includes an address selection MOSFET QS and an information holding capacitor CS as illustrated in FIG. 6, and the gate of the MOSFET QS as a selection terminal is connected to the corresponding word line WL, and data A large number of well-known dynamic memory cells DMC, in which the drain or source of the MOSFET QS as an input / output terminal is connected to the corresponding bit line BL, are provided. One electrode of the capacitor CS is a common electrode PL, and is supplied with a predetermined power supply equal to half of the power supply voltage. As illustrated in FIG. 7, the memory cell array 12MA has a known folded bit line structure with respect to the sense amplifier SAd in the static latch form, and includes bit lines BLd_0 to BLd_Md. Word lines WLd_0 to WLd_Nd are arranged in a direction crossing the bit lines BLd_0 to BLd_Md, and a redundant word line WLdR for defect relief is further provided. Although not specifically shown, it is also possible to employ redundant bit lines. Bit lines BLd_0 to BLd_Md are commonly connected to a common data line 12CD via Y selectors YSd_0 to YSd_Md. As shown in FIG. 1, one of the word lines WLd_0 to WLd_Nd and the redundant word line WLdR is selected by an X decoder 12XD. One of the Y selectors YSd_0 to YSd_Md is turned on by the decode output of the Y decoder 12YD. In FIG. 1, it is understood that N sets of the memory cell array 12MA and the Y selectors YSd_0 to YSd_Md are provided in the front and back direction of the paper surface. Therefore, when the selection operation by the X decoder 12XD and the Y decoder 12YD is performed, data is input / output to / from the common data line 12CD in units of N bits. Write data is supplied from the data bus 16 to the input buffer 12IB, and the write buffer 12WB drives the bit line via the common data line 12CD in accordance with the input data. In the data read operation, read data transmitted from the bit line to the common data line 12CD is amplified by the main amplifier 12MA, and this is output from the output buffer 12OB to the data bus 16.

  Relief information for specifying the row address of the normal word line to be relieved by the redundant word line WLdR is set in the relieve address register 12AR. The relief address register 12AR is composed of a multi-bit static latch, and its data input terminal is made conductive to the data bus 16 in response to the high level of the reset signal RESET, and relief information is loaded from the data bus 16. When the loaded relief information is valid, the relief information is compared with the row address signal from the address buffer 12AB by the address comparison circuit 12AC. When the comparison result is coincident, the detection signal 12φ is set to the logical value “1”, and otherwise, it is set to the logical value “0”. The X decoder 12XD and the Y decoder 12YD are supplied with the address signal of the address bus 15 via the address buffer 12AB, and decode the supplied address signal. In particular, the X decoder 12XD decodes the row address signal from the address buffer 12AB when the detection signal 12φ supplied from the address comparison circuit 12AC is a logical value “0”, which means a mismatch, but the detection signal 12φ means a match. When the logical value is “1”, decoding of the row address signal from the address buffer 12AB is prohibited, and the redundant word line WLdR is selected instead. Thereby, the memory access related to the defective word line is replaced with the selection operation of the redundant memory cell related to the redundant word line WLdR.

  The internal timing control of the DRAM 12 is performed by the timing controller 12TC. The timing controller 12TC is supplied with a strobe signal such as a read signal and a write signal from the CPU 10 via the control bus 17 and a multi-bit address signal which is regarded as a memory selection signal from the address bus 15. When the operation selection of the DRAM 12 is detected by the timing controller 12CT, circuits such as the X decoder 12XD are activated, and when the read operation is instructed by the read signal, the storage information of the memory cell selected by the memory cell array 12MA Is output to the data bus 16 via the main amplifier 12MA and the output buffer 12OB, and when the write operation is instructed by the write signal, the memory cell selected in the memory cell array 12MA includes the input buffer 12IB and the write buffer 12WB. The data input via is written.

<< SRAM >>
The SRAM 13 includes a number of known CMOS static memory cells SMC as illustrated in FIG. 8 in the memory cell array 13MA. That is, the CMOS static memory cell SMC includes P-channel MOSFETs QP1 and QP2 and N-channel MOSFETs QN1 to QN4 as shown in FIG. Each of QP1 and QN1 and each of QP2 and QN2 are considered to constitute a CMOS inverter, and an input terminal and an output terminal thereof are cross-connected to constitute one CMOS latch circuit as a whole. QN3 and QN4 constitute a selection switch. The gates of QN3 and QN4 constitute a selection terminal of the memory cell and are connected to the corresponding word line WL. The drains or sources of QN3 and QN4 connected to the corresponding pair of bit lines BL and BBL are used as data input / output terminals of the memory cells. The memory cell may be configured in a resistive load type static latch configuration. As illustrated in FIG. 9, the memory cell array 13MA includes complementary bit lines BLs_0 and BLBs_0 to BLs_Ms and BLBs_Ms. Word lines WLs_0 to WLs_Ns are arranged in a direction crossing the complementary bit lines BLs_0, BLBs_0 to BLs_Ms, BLBs_Ms, and redundant word lines WLsR for defect relief are further provided. Although not specifically shown, it is also possible to employ redundant bit lines. The complementary bit lines BLs_0, BLBs_0 to BLs_Ms, BLBs_Ms are commonly connected to the common data line 13CD via the Y selectors YSs_0, YSBs_0 to YSs_Ms, YSBs_Ms. As shown in FIG. 1, one of the word lines WLs_0 to WLs_Ns and the redundant word line WLsR is selected by an X decoder 13XD. A pair of Y selectors YSs_0, YSBs_0 to YSs_Ms, YSBs_Ms is turned on by the decode output of the Y decoder 13YD. In FIG. 1, it should be understood that N sets of the memory cell array 13MA and Y selectors YSs_0, YSBs_0 to YSs_Ms, YSBs_Ms are provided in the front and back direction of the paper surface. Therefore, when the selection operation by the X decoder 13XD and the Y decoder 13YD is performed, data is input / output to / from the common data line 13CD in units of N bits. Write data is supplied from the data bus 16 to the input buffer 13IB, and the write buffer 13WB drives the bit line via the common data line 13CD according to the input data. In the data read operation, read data transmitted from the bit line to the common data line 13CD is amplified by the sense amplifier 13SA, and this is output from the output buffer 13OB to the data bus 16.

  Relief information for specifying the row address of the normal word line to be relieved by the redundant word line WLsR is set in the relieve address register 13AR. The relief address register 13AR is composed of a multi-bit static latch, and its data input terminal is made conductive to the data bus 16 in response to the high level of the reset signal RESET, and relief information is loaded from the data bus 16. When the loaded relief information is valid, the relief information is compared with the row address signal from the address buffer 13AB by the address comparison circuit 13AC. When the comparison result is coincident, the detection signal 13φ is set to the logical value “1”, and otherwise, it is set to the logical value “0”. The X decoder 13XD and the Y decoder 13YD are supplied with the address signal of the address bus 15 via the address buffer 13AB and decode the supplied address signal. In particular, the X decoder 13XD decodes the row address signal from the address buffer 13AB when the detection signal 13φ supplied from the address comparison circuit 13AC has a logical value “0”, which means a mismatch, but the detection signal 13φ means a match. When the logical value is “1”, decoding of the row address signal from the address buffer 12AB is prohibited, and the redundant word line WLsR is selected instead. As a result, the memory access related to the defective word line is replaced with the selection operation of the redundant memory cell related to the redundant word line WLsR.

  The internal timing control of the SRAM 13 is performed by the timing controller 13TC. A strobe signal such as a read signal and a write signal is supplied from the CPU 10 to the timing controller 13TC via the control bus 17, and a multi-bit address signal regarded as a memory selection signal is supplied from the address bus 15. When the operation selection of the SRAM 13 is detected by the timing controller 13CT, circuits such as the X decoder 13XD are activated, and when the read operation is instructed by the read signal, the storage information of the memory cell selected by the memory cell array 13MA Is output to the data bus 16 via the sense amplifier 13SA and the output buffer 13OB, and when the write operation is instructed by the write signal, the memory cell selected by the memory cell array 13MA includes the input buffer 13IB and the write buffer 13WB. The data input via is written.

<Flash memory>
The flash memory 11 includes a large number of nonvolatile memory cells (flash memory cells) FMC illustrated in FIG. 10 in the memory cell array 11MA. The memory cell FMC is composed of one memory cell transistor having a control gate (CG), a floating gate (FG), a source (SC), and a drain (DR). As illustrated in FIG. 11, the memory cell array 11MA includes bit lines BLf_0 to BLf_Mf to which the drains of the flash memory cells FMC are coupled, word lines WLf_0 to WLf_Nf to which the control gates of the flash memory cells FMC are coupled, and flash memory. It has a source line SLf to which the source of the cell FMC is coupled. Although not particularly limited, in this example, the source line SLf is shared by the memory cells FMC. The bit lines BLf_0 to BLf_Mf are commonly connected to the common data line 11CD via the Y selectors YSf_0 to YSf_Mf. As shown in FIG. 1, the selection operation for the word lines WLf_0 to WLf_Nf is performed by an X decoder 11XD. The supply voltage for the selected word line and the unselected word line is controlled by the sequence controller 11SQ according to the erase, write, and read operations. One of the Y selectors YSf_0 to YSf_Mf is turned on by the decode output of the Y decoder 11YD. In FIG. 1, it should be understood that the memory cell array 11MA and the Y selectors YSf_0 to YSf_Mf are provided in N sets in the front and back direction of the paper. Therefore, when the selection operation by the X decoder 11XD and the Y decoder 11YD is performed, data can be input / output between the memory cell and the common data line 11CD in units of N bits. Write data is supplied from the data bus 16 to the input buffer 11IB, and the write buffer 11WB drives the bit line via the common data line 11CD according to the input data. In the data read operation, read data transmitted from the bit line to the common data line 11CD is amplified by the sense amplifier 11SA, and this is output from the output buffer 11OB to the data bus 16. In this example, the erase operation is performed in units of word lines. The source line voltage not shown in FIG. 1 is supplied from the sequence controller 11SQ with a source line voltage corresponding to each operation mode of erasing, writing, and reading.

  The sequence controller 11SQ performs sequence control and voltage control of the flash memory 11. Here, a voltage control mode by the sequence controller 11SQ will be described. First, the memory cell FMC (N-channel MOS memory cell transistor) can hold information according to the amount of charge in the floating gate. For example, when charge is injected into the floating gate, the threshold voltage of the memory cell increases. By increasing the threshold voltage above the voltage value applied to the control gate, the memory current stops flowing. Further, the threshold voltage is lowered by discharging the charge from the floating gate. By making the threshold voltage lower than the voltage value applied to the control gate, the memory current flows. For example, as illustrated in FIG. 12, a low threshold voltage state is a “0” information holding state (for example, a writing state), and a high threshold voltage state is a “1” information holding state (for example, an erasing state). Can be assigned. Since this is a definitional matter, there is no problem even if the opposite definition is given. The memory operation is roughly divided into read, program, and erase. Write verify and erase verify are substantially the same as read.

  In the read operation, a read potential (for example, Vcc = 5 V) is applied to the control gate CG. The stored information of the selected memory cell at this time is determined as “0” or “1” depending on whether or not a current flows through the memory cell. In erasing, as illustrated in FIG. 13, a positive voltage (for example, 10V) is applied to the control gate CG, and a negative voltage (for example, −10V) is applied to the source of the memory cell. The drain DR may be floating, or may have the same negative voltage (eg, −10 V) as the well. This makes it possible to inject charges into the floating gate by the tunnel effect. As a result, the threshold voltage of the memory cell FMC increases. Erase verification is substantially the same as the read operation except that the word line voltage for verification is different. In writing, as illustrated in FIG. 13, a negative potential (for example, −10 V) is applied to the control gate CG, a positive voltage (for example, 7 V) is applied to the drain DR, and the source SC is floated. As a result, charge is discharged only to the memory cell in which a positive voltage is applied to the drain. As a result, the threshold voltage of the memory cell FMC decreases. The subsequent write verify operation is performed in the same manner as the above read operation.

<< second single-chip microcomputer >>
FIG. 14 shows a second single-chip microcomputer which is another example of the semiconductor integrated circuit according to the present invention. The single-chip microcomputer 1B shown in the figure is different from that shown in FIG. 1 in having a redundant configuration for defect relief. That is, the memory cell array 11MA has redundant word lines WLfR in addition to the normal word lines WLf_0 to WLf_Nf. The control gates of the memory cells FMC are also coupled to the redundant word line WLfR, and their drains are coupled to the corresponding bit lines and the sources are coupled to the source lines. Which of the normal word lines WLf_0 to WLf_Nf is to be replaced with the selection of the redundant word line WLfR is determined by the repair information set in the repair address register 11AR. The relief row address information included in the relief information is compared with the row address signal from the address buffer 11AB by the address comparison circuit 11AC. When the comparison results match, the address comparison circuit 11AC gives a detection signal 11φ having a logical value “1” to the X decoder 11XD. When the detection signal 11φ is the logical value “1”, the X decoder 11XD suppresses the word line selection operation by the row address from the address buffer 11AB, and selects the redundant word line WLfR instead. As a result, the memory access related to the defective word line is replaced with the selection operation of the redundant memory cell related to the redundant word line WLfR.

  In this configuration, the reading of the relief information to the data bus 16 during the reset period is the same as the configuration in which it is performed once as in the case of FIG. Therefore, in the case of FIG. 14, all N bits of relief information must be distributed to three relief address registers 11AR, 12AR, and 13AR at a time. In order to satisfy this, the data input terminals of the three relief address registers 11AR, 12AR, and 13AR are separately coupled without overlapping with the signal lines of the respective bits of the N-bit data bus.

  FIG. 15 shows an example of relief information stored in the relief information storage area of the flash memory 11. Compared to FIG. 2, the repair row addresses AF3 to AF0 of the flash memory 11 and the repair enable bit RE_F of the flash memory are increased. If the relief information read out to the data bus 16 is N bits in total, the signal lines of the data bus 16 are coupled to the data input terminals of the corresponding relief address registers 11AR, 12AR, 13AR while maintaining the arrangement of FIG. ing. The bit RE_F indicates the validity of the row address information AF3 to AF0 by a logical value “1”. The relief enable bit RE_F loaded in the relief address register 11AR activates the address comparison circuit 11AC when the logical value is “1”, and keeps the address comparison circuit 11AC in an inactive state when the logical value is “0”. Thus, the detection signal 11φ is fixed to the mismatch level “0”.

  FIG. 16 shows the timing of initial load processing of relief information during the reset period. A reset period is a period in which the reset signal RESET is at a high level due to a power-on reset upon power-on or a system reset. When the supplied power is stabilized, the word line WLf_0 and the Y selector YSf_0 are selected, and the relief information of the flash memory 11, DRAM 12 and SRAM 13 is read in parallel to the data bus 16. The read relief information of the flash memory 11 is loaded into the relief address register 11AR, the relief information of the DRAM 12 is loaded into the relief address register 12AR, the relief information of the SRAM 13 is loaded into the relief address register 13AR, and the load data is latched by reset release. .

  According to the single chip microcomputer 1B, it is possible to relieve defects that occur in the flash memory 11. The other points are the same as those of the single chip microcomputer 1A shown in FIG. 1, and detailed description thereof is omitted.

<< Third single-chip microcomputer >>
FIG. 17 shows a third single-chip microcomputer as still another example of the semiconductor integrated circuit according to the present invention. In the single-chip microcomputer 1C shown in the figure, the operation for reading relief information from the flash memory is performed in a plurality of cycles, and the plurality of relief address registers are configured to latch data in order for each relief information read cycle. Is different from that of FIG. That is, the single-chip microcomputer 1C is provided with a clock pulse generator (CPG) 19 and a control circuit 20 as a clock control circuit that is initialized in response to a reset instruction (reset period) by a reset signal RESET.

  The clock pulse generator 19 includes, for example, an oscillation circuit using an oscillator, a frequency divider circuit, a PLL circuit, and the like. When the operation power is turned on and the reset signal RESET is asserted, the internal operation is stabilized and a clock signal can be generated. In response to the reset signal RESET being negated, the clock signal CLKR is generated. As exemplified in FIG. 18, the clock signal CLKR is not particularly limited, but is generated three times, and is supplied to the control circuit 20. The CPU 10 is initialized by a reset signal RST generated from the clock pulse generator 19. The CPU 10 is reset until the third clock signal CLKR is generated, as illustrated in FIG. When the reset period by the reset signal RST ends, the CPU 10 starts reset exception processing in synchronization with the clock signal CLK generated from the clock pulse generator 19.

  In the reset period by the reset signal RST for the CPU 10, the control circuit 20 performs initial load control of relief information. That is, as illustrated in FIG. 18, the control circuit 20 asserts the control signal φW0 during the first cycle and the second cycle of the clock signal CLKR, and asserts the control signal φB0 in response to the first cycle. Then, the control signal φB1 is asserted in response to the second cycle. The sequence controller 11SQ activates the sense amplifier 11SA and the output buffer 11OB in response to the assertion period of the control signal φW0, and controls the voltage of the flash memory so that a read operation is possible. The X decoder 11XD gives a read selection level to the word line WLf_0 in response to the assertion period of the control signal φW0. The Y decoder 11YD selects the bit line BLf_0 by the Y selector YSf_0 during the assertion period of the control signal φB0. As a result, during the assertion period of control signal φB0 (the first cycle of clock signal CLKR), relief information is read from data memory 16 to N-bit memory cells at the intersection of word line WLf_0 and bit line BLf_0. At this time, the control signal φB0 is supplied to the relief address register 12AR of the DRAM 12, and the data on the data bus 16 is input during the high level period of the control signal φB0 and the input data is latched by the low level. Is latched in the relief address register 12AR. Further, the Y decoder 11YD selects the bit line BLf_1 by the Y selector YSf_1 in the assertion period of the next control signal φB1. As a result, during the assertion period of control signal φB1 (second cycle of clock signal CLKR), relief information is read from data memory 16 to N-bit memory cells at the intersection of word line WLf_0 and bit line BLf_1. At this time, the control signal φB1 is supplied to the relief address register 13AR of the SRAM 13, and the register 13AR inputs the data on the data bus 16 during the high level period of the control signal φB1, and latches the input data according to the low level. The relief information is latched in the relief address register 13AR.

  Therefore, the relief information of the DRAM 12 is stored in the memory cell at the intersection of the word line WLf_0 and the bit line BLf_0, and the relief information of the SRAM 13 is stored in the memory cell at the intersection of the word line WLf_0 and the bit line BLf_1. Then, in response to the reset instruction of the single chip microcomputer 1C, the repair information can be internally transferred to the DRAM 12 and the SRAM 13 in order in N bits. The number of internal transfers of relief information for one circuit is not limited to one, but can be determined as appropriate according to the redundant logical scale proportional to the logical scale of the circuit. For example, the number of control signals supplied to the Y decoder may be increased, a separate Y selector may be selected for each control signal, and the number of relief address registers of a circuit for inputting relief information may be increased as necessary. In the case of the configuration described with reference to FIG. 1, the period of the initial loading operation of the repair information depends on the reset period of the reset signal RESET. When the amount of relief information to be initially loaded is large, the reset period by the reset signal RESET must be controlled outside the microcomputer. In the case of FIG. 17, after the operation of the clock pulse generator 19 is stabilized by the reset signal RESET, the control circuit 20 in the microcomputer 1C autonomously controls the initial load processing of the repair information, so that the initial load is performed. Even when there is a large amount of relief information to be repaired, initial loading of the relief information can be reliably performed without requiring a special operation outside the microcomputer. The other points are the same as those of the single chip microcomputer 1A shown in FIG. 1, and detailed description thereof is omitted.

  In view of the increase in the degree of integration represented by system-on-chip and the like, the flash memory 11 which is one circuit module mounted on the large-scale integrated circuit is efficiently connected with another circuit module. In order to use it, information stored in the flash memory 11 is used for defect relief of the SRAM 13 or DRAM 12 different from the flash memory 11. At this time, the configuration by the internal transfer of the relief information via the data bus 16 and the serial internal transfer divided into a plurality of cycles of the relief information is proportional to the increase in the defect according to the large capacity of the SRAM 13 or the DRAM 12. When the amount of repair information increases, it is important in that the processing for reflecting the information on each SRAM 13 or DRAM 12 can be realized at high speed with respect to an increase in the amount of repair information.

《Block replacement》
The replacement to redundancy described so far has been performed by address comparison. However, as illustrated in FIG. 19, it can also be performed by replacement of a memory mat or memory block. For example, memory mats MAT0 to MAT7 are memory blocks in which normal memory cells are arranged in a matrix. In this example, 1-bit data input / output terminals D0 to D7 are assigned to each memory block, and Y selector circuits YSW0 to YSW7, read / write circuits (sense amplifiers and write amplifiers) RW0 to RW7, etc. are arranged therebetween. Has been. A redundant memory mat MATR in which memory cells for defect relief are arranged in a matrix is provided, and a redundant Y selector circuit YSWR and a read / write circuit RWR are connected to the redundant memory mat MATR. The memory mats MAT0 to MAT7 and the redundant memory mat MATR have the same circuit configuration. The Y selector circuits YSW0 to YSW7 and YSWR select one bit line or a pair of complementary bit lines from the corresponding memory mat.

  In order to be able to replace one of the memory mats MAT0 to MAT7 with the redundant memory mat MATR, selectors SEL0 to SEL7 are provided. The selectors SEL0 to SEL7 select one of the input / output terminals of the read / write circuit RWR and the input / output terminals of the read / write circuits RW0 to RW7 and connect them to the data input / output terminals D0 to D7. A selection control signal for the selectors SEL0 to SEL7 is generated by the decoder DL, and relief information is given to the decoder DL from the relief information register AR. The method of initial loading of relief information is the same as described above.

  According to the example of FIG. 19, the repair information includes a repair enable bit RE and 3-bit selection bits A2 to A0. The decoder DL is configured by AND gates AND0 to AND7 that constitute decoding logic for complementary signals of the selection bits A2 to A0, and the outputs of the AND gates AND0 to AND7 are supplied to the selection terminals of the corresponding selectors SEL0 to SEL7. A relief enable bit RE is supplied to each of the AND gates AND0 to AND7, and when this is in a relief enable state having a logical value “1”, a decoding operation can be performed. In other words, when the repair enable bit RE is in the logic “0” state, the output selection signals of the AND gates AND0 to AND7 are all forced to the non-selection level.

  If the repair is performed by replacing the memory mat or the memory block, the address comparison operation is not necessary, and the access time can be increased. Further, the number of bits of relief information can be reduced with respect to the scale that can be rescued. Therefore, it is suitable for a large capacity DRAM. However, the chip area occupied by redundancy is larger than that in the configuration in which address comparison is performed. The configuration of FIG. 19 can be applied to any of the SRAD 13, the DRAM 12, and the flash memory 11.

<Application to trimming circuit>
In the above description, the example in which the relief information for redundancy is stored and used in the flash memory 11 has been described. However, trimming information may be stored and used instead of the relief information or together with the relief information. It is. Hereinafter, several examples of circuits that can determine circuit characteristics using trimming information will be described.

  FIG. 20 shows an example of a single chip microcomputer having a step-down power supply circuit. The step-down power supply circuit 31 steps down a power supply voltage VDD such as 5 V or 3.3 V supplied from the outside of the single chip microcomputer 30 to generate an internal power supply voltage VDL. The lowered internal power supply voltage VDL is used as an operation power supply for the CPU 10, flash memory 11, DRAM 12, SRAM 13 and the like. Such a step-down voltage VDL is used in order to guarantee the reliability of the circuit operation when the circuit elements are miniaturized in order to improve the degree of integration and the operation speed, and to realize low power consumption. It is. The input / output circuit 14 interfaced with the outside uses the external power supply voltage VDD as an operating power supply. VSS is the ground voltage of the circuit. The step-down power supply circuit 31 includes a voltage trimming register 31DR that latches control information (voltage trimming information) for determining a reference voltage for defining the level of the internal power supply voltage VDL. In the initial loading of the voltage trimming information to the register 31DR, the voltage trimming information is read from the flash memory 11 to the data bus 16 in response to a reset instruction in the same manner as the initial loading of the relief information described above. The voltage trimming information is latched in the register 31DR.

  FIG. 21 shows an example of the step-down power supply circuit 31. The step-down voltage is output from a source follower circuit composed of an n-channel MOS transistor M5 and a resistance element R5. The conductance of the transistor M5 is negatively feedback controlled by the operational amplifier AMP2. Voltage VDL is logically equal to control voltage VDL1. The control voltage VDL1 is output from a source follower circuit composed of an n-channel MOS transistor M4 and resistance elements R0 to R4. The conductance of the transistor M4 is negatively feedback controlled by the operational amplifier AMP1. In the feedback system, switch MOS transistors M0 to M3 capable of selecting a resistance voltage dividing ratio by the resistors R0 to R4 are provided to constitute a trimming circuit. Selection of the switch MOS transistors M0 to M3 is performed by a decoder DEC1 that decodes the 2-bit voltage trimming information TR1 and TR0. The feedback voltage thus formed is compared with the reference voltage generated by the reference voltage generation circuit VGE1 by the operational amplifier AMP1. The operational amplifier AMP1 performs negative feedback control so that the control voltage VDL1 becomes equal to the reference voltage Vref.

  When the element characteristics of the step-down power supply circuit 31 vary relatively greatly due to the influence of the manufacturing process, the resistance voltage division ratio selected by the decoder DEC1 is changed so that the internal power supply voltage VDL1 falls within the desired range of design values. . Information for this can be obtained in advance from circuit characteristics grasped by the device test. As described above, a predetermined area of the flash memory 11 (predetermined address area corresponding to the storage area of the relief information) by the EPROM writer mode or the like. You should write in advance. When the microcomputer 30 is reset, the voltage trimming information TR0 and TR1 is initially loaded from the flash memory 11 to the voltage trimming register 31DR.

  FIG. 22 shows an example of a refresh timer for controlling the refresh interval of the memory cells in the data holding mode of the DRAM 12. CM is a storage capacitor for monitoring, and is designed so that the data holding time is slightly shorter than the storage capacitor of the dynamic memory cell. The n-channel MOS transistor M15 is a charging transistor for the monitoring storage capacitor CM. As illustrated in FIG. 23, the transistor M15 is turned on during the refresh operation period and is turned off during the data holding period. In the data holding period, the voltage of the node VN is lowered by the leakage of the monitoring storage capacitor CM. The degree of level drop is detected by the comparator AMP3. The comparator AMP3 outputs a high level when the level of the node VN becomes lower than the reference voltage VR1. This state sets the set / reset type flip-flop FF. As a result, the counter CNT starts the counting operation and generates the refresh clock φREF. A refresh operation is performed in synchronization with the refresh clock φREF. For example, a refresh operation for each word line is performed in synchronization with the clock cycle of the refresh clock φREF while sequentially incrementing a refresh address counter (not shown). The flip-flop FF is reset by a carry caused by overflow of the counter CNT, and a series of fresh operations are completed. During the refresh operation, the transistor M15 is turned on, and the monitoring storage capacitor CM is charged to detect the next refresh timing. When the refresh operation ends, the transistor M15 is cut off and the refresh timing detection operation due to leak is performed again.

  The charge retention characteristic of the monitor storage capacitor CM is expected to fluctuate due to the influence of the process. Causes a data error or data destruction in many memory cells having charge retention characteristics. Therefore, it is possible to employ the reference voltage generation circuit 12RF that can adjust the reference voltage VR1 according to the charge holding performance of the monitoring storage capacitor CM.

  As illustrated in FIG. 22, the reference voltage generation circuit 12RF is output from a source follower circuit including an n-channel MOS transistor M14 and resistance elements R10 to R14. The conductance of the transistor M14 is negatively feedback controlled by the operational amplifier AMP4. In the feedback system, switch MOS transistors M10 to M13 capable of selecting a resistance voltage dividing ratio by the resistors R10 to R14 are provided to constitute a trimming circuit. Selection of the switch MOS transistors M10 to M13 is performed by a decoder DEC2 that decodes the 2-bit voltage trimming information RF1 and RF0. The feedback voltage thus formed is compared with the reference voltage VR generated by the reference voltage generation circuit VGE2 by the operational amplifier AMP4. The operational amplifier AMP4 performs negative feedback control so that the reference voltage VR1 is equal to the reference voltage VR.

  When the charge retention performance of the monitor storage capacitor CM fluctuates beyond the allowable range due to the influence of the manufacturing process, the resistance voltage division ratio selected by the decoder DEC2 is appropriately changed. Information for that purpose can be obtained in advance from the charge retention performance of the capacitor CM ascertained by the device test. As described above, a predetermined area of the flash memory 11 (corresponding to the storage area for the relief information) by the EPROM writer mode or the like. It may be written in advance in a predetermined address area. When the microcomputer 30 is reset, the voltage trimming information TR0 and TR1 is initially loaded from the flash memory 11 to the refresh optimization register 12DR.

  FIG. 24 shows a delay circuit for the sense amplifier activation signal φSA as an example of a timing adjustment delay circuit in the timing controller 13TC of the SRAM 13. The timing controller 13TC has four stages of delay circuits DL0 to DL3 in series and CMOS transfer gates TG0 to TG3 for selecting the outputs of the delay circuits DL0 to DL3. The outputs of the CMOS transfer gates TG0 to TG3 are wired OR, and the signal at the coupling node is supplied to the sense amplifier 13SA as the sense amplifier activation signal φSA. Which of the CMOS transfer gates TG0 to TG3 is turned on is performed by the decoder DEC3 that decodes the 2-bit timing adjustment information TM0 and TM1.

  When the access speed of the SRAM 13 fluctuates due to the influence of the manufacturing process, it may be desirable to adjust the activation timing of the sense amplifier accordingly in view of high-speed access or stabilization of the data read operation. Accordingly, the selection state of the CMOS transfer gates TG0 to TG3 may be determined. The information for that can be obtained in advance from the Aqua S speed performance grasped by the device test. As described above, the predetermined area of the flash memory 11 (predetermined address corresponding to the storage area for the relief information) is obtained by the EPROM writer mode. You may write it in advance in the area. When the microcomputer 30 is reset, the timing adjustment information TM0 and TM1 is initially loaded from the flash memory 11 to the timing adjustment register 13DR via the data bus 16 by the same procedure as the relief information.

  The techniques described in the defect relief of FIG. 14, voltage trimming of FIG. 21, optimization of the refresh interval of FIG. 22, and timing adjustment of the timing controller of FIG. 24 are performed by one single-chip microcomputer 30 illustrated in FIG. The present invention can be applied collectively to such semiconductor integrated circuits. At this time, the information stored in the flash memory 11 can be positioned as initialization data for determining a part of the functions of the circuit, and is stored in the memory cell array 11MA of the flash memory 11 in a format as shown in FIG. The

  FIG. 26 shows an example of a system for designing a semiconductor integrated circuit using a computer.

  In the figure, reference numeral 100 denotes a computer (also referred to as an electronic computer) such as a personal computer, and reference numeral 101 denotes a keyboard for inputting data to the electronic computer. Reference numeral 102 denotes a recording medium such as a disk.

  Data necessary for designing a semiconductor integrated circuit is recorded in advance on this recording medium. For example, in order to design a semiconductor integrated circuit as shown in FIG. 1, the recording medium 102 includes data 103 for determining the configuration of the flash memory (11), data 104 for determining the configuration of the DRAM (12), relief Data 105 that defines the configuration of the address register (12AR), data 106 that defines the configuration of the data bus (16), and the like are recorded.

  A semiconductor integrated circuit can be designed on the electronic computer by reading necessary data from the recording medium into the electronic computer according to the object to be designed.

  Each of the data is a program written in a specific computer language that can be understood by an electronic computer (for example, an RTL (Register Transfer Level) model or an HDL (Hardware Description Language) model), or when actually manufacturing a semiconductor integrated circuit. It may be data (coordinate data, connection wiring data) relating to the mask used for the above. Of course, a combination of both may be used as the data.

  In the above description, the data defining the configuration of the relief address register is the data 105, but of course, a register used to change the electrical characteristics (for example, the voltage trimming register shown in FIG. 20, FIG. 22). The configuration of the refresh optimization register shown in FIG. 5, the timing adjustment register shown in FIG. 24, or their composite register as shown in FIG. 25) may be determined by this data 105.

  In FIG. 1, the relief address register (12AR) and the address comparison circuit (12AC) are described as being provided in the DRAM (12). , Y selector, write buffer, input buffer, main amplifier, output buffer) may be used as data 105 different from the data 104 defining the configuration. Of course, the DRAM (12) shown in FIG. 1 may be handled as one data group.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the semiconductor integrated circuit according to the present invention is not limited to a single-chip microcomputer, and the type of built-in circuit module of the single-chip microcomputer is not limited to the above example, and can be changed as appropriate. Further, the electrically rewritable nonvolatile memory is not limited to the flash memory, and a memory cell including a selection MOS transistor and a MNOS (metal nitride oxide semiconductor) type storage transistor may be adopted. Good. Further, the voltage application state of writing and erasing of the flash memory is not limited to the above and can be changed as appropriate. The non-volatile memory may store multi-value information of four or more values. The volatile memory is not limited to SRAM and DRAM, and may be a ferroelectric memory or the like.

  In a memory such as a DRAM, SRAM, or flash memory, a redundant word line is selected based on an address comparison result by an address comparison circuit, so that the selection timing tends to be delayed compared to that of a normal word line. Such timing delays are not negligible, especially when the semiconductor integrated circuit should operate with a significantly faster operating cycle. For such a case, if a slight increase in area is allowed, the information storage capacity in the dynamic memory cell for redundancy can be made larger than that in the normal memory cell, or the capacity for redundancy can be increased. The size of the static memory cell or the flash memory cell can be increased so as to increase the conductance of the transistor. That is, in this case, the amount of read signal applied to the bit line from the selected redundant memory cell can be increased, and normal data can be read even if the read sense operation timing is advanced accordingly. As a result, the influence of the delay in selecting the redundant word line can be substantially reduced by increasing the speed of the sensing operation after selecting the memory cell.

  The technique for adjusting the refresh period of the DRAM as described with reference to FIG. 22 can be changed. When the data retention time characteristics of some dynamic memory cells are relatively different from the charge voltage retention characteristics of the capacitor CM in FIG. 22, the refresh operation is performed within the normal operation period of the dynamic memory cells. So that the reference voltage VR1 of FIG. 22 can be positively changed. In the trimming for guaranteeing the refresh operation of the DRAM, instead of FIG. 22, a clock signal such as a system clock signal of the semiconductor integrated circuit is counted, and the count number of the counter or timer for forming the refresh timing signal is changed. It can also be adopted. Further, the present invention has a great effect in a system LSI that is system-on-chip, but it goes without saying that the present invention can also be applied to a logic LSI other than the system LSI. Further, in FIG. 1, FIG. 14 or FIG. 15, each memory module 11, 12, 13 has been described as including one redundant word line, but the number may be plural. Thereby, not only the repair efficiency is improved, but also the defect detected in each step of defect repair steps S2, S7 and S10 according to FIG. 14A can be repaired.

1 is a block diagram of a first single chip microcomputer according to an example of a semiconductor integrated circuit of the present invention. FIG. It is explanatory drawing which shows a detailed example of the relief information used with the single chip microcomputer of FIG. It is a timing chart which shows an example of the initial load process of the relief information in a reset period. It is the flowchart which showed the time when defect relief is possible with respect to a single chip microcomputer from the manufacturing process in time series. It is device sectional drawing which showed roughly the mode of the laser-cut opening part of a fuse with respect to a copper wiring system process. It is a circuit diagram which shows an example of a dynamic type memory cell. It is a schematic explanatory drawing which shows an example of the memory cell array of DRAM. It is a circuit diagram which shows an example of a CMOS static type memory cell. It is a schematic explanatory drawing which shows an example of the memory cell array of SRAM. It is a circuit diagram which shows an example of a flash memory cell. It is a schematic explanatory drawing which shows an example of the memory cell array of flash memory. It is explanatory drawing which shows an example of the writing state in a flash memory, and an erasing state. It is explanatory drawing which shows an example of the voltage application state in each of write-in operation | movement and erase | elimination operation | movement of flash memory. It is a block diagram of the 2nd single chip microcomputer which is another example of the semiconductor integrated circuit concerning this invention. It is explanatory drawing which shows an example of the relief information in a 2nd single chip microcomputer. It is a timing chart which shows an example of the initial load process of the relief information in the 2nd single chip microcomputer. It is a block diagram of the 3rd single chip microcomputer which is another example of the semiconductor integrated circuit concerning this invention. 12 is a timing chart illustrating an example of a process for initially loading relief information during a reset period in a third single-chip microcomputer. FIG. 4 is a block diagram schematically showing an example of a memory adopting a configuration in which a memory mat or a defect repair is performed by replacement of a memory block. It is a block diagram showing an example of a single chip microcomputer having a step-down power supply circuit. It is a circuit diagram showing an example of a step-down power supply circuit. 3 is a circuit diagram showing an example of a refresh timer for controlling a refresh interval of memory cells in a data holding mode of the DRAM 12. FIG. 24 is a timing chart illustrating an example of the operation of the refresh timer illustrated in FIG. 3 is a circuit diagram showing an example of a timing adjustment circuit for a sense amplifier activation signal in the timing controller of the SRAM 13; FIG. The techniques described in FIG. 14 for defect relief, FIG. 21 voltage trimming, FIG. 22 refresh interval optimization, and timing controller timing adjustment in FIG. 24 are combined into one single-chip microcomputer illustrated in FIG. FIG. 4 is an explanatory diagram showing an example of a format of initialization data stored in a flash memory when applied in the above manner. 1 is a conceptual diagram showing an example of a system for designing a semiconductor integrated circuit according to the present invention using a computer.

Explanation of symbols

1AS, 1B. 1C single chip microcomputer 10 CPU
11 Flash memory FMC Flash memory cell WLf_0 to WLf_Mf Normal word line WLfR Redundant word line BLf_0 to BLfMf Bit line 11MA Memory cell array 11SQ Sequence controller 11MR Mode register MB1, MB2 Mode bit 11AC Address comparison circuit 11AR Relief address register 12 DRAM
DMC dynamic memory cell WLd_0 to WLd_Md Normal word line WLdR Redundant word line BLd_0 to BLdMd Bit line 12MA Memory cell array 12TC Timing controller 12AR Relief address register 12AC Address comparison circuit 12RF Reference voltage generation circuit DEC2 Decoder 12DR Refresh optimization register 13 SRAM
SMC Static memory cells WLs_0 to WLs_Ms Normal word lines WLsR Redundant word lines BLs_0 to BLsMs Bit lines 13MA Memory cell array 13TC Timing controller 13AR Relief address register 13AC Address comparison circuit DEC3 Decoder 13DR Timing adjustment register 15 Address bus 16 Data bus 17 Control bus 30 Single-chip microcomputer 31 Step-down voltage generator DEC1 Decoder 31DR Voltage trimming register

Claims (7)

A semiconductor integrated circuit formed on one semiconductor substrate,
A step-down circuit that receives the first and second external voltages and generates an internal voltage;
A volatile storage circuit coupled to the step-down circuit for storing information for adjusting a voltage level of the internal voltage;
An input / output circuit that receives the first and second external potentials and inputs data from outside the semiconductor integrated circuit or outputs data to the outside of the semiconductor integrated circuit;
A central processing unit that receives the internal voltage and the second external voltage and is operated between the internal voltage and the second external voltage;
An electrically writable nonvolatile memory element that stores the information according to the threshold value,
The information stored in the electrically writable nonvolatile memory element is read in response to initialization of the semiconductor integrated circuit,
The volatile storage circuit stores the information read from the electrically writable nonvolatile memory element in response to initialization of the semiconductor integrated circuit, so that the internal voltage adjusted by the information is changed. A semiconductor integrated circuit supplied from the step-down circuit to the central processing unit. In claim 1,
A semiconductor integrated circuit having a data bus coupled between the input / output circuit and the central processing unit. In claim 1,
The electrically writable nonvolatile memory element is a semiconductor integrated circuit having a region where electrons are to be charged. In claim 1,
The electrically writable nonvolatile memory element is a semiconductor integrated circuit having a control gate and a floating gate. In claim 2,
A semiconductor integrated circuit including a volatile memory coupled to the data bus and receiving the internal voltage. In claim 1,
A semiconductor integrated circuit including a nonvolatile memory including the electrically writable nonvolatile memory element. In claim 1,
The step-down circuit is
A reference potential generating circuit for generating a reference potential;
An amplifier circuit having a first input terminal coupled to receive the reference potential, a second input terminal, and an output terminal;
A MOSFET having a gate coupled to the output of the amplifier circuit, a source coupled to receive the first external voltage, and a drain;
A plurality of resistive elements coupled between the source of the MOSFET and the second external voltage;
A plurality of switching MOS transistors each having a source / drain path coupled between the second input of the amplifier circuit and a corresponding common connection point of the plurality of resistance elements;
A semiconductor integrated circuit in which one of the plurality of switching MOS transistors is turned on according to the information stored in the volatile storage circuit.

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