JP2006114036A - Ｓｍｔディスパッチのための命令グループ形成およびメカニズム - Google Patents

Ｓｍｔディスパッチのための命令グループ形成およびメカニズム Download PDF

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Publication number
JP2006114036A
JP2006114036A JP2005294193A JP2005294193A JP2006114036A JP 2006114036 A JP2006114036 A JP 2006114036A JP 2005294193 A JP2005294193 A JP 2005294193A JP 2005294193 A JP2005294193 A JP 2005294193A JP 2006114036 A JP2006114036 A JP 2006114036A
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resource
processor
instruction
program instructions
instructions
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JP2005294193A
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Japanese (ja)
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JP2006114036A5 (enExample
Inventor
Brian William Curran
ブライアン・ウィリアム・カラン
Brian R Konigsburg
ブライアン・アール・カニグスバーグ
Qui Le Hung
ハン・クイ・ル
Luick David Arnold
デイヴィッド・アーノルド・ルイック
Dung Quoc Nguyen
ダン・クオ・ニューイェン
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International Business Machines Corp
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International Business Machines Corp
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Publication of JP2006114036A publication Critical patent/JP2006114036A/ja
Publication of JP2006114036A5 publication Critical patent/JP2006114036A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
JP2005294193A 2004-10-14 2005-10-06 Ｓｍｔディスパッチのための命令グループ形成およびメカニズム Pending JP2006114036A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/965,143 US7237094B2 (en) 2004-10-14 2004-10-14 Instruction group formation and mechanism for SMT dispatch

Publications (2)

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JP2006114036A true JP2006114036A (ja) 2006-04-27
JP2006114036A5 JP2006114036A5 (enExample) 2009-08-06

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JP2005294193A Pending JP2006114036A (ja) 2004-10-14 2005-10-06 Ｓｍｔディスパッチのための命令グループ形成およびメカニズム

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US (1) US7237094B2 (enExample)
JP (1) JP2006114036A (enExample)
CN (1) CN100357884C (enExample)

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JP2012515386A (ja) * 2009-01-16 2012-07-05 イマジネイション テクノロジーズ リミテッド マルチスレッド式データ処理システム
CN102662632A (zh) * 2012-03-14 2012-09-12 北京神州数码思特奇信息技术股份有限公司 一种利用信号量实现的序列号生成方法和生成器
JP2012525620A (ja) * 2009-04-28 2012-10-22 イマジネイション テクノロジーズ リミテッド マルチスレッドマイクロプロセッサにおける命令の発行をスケジュールするための方法及び装置
JP2017516215A (ja) * 2014-05-12 2017-06-15 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ 動的な命令ストリーム・マッピングを使用するプロセッサ・コア、プロセッサ・コアを含むコンピュータ・システム、およびプロセッサ・コアによってプログラム命令を実行する方法（動的な命令ストリーム・マッピングを使用する並列スライス・プロセッサ）
US10545762B2 (en) 2014-09-30 2020-01-28 International Business Machines Corporation Independent mapping of threads
US10983800B2 (en) 2015-01-12 2021-04-20 International Business Machines Corporation Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices
US11150907B2 (en) 2015-01-13 2021-10-19 International Business Machines Corporation Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
JP2024511764A (ja) * 2021-03-31 2024-03-15 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド ウェーブフロント（ｗａｖｅｆｒｏｎｔ）の選択及び実行

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US8860737B2 (en) * 2003-10-29 2014-10-14 Nvidia Corporation Programmable graphics processor for multithreaded execution of programs
JPWO2006134693A1 (ja) * 2005-06-15 2009-01-08 松下電器産業株式会社 プロセッサ
US7434032B1 (en) 2005-12-13 2008-10-07 Nvidia Corporation Tracking register usage during multithreaded processing using a scoreboard having separate memory regions and storing sequential register size indicators
KR100837400B1 (ko) * 2006-07-20 2008-06-12 삼성전자주식회사 멀티스레딩/비순차 병합 기법에 따라 처리하는 방법 및장치
US9069547B2 (en) 2006-09-22 2015-06-30 Intel Corporation Instruction and logic for processing text strings
US20080229062A1 (en) * 2007-03-12 2008-09-18 Lorenzo Di Gregorio Method of sharing registers in a processor and processor
US7707390B2 (en) * 2007-04-25 2010-04-27 Arm Limited Instruction issue control within a multi-threaded in-order superscalar processor
EP2169538A4 (en) * 2007-06-20 2010-12-01 Fujitsu Ltd INSTRUCTIONS PROCESSOR
US20090210664A1 (en) * 2008-02-15 2009-08-20 Luick David A System and Method for Issue Schema for a Cascaded Pipeline
US7870368B2 (en) 2008-02-19 2011-01-11 International Business Machines Corporation System and method for prioritizing branch instructions
US8108654B2 (en) * 2008-02-19 2012-01-31 International Business Machines Corporation System and method for a group priority issue schema for a cascaded pipeline
US20090210666A1 (en) * 2008-02-19 2009-08-20 Luick David A System and Method for Resolving Issue Conflicts of Load Instructions
US7877579B2 (en) * 2008-02-19 2011-01-25 International Business Machines Corporation System and method for prioritizing compare instructions
US7996654B2 (en) * 2008-02-19 2011-08-09 International Business Machines Corporation System and method for optimization within a group priority issue schema for a cascaded pipeline
US20090210672A1 (en) * 2008-02-19 2009-08-20 Luick David A System and Method for Resolving Issue Conflicts of Load Instructions
US7865700B2 (en) 2008-02-19 2011-01-04 International Business Machines Corporation System and method for prioritizing store instructions
US8095779B2 (en) * 2008-02-19 2012-01-10 International Business Machines Corporation System and method for optimization within a group priority issue schema for a cascaded pipeline
US7984270B2 (en) 2008-02-19 2011-07-19 International Business Machines Corporation System and method for prioritizing arithmetic instructions
US7882335B2 (en) * 2008-02-19 2011-02-01 International Business Machines Corporation System and method for the scheduling of load instructions within a group priority issue schema for a cascaded pipeline
US8108655B2 (en) * 2009-03-24 2012-01-31 International Business Machines Corporation Selecting fixed-point instructions to issue on load-store unit
US8127115B2 (en) * 2009-04-03 2012-02-28 International Business Machines Corporation Group formation with multiple taken branches per group
JP5463076B2 (ja) * 2009-05-28 2014-04-09 パナソニック株式会社 マルチスレッドプロセッサ
US8171224B2 (en) * 2009-05-28 2012-05-01 International Business Machines Corporation D-cache line use history based done bit based on successful prefetchable counter
US8332587B2 (en) * 2009-05-28 2012-12-11 International Business Machines Corporation Cache line use history based done bit modification to I-cache replacement scheme
US8140760B2 (en) * 2009-05-28 2012-03-20 International Business Machines Corporation I-cache line use history based done bit based on successful prefetchable counter
US8291169B2 (en) 2009-05-28 2012-10-16 International Business Machines Corporation Cache line use history based done bit modification to D-cache replacement scheme
CN101957744B (zh) * 2010-10-13 2013-07-24 北京科技大学 一种用于微处理器的硬件多线程控制方法及其装置
US9304774B2 (en) * 2011-02-04 2016-04-05 Qualcomm Incorporated Processor with a coprocessor having early access to not-yet issued instructions
US9465755B2 (en) 2011-07-18 2016-10-11 Hewlett Packard Enterprise Development Lp Security parameter zeroization
TWI447646B (zh) 2011-11-18 2014-08-01 Asmedia Technology Inc 資料傳輸裝置及多個指令的整合方法
US8856193B2 (en) * 2011-12-20 2014-10-07 Sap Se Merge monitor for table delta partitions
US9798548B2 (en) 2011-12-21 2017-10-24 Nvidia Corporation Methods and apparatus for scheduling instructions using pre-decode data
US9513915B2 (en) * 2012-03-28 2016-12-06 International Business Machines Corporation Instruction merging optimization
US9405701B2 (en) 2012-03-30 2016-08-02 Intel Corporation Apparatus and method for accelerating operations in a processor which uses shared virtual memory
US9336057B2 (en) 2012-12-21 2016-05-10 Microsoft Technology Licensing, Llc Assigning jobs to heterogeneous processing modules
CN105446700B (zh) * 2014-05-30 2018-01-02 华为技术有限公司 一种指令执行方法以及顺序处理器
US9715392B2 (en) * 2014-08-29 2017-07-25 Qualcomm Incorporated Multiple clustered very long instruction word processing core
US11275590B2 (en) * 2015-08-26 2022-03-15 Huawei Technologies Co., Ltd. Device and processing architecture for resolving execution pipeline dependencies without requiring no operation instructions in the instruction memory
US10423423B2 (en) 2015-09-29 2019-09-24 International Business Machines Corporation Efficiently managing speculative finish tracking and error handling for load instructions
US20170300361A1 (en) * 2016-04-15 2017-10-19 Intel Corporation Employing out of order queues for better gpu utilization
US11314516B2 (en) * 2018-01-19 2022-04-26 Marvell Asia Pte, Ltd. Issuing instructions based on resource conflict constraints in microprocessor
CN108400866B (zh) * 2018-03-01 2021-02-02 中国人民解放军战略支援部队信息工程大学 一种粗粒度可重构密码逻辑阵列
CN112445619A (zh) * 2020-11-30 2021-03-05 海光信息技术股份有限公司 在多线程系统中动态共享有序资源的管理系统和方法

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012515386A (ja) * 2009-01-16 2012-07-05 イマジネイション テクノロジーズ リミテッド マルチスレッド式データ処理システム
JP2012525620A (ja) * 2009-04-28 2012-10-22 イマジネイション テクノロジーズ リミテッド マルチスレッドマイクロプロセッサにおける命令の発行をスケジュールするための方法及び装置
CN102662632A (zh) * 2012-03-14 2012-09-12 北京神州数码思特奇信息技术股份有限公司 一种利用信号量实现的序列号生成方法和生成器
JP2017516215A (ja) * 2014-05-12 2017-06-15 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ 動的な命令ストリーム・マッピングを使用するプロセッサ・コア、プロセッサ・コアを含むコンピュータ・システム、およびプロセッサ・コアによってプログラム命令を実行する方法（動的な命令ストリーム・マッピングを使用する並列スライス・プロセッサ）
US10545762B2 (en) 2014-09-30 2020-01-28 International Business Machines Corporation Independent mapping of threads
US11144323B2 (en) 2014-09-30 2021-10-12 International Business Machines Corporation Independent mapping of threads
US10983800B2 (en) 2015-01-12 2021-04-20 International Business Machines Corporation Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices
US11150907B2 (en) 2015-01-13 2021-10-19 International Business Machines Corporation Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
US11734010B2 (en) 2015-01-13 2023-08-22 International Business Machines Corporation Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
US12061909B2 (en) 2015-01-13 2024-08-13 International Business Machines Corporation Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
JP2024511764A (ja) * 2021-03-31 2024-03-15 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド ウェーブフロント（ｗａｖｅｆｒｏｎｔ）の選択及び実行

Also Published As

Publication number Publication date
US7237094B2 (en) 2007-06-26
US20060101241A1 (en) 2006-05-11
CN1760826A (zh) 2006-04-19
CN100357884C (zh) 2007-12-26

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