JP2006112346A - Signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately perform digital filter processing on a second device side even if noise occurs in an A/D converting request command from a second device to a first device in a signal processor enabling the second device performing the digital filter processing for the time-series A/D converted values of analog signals to transmit the A/D conversion request command to the first device with an A/D converter for each prescribed interval and acquiring, as a response to the command, the A/D converted values of analog signals from the first device. <P>SOLUTION: When a chip select signal (CS) given from a processing IC as the second device is low, an input IC as the first device communicates with the processing IC and returns the A/D converted values for each receipt of the A/D conversion request command (cmdB). Particularly, the signal processor transmits the A/D converted values (S570) irrespective of the type of the command from the processing IC until the CS becomes high after the device determines once that it received cmdB after the CS becomes low (S440: NO). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a signal processing apparatus that performs A / D conversion on an analog signal to perform digital filter processing.

  2. Description of the Related Art Conventionally, in an apparatus for controlling an automobile engine, for example, an analog signal (a so-called knock signal) from a knock sensor is A / D converted at a certain sampling interval by an A / D converter, and the A / D conversion is performed. The time-series data is supplied to a digital filter, and the presence or absence of knocking is determined (knock determination) using the digital filter processing result (see, for example, Patent Document 1).

  And as a form of the signal processing apparatus which performs A / D conversion of an analog signal and performs digital filter in this way, the first apparatus having an A / D converter, and the first apparatus and a fixed line via a communication line It consists of a second device that communicates every time, sequentially acquires A / D conversion values of analog signals by the A / D converter, and performs digital filter processing on the acquired time-series A / D conversion values Each time the second device transmits an A / D conversion request command of a plurality of types of commands to the first device at regular intervals, and the first device receives the A / D conversion request command, A A mode in which the A / D conversion value of the analog signal is transferred from the first device to the second device by returning the A / D conversion value of the analog signal by the / D converter to the second device. (For example, see Patent Document 2) .

In general, each of the first device and the second device is integrated into an IC. When the chip select signal as a communication permission signal given from the outside is at an active level, the IC as the first device Configured to communicate with the IC. Therefore, the second device communicates with the first device at regular intervals after setting the chip select signal as a communication permission signal for the first device to the active level.
JP-A-7-293314 JP-A-9-282265

  By the way, in the signal processing device of the above embodiment, when the first device receives the A / D conversion request command from the second device, the A / D conversion value of the analog signal is returned to the second device. If an A / D conversion request command from the second device is garbled due to noise and is received as a different command by the first device, an A / D conversion value is returned from the first device to the second device. Or a value different from the original A / D conversion value may be returned. When such an event occurs, the digital filter processing result on the second device side becomes inaccurate. In digital filter processing, it is necessary to sequentially process continuous A / D conversion values at regular intervals. If the A / D conversion values are missing or suddenly become indefinite values, a correct digital filter processing result is obtained. In other words, the accuracy of control using the filter processing result is lowered.

  The present invention has been made in view of these problems, and the second device that performs digital filter processing on time-series A / D conversion values of analog signals is changed to a first device having an A / D converter. In a signal processing device configured to transmit an A / D conversion request command at regular time intervals and acquire an A / D conversion value of an analog signal from the first device as a response to the command, the first signal from the second device is An object is to enable the second device to accurately perform digital filter processing even when noise is added to the A / D conversion request command to the device.

  The signal processing device according to claim 1, which has been made to achieve the above object, has an A / D converter for A / D converting an analog signal, and other when an external communication permission signal is at an active level. A first device that communicates with the first device via a communication line; and the first device that is connected to the first device via a communication line, and the communication permission signal is set to an active level to communicate with the first device at regular intervals, A second apparatus that sequentially acquires A / D conversion values of the analog signal by the A / D converter at regular intervals and performs digital filter processing on the acquired time-series A / D conversion values. In this signal processing device, the second device transmits an A / D conversion request command of a plurality of types of commands to the first device at regular intervals while the communication permission signal is set to the active level. Each time one device receives the A / D conversion request command, the A / D conversion value of the analog signal from the A / D converter is sent back to the second device, so that the first device transfers to the second device. The A / D conversion value of the analog signal by the A / D converter is transferred every predetermined time.

  In particular, in this signal processing device, when the first device once determines that the A / D conversion request command has been received after the communication permission signal becomes active level, the communication permission signal then becomes inactive level. Until, every time a command from the second device is received regardless of whether the command from the second device is an A / D conversion request command, an analog signal from the A / D converter is sent to the second device. A / D conversion values are transmitted.

  According to such a signal processing device of claim 1, after the first device receives the A / D conversion request command even once after the communication permission signal becomes the active level, the first device receives the A from the second device. Even if noise is added to the / D conversion request command and the A / D conversion request command is received as an indefinite command or a different command, it is sent to the second device in exactly the same way as when the A / D conversion request command is received. Since the AD conversion value is transmitted, the second device can receive the correct A / D conversion value and can accurately perform the digital filter processing.

  Next, in the signal processing device according to claim 2, in the signal processing device according to claim 1, after the second device sets the communication permission signal to an active level, the second device sends a signal other than an A / D conversion request command to the first device. After transmitting a predetermined number of function setting commands, transmission of an A / D conversion request command is started. When the first device receives the function setting command after the communication permission signal becomes active, The internal functions are set according to the function setting command.

  According to such a signal processing device of claim 2, the function of transmitting from the second device to the first device prior to the A / D conversion request command for each communication period between the first device and the second device. The setting command allows the setting of the internal function of the first device to be changed arbitrarily, which is very advantageous.

  The function setting command may be a command for setting any function. For example, an amplifier (amplifier) that amplifies an analog signal input to the A / D converter by the first device. , A command to command the gain of the amplifier can be considered. In addition, for example, the first device selects any one of a plurality of input channels for inputting different analog signals, and the analog signal input to the selected input channel is converted into an A / D converter. If it is provided with a multiplexer to be input to, a command for instructing the input channel to be selected by the multiplexer can be considered.

In the signal processing device according to claim 2, it is preferable that the number of times the second device transmits the function setting command is the number of times as described in claim 3.
That is, the time required for stabilizing the output of the A / D converter after the communication permission signal becomes active level (in other words, the time required for completing the initial setting of the A / D converter). Assuming T1 and T2 as the predetermined time, which is the communication interval between the first device and the second device, the second device sets the function permission command to “T1 / T2” or higher after setting the communication permission signal to the active level. It is preferable that the transmission of the A / D conversion request command is started after the number of times of the integer value is transmitted. That is, the transmission period of the function setting command is used as time gain until the output of the A / D converter is stabilized.

  And according to such a signal processing device of claim 3, the second device can acquire the A / D conversion value by the A / D converter after the output value is stabilized, The accuracy of digital filter processing can be improved. In addition, it is not necessary to set a special command for intentionally providing a delay.

  Next, in the signal processing device according to claim 4, in the signal processing device according to claims 2 and 3, the second device has a function from when the communication permission signal is set to the active level to when the A / D conversion request command is transmitted. The number of setting commands to be transmitted is included in the function setting command and transmitted to the first device. Then, the first device sets the number of transmissions included in the function setting command from the second device and the function setting actually transmitted from the second device after the communication permission signal becomes the active level. The number of commands is compared, and if they do not match, it is determined that there is an abnormality.

  According to such a signal processing device of claim 4, since the first device can know the number of function setting commands transmitted from the second device, the function setting commands from the second device are Even if the data is converted into an A / D conversion request command due to noise and the converted A / D conversion request command is received, the occurrence of such an abnormality can be detected.

  Next, in the signal processing device according to claim 5, in the signal processing device according to claims 2 to 4, the first device includes abnormality information representing a communication abnormality that occurs during a period in which the communication permission signal is at an active level. When the communication permission signal once becomes inactive level and then becomes active level, it is included in the response data for the function setting command and transmitted to the second device.

  According to such a signal processing device of claim 5, the communication abnormality information from the first device to the second device is included in the response data for the function setting command and sent in the next communication period. Therefore, it is not necessary to transmit the communication abnormality information together with the A / D conversion value.

  For this reason, all or more bits of response data from the first device in response to the A / D conversion request command from the second device can be converted to A / D conversion value data. It is possible to efficiently transfer the A / D conversion value to the two devices. In addition, it is advantageous in that it is more reliable to transmit the occurrence of a communication abnormality during the next normal communication period than to transmit during the communication period in which the abnormality has occurred.

  The communication abnormality detected by the first device may be any abnormality. For example, after the function setting command from the second device is over and the A / D conversion request command is received, An abnormality described in claim 4 is conceivable, such as receiving a function setting command.

  Next, in the signal processing device according to claim 6, in the signal processing device according to claims 2 to 5, the first device outputs analog signals from a plurality of knock sensors for detecting engine knock as analog signals. Among the plurality of analog signals, one analog signal indicated by the function setting command from the second device is selected and input to the A / D converter.

  When any of the knock determination sections set for each cylinder of the engine ends, the second device changes the communication permission signal from the active level to the inactive level, and then the knock determination section of the next cylinder arrives. Before setting the communication permission signal to an active level and transmitting a function setting command, the first device is made to select an analog signal for determining knocking of the next cylinder among the plurality of analog signals. The transmission of the A / D conversion request command is also started.

  That is, when the analog signal from the knock sensor is A / D converted and further subjected to digital filter processing to determine the presence or absence of knocking (knock determination), the point at which the knock determination section, which is the target period for such knock determination, has started When the digital filter processing of the A / D conversion value is started, the initial processing result of the digital filter processing does not indicate an accurate value, and the knock determination over the entire knock determination section cannot be performed accurately. In digital filter processing, an appropriate output value cannot be obtained for an initial input, and the number of inputs corresponding to the order and configuration of the digital filter processing is required until an appropriate output value is obtained. Because.

  Therefore, in the signal processing device according to the sixth aspect, the analog signal input to the A / D converter is switched before the knock determination section of the next cylinder starts after the knock determination section of any cylinder ends. The A / D conversion of the analog signal is started and the A / D conversion value is transferred from the first device to the second device, so that A / D conversion and digital filter processing can be started.

  For this reason, before the knock determination section starts, the A / D converter can stabilize the output value (processing result) of the digital filter processing from the beginning, and the digital filter processing result is used. The accuracy of knock determination can be improved.

  Next, in the signal processing device according to claim 7, in the signal processing device according to claims 2 to 6, the second device receives the data received from the first device in response to the function setting command (that is, the first to the function setting command). Data stored in response data from one device) and received data from the first device in response to the A / D conversion request command (that is, from the first device in response to the A / D conversion request command). And a second storage unit in which the response data is received).

  According to such a signal processing device of claim 7, since the storage unit for storing the received data for the command is separated for each command, the received data for the A / D conversion request command (that is, The received data for the function setting command is not overwritten with the A / D conversion value), and the second device checks the received data for the function setting command after the communication with the first device is completed. Can do. Therefore, the processing load of the second device can be reduced.

  Next, in the signal processing device according to claim 8, in the signal processing device according to claims 2 to 7, after the second device sets the communication permission signal to the active level, the function setting having the same contents is set as a function setting command. Multiple commands are sent. The first device takes a majority vote of the contents of a plurality of function setting commands received from the second device, and sets internal functions according to the result of the majority vote.

  According to such a signal processing device of claim 8, the first device takes the majority of the function setting commands received a plurality of times from the second device, and therefore the function setting commands from the second device to the first device. In particular, even if noise is added to the last function setting command, internal functions (for example, the input channel and gain described above) can be set correctly.

  Next, in the signal processing device according to claim 9, in the signal processing device according to claims 1 to 8, the timing signal for each predetermined time is generated on the first device side, and an A / D converter is generated according to the timing signal. A / D conversion of analog signals and communication between the first device and the second device are performed.

  According to such a signal processing device of the ninth aspect, since the first device side having the A / D converter generates the timing every predetermined time, the A / D conversion interval is made accurate. Can do. In other words, as a reverse configuration, the second device becomes a master in determining the timing. For example, the first device activates the A / D converter upon receiving a command at regular intervals from the second device. Although a configuration in which an A / D conversion value is transmitted is also conceivable, in this configuration, there is a possibility that the A / D conversion timing may be shifted due to a communication delay or the like. On the other hand, according to the signal processing device of the ninth aspect, the digital filter processing can be performed on the accurate A / D conversion value at every fixed time, and the accuracy of control using the filter processing result is improved. Can be increased.

  Hereinafter, a signal processing apparatus according to an embodiment to which the present invention is applied will be described. The signal processing apparatus according to the present embodiment is used for knock determination of, for example, a V-type 6-cylinder engine mounted on an automobile.

  First, as shown in FIG. 1, the signal processing apparatus according to the present embodiment includes an input IC 11 serving as a first apparatus and a processing IC 13 serving as a second apparatus. The input IC 11 and the processing IC 13 include five described later. The signal lines 1 to 5 are communicably connected.

  The input IC 11 selects any one of the communication unit 15 for communicating with the processing IC 13, the A / D converter 17, and the plurality of input channels ch0 to chN, and sets the selected input channel. A multiplexer (MPX) 19 that outputs an input analog signal, an amplifier (Amp) 21 that amplifies the output of the multiplexer 19 with a predetermined gain and inputs the amplified signal to the A / D converter 17, and an A / D converter 17 A timer (Timer) 23 that generates and outputs a timing signal for every predetermined time Tc (in this embodiment, every 10 μs) for determining the activation interval (ie, A / D conversion interval) and the communication interval between the ICs 11 and 13; And a control unit 25 for controlling them.

  Of the input channels ch0 to chN of the multiplexer 19, the knocking of each cylinder (first cylinder # 1, third cylinder # 3, and fifth cylinder # 5) of the right bank in the engine is detected in the channel ch0. The analog signal from the first knock sensor 27 provided for the purpose is input, and each cylinder (second cylinder # 2, fourth cylinder # 4, and sixth cylinder # 6) of the left bank in the engine is input to the channel ch1. An analog signal is input from a second knock sensor 29 provided to detect the knocking.

  The processing IC 13 includes a communication unit 31 for communicating with the input IC 11 and a crank position (not shown) based on a known rotation pulse signal (not shown) generated by a rotation sensor in synchronization with the rotation of the crankshaft of the engine. A rotation processing unit 33 for detecting the rotation position of the crankshaft, a digital filter 35 for performing digital filter processing, a memory 37 for sequentially storing the processing results of the digital filter 35, and activation of the communication unit 31 and the digital filter 35. CPU39 which performs processing, such as / stop.

  The communication unit 31 includes a register 41 in which the number of commands A (cmdA), which will be described later, among commands sent from the processing IC 13 to the input IC 11 (indicated as “cmd” in the drawing) is written, and a command A register 42 to which data (command A transmission data) to be transmitted as A is written, a register 43 to which data (command B transmission data) to be transmitted as command B (cmdB) described later is written, and an input IC 11 for the command A Register 44 serving as a first storage unit for storing data (command A received data) received, and data for receiving response data from the input IC 11 for command B (command B received data) are stored. A register 45 serving as a second storage unit is provided.

  The communication unit 15 on the input IC 11 side also includes a transmission data register 46 that stores data to be transmitted from the input IC 11 to the processing IC 13 and a reception data register 47 that stores reception data from the processing IC 13. Yes.

  On the other hand, among the signal lines 1 to 5 connecting the input IC 11 and the processing IC 13, the signal line 1 is a signal line for a chip select signal CS for the input IC 11. When the communication unit 31 of the processing IC 13 sets the level of the signal line 1 (that is, the level of the chip select signal CS) to the active level (low level in the present embodiment), the communication unit 15 of the input IC 11 performs the communication operation. The communication to be performed is permitted.

  The signal line 2 is a signal line for supplying the communication clock CLK from the communication unit 31 of the processing IC 13 to the communication unit 15 of the input IC 11. The communication units 15 and 31 of both ICs 11 and 13 transmit and receive data one bit at a time in synchronization with the communication clock CLK.

  The signal line 3 is a communication line for transmitting data from the communication unit 31 of the processing IC 13 to the communication unit 15 of the input IC 11, and the signal line 4 is the communication unit 31 of the processing IC 13 from the communication unit 15 of the input IC 11. It is a communication line for transmitting data to.

  Further, the signal line 5 sends a trigger signal Tg that goes high every time the timing signal is output from the timer 23 (that is, a trigger signal that rises every 10 μs) from the communication unit 15 of the input IC 11 to the communication unit of the processing IC 13. 31 is a signal line for supplying to 31.

Next, the format of communication data exchanged between the input IC 11 and the processing IC 13 will be described with reference to FIG.
First, in this embodiment, communication data exchanged by one communication between both ICs 11 and 13 is 16 bits.

Then, two types of commands, command A and command B, are transmitted from the processing IC 13 to the input IC 11 as shown in FIG.
The command A corresponds to a function setting command, and is a command for instructing the input IC 11 at least a channel (ch) to be selected by the multiplexer 19 and the gain of the amplifier 21.

  The command A includes a 2-bit command code “10” indicating that the command is the command A, 2 bits indicating the channel to be selected by the multiplexer 19, 3 bits indicating the gain of the amplifier 21, and the like. It consists of 3 bits indicating information (other 1) and the remaining 6 bits. The remaining 6 bits are unused and are always set to “0”.

  Command B corresponds to an A / D conversion request command, and is a command for requesting A / D conversion of an analog signal by the A / D converter 17 and its A / D conversion value from the input IC 11.

  The command B includes a 2-bit command code “01” indicating that the command is the command B, and the remaining 14 bits. The remaining 14 bits are unused and are always set to “0”. The

  On the other hand, from the input IC 11 to the processing IC 13, as shown in FIG. 2B, response data for reporting the setting result for the command A from the processing IC 13 (hereinafter referred to as command A response data), and Response data for the command B (hereinafter referred to as command B response data) is transmitted.

  The command A response data is actually set with a 2-bit command code “10” indicating that the response data is for command A, and 2 bits indicating the channel actually selected by the multiplexer 19. It consists of 3 bits indicating the gain of the amplifier 21, 3 bits indicating other information (other 2), and the remaining 6 bits. The remaining 6 bits are unused and are always set to "0".

  The command B response data is composed of a 2-bit command code “01” indicating that the response data is for the command B, and 14 bits as an A / D conversion value by the A / D converter 17. .

  Next, an outline of communication performed between the input IC 11 and the processing IC 13 will be described with reference to FIGS. In the following description, “CA” means the rotation angle (crank angle) of the crankshaft of the engine, and “TDC” means the top dead center of the cylinder. 3 shows the timing of every 30 ° CA of the engine (each time the crankshaft rotates 30 °). FIG. 4 shows a communication state in a period surrounded by a dotted square frame K1 in FIG.

  First, as shown in FIG. 3, in this embodiment, the knock determination interval (the presence / absence of knocking) for the cylinder from the TDC timing of each cylinder to the timing of ATDC 90 ° CA (after 90 ° CA from TDC) is determined. The section to be determined).

  (1) Then, at the timing of ATDC 90 ° CA of any cylinder and the end timing of the knock determination section of that cylinder, the chip select signal CS from the processing IC 13 to the input IC 11 changes from low level to high level (non-level). Active level), the communication between the ICs 11 and 13 is temporarily terminated, and then the processing IC 13 completes the preparation process for the next communication period, and at this time, the knock determination section of the next cylinder starts. It is well before the TDC timing. At that time, the chip select signal CS from the processing IC 13 to the input IC 11 is switched to the low level, and communication between the ICs 11 and 13 is started again.

  For this reason, the chip select signal CS changes from the low level to the high level at the ATDC 90 ° CA timing of any cylinder, and changes from the high level to the low level sufficiently before the TDC timing of the next cylinder.

  (2) Here, when the chip select signal CS changes from the high level to the low level, the communication unit 31 of the processing IC 13 outputs the communication clock CLK to the input IC 11 via the signal line 2 as shown in FIG. At the same time, the command A (command A transmission data) in the register 42 is transmitted bit by bit through the signal line 3 in synchronization with the communication clock CLK. In parallel with this, the communication unit 31 of the processing IC 13 receives the data transmitted from the input IC 11 via the signal line 4 bit by bit in synchronization with the communication clock CLK and stores it in the register 44. .

  (3) The communication unit 15 of the input IC 11 receives the command A sent from the processing IC 13 via the signal line 3 bit by bit in synchronization with the communication clock CLK, and stores it in the reception data register 47. At the same time, the transmission data in the transmission data register 46 is transmitted to the processing IC 13 bit by bit via the signal line 4 in synchronization with the communication clock CLK.

  Therefore, in synchronization with the communication clock CLK, the command A in the register 42 in the communication unit 31 of the processing IC 13 is transferred to the reception data register 47 in the communication unit 15 of the input IC 11 and at the communication unit 15 of the input IC 11. The transmission data in the transmission data register 46 is transferred to the register 44 in the communication unit 31 of the processing IC 13.

  Immediately after the chip select signal CS becomes low level, valid data is not stored in the transmission data register 46 in the communication unit 15 of the input IC 11, so that it is first transmitted from the input IC 11 to the processing IC 13. The default data is dummy data. In the input IC 11, the input channel selected by the multiplexer 19 is set to either channel ch 0 or channel ch 1 and the gain of the amplifier 21 is set in accordance with the instruction content of the command A received from the processing IC 13. Also, the time from when the chip select signal CS becomes low level to when the first data transmission / reception (data exchange) between the ICs 11 and 13 according to (2) and (3) is completed is less than 10 μs. .

  (4) On the other hand, when the chip select signal CS becomes low level, the input IC 11 starts the timer 23 and thereafter outputs a timing signal from the timer 23 every 10 μs. In the “Timer” stage (second stage from the bottom) in FIG. 4, the upward arrow (↑) indicates the timing of every 10 μs at which the timing signal is output from the timer 23.

  (5) Each time the timing signal is output from the timer 23, the trigger signal Tg from the input IC 11 to the processing IC 13 becomes high level, and the A / D converter 17 is connected to the multiplexer 19 in the input IC 11. A / D conversion is performed on the analog signal input via the amplifier 21.

  (6) When the trigger signal Tg from the input IC 11 becomes high level, in the processing IC 13, the communication unit 31 transmits the command A in the register 42 to the input IC 11 and inputs the same as in (2) above. Data sent from the IC 11 is stored in the register 44.

  (7) Then, the communication unit 15 of the input IC 11 also stores the command A from the processing IC 13 in the reception data register 47 and the transmission data in the transmission data register 46 in the processing IC 13 in the same procedure as the above (3). In this case, the transmission data register 46 stores command A response data for reporting the setting result for the command A received last time.

  Therefore, the command A having the same contents as the previous command is transmitted from the processing IC 13 to the input IC 11, and the command A response data for reporting the setting result for the previous command A (in FIG. 4). In this case, “result” is transmitted.

(8) After that, when the data transmission / reception between the ICs 11 and 13 by the above (6) and (7) is completed, the trigger signal Tg from the input IC 11 to the processing IC 13 returns to the low level.
In this embodiment, since the communication clock CLK is 2 MHz and the communication data is 16 bits, the time required for one data transmission / reception is 8 μs (= 0.5 μs × 16), and the trigger signal Tg The delay from when the signal becomes high level to when communication is started is 1 μs or less. Furthermore, the time required for A / D conversion by the A / D converter 17 is within 9 μs. Therefore, all data transmission / reception and A / D conversion are completed within 10 μs, which is the communication interval between the ICs 11 and 13.

(9) Thereafter, the above operations (6) to (8) are repeated until the number of transmissions of the command A from the processing IC 13 reaches a predetermined number (4 times in the present embodiment).
Note that the above (2) to (9) are operations during a period surrounded by a dotted square frame K2 in FIG.

  (10) When the command A transmitted from the processing IC 13 reaches the fourth command, and then the trigger signal Tg from the input IC 11 to the processing IC 13 becomes high level, the communication unit 31 of the processing IC 13 and the communication unit 15 of the input IC 11 However, data is transmitted and received in the same manner as in (6) and (7) above. In this case, the communication unit 31 of the processing IC 13 transmits the command B in the register 43 to the input IC 11, and in parallel therewith, Data sent from the input IC 11 is stored in the register 44.

  Therefore, in the first data transmission / reception after the transfer of the fourth command A is completed, the command B is transmitted from the processing IC 13 to the input IC 11, and the setting result for the previous command A is transmitted from the input IC 11 to the processing IC 13. Is transmitted, and the command A response data is stored in the register 44.

This (10) is the operation during the period surrounded by the dotted square frame K3 in FIG.
(11) After that, when the next 10 μs timing comes and the trigger signal Tg from the input IC 11 to the processing IC 13 becomes high level, the communication unit 31 of the processing IC 13 and the communication unit of the input IC 11 15 transmits and receives data in the same manner as in the above (6) and (7). In this case, the communication unit 31 of the processing IC 13 transmits the command B in the register 43 to the input IC 11 and from the input IC 11. The sent data is stored not in the register 44 but in the register 45.

  Further, the communication unit 15 of the input IC 11 stores the command B transmitted from the processing IC 13 in the reception data register 47 and transmits the transmission data in the transmission data register 46 to the processing IC 13. In this case, In the transmission data register 46, the latest A / D conversion value by the A / D converter 17 (that is, the A / D converter 17 by the A / D converter 17 during the previous data transmission / reception) as response data for the command B received last time. Command B response data including the converted value) is stored.

  For this reason, the same command B as the previous one is transmitted from the processing IC 13 to the input IC 11, and the command B response data including the latest A / D conversion value by the A / D converter 17 is transmitted from the input IC 11 to the processing IC 13. In FIG. 4, "AD value" is transmitted.

(12) Thereafter, the operation of (11) is repeated until the chip select signal CS from the processing IC 13 to the input IC 11 becomes high level.
The above (11) and (12) are the operations during the period surrounded by the dotted square frame K4 in FIG.

  In the above (11), on the processing IC 13 side, the A / D conversion value from the input IC 11 stored in the register 45 of the communication unit 31 is directly transferred to the digital filter 35 and subjected to digital filter processing. The filter processing results every 10 μs by the digital filter 35 are sequentially stored in the memory 37. The memory 37 may store the filter processing results every 10 μs as they are, but store them in a data-compressed form, for example, by adding a predetermined crank angle or a predetermined number. May be. On the other hand, in the "A / D conversion process" stage (bottom stage) in FIG. 4, the A / D conversion values from the left to the third A / D conversion value are indicated with "(AD conversion)". Indicates that the third A / D conversion value is not actually used for digital filter processing (that is, not transmitted to the processing IC 13).

  Next, in order to realize the communication between the ICs 11 and 13 as described above, the contents of the processes respectively executed by the CPU 39 of the processing IC 13, the communication unit 31 of the processing IC 13, and the communication unit 15 of the input IC 11. This will be described with reference to FIGS.

  First, FIG. 5 is a flowchart showing the contents of 30 ° CA interrupt processing executed every 30 ° CA by the CPU 39 of the processing IC 13. The 30 ° CA interrupt process is activated by a command from the rotation processing unit 33.

  As shown in FIG. 5, when the CPU 39 of the processing IC 13 starts the 30 ° CA interrupt process, first, in S110, the current crank position detected by the rotation processing unit 33 is referred to and the current 30 ° CA is detected. It is determined whether each timing is the timing of ATDC 90 ° CA of any cylinder (that is, whether the current crank position is ATDC 90 ° CA of any cylinder).

  If it is not the timing of ATDC 90 ° CA of any cylinder (S110: NO), the processing is terminated as it is, but if it is the timing of ATDC 90 ° CA of any cylinder (S110: YES), the process proceeds to S120. Proceeding, a stop instruction is issued to the digital filter 35 and the communication unit 31 to stop their operations. Then, the communication unit 31 sets the chip select signal CS to the input IC 11 to the high level in S220 of FIG. 6 to be described later. Accordingly, the communication unit 15 of the input IC 11 also stops the communication operation. Become.

  In subsequent S 130, the filter processing result by the digital filter 35 is read from the memory 37. Of the filter processing results read out here, the filter processing results from the previous TDC timing to the current ATDC 90 ° CA timing are used for knock determination (determination of knocking) by the CPU 39 or another CPU. Further, the knock determination result is fed back to the ignition timing control of the engine.

  Next, in S140, the received data is read from the register 44 of the communication unit 31. The received data read from the register 44 at this time is the last command A response data transmitted by the input IC 11 during the previous communication period (that is, the input IC 11 transmits when the processing IC 13 first transmits the command B). Command A response data) received from the input IC 11 during the period surrounded by the square frame K3 in FIG.

  Then, in the next S150, as preparation processing for the next communication period, the command A data (command A transmission data) to be transmitted to the input IC 11 in the next communication period is written in the register 42 of the communication unit 31, and Command B data (command B transmission data) to be transmitted to the input IC 11 is written to the register 43 of the communication unit 31, and further, the number of transmissions of the command A (“4” in this embodiment) is written to the register 41 of the communication unit 31. .

  Of the bits of command A transmission data to be written to the register 42 at this time, 2 bits (third and fourth bits from the head) indicating the channel to be selected by the multiplexer 19 are the two knock sensors 27 and 29. Of these, the value is set to select a channel to which an analog signal is input from a knock sensor on the bank side where a cylinder that reaches TDC next is provided. Therefore, for example, if the current ATDC 90 ° CA timing is the ATDC 90 ° CA timing of the sixth cylinder # 6, the command A to be written to the register 42 is the first cylinder # 1 since it is the first cylinder # 1. The third and fourth bits from the beginning of the transmission data are set to values for selecting the channel ch0 corresponding to the knock sensor 27 on the right bank side (see FIG. 3).

  Next, in S160, the digital filter 35 is initialized, and an activation instruction is issued to the digital filter 35 and the communication unit 31 to activate them. Then, the communication unit 31 changes the chip select signal CS to the input IC 11 from the high level to the low level in S230 of FIG. 6 to be described later, and starts the communication operation with the input IC 11.

  Next, in S170, it is checked whether or not the content of the reception data (command A reception data) read from the register 44 in S140 is normal. That is, the setting result content on the input IC 11 side represented by the command A received data read from the register 44 is compared with the setting instruction content of the command A transmitted to the input IC 11 during the previous communication period, and both contents match. If it matches, it is determined as normal, and if it does not match, it is determined as abnormal.

  If it is determined in S170 that it is normal, the 30 ° CA interrupt processing is terminated as it is. If it is determined that there is an abnormality, the process proceeds to S180, for example, the input IC 11 is reset, Fail-safe abnormality processing such as discarding the filter processing result read from the memory 37 in S130 without using it for knock determination is performed, and then the 30 ° CA interrupt processing is terminated.

  Next, as shown in FIG. 6, the communication unit 31 of the processing IC 13 first, in S210, either a stop instruction issued by the CPU 39 in the process of S120 or a start instruction issued by the CPU 39 in the process of S160. If the stop instruction is received, the process proceeds to S220, and the chip select signal CS to the input IC 11 is set to the high level. Then, the process returns to S210.

If the activation instruction is received from the CPU 39, the process proceeds from S210 to S230, the chip select signal CS to the input IC 11 is set to the low level, and the process proceeds to the next S240.
In S240, as described in (2) above, the communication clock CLK is output to the input IC 11 via the signal line 2, and the command A transmission data in the register 42 is synchronized with the communication clock CLK. (That is, the data of the command A written to the register 42 by the CPU 39 in S150 of FIG. 5) is transmitted bit by bit through the signal line 3, and in parallel with this, from the input IC 11 through the signal line 4 Received data is received bit by bit and stored in the register 44 as command A received data. However, as described above, at the time of the first data transmission / reception after the chip select signal CS becomes low level, the data transmitted from the input IC 11 is dummy data having a default value.

  Next, in S250, it is determined whether or not a stop instruction is received from the CPU 39. If a stop instruction is received, the process proceeds to S220. If a stop instruction is not received, the process proceeds to the next S260 and the input IC11. It is determined whether the trigger signal Tg from is at a high level.

  If the trigger signal Tg is not at a high level (if it is at a low level), the process returns to S250, but if the trigger signal Tg is at a high level (S260: YES), the process proceeds to S270.

  In S270, the number of transmissions in the register 41 (that is, the number of transmissions of the command A written by the CPU 39 to the register 41 in S150 in FIG. 5 = 4) is read, and the number of transmissions read is a variable “command A number”. And the value of the command A number is decremented (−1).

  Then, in the next S280, it is determined whether or not the value of the command A number has become 0. If the value of the command A number is not 0, the process returns to S240. If it is determined in S280 that the command A number value is 0, the process proceeds to S290 without returning to S240.

  Therefore, the communication unit 31 of the processing IC 13 performs the processing of S240 to S280 four times after setting the chip select signal CS to the low level in S230, thereby transmitting and inputting the command A to the input IC11. Data reception from the IC 11 is performed four times. And the communication operation | movement in the period in the square frame K2 of FIG. 4 described by said (2)-(9) is implement | achieved by this process of S240-S280.

  Next, in S290, the same data transmission / reception operation as in S240 is performed. However, the command B transmission data in the register 43 (that is, the CPU 39 in S150 in FIG. 5) is not sent to the input IC 11 but the command A transmission data in the register 42. The command B data written to the register 43 is transmitted.

  Then, in subsequent S300, it is determined whether or not a stop instruction from the CPU 39 has been received. If a stop instruction has been received, the process proceeds to S220. If a stop instruction has not been received, the process proceeds to the next S310 to input. It is determined whether or not the trigger signal Tg from the IC 11 is at a high level. If the trigger signal Tg is not at a high level (if it is at a low level), the process returns to S300, but if the trigger signal Tg is at a high level (S310: YES), the process proceeds to S320.

  Therefore, the communication unit 31 of the processing IC 13 transmits the command B in the first data transmission / reception after transmitting the fourth command A, and the command A (that is, four commands) transmitted last time is transmitted to the register 44. Command A response data from the input IC 11 for reporting the setting result for the command A) of the eye is stored as command A received data.

And the communication operation in the period within the square frame K3 of FIG. 4 described in the above (10) is realized by the processing of S290 to S310.
Next, in S320, the same data transmission / reception operation as in S290 is performed, and the same command B as the previous one is transmitted to the input IC, but the data sent from the input IC11 is received by the register 45 instead of the register 44. Store as data. Of the data stored in the register 45, the lower 14 bits (that is, the A / D conversion value from the input IC 11) excluding the first 2 bits are transferred to the digital filter 35.

  Next, in S330, it is determined whether or not a stop instruction is received from the CPU 39. If a stop instruction is received, the process proceeds to S220. If a stop instruction is not received, the process proceeds to S340 and the input IC 11 receives the instruction. It is determined whether or not the trigger signal Tg is at a high level. If the trigger signal Tg is not at a high level (if it is at a low level), the process returns to S330. If the trigger signal Tg is at a high level (S340: YES), the process returns to S320 to transmit / receive data again. (Specifically, the command B is transmitted to the input IC 11 and the command B response data is received from the input IC 11).

And the communication operation in the period within the square frame K4 of FIG. 4 described in the above (11) and (12) is realized by the processing of S320 to S340.
Next, as shown in FIG. 7, the communication unit 15 of the input IC 11 first determines in S410 whether or not the chip select signal CS from the processing IC 13 is low level, and the chip select signal CS becomes low level. Wait without doing anything. That is, the communication operation is stopped.

  If it is determined that the chip select signal CS is at the low level (S410: YES), the process proceeds to S420, and data is transmitted and received in synchronization with the communication clock CLK supplied from the processing IC 13 via the signal line 2.

  That is, as described in the above (3), 16-bit data transmitted from the processing IC 13 via the signal line 3 is received bit by bit and stored in the reception data register 47, and in the transmission data register 46. 16-bit transmission data is transmitted to the processing IC 13 bit by bit through the signal line 4. However, as described above, the transmission data to be transmitted first after the chip select signal CS becomes the low level is the default value dummy data.

  When such 16-bit data transmission / reception is completed, the trigger signal Tg to the processing IC 13 is set to a low level in the next S430. Since the initial value of the trigger signal Tg when the chip select signal CS changes from the high level to the low level is the low level, the trigger signal Tg continues to remain at the low level at the time of the first data transmission / reception. (See FIG. 4).

  In subsequent S440, whether the received data is command A depending on whether or not the first 2 bits (command code) in the received data in the received data register 47 received this time in S420 is “10”. If YES in step S450, the flow advances to step S450 to cause the control unit 25 to set the input channel selected by the multiplexer 19, the gain of the amplifier 21, and the like according to the instruction content of the received command A.

  Next, in S460, in preparation for the next transmission, the setting result for the command A received this time (that is, the channel actually selected by the multiplexer 19 and the gain of the amplifier 21 actually set) is reported to the processing IC 13. Command A response data is generated and stored in the transmission data register 46.

  Then, in subsequent S470, it is determined whether or not the chip select signal CS remains at a low level. If the chip select signal CS is not at a low level (if it is at a high level), the process returns to S410, but the chip select signal CS is returned. If the signal CS remains at the low level, the process proceeds to S480, where it is determined whether or not the timing signal is output from the timer 23 every 10 μs. If the timing signal is not output, the process returns to S470. If the timing signal is output, the process proceeds to S490.

  In S490, the trigger signal Tg to the processing IC 13 is set from the low level until then to the high level, and in the next S500, the A / D converter 17 starts A / D conversion. Then, the process returns to S420.

  Then, since the trigger signal Tg becomes high level, data transmission / reception with the processing IC 13 is performed again in S420. In this case, in S420, the data was stored in the transmission data register 46 in the previous S460. The command A response data is transmitted to the processing IC 13.

  Then, while the command A is continuously transmitted from the processing IC 13 and it is determined in S440 that the received data is the command A, the processing of S420 to S500 is repeated. And the communication operation in the period in the square frames K2 and K3 in FIG. 4 is realized by the processing of S420 to S500.

  On the other hand, if it is determined in S440 that the received data received this time in S420 is not command A (S440: NO), it is determined that the data received this time is command B, and the process proceeds to S510. Note that such a determination can be made because, in the present embodiment, either the command A or the command B is transmitted from the processing IC 13 to the input IC 11.

  In S510, it is confirmed as a precaution based on the first two bits (command code) in the received data whether the received data in the received data register 47 received this time is the command B or not. That is, it is confirmed whether or not the first two bits in the received data are “01”. If the received data is not command B, it indicates that an abnormality that an indefinite command has been received (that is, an abnormality that a command that is not command B but that command B should have been received) has occurred. Anomaly information is stored.

  In the next S520, as the next transmission preparation, as the response data for the command B received this time, the latest A / D conversion value by the A / D converter 17 (that is, the A / D during the current data transmission / reception). Command B response data including the value A / D converted by the converter 17 is created and stored in the transmission data register 46.

  In subsequent S530, it is determined whether or not the chip select signal CS remains at a low level. If the chip select signal CS is not at a low level (if it has become a high level), the process returns to S410. If the signal CS remains at the low level, the process proceeds to S540, and it is determined whether or not the timing signal is output from the timer 23 every 10 μs. If the timing signal is not output, the process returns to S530, but if the timing signal is output, the process proceeds to S550.

In S550, the trigger signal Tg to the processing IC 13 is set from the low level until then to the high level, and in the next S560, the A / D converter 17 starts A / D conversion.
Thereafter, the process proceeds to S570, and data is transmitted and received in synchronization with the communication clock CLK supplied from the processing IC 13 via the signal line 2 in the same manner as in S420. However, in this case, the command B response data stored in the transmission data register 46 in the previous S520 is transmitted to the processing IC 13.

When data transmission / reception of 16 bits is completed in S570, the process proceeds to S580, the trigger signal Tg to the processing IC 13 is set to a low level, and then the process returns to S510.
For this reason, after determining that the received data is not command A (command B) in S440 and proceeding to S510, S510 to S530 until it is determined that the chip select signal CS has become high level. Every time the processing of S580 is repeated and the timing signal is output from the timer 23, the command B is received from the processing IC 13 and the latest A / D conversion value every 10 μs is transmitted to the processing IC 13 as command B response data. Will be. Further, the processing of S510 to S580 is repeated regardless of whether or not the command from the processing IC 13 is the command B. By the processing of S510 to S580, the processing within the rectangular frame K4 in FIG. The communication operation during the period is realized.

  In the signal processing apparatus of the present embodiment as described above, the processing IC 13 transmits the command B to the input IC 11 every predetermined time Tc (= 10 μs) while the chip select signal CS to the input IC 11 is at a low level. Each time the input IC 11 receives the command B, the A / D conversion value of the analog signal by the A / D converter 17 is returned to the processing IC 13 as command B response data, so that the input IC 11 returns to the processing IC 13. The A / D conversion value for every fixed time Tc is transferred, and the A / D conversion value for every fixed time Tc is digitally filtered by the digital filter 35 on the processing IC 13 side.

  In particular, in the signal processing apparatus according to the present embodiment, when the input IC 11 determines once that the command B has been received after the chip select signal CS becomes low level (S440: NO), then the chip select signal CS is Until a high level is reached, the latest A / D conversion value by the A / D converter 17 is received each time a command from the processing IC 13 is received, regardless of whether the command from the processing IC 13 is the command B or not. (Command B response data transmission) is performed.

  Therefore, according to the signal processing apparatus of the present embodiment, the input IC 11 receives the command B even once after the chip select signal CS becomes low level, as exemplified in the period within the square frame K4 in FIG. After that, even if noise is added to the command B from the processing IC 13 and the command B is received as an indefinite command (undefined command) or command A, the processing IC 13 is exactly the same as when no noise is applied. Since the AD conversion value is transmitted to the processing IC 13, the correct time-series A / D conversion value can be received by the processing IC 13, and the A / D conversion input to the digital filter 35 on the processing IC 13 side. It is possible to prevent the value from being cut off in the middle or suddenly becoming an indefinite value. Therefore, digital filter processing can be performed accurately.

  For example, if the present invention is not applied, if the signal B 3 from the processing IC 13 to the input IC 11 has noise and the command B becomes an indefinite command, the A / D conversion from the input IC 11 to the processing IC 13 is performed. Either no value is returned or an indefinite value is returned. Then, as shown in FIG. 8A, the input to the digital filter 35 becomes an indefinite value (0 in this example) and is processed as a different frequency. As a result, correct knock determination can be performed. It becomes impossible.

  When the signal B 3 from the processing IC 13 to the input IC 11 is noised and the command B becomes the command A, the input IC 11 has a selection channel of the multiplexer 19 (specifically, an input channel selected by the multiplexer 19) or The gain of the amplifier 21 is switched unnecessarily. Then, as shown in FIG. 8B, the subsequent input to the digital filter 35 becomes an A / D conversion value of a different input channel or an A / D conversion value with a different gain. A correct knock determination cannot be made. In particular, when the A / D converter 17 is an oversampling A / D converter, if the input channel or gain changes and a completely different voltage is input, then the correct setting is made. Even if it can be restored, it takes time until the output of the A / D converter 17 converges, and the influence remains several times after the noise generation timing.

  On the other hand, in the signal processing apparatus according to the present embodiment, after receiving the command B once, the input IC 11 performs an operation on the command B no matter what command is received, so that noise is generated in the signal line 3. Even if it is on the board, the processing IC 13 can capture the correct A / D conversion values and carry out the digital filter processing correctly. Therefore, correct knock determination can be performed.

  Further, in the signal processing apparatus of the present embodiment, the processing IC 13 sets the chip select signal CS to the low level, then transmits the function setting command A to the input IC 11 and then starts to transmit the command B. When receiving the command A, the IC 11 sets the selected channel of the multiplexer 19 and the gain of the amplifier 21 according to the command A. Therefore, for each communication period between the input IC 11 and the processing IC 13, the setting of the selected channel and gain in the input IC 11 can be changed by the command A transmitted from the processing IC 13 to the input IC 11 prior to the command B.

Here, in the present embodiment, the number of times that the processing IC 13 transmits the command A is set to four times, for the following reason.
First, in the present embodiment, a predetermined time T1 is required until the output of the A / D converter 17 is stabilized after the chip select signal CS becomes low level. This uses an oversampling A / D converter as the A / D converter 17 and requires several tens of μs as a calibration time (output stabilization time) of the A / D converter 17 itself. Furthermore, it is because a certain time is required to change the selected channel of the multiplexer 19 and the gain of the amplifier 21. In the present embodiment, 30 μs is required as the predetermined time T1.

  Therefore, in this embodiment, the processing IC 13 transmits the command A four times, which is an integer value equal to or greater than “T1 / Tc = 30 μs / 10 μs”, until the output of the A / D converter 17 becomes stable. Earn time.

  For this reason, the A / D conversion value after the output of the A / D converter 17 is stabilized is returned as the command B response data for the command B from the input IC 11 to the processing IC 13. The accuracy of the digital filter processing at can be improved. In addition, it is not necessary to set a special command for intentionally providing a delay.

  On the other hand, in the signal processing device of the present embodiment, the processing IC 13 changes the chip select signal CS from low level to high level at the timing of ATDC 90 ° CA when the knock determination section of each cylinder ends, and immediately after that, An analog signal for determining the knocking of the next cylinder by starting the transmission of the command A by setting the chip select signal CS to the low level sufficiently before the TDC timing at which the knocking determination section of the next cylinder arrives. Is selected by the multiplexer 19 of the input IC 11 and the transmission of the command B is also started. Thus, A / D conversion and digital filter processing can be started before the knock determination section of each cylinder is started.

  For this reason, before the knock determination section starts, the A / D converter 17 can also stabilize the output value (digital filter processing result) of the digital filter 35 from the beginning, and consequently the digital filter processing result. The accuracy of knock determination using can be improved. That is, the period from BTDC 90 ° CA to TDC of each cylinder is a period for stabilizing the output value of the digital filter 35.

  In this embodiment, the communication unit 31 of the processing IC 13 includes a register 44 that stores command A reception data as a response result to the command A, and a register that stores command B reception data as a response result to the command B. And 45 separately.

  Therefore, the command A received data is not overwritten with the command B received data, and the CPU 39 of the processing IC 13 reads the command A received data from the register 44 after the communication with the input IC 11 is finished (S140). Command A received data can be checked (S170), and the processing load on the CPU 39 can be reduced.

  The configuration in which the register 44 and the register 45 are separately provided in this way is as follows: “After the input IC 11 receives the command B (A / D conversion request command) once, the chip select signal CS (communication permission signal) is inactive level. Until the command is received, the A / D conversion value of the analog signal by the A / D converter 17 is sent to the processing IC 13 every time the command from the processing IC 13 is received regardless of whether the command from the processing IC 13 is the command B or not. It can be used even if it is not a configuration of “transmitting”.

That is, if the input IC 11 is called a first device and the processing IC 13 is called a second device, the second device only needs to have the characteristics of the following filter processing device.
That is, “a first device that has an A / D converter that A / D converts an analog signal and communicates with another device via a communication line when an external communication permission signal is at an active level;
The analog signal by the A / D converter is connected for a certain time by being connected to the first device via the communication line and communicating with the first device at a certain time by setting the communication permission signal to an active level. A second device that sequentially acquires each A / D conversion value and performs digital filter processing on the acquired time-series A / D conversion value;
The second device transmits an A / D conversion request command of a plurality of types of commands to the first device at regular intervals in a state where the communication permission signal is set to an active level. Each time the A / D conversion request command is received, the A / D conversion value of the analog signal by the A / D converter is returned to the second device, thereby the first device to the second device. The A / D conversion value of the analog signal by the A / D converter is transferred at regular intervals,
Further, after setting the communication permission signal to an active level, the second device transmits a predetermined number of function setting commands other than the A / D conversion request command to the first device, and then the A / D In the signal processing device for starting transmission of the D conversion request command, a filter processing device used as the second device,
A first storage for storing received data from the first device for the function setting command; and a second storage for storing received data from the first device for the A / D conversion request command. A filter processing device characterized by being provided separately.

  Then, according to the second device having such a feature, as described in S170 of FIG. 5, even when noise is applied to the function setting command from the second device to the first device, By comparing the received data stored in the storage unit (received data from the first device for the function setting command) with the data of the function setting command transmitted from the second device to the first device, communication error Can be detected and whether or not wrong data has been used for the digital filter can be surely confirmed, so that the digital filter processing can be performed accurately.

  On the other hand, in the above-described embodiment, a timing signal for every predetermined time Tc is generated on the input IC 11 side, and according to the timing signal, A / D conversion of the analog signal by the A / D converter 17 and communication between the ICs 11 and 12 are performed. And are to be executed.

  For this reason, the A / D conversion interval can be made accurate. In other words, as a reverse configuration, the processing IC 13 becomes a master for determining the timing. For example, when the input IC 11 receives a command from the processing IC 13 every predetermined time Tc, the A / D converter 17 is activated and A Although a configuration in which a / D conversion value is transmitted is also conceivable, in this configuration, there is a possibility that the A / D conversion timing is shifted due to a communication delay or the like. On the other hand, according to the signal processing device of the present embodiment, digital filter processing can be performed on an accurate A / D conversion value for each constant time Tc, and knock determination using the filter processing result can be performed. Accuracy can be increased.

  By the way, in the above embodiment, the communication unit 15 of the input IC 11 determines whether or not the first two bits of the received data are “10” indicating the command A in S440 of FIG. For example, it is determined that the received data is the command B, but in S440, it is determined whether or not the first 2 bits of the received data are “01” indicating the command B. Otherwise, it is determined that the received data is the command A and the process proceeds to S450. If “01”, the received data is determined to be the command B and the process proceeds to S510.

  In the above embodiment, the CPU 39 of the processing IC 13 may include the number of command A transmissions in the command A transmission data written to the register 42 in S150 of FIG. For example, 3 bits of the 8th to 10th bits (3 bits indicated as “other 1” in FIG. 2) from the head of the command A transmission data can be used as data representing the number of commands A transmitted. In this way, the number of transmissions of the command A is included in the command A and transmitted from the processing IC 13 to the input IC 11.

  Further, in this case, the input IC 11 includes the number of transmissions included in the command A from the processing IC 13 and the command A actually transmitted from the processing IC 13 after the chip select signal CS becomes low level. The number (that is, the number of continuous times from S440 to S450 in FIG. 7) is compared.

  With this configuration, even when the command A from the processing IC 13 is garbled into the command B due to noise and the garbled command B is received, for example, the input IC 11 receives such an abnormality (that is, the command It is possible to detect the occurrence of a command number abnormality in which the number of A is not a normal value.

  In the above embodiment, the communication unit 15 of the input IC 11 displays abnormality information (for example, abnormality information stored in S510 of FIG. 7) indicating a communication abnormality that occurred during the communication period in which the chip select signal CS is at a low level. In the next communication period in which the chip select signal CS once becomes a high level and then becomes a low level, the command A response data may be included and transmitted to the processing IC 13. For example, if the communication unit 15 creates the command A response data in S460 of FIG. 7 and there is abnormality information stored in the process of S510 during the previous communication period, the communication unit 15 starts from the top of the command A response data. 8 bits to 10 bits (3 bits indicated as “other 2” in FIG. 2) can be used as data representing the abnormality information.

  By doing so, it is not necessary to transmit abnormality information indicating an abnormality that has occurred during the communication period from the input IC 11 to the processing IC 13 together with the A / D conversion value, and therefore, from the input IC 11 to the processing IC 13. The A / D conversion value can be transferred efficiently. In addition, it is advantageous in that it is more reliable to transmit the occurrence of an abnormality during the next normal communication period than to transmit during the communication period in which the abnormality has occurred.

Note that the abnormality information transmitted from the input IC 11 in the command A response data may be information indicating the occurrence of the above-described abnormality in the number of commands.
In the above embodiment, the communication unit 15 and the control unit 25 of the input IC 11 take the majority of the contents of the four commands A received from the processing IC 13, and the internal function of the input IC 11 according to the result of the majority ( It may be configured to set the selected channel of the multiplexer 19 and the gain of the amplifier 21.

  With this configuration, the internal function of the input IC 11 can be set correctly even if noise is added to the last (fourth) command A among the commands A from the processing IC 13 to the input IC 11. become able to.

  On the other hand, in the above embodiment, of the bits in the command B response data from the input IC 11 to the processing IC 13, 2 bits other than the A / D conversion value are not command data but redundant bits (such as parity) for communication error check. It is also good. If the A / D conversion value by the A / D converter 17 is 16 bits instead of 14 bits, all the bits of the command B response data may be converted to A / D conversion values.

  In the above embodiment, the analog signal (knock signal) to be A / D converted that is input from the knock sensors 27 and 29 to the multiplexer 19 of the input IC 11 is, for example, in the range of ± 2.5 V centered on 2.5 V. The A / D conversion value transmitted from the input IC 11 to the processing IC 13 is a signal of 0 to 5 V that changes, and the following forms (A) or (B) are conceivable. In any case, it is assumed that the number of bits of the A / D conversion value is 14 bits.

  (A): First, the actual center value of the knock signal is measured in advance by the A / D converter 17. On the input IC 11 side, a value obtained by subtracting the measured value of the center value as an offset value from each A / D conversion value obtained by A / D converting the knock signal during the communication period with the processing IC 13 is transmitted to the processing IC 13. A / D conversion value to be used. In other words, in this case, offset correction is performed on the input IC 11 side, and the processing IC 13 is notified that “center value (2.5 V) = 0 count, maximum value (5 V) = + 8192 count, minimum value (0 V) = −. An A / D conversion value of “8192 counts” will be transmitted.

  (B): Without performing offset correction on the input IC 11 side, each A / D conversion value obtained by A / D converting the knock signal is transmitted as it is from the input IC 11 to the processing IC 13. That is, an A / D conversion value “0V = 0 count, 5V = 16383” is transmitted to the processing IC 13.

  In this case, on the processing IC 13 side, the offset value corresponding to the center value of the knock signal is subtracted from each A / D conversion value received from the input IC 11, and “center” is the same as in the case of (1) above. A / D conversion values of “value (2.5V) = 0 count, maximum value (5V) = + 8192 count, minimum value (0V) = − 8192 count” may be obtained.

  The offset value used on the processing IC 13 side may be a fixed value (= 8192), but the measured value obtained by measuring the actual center value of the knock signal by the A / D converter 17 is processed from the input IC 11 as the offset value. You may make it transmit to IC13 in advance.

  Further, when the offset value is obtained by actual measurement, if the center value of the knock signal is not 2.5 V, the A / D conversion value after the offset correction (A / D conversion value after subtracting the offset value) overflows. Therefore, on the processing IC 13 side, the A / D conversion value after offset correction is further set to the minimum value if the value is smaller than the minimum value, and the maximum value if the value is larger than the maximum value. What is necessary is just to implement guard processing, such as. In this way, the A / D conversion value subject to digital filter processing can be correctly processed without overflowing.

  On the other hand, the digital filter 35 in the processing IC 13 may be an FIR type, but an IIR type is used in this embodiment. This is because when a low-frequency signal is digitally filtered until the engine rotates at a high speed, the knock determination section ends before the filter and the filter processing result are stabilized if the FIR type digital filter is used.

  As mentioned above, although one Embodiment of this invention was described, this invention is not limited to such Embodiment at all, Of course, in the range which does not deviate from the summary of this invention, it can implement in a various aspect. .

  For example, in the above embodiment, the input IC 11 continuously executes A / D conversion every 10 μs in the background in order to quickly return the A / D conversion value to the processing IC 13, and each A / D conversion value is However, for example, the configuration may be such that when the command B is received, the A / D converter 17 is activated and the A / D conversion value is transmitted. In this case as well, once the input IC 11 receives the command B, the A / D converter 17 is activated and the A / D conversion value is obtained no matter what command is received thereafter. What is necessary is just to comprise so that operation | movement of transmitting may be performed.

  In the above embodiment, the knock sensors 27 and 29 are vibration sensors that output an analog signal corresponding to the vibration of the engine. However, as an analog signal to be A / D converted, the pressure in the cylinder is detected. It may be a signal from the cylinder pressure sensor (CPS) or a signal representing an ionic current. Furthermore, the analog signal to be A / D converted is not limited to a signal for performing engine knock determination, and may be another analog signal.

It is a block diagram showing the structure of the signal processing apparatus of embodiment. It is a figure showing the format of communication data. It is a 1st time chart showing the outline | summary of the communication implemented by input IC and processing IC. It is a 2nd time chart showing the outline | summary of the communication implemented by input IC and processing IC. It is a flowchart showing the 30 degree CA interruption process performed with CPU of processing IC. It is a flowchart showing the process performed by the communication part of process IC. It is a flowchart showing the process performed by the communication part of input IC. It is explanatory drawing explaining the problem when this invention is not applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1-5 ... Signal line, 11 ... Input IC (1st apparatus), 13 ... Processing IC (2nd apparatus), 15, 31 ... Communication part, 17 ... A / D converter, 19 ... Multiplexer, 21 ... Amplifier, DESCRIPTION OF SYMBOLS 23 ... Timer, 25 ... Control part, 27, 29 ... Knock sensor, 33 ... Rotation processing part, 35 ... Digital filter, 37 ... Memory, 41-45 ... Register, 46 ... Transmission data register, 47 ... Reception data register

Claims (9)

A first device having an A / D converter for A / D converting an analog signal and communicating with another device via a communication line when a communication permission signal from the outside is at an active level;
The analog signal by the A / D converter is connected for a certain time by being connected to the first device via the communication line and communicating with the first device at a certain time by setting the communication permission signal to an active level. A second device that sequentially acquires each A / D conversion value and performs digital filter processing on the acquired time-series A / D conversion value;
The second device transmits an A / D conversion request command of a plurality of types of commands to the first device at regular intervals in a state where the communication permission signal is set to an active level. Each time the A / D conversion request command is received, the A / D conversion value of the analog signal by the A / D converter is returned to the second device, thereby the first device to the second device. A signal processing device to which an A / D conversion value of the analog signal by the A / D converter is transferred every predetermined time,
The first device once determines that the A / D conversion request command has been received after the communication permission signal becomes active level, and thereafter, until the communication permission signal becomes inactive level, Regardless of whether the command from the two devices is the A / D conversion request command or not, every time the command from the second device is received, the analog signal by the A / D converter is sent to the second device. Sending an A / D conversion value;
A signal processing device. The signal processing device according to claim 1,
After the communication permission signal is set to an active level, the second device transmits a predetermined number of function setting commands other than the A / D conversion request command to the first device, and then performs the A / D conversion. Start sending request command,
When the first device receives the function setting command after the communication permission signal becomes an active level, the first device sets an internal function according to the function setting command;
A signal processing device. The signal processing device according to claim 2,
The time required until the output of the A / D converter is stabilized after the communication permission signal becomes an active level is T1, and the predetermined time which is a communication interval between the first device and the second device is set as T1. T2
The second device sets the communication permission signal to an active level, transmits the function setting command for an integer number of times equal to or greater than “T1 / T2”, and then transmits the A / D conversion request command. To get started,
A signal processing device. In the signal processing device according to claim 2 or 3,
The second device includes the number of function setting commands transmitted from when the communication permission signal is set to an active level to when the A / D conversion request command is transmitted, in the function setting command. It is designed to send to 1 device,
The first device includes the function setting command that is actually transmitted from the second device after the number of transmissions included in the function setting command and the communication permission signal becomes an active level. Comparing the number of
A signal processing device. The signal processing device according to any one of claims 2 to 4,
When the communication permission signal once becomes an inactive level and then becomes an active level, the first device, when the communication permission signal once becomes an inactive level, Including it in response data to the function setting command and transmitting it to the second device;
A signal processing device. The signal processing device according to any one of claims 2 to 5,
The first device receives analog signals from a plurality of knock sensors for detecting engine knocking as the analog signals, and among the plurality of analog signals, a function setting command from the second device is used. One analog signal to be instructed is selected and input to the A / D converter,
When one of the knock determination intervals set for each cylinder of the engine ends, the second device changes the communication permission signal from the active level to the inactive level, and then the knock determination interval for the next cylinder arrives. Before the operation, the communication permission signal is set to an active level, and the function setting command is transmitted, so that, among the plurality of analog signals, an analog signal for determining knocking of the next cylinder is determined as the first signal. The device is selected and the transmission of the A / D conversion request command is started.
A signal processing device. The signal processing device according to any one of claims 2 to 6,
The second device stores a first storage unit that stores data received from the first device for the function setting command, and stores data received from the first device for the A / D conversion request command. Providing a second storage unit separately;
A signal processing device. The signal processing device according to any one of claims 2 to 7,
The second device transmits a plurality of function setting commands having the same contents as the function setting command after setting the communication permission signal to an active level,
The first device takes a majority vote of the contents of the plurality of function setting commands received from the second device, and sets an internal function according to the result of the majority vote;
A signal processing device. The signal processing device according to any one of claims 1 to 8,
A timing signal for each predetermined time is generated on the first device side, and according to the timing signal, A / D conversion of the analog signal by the A / D converter and communication between the first device and the second device. Is executed,
A signal processing device.

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