JP2006109091A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the clock signal delay variation increases to reduce the operation margin due to the transistor driving power deterioration when partly stopping unwanted clock signals according to the operating condition for reducing the power. <P>SOLUTION: A clock signal control circuit 1 is used which inputs a clock signal CLK, a stop signal EN, a fixed output switching signal INV to generate and output a signal corresponding to the clock signal as a register control signal with the clock stop signal is high, and a signal corresponding to the fixed output switching signal as a register control signal when the clock stop signal is low. A select circuit 10 or 13 is added to a register input unit to prevent the malfunction due to switching of the register control signal during the clock stopped. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly, to an improved clock signal control circuit for controlling the operation of a register built in a semiconductor device such as an LSI composed of MOS transistors.

  In recent years, a technique of partially stopping unnecessary clock signals according to the operating state of an LSI has been widely used in order to reduce the power consumption of the LSI. According to this method, instead of using the clock signal as the register control signal as it is, the clock signal is controlled using the second control signal indicating the operation state, thereby reducing the power required for driving the register. can do.

  FIG. 12 shows an example of the configuration of a semiconductor device using such a conventional clock signal control circuit. In addition, the same code | symbol as a terminal shall be used also for the data and signal input / output from each terminal in a figure.

  In FIG. 12, the clock signal control circuit 2 has a clock signal terminal CLK and a clock stop signal terminal EN as input terminals, and a register control signal terminal GCK as output terminals.

The clock generation circuit 100 generates a clock signal CLK and outputs it to the clock signal terminal of the clock signal control circuit 2.
The controller 101 generates a clock stop signal EN and outputs it to the clock stop signal terminal of the clock signal control circuit 2.
The flip-flop circuits 20 to 23 each have a D terminal and a CK terminal as input terminals and a Q terminal as an output terminal.

  The data input terminals D0 to D3 of this semiconductor device are connected to the D terminals of the flip-flop circuits 20 to 23, and the data output terminals Y0 to Y3 are connected to the Q terminals of the flip-flop circuits 20 to 23, respectively. The register control signal terminal GCK is connected to the CK terminals of the flip-flop circuits 20-23.

  FIG. 13 shows a configuration example of a clock signal control circuit 2 of a conventional semiconductor device, which generates and outputs a logical product of two input signals A and B. In the example of FIG. 12, the clock signal control circuit 2 is realized by a 2-input AND circuit AND60, and outputs a logical product of the clock signal terminal CLK and the clock stop signal terminal EN as a register control signal GCK.

  FIG. 14 shows an example of the configuration of flip-flop circuits 20 to 23 in a conventional semiconductor device, which includes PMOS transistors P1 to P7, NMOS transistors N1 to N7, and inverting circuits X1 to X5. Is output.

  The inverting circuit X1 outputs the inverted value of the input signal CK to the node n1, and the inverting circuit X2 outputs the inverted value of the node n1 to n2. For this reason, the value of the node n2 becomes equal to the value of the input signal CK. The inverting circuit X3 outputs the inverted value of n3 to the node n4. The inverting circuit X4 outputs the inverted value of n5 to the node n6, and the inverting circuit X5 outputs the inverted value of the node n6 as the output signal Q.

  The MOS transistors N5 and P5 that share the source and drain constitute a transfer gate TG1, and transmit a signal from the node n4 to the node n5 only when the input signal CK is at the H level.

  MOS transistors N1, N2, P1, and P2 constitute a tristate inverter T11, and output an inverted value of the input signal D to the node n3 only when the input signal CK is at L level, and the node n3 when the input signal CK is at H level. Do not drive.

  MOS transistors N3, N4, P3 and P4 constitute a tri-state inverter T12, which outputs an inverted value of n4 to node n3 only when input signal CK is at H level, and drives node n3 when input signal CK is at L level. do not do.

  MOS transistors N6, N7, P6 and P7 constitute a tri-state inverter T13, which outputs an inverted value of n6 to node n5 only when input signal CK is at L level, and drives node n5 when input signal CK is at H level. do not do.

In summary,
CK is L => T11, so n1 = / D ("/" indicates inversion of signal)
And T12 is off ("off" means not driving the node of the output)
And TG1 is off and n5 = / n6 by T13
Also,
CK is H⇒T11 is OFF and T3 is n3 = / n4
And n5 = n4 by TG1
And T13 is turned off.

  Thus, when the input signal CK is at L level, the tri-state inverter T13 (MOS transistors N6, N7, P6, P7) operates as an inverting circuit, and thus forms an inverter loop together with the inverting circuit X4. At this time, since the transfer gate TG11 (MOS transistors N5 and P5) does not drive the node n5, the nodes n5 and n6 hold the previous state. As a result, the output signal terminal Q outputs the previous signal. The tri-state inverter T11 (MOS transistors N1, N2, P1, and P2) outputs an inverted value of the input signal D to the node n3, and the node n4 outputs the same value as the input signal D by the inverting circuit X3. At this time, since the transfer gate TG1 and the tristate inverter T12 (MOS transistors N3, N4, P3, P4) are off, the node n4 holds this value.

  When the input signal CK is at the H level, the tri-state inverter T12 (MOS transistors N3, N4, P3, P4) operates as an inverting circuit, and thus forms an inverter loop together with the inverting circuit X3. At this time, since the tri-state inverter T11 (MOS transistors N1, N2, P1, and P2) does not drive the node n3, the nodes n3 and n4 hold the previous state. Since the transfer gate TG11 (MOS transistors N5, P5) transmits the contents of the node n4 to the node n5, and the tristate inverter T12 (MOS transistors N6, N7, P6, P7) does not drive the node n5, the inverting circuit X4 The same value as the node n4 is output to the Q output via X5.

  Therefore, the circuit of FIG. 14 takes in the value of the input D at the rising edge when the CK signal changes from L to H, outputs this to the Q output, and otherwise holds the previous state. Works as.

  In the semiconductor device of FIG. 12 having such flip-flops 20 to 23, when the clock control signal EN is at the H level, the flip-flop circuits 20 to 23 receive the data output signal according to the values of the data input signals D0 to D3. Y0 to Y3 are updated at a timing synchronized with the clock signal CLK. On the other hand, when the clock control signal EN is at the L level, the register control signal GCK is fixed, and the data output signals Y0 to Y3 are not updated and retain the previous contents.

In this case, both the power necessary for driving the register control signal terminal GCK and the power consumed by the flip-flop circuits 20 to 23 are suppressed.
JP-A-9-284101 (page 9, FIG. 19)

  When the conventional clock signal control circuit described above is used, when the register control signal GCK is fixed at the same value for a long time, the gate of the MOS transistor controlled by GCK is also held at the same potential for a long time. In the example of FIG. 12, this corresponds to the transistors P1, P3, P5, P6, N2, N4, N5, N7 and the transistors constituting the inverting circuits X1, X2 of FIG.

  In recent years, transistor performance due to Negative Bias Temperature Instability (characteristics that drive capability deteriorates when a low voltage is applied to the gate to the substrate; hereinafter referred to as NBTI) due to process miniaturization and drive voltage reduction Deterioration of the material has become an issue.

  In particular, when a plurality of register control signals are generated using a plurality of clock stop signals, the amount of delay variation due to aging deterioration differs for each register control signal, so that malfunction due to clock skew (arrival time difference) is likely to occur.

  In order to prevent malfunction caused by delay variation due to NBTI, it is necessary to set a larger circuit operation margin than in the past. However, an increase in the operating margin becomes a factor that hinders speeding up and a cost increase due to an increase in circuit scale, which is a major problem in circuit design.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to reduce delay variation of the register control signal and to achieve both low power consumption and high-speed operation by partially stopping the clock. It is an object to provide a semiconductor device having a clock signal control circuit.

  In order to solve the above-described problem, a semiconductor device according to claim 1 of the present invention is configured to stop a clock signal that periodically repeats a first logic value and a second logic value and output of the clock signal. And a fixed output switching signal for switching the value of the output signal when output as a fixed value. When the clock stop signal is the first logic value, the clock signal corresponds to the clock signal. A clock signal control circuit that generates and outputs a signal as a register control signal, and generates and outputs a signal corresponding to the fixed output switching signal as the register control signal when the clock stop signal is the second logic value; A data signal, a second data signal, and the clock stop signal are input, and when the clock stop signal is the first logic value, the first data signal is A selection circuit that generates and outputs a corresponding signal, and generates and outputs a signal corresponding to the second data signal when the clock stop signal is the second logic value, an output signal of the selection circuit, and the register control And a logic circuit that updates the output in synchronization with the register control signal, and a logic that repeats the first and second logic values at a period sufficiently longer than the clock signal as the fixed output switching signal. And an output switching signal generation circuit for generating a signal, wherein an output node of the synchronization circuit is connected to an input node of the second data signal.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the synchronization circuit receives the output signal of the selection circuit and the register control signal as input. A signal corresponding to the output signal of the selection circuit is generated and output when transitioning from the second logic value to the first logic value, and the previous output value is held otherwise. It is characterized by.

  According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the synchronization circuit receives the output signal of the selection circuit and the register control signal, and the register control signal is In the case of the first logical value, a signal corresponding to the output signal of the selection circuit is generated and output. In other cases, the previous output value is held.

  According to a fourth aspect of the present invention, there is provided a semiconductor device having a clock signal that periodically repeats the first logic value and the second logic value, a clock stop signal for stopping the output of the clock signal, A fixed output switching signal for switching the value of the output signal when output as a fixed value is input, and when the clock stop signal is the first logic value, a signal corresponding to the clock signal is used as a register control signal A clock signal control circuit that generates and outputs a signal corresponding to the fixed output switching signal as the register control signal when the clock stop signal is the second logic value, a first data signal, and the register The control signal and the clock stop signal are input, the clock stop signal is the second logical value, and the register control signal is the second argument. A synchronous circuit that generates and outputs a signal corresponding to the first data signal when transitioning from a value to the first logical value; otherwise, holds a previous output value; and the fixed output switching signal And an output switching signal generation circuit for generating a logic signal that repeats the first and second logic values with a period sufficiently longer than that of the clock signal.

  According to a fifth aspect of the present invention, in the semiconductor device according to the first or fourth aspect, the clock signal control circuit generates and outputs a logical product signal of the clock signal and the clock stop signal. A first AND circuit; a first inverting circuit that generates and outputs an inverted signal of the clock stop signal; and a first that generates and outputs a logical sum signal of the clock signal and the output signal of the first inverting circuit. A logical sum circuit, a second logical product circuit that generates and outputs a logical product signal of the output signal of the first logical product circuit and the fixed output switching signal, and generates and outputs an inverted signal of the fixed output switching signal. A second inverting circuit that generates, outputs a logical product signal of the output signal of the first logical sum circuit and the output signal of the second inverting circuit, and the second logical circuit. The output signal of the product circuit and the third And a second logical sum circuit that generates and outputs a logical sum signal with the output signal of the logical product circuit, and outputs the output result of the second logical sum circuit as the register control signal. is there.

  According to a sixth aspect of the present invention, there is provided a semiconductor device having a clock signal that periodically repeats the first logic value and the second logic value, and a first clock stop for stopping the output of the clock signal. When the first clock stop signal is the first logic value, the signal and a fixed output switching signal for switching the value of the output signal when output as a fixed value are input. A signal is generated and output as a first register control signal, and a signal corresponding to the fixed output switching signal is generated and output as the first register control signal when the first clock signal has a second logic value. The clock signal control circuit, the first register control signal, the first clock stop signal, and the second clock stop signal for stopping the output of the clock signal are input. When both the first clock stop signal and the second clock stop signal are at the first logic value, a signal corresponding to the first register control signal is generated and output as a second register control signal, A second clock signal control circuit for generating and outputting a fixed value as the second register control signal when the first clock stop signal is the second logic value; and outputting in synchronization with the second register control signal And an output switching signal generating circuit for generating a logic signal that repeats the first and second logic values at a sufficiently longer period than the clock signal as the fixed output switching signal. It is a feature.

  According to a seventh aspect of the present invention, in the semiconductor device according to the sixth aspect, the synchronization circuit receives the first data signal and the second register control signal as inputs. When the second register control signal transitions from the second logic value to the first logic value, a signal corresponding to the first data signal is generated and output; otherwise, the previous output value is set. It is what hold | maintains.

  The semiconductor device according to an eighth aspect of the present invention is the semiconductor device according to the sixth aspect, wherein the synchronization circuit receives the first data signal and the second register control signal as inputs. A signal corresponding to the first data signal is generated and output when the second register control signal is the first logic value, and the previous output value is held otherwise. To do.

  According to a ninth aspect of the present invention, in the semiconductor device according to the sixth aspect, the first clock signal control circuit is a logical product signal of the clock signal and the first clock stop signal. A first logical product circuit that generates and outputs the first clock stop signal, a first inverting circuit that generates and outputs an inverted signal of the first clock stop signal, and a logical sum of the clock signal and the output signal of the first inverting circuit A first logical sum circuit that generates and outputs a signal; a second logical product circuit that generates and outputs a logical product signal of the output signal of the first logical product circuit and the fixed output switching signal; and the fixed output switching A second inverting circuit that generates and outputs an inverted signal of the signal, and a third AND circuit that generates and outputs a logical product signal of the output signal of the first OR circuit and the output signal of the second inverting circuit. And an output signal of the second AND circuit A second logical sum circuit that generates and outputs a logical sum signal with the output signal of the third logical product circuit, and outputs an output result of the second logical sum circuit as the first register control signal. It is characterized by this.

  According to the configuration of the above first to ninth aspects, even when the content of the register control signal is fixed to a constant value by the clock stop signal, the value of the register control signal can be switched by the fixed output switching signal. Therefore, it is possible to prevent the register control signal from being held at a constant potential for a long time by controlling the fixed output switching signal. Therefore, the drive capability deterioration of the transistor driven by the register control signal in the synchronous circuit is reduced, and the operation margin is prevented from being reduced due to the delay variation, so that it is not necessary to secure an extra operation margin at the time of design and the operation speed is improved. be able to.

  According to the first aspect of the present invention, the value of the register control signal can be switched by the fixed output switching signal even when the content of the register control signal is fixed to a constant value by the clock stop signal. By controlling the fixed output switching signal, it is possible to prevent the register control signal from being held at a constant potential for a long time. Therefore, the drive capability deterioration of the transistor driven by the register control signal in the synchronous circuit is reduced, and the reduction of the operation margin due to the delay variation is prevented, so that it is not necessary to secure an extra operation margin at the time of design and the operation speed is improved. Can do.

  In addition, even when designing semiconductor devices with the same operating speed, it is possible to design with a smaller operating margin, so the circuit area can be reduced by reducing the gate size of the transistor, and the timing design man-hours associated with measures such as clock skew Is reduced. As a result, it is also effective in reducing the development and manufacturing costs of semiconductor devices.

  According to the invention of claim 2 of the present application, the present invention can be applied to a synchronous circuit using a flip-flop circuit, and the same effect as that of the invention of claim 1 can be obtained.

  Further, according to the invention of claim 3 of the present application, it can be applied to a synchronous circuit using a latch circuit, and the same effect as that of the invention of claim 1 can be obtained.

  According to the invention of claim 4 of the present application, it can be applied to a synchronous circuit using a load hold type flip-flop circuit, and the same effect as that of the invention of claim 1 can be obtained.

  According to the invention of claim 5 of the present application, as a clock control circuit, a first AND circuit that generates and outputs a logical product signal of the clock signal and the clock stop signal, and an inverted signal of the clock stop signal A first inverting circuit that generates and outputs a first OR circuit that generates and outputs a logical sum signal of the clock signal and the output signal of the first inverting circuit, and an output of the first AND circuit A second AND circuit for generating and outputting a logical product signal of the signal and the fixed output switching signal, a second inversion circuit for generating and outputting an inverted signal of the fixed output switching signal, and the first OR circuit A third AND circuit that generates and outputs a logical product signal of the output signal of the second inversion circuit and the output signal of the second AND circuit and the output of the third logical product circuit Second to generate and output a logical sum signal with the signal And a logical OR circuit, the output of the OR circuit of the second can be applied to those having a structure of outputting as the register control signal, the same effect as the invention of claims 1 to 4 is obtained.

  According to the invention of claim 6 of the present application, the same effect as that of the invention of claim 1 can be obtained even in a configuration using two types of signals as the clock stop signal.

  Further, according to the invention of claim 7, the present invention can be applied to a synchronous circuit using a flip-flop circuit, and the same effect as that of the invention of claim 6 can be obtained.

  According to the invention of claim 8, it can be applied to a synchronous circuit using a latch circuit, and the same effect as that of the invention of claim 6 can be obtained.

  According to the ninth aspect of the present invention, the first clock control circuit having the same configuration as that of the fifth aspect can be used, and the same effect as the sixth to eighth aspects of the present invention can be used. Is obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
The first embodiment corresponds to the first, second, and fifth aspects of the invention.
FIG. 1 shows a semiconductor device having a clock signal control circuit according to Embodiment 1 of the present invention, and shows an example when a flip-flop circuit is used as a synchronizing circuit.

  In FIG. 1, a clock signal control circuit 1 generates a register control signal GCK for controlling the operation of a register. The selection circuits 10 to 13 select either the input data D0 to D3 of this semiconductor device or the output data Y0 to Y3 of this semiconductor device. The flip-flop circuits (synchronization circuits) 20 to 23 receive the output signals of the selection circuits 10 to 13 and the register control signal GCK, and constitute a register. The clock generation circuit 100 generates a clock signal CLK. The controller 101 generates a clock stop signal EN. The clock stop signal EN is a signal for stopping the clock signal control circuit 1 from outputting the clock signal CLK as the register control signal GCK. The output switching signal generation circuit 102 outputs a fixed output switching signal INV. The fixed output switching signal INV is a fixed value output from the clock signal control circuit 1 as the register control signal GCK to either the H level (first logic value) or the L level (second logic value). This is a signal for switching, and has a sufficiently long period with respect to the clock signal CLK.

  Further, in the following description, the symbols representing the above-described data / signals are also used as symbols for terminals that input / output them. That is, the above-described CLK is also used as a code indicating a clock signal terminal. INV is a fixed output switching signal terminal, EN is a clock stop signal terminal, GCK is a register control signal, D0 to D3 are data input terminals, and Y0 to Y3 are data output terminals. To do.

  FIG. 2A shows an example of the configuration of the clock signal control circuit 1. Three input signals A, B, and C are inputted and one output signal Y is outputted. In the configuration example of FIG. 2A, a logical product signal a of input signals A and B is obtained by a two-input AND circuit AND1, and a logical product signal a and an input signal C are obtained by a two-input AND circuit AND2. The logical product signal b is obtained, the logical sum signal c of the inverted signal / B of the input signal B by the inverting circuit X101 and the input signal A is obtained by the two-input logical sum circuit OR1, and the input signal C by the inverting circuit X102. A logical product signal d of the inverted signal / C and the logical sum signal c is obtained by a two-input logical product circuit AND3, and a logical sum of the logical product signal b and the logical product signal d is obtained by a two-input logical sum circuit OR2. A signal (= A · B · C + A · / C + / B · / C) is obtained as an output signal Y.

  FIG. 3 shows a configuration example of the selection circuits 10 to 13 and outputs a value corresponding to either the input signal A or B as the output signal Y according to the value of the input signal S. In the configuration example of FIG. 3, the logical product signal e of the input signals A and S is obtained by the 2-input logical product circuit AND4, and the logical product of the inverted signal / S of the input signal S and the input signal B by the inverting circuit X103. The signal f is obtained by the AND circuit AND5 having two inputs, and the OR signal (= A · S + B · / S) of the AND signal e and the AND signal f is output by the two-input OR circuit OR3. As obtained.

  FIG. 4 shows a configuration example of the flip-flop circuits 20 to 23, which includes PMOS transistors P1 to P7, NMOS transistors N1 to N7, and inverting circuits X1 to X5, which inputs signals CK and D and outputs a signal Q. is there.

In the configuration example of FIG. 1, for simplicity of explanation, there is shown a case where there is one register control signal and the number of flip-flops controlled by the register control signal is four. There are a plurality of flip-flop groups having a plurality of terminals and controlled by a common register control signal. The number of flip-flops controlled by a common register control signal is not limited, and any number of flip-flops may be used as long as it is an integer of 1 or more.
In such a case, the clock signal control circuit may be configured as shown in FIGS. 2B and 2C.

  In FIG. 2B, two groups are controlled by dedicated clock stop signals EN1 and EN2 for each group, but the fixed output switching signal INV is used in common between the groups. FIG. 2C shows a configuration example in the case where the clock stop signals EN1 and EN2 and the fixed output switching signals INV1 and INV2 use dedicated signals for each group.

  In the first embodiment, the configuration of the clock signal control circuit 1 is different from the conventional example. However, the flip-flop circuits 20-23 (shown in FIG. 4) have the same configuration as the conventional example shown in FIG. When the clock control signal EN is at the H level, the flip-flop circuit updates the output data Q in synchronization with the clock signal CLK. When the clock control signal EN is at the L level, the flip-flop circuit holds the previous output data. This is the same as the conventional example.

  The clock signal control circuit 1 receives the clock signal CLK, the clock stop signal EN, and the fixed output switching signal INV, and outputs a register control signal GCK synchronized with the clock signal CLK.

  In the clock signal control circuit 1, when the clock stop signal EN is at the H level (first logic value), the content of the register control signal GCK is a signal synchronized with the clock signal CLK. This is the same as in the case of the conventional example shown in FIG. 11, and the contents of the register control signal GCK are the same regardless of whether the fixed output switching signal INV is at H level or L level.

  On the other hand, when the clock stop signal EN is at L level (second logic value), if the fixed output switching signal INV is at H level, the register control signal GCK indicates L level regardless of the state of the clock signal CLK, and the fixed output If the switching signal INV is at L level, the register control signal GCK indicates H level regardless of the state of the clock signal CLK.

That is, EN = H ⇒ GCK = CLK
EN = L and INV = H ⇒ GCK = L
EN = L and INV = L ⇒ GCK = H

  Therefore, it is possible to invert the contents of the register control signal GCK in the clock stop state (the state where the clock stop signal EN is at the L level) by the fixed output switching signal INV.

  For this reason, the value of the register control signal GCK can be periodically switched by outputting a signal periodically switching between high and low as the fixed output switching signal INV by the output switching signal generation circuit 102. Further, by setting the output switching signal generation circuit 102 so that the cycle of the fixed output switching signal INV is sufficiently larger than the clock signal CLK, the value of the register control signal GCK is fixed for a long time. It becomes possible to prevent NBTI and deterioration of transistor performance due to this.

  Since the output switching signal generation circuit 102 can be realized by, for example, a frequency dividing circuit for the clock signal CLK, NBTI and the like can be prevented with only a slight increase in circuit scale.

  In the first embodiment, the selection circuits 10 to 13 are added. This is because the outputs of the flip-flop circuits 20 to 23 are switched when the potential of the register control signal GCK is switched by the fixed output switching signal INV. This is for the purpose of preventing the data from being updated.

  These selection circuits 10 to 13 receive the data input signals D0 to D3, the data output signals Y0 to Y3 (output nodes) of the flip-flop circuits 20 to 23, and the clock stop signal EN as input terminals A (first data signals) and When the clock stop signal EN is at the H level, the contents of the data input signals D0 to D3 are output. When the clock stop signal EN is at the L level, the data output signal is input to the input terminal B (second data signal). The contents of Y0 to Y3 are output.

That is, EN = H => Y = D0 (D1, D2, D3)
EN = L ⇒ Y = Y0 (Y1, Y2, Y3)

  The output terminals Y of the selection circuits 10 to 13 are connected to the input terminals D of the flip-flop circuits 20 to 23. When the clock stop signal EN is at the L level, the flip-flop circuit 20 regardless of the content of the fixed output switching signal INV. Since the data output signals Y0 to Y3 of .about.23 are selected and output to the data input terminals D0 to D3 of the flip-flop circuits 20 to 23, the contents of the data output signals Y0 to Y3 can be held in the previous state. it can.

  As described above, according to the first embodiment, the contents of the register control signal GCK can be switched by the fixed output switching signal INV even when the clock stop signal EN is at the L level. By controlling the value, the register control signal GCK can be prevented from being held at a constant potential for a long time.

  Therefore, by using this clock signal control circuit 1, the flip-flop transistors P1, P3, P5, P6, N2, N4, N5, N7 in the flip-flop circuit shown in FIG. In addition, the deterioration of the driving capability of the transistors constituting the inverting circuits X1 and X2 is reduced, and the reduction of the operating margin due to delay variation is prevented, so that it is not necessary to secure an extra operating margin at the time of design, and the operating speed can be improved. it can.

  In addition, by including the selection circuits 10 to 13, it is possible to prevent the outputs of the flip-flop circuits 20 to 23 from being updated when the potential of the register control signal GCK is switched by the fixed output switching signal INV.

Although FIG. 1 shows a configuration in which a flip-flop circuit is used as the synchronization circuit, the present invention is effective even when a circuit controlled by a clock signal other than the flip-flop circuit is applied.
This case is shown in the second and third embodiments.

(Embodiment 2)
The second embodiment corresponds to the first and fourth aspects of the invention.
FIG. 5 shows a semiconductor device according to the second embodiment of the present invention, and shows an example in which a load hold type flip-flop circuit is used as a synchronizing circuit.

  In FIG. 5, load hold type flip-flop circuits 30 to 33 constitute a register, which is provided in place of the flip-flop circuits 20 to 23 and the selection circuits 10 to 13 of FIG.

  FIG. 6 shows an example of the configuration of load hold type flip-flop circuits (synchronous circuits) 30 to 33, which includes PMOS transistors P11 to P19, NMOS transistors N11 to N19, and inverting circuits X14 to X20, and a signal CK (register control signal GCK). ), LH (clock stop signal EN) and D (input signals D0 to D3 of the semiconductor device) are input and a signal Q (output signals Y0 to Y3 of the semiconductor device) is output.

  The inverting circuit X14 outputs the inverted value of the input signal CK to the node n11, and the inverting circuit X15 outputs the inverted value of the node n11 to n12. For this reason, the value of the node n12 is equal to the value of the input signal CK. The inverting circuit X16 outputs the inverted value of the input signal LH to the node n13. The inverter circuit X17 outputs the inverted value of n15 to the node n16, the inverter circuit X18 outputs the inverted value of n17 to the node n18, the inverter circuit X19 outputs the inverted value of n18 to the node n19, and the inverter circuit X20 The inverted value of n18 is output as the output signal Q.

  The MOS transistors N17 and P17 sharing the source and drain form a transfer gate TG11 and transmits a signal from the node n14 to n15 only when the input signal CK is at L level. The MOS transistors N18 and P18 sharing the source and drain form a transfer gate TG12, and transmits a signal from the node n16 to n17 only when the input signal CK is at the H level. The MOS transistors N19 and P19 sharing the source and drain form a transfer gate TG13 and transmits a signal from the node n19 to n17 only when the input signal CK is at L level.

  MOS transistors N15, N16, P15, and P16 form a tri-state inverter T21, which outputs an inverted value of n16 to node n15 only when input signal CK is at H level, and drives node n15 when input signal CK is at L level. do not do.

  The inverting circuit X6 and the MOS transistors N11 to N14 and P11 to P14 form a selection circuit SC. When the LH signal is at L level, the inverted value of the input signal D is output to the node n14, and the input signal LH is at H level. In this case, the inverted value of n19 is output to node n14. That is, in the selection circuit SC, the MOS transistors N11, N12, P11, and P12 form a tri-state inverter T22, and output an inverted value of the input signal D to the node n14 only when the input signal LH is at the L level. When n is at the H level, the node n14 is not driven. In this selection circuit SC, the MOS transistors N13, N14, P13, and P14 form a tristate inverter T23, and when the input signal LH is at the H level, the inverted value of n19 is output to the node n14, and the input signal CK When it is at the H level, the node n14 is not driven.

  When the input signal CK is at L level, the contents of the node n19 are transmitted to the node n17 by the transfer gate TG13 (MOS transistors N19 and P19), so that the inverting circuits X18 and X19 form an inverter loop, and the nodes n17 to n19 and the output Signal Q retains its previous state. At this time, since the transfer gate TG12 (MOS transistors N18 and P18) does not transmit the contents of the node n16 to the node n17, the nodes n17 to n19 and the output signal Q are not affected by the input signals LH and D. The node n19 holds the same content as the output signal Q. On the other hand, since transfer gate TG11 (MOS transistors N17 and P17) transmits the content of n14 to node n15, when input signal LH is at L level, the content of node n16 is equal to input signal D and input signal LH is at H level. Is equal to the output signal Q.

  When the input signal CK is at the H level, the tristate inverter T21 (MOS transistors N15, N16, P15, P16) operates as an inverting circuit, and thus forms an inverter loop together with the inverting circuit X17. At this time, the transfer gate TG11 (MOS transistors N17 and P17) does not drive the node n15, and the transfer gate TG13 (MOS transistors N19 and P19) does not drive the node n17, so that the node n15 maintains the previous state. Since the transfer gate TG12 (N18 and P18) drives the node n15, the nodes n16, n17, n19 and the output signal Q are inverted values of the node n15, that is, the input signal D when the input signal LH is at the L level. And the content of node n18 is equal to node n15.

  As a result, the circuit of FIG. 6 outputs the content of the input signal D as the output signal Q if the input signal LH is at the L level when the input signal CK transitions from the L level to the H level, and otherwise. It operates as a load-hold type flip-flop circuit that holds the contents of the output signal Q in the previous state.

  Thus, according to the second embodiment, the contents of the register control signal GCK can be switched by the fixed output switching signal INV even when the clock stop signal EN is at the L level. By controlling the value, the register control signal GCK can be prevented from being held at a constant potential for a long time.

  Therefore, by using this clock signal control circuit 1, in the case where the load hold type flip-flop circuit shown in FIG. 6 is used as the synchronization circuit, the transistors P15, P17, P18, P19, N16 of the load hold type flip-flop circuit are used. , N17, N18, N19 and inversion circuits X14, X15, the deterioration of the driving capability of the transistors is reduced and the reduction of the operating margin due to delay variation is prevented, so that it is not necessary to secure an extra operating margin at the time of design. Speed can be improved.

  In addition, since this load hold type flip-flop circuit has a built-in selection circuit, the output of the flip-flop circuits 30 to 33 is prevented from being updated when the potential of the register control signal GCK is switched by the fixed output switching signal INV. This is possible without providing a separate selection circuit.

(Embodiment 3)
The third embodiment corresponds to the first and third aspects of the invention.
FIG. 7 shows a semiconductor device according to the third embodiment of the present invention, and shows an example when a latch circuit is used as a synchronizing circuit.

  FIG. 8 shows an example of the configuration of the latch circuits 40 to 43, which includes PMOS transistors P20 to P22, NMOS transistors N20 to N22, and inverting circuits X21 to X25, and includes input signals G (register control signals GCK) and D (present Input signals D0 to D3) of the semiconductor device are input and output signals Q (output signals Y0 to Y3 of the present semiconductor device) are output. The inverting circuit X21 outputs the inverted value of the input signal G to the node n21, and the inverting circuit X22 outputs the inverted value of the node n21 to the node n22. For this reason, the value of the node n22 is equal to the value of the input signal G. The inverting circuit X23 outputs the inverted value of n25 to the node n24. The inverting circuit X24 outputs the inverted value of n23 to the node n25, and the inverting circuit X25 outputs the inverted value of the node n23 as the output signal Q.

  The MOS transistors N22 and P22 sharing the source and drain form a transfer gate TG21, and transmits a signal from the node n24 to n23 only when the input signal G is at L level.

  MOS transistors N20, N21, P20 and P21 form a tri-state inverter T31, which outputs an inverted value of input signal D to node n23 only when input signal G is at H level, and node n23 when input signal G is at L level. Do not drive.

  When the input signal G is at the H level, the MOS transistors N20, N21, P20, P21 operate as an inverting circuit, and the transfer gate TG21 (N22 and P22) does not drive the node n23, so that the input is made via the inverting circuit X25. The content of the signal D is output as the output signal Q.

  When the input signal G is at L level, the contents of the node n24 are transmitted to n23 by the transfer gate TG21 (N22 and P22), so that the inverting circuits X23 to X24 form an inverter loop. At this time, since the tristate inverter T31 (MOS transistors N20, N21, P20, P21) does not drive the node n23, the nodes n23 to n25 and the output signal Q retain the previous contents and are not affected by the input signal D.

  As a result, FIG. 8 shows that the content of the input signal D when the input signal G is at the H level is output to the output signal Q, and the content of the output signal Q is maintained as before when the input signal G is at the L level. It operates as a latch circuit.

  As described above, according to the third embodiment, the contents of the register control signal GCK can be switched by the fixed output switching signal INV even when the clock stop signal EN is at the L level. By controlling the value, the register control signal GCK can be prevented from being held at a constant potential for a long time.

  Therefore, by using this clock signal control circuit 1, in the case where the latch circuit shown in FIG. 8 is used as a synchronous circuit, the transistors constituting the transistors P20, P22, N21, N22 and the inverting circuits X21, X22 of the latch circuit are used. As a result, it is not necessary to secure an extra operating margin at the time of design, and the operating speed can be improved.

  In addition, by including the selection circuits 10 to 13, it is possible to prevent the outputs of the latch circuits 40 to 43 from being updated when the potential of the register control signal GCK is switched by the fixed output switching signal INV.

(Embodiment 4)
The fourth embodiment corresponds to the sixth and seventh aspects of the invention.
FIG. 9 shows a semiconductor device according to the fourth embodiment of the present invention, and shows an example in which the first and second clock signal control circuits are used and the flip-flop circuit is used as the synchronization circuit.

  In FIG. 9, 1 is the same clock control circuit (first clock signal control circuit) as in the first to third embodiments, 50 to 53 are second clock signal control circuits, 20 to 23 are flip-flop circuits, and CLK is Clock signal terminal, INV is a fixed output switching signal terminal, EN is a first clock stop signal terminal, E0 to E3 are second clock stop signal terminals, GCK is a first register control signal, and G0 to G3 are second signals. Register control signals, D0 to D3 are data input terminals, Y0 to Y3 are data output terminals, and data / signals input / output from these terminals will be described using the same reference numerals.

FIG. 10 shows an example of the configuration of the second clock signal control circuits 50 to 53. Three input signals A, B, and C are input and one output signal Y is output.
In the example of FIG. 10, the clock signal control circuits 50 to 53 are realized by a three-input AND circuit AND6. The first register control signal terminal GCK, the clock stop signal terminal EN, the second register control signal E0 to The logical product of E3 is output as the register control signal GCK.

  In the configuration example of FIG. 9, for the sake of simplicity of explanation, there is one first register control signal GCK and one flip-flop controlled by the second register control signals G0 to G3. However, there are usually a plurality of first clock stop signal terminals, and the number of second clock signal control circuits controlled by the common first register control signal GCK is not limited, and one or more. Any number of integers can be used. Further, the number of flip-flops controlled by the second register control signal is not limited, and any number of flip-flops may be used as long as it is an integer of 1 or more.

The present invention is effective even when buffer cells are inserted into the first register control signal GCK or the second register control signals G0 to G3 alone or in a tree shape for load distribution.
Flip-flop circuits 20 to 23 in the fourth embodiment have the same configuration as that of the conventional example shown in FIG.

The first clock signal control circuit 1 operates in the same manner as the clock control circuit in the first embodiment.
That is, the first clock signal control circuit 1 receives the clock signal CLK, the first clock stop signal EN, and the fixed output switching signal INV, and outputs the first register control signal GCK synchronized with the clock signal CLK. .

  When the first clock stop signal EN is at the H level, the content of the first register control signal GCK is a signal synchronized with the clock signal CLK. This is the same as in the case of the conventional example shown in FIG. 14, and the contents of the first register control signal GCK are the same regardless of whether the fixed output switching signal INV is at H level or L level.

  On the other hand, when the first clock stop signal EN is at the L level, if the fixed output switching signal INV is at the H level, the first register control signal GCK indicates the L level regardless of the state of the clock signal CLK, and the fixed output If the switching signal INV is at L level, the first register control signal GCK indicates L level regardless of the state of the clock signal CLK, and if the fixed output switching signal is at L level, the first register control signal GCK is clock signal. Shows H level regardless of the state of CLK.

  As described above, it is possible to invert the contents of the first register control signal GCK in the clock stop state (the state where the clock stop signal EN is at the H level) by the fixed output switching signal INV.

  On the other hand, the second clock signal control circuits 50 to 53 can prevent the outputs of the flip-flop circuits 20 to 23 from being updated when the potential of the first register control signal GCK is switched by the fixed output switching signal INV. .

  That is, when the second register control signals E0 to E3 are at the L level, the outputs of the flip-flop circuits 20 to 23 are not updated regardless of the state of the first register control signal GCK. As a result, even when the first clock stop signal EN is at the L level, the contents of the register control signal GCK can be switched by the fixed output switching signal INV. Therefore, the register control is performed by controlling the value of the fixed output switching signal INV. It is possible to prevent the signal GCK from being held at a constant potential for a long time.

  When the first clock stop signal EN is at the L level, the update of the output data of the flip-flops 20 to 23 is suppressed, but when the first clock stop signal EN is at the H level, the flip-flops 20 to 23 are These are individually controlled by two register control signals E0 to E3.

  Thus, according to the fourth embodiment, even when the clock stop signal EN is at the L level, the contents of the register control signal GCK can be switched by the fixed output switching signal INV, and the value of the fixed output switching signal INV can be changed. By controlling, it is possible to prevent the register control signal GCK from being held at a constant potential for a long time.

  Accordingly, the drive capability deterioration of the transistors constituting the second control circuits 50 to 53 is reduced, and the reduction of the operation margin due to the delay variation is prevented, so that it is not necessary to secure an extra operation margin at the time of design, and the operation speed is reduced. Can be improved.

  In this case, since the second register control signals G0 to G3 output from the second clock signal control circuits 50 to 53 are L, the drive capability of the transistors constituting the flip-flop circuits 20 to 23 is deteriorated. I'm worried. However, the influence of the deterioration of the driving capability is proportional to the delay time. In an actual LSI, the delay time (T1) between CLK and GCK is longer than the delay time (T2) between GCK and G0 (or G3). Therefore, by mounting so that T1 >> T2, it is possible to reduce the deterioration of the driving capability of the transistors constituting the flip-flop circuits 20 to 23, and to reduce the operation margin due to delay variation. Since the decrease is prevented, it becomes unnecessary to secure an extra operation margin at the time of design, and the operation speed can be improved.

(Embodiment 5)
The fifth embodiment corresponds to the sixth and eighth aspects of the invention.
FIG. 11 shows a semiconductor device according to the fifth embodiment of the present invention, and shows an example in which the first and second clock signal control circuits are provided and the latch circuit is used as the synchronization circuit.

  In the fifth embodiment, latch circuits 40 to 43 are provided in place of the flip-flop circuits 20 to 23 in the semiconductor device according to the fourth embodiment of FIG. 9, and the outputs from the second clock signal control circuits 20 to 23 are provided. The second register control signals G0 to G3 are input to the G terminals of the flip-flops 40 to 43, and are the same as in the configuration of the fourth embodiment.

  Thus, according to the fifth embodiment, even when the clock stop signal EN is at the L level, the contents of the register control signal GCK can be switched by the fixed output switching signal INV, and the value of the fixed output switching signal INV can be changed. By controlling, it is possible to prevent the register control signal GCK from being held at a constant potential for a long time.

  Accordingly, the drive capability deterioration of the transistors constituting the second control circuits 50 to 53 is reduced, and the reduction of the operation margin due to the delay variation is prevented, so that it is not necessary to secure an extra operation margin at the time of design, and the operation speed is reduced. Can be improved.

  Further, in this case, since the second register control signals G0 to G3 output from the second clock signal control circuits 50 to 53 become L, there is a concern that the driving capability of the transistors constituting the latch circuits 40 to 43 is deteriorated. It is. However, the influence of the deterioration of the driving capability is proportional to the delay time. In an actual LSI, the delay time (T1) between CLK and GCK is longer than the delay time (T2) between GCK and G0 (or G3). Therefore, by mounting so as to satisfy T1 >> T2, deterioration of the driving ability of the transistors constituting the latch circuits 40 to 43 can be reduced, and the operation margin is reduced due to delay variation. Therefore, it is not necessary to secure an extra operation margin at the time of design, and the operation speed can be improved.

  Although the flip-flop circuit or the latch circuit in the first to fifth embodiments has been described as a register, these may be part of a memory. Therefore, the present invention can be applied to a microprocessor, a microcomputer, a DSP (Digital Signal Processor), various memories, various logic circuits, a system LSI, and the like.

  Further, the output switching signal generation circuit generates a signal that periodically switches between high and low by, for example, forming a clock signal CLK by a frequency divider that divides the clock signal CLK by a sufficiently large frequency dividing ratio. However, this may be configured by a circuit other than the frequency divider.

Further, since the deterioration of the transistor occurs in a very long time (up to several years), there is no problem even if the cycle of the fixed output switching signal INV which is the output signal is about 1 billion times the clock signal CLK.
Moreover, the period may not necessarily be constant as long as high and low are sequentially switched over time.

  Furthermore, the configuration of the clock signal control circuit shown in FIG. 4 of the first embodiment may be applied to the clock signal control circuit of the second or second embodiment, and further, the first of the fourth and fifth embodiments. You may apply to a clock signal control circuit.

  As described above, the semiconductor device according to the present invention reduces the drive capability deterioration of the transistor driven by the register control signal in the synchronous circuit, and prevents the operation margin from being reduced due to the delay variation. It has the effect that it is not necessary to secure an operation margin and the operation speed can be improved, and is useful as a circuit for controlling the operation of a register built in a semiconductor device such as an LSI composed of MOS transistors.

The circuit diagram which shows the structure of the semiconductor device which has a clock signal control circuit by Embodiment 1 of this invention 1 is a circuit diagram showing a configuration example of a clock signal control circuit in Embodiment 1 of the present invention. The circuit diagram which shows the other structural example of the clock signal control circuit in Embodiment 1 of this invention The circuit diagram which shows the further another structural example of the clock signal control circuit in Embodiment 1 of this invention. 1 is a circuit diagram showing a configuration example of a selection circuit in FIG. 1 is a circuit diagram showing a configuration example of a flip-flop circuit in FIG. A circuit diagram showing a configuration of a semiconductor device having a clock signal control circuit according to a second embodiment of the present invention FIG. 5 is a circuit diagram showing a configuration example of the load hold type flip-flop circuit in FIG. Circuit diagram showing a configuration of a semiconductor device having a clock signal control circuit according to a third embodiment of the present invention 7 is a circuit diagram showing a configuration example of the latch circuit in FIG. A circuit diagram showing composition of a semiconductor device which has a clock signal control circuit by Embodiment 4 of the present invention. FIG. 9 is a circuit diagram showing a configuration example of the second clock signal control circuit in FIG. A circuit diagram showing composition of a semiconductor device which has a clock signal control circuit by a 5th embodiment of the present invention. Circuit diagram showing an example of use of a clock signal control circuit in a conventional example Configuration diagram of conventional clock signal control circuit Circuit diagram showing a configuration example of a conventional flip-flop circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Clock signal control circuit 2 Clock signal control circuit 10-13 Selection circuit 20-23 Flip-flop circuit 30-33 Load hold type flip-flop circuit 40-43 Latch circuit 50-53 Clock signal control circuit 100 Clock generation circuit 101 Controller 102 Output Switching signal generation circuit X1 to X5, X14 to X25, X101 to X103, X101-1, X101-2, X102-1, X102-2, X111, X112, X121, X122 Inversion circuit OR1 to OR3, OR1-1, OR1 -2, OR2-1, OR2-2, OR11, OR12, OR21, OR22 OR circuits AND1-AND6, AND60, AND1-1, AND1-2, AND2-1, AND2-2, AND11, AND12, AND21, AND22 AND circuit INV, INV1, INV2 fixed output switching signal terminal CLK clock signal terminal EN, EN1, EN2 clock stop signal terminal GCK, GCK1, GCK2 register control signal D0-D3 data input terminal Y0-Y3 data output terminal A, B, C, S, CK, D Input terminals Y, Q Output terminals P1-P7, P11-P22 PMOS transistors N1-N7, N11-N22 NMOS transistors n1-n6, n11-n19, n21-n25

Claims (9)

A clock signal that periodically repeats the first logic value and the second logic value, a clock stop signal for stopping the output of the clock signal, and a value of the output signal when output as a fixed value are switched. And a signal corresponding to the clock signal is generated and output as a register control signal when the clock stop signal is the first logic value, and the clock stop signal is the second logic signal. A clock signal control circuit that generates and outputs a signal corresponding to the fixed output switching signal as the register control signal when it is a value;
The first data signal, the second data signal, and the clock stop signal are input, and when the clock stop signal is the first logic value, a signal corresponding to the first data signal is generated and output. A selection circuit that generates and outputs a signal corresponding to the second data signal when the clock stop signal is the second logic value;
A synchronization circuit that receives the output signal of the selection circuit and the register control signal as input, and updates the output in synchronization with the register control signal;
An output switching signal generating circuit for generating a logic signal that repeats the first and second logic values at a sufficiently longer period than the clock signal as the fixed output switching signal;
An output node of the synchronization circuit is connected to an input node of the second data signal;
A semiconductor device. The semiconductor device according to claim 1,
The synchronization circuit receives an output signal of the selection circuit and the register control signal, and outputs the output of the selection circuit when the register control signal transits from the second logic value to the first logic value. A signal corresponding to the signal is generated and output, otherwise the previous output value is retained.
A semiconductor device. The semiconductor device according to claim 1,
The synchronization circuit receives the output signal of the selection circuit and the register control signal, and generates and outputs a signal corresponding to the output signal of the selection circuit when the register control signal is a first logical value, In other cases, the previous output value is retained.
A semiconductor device. A clock signal that periodically repeats the first logic value and the second logic value, a clock stop signal for stopping the output of the clock signal, and a value of the output signal when output as a fixed value are switched. And a signal corresponding to the clock signal is generated and output as a register control signal when the clock stop signal is the first logic value, and the clock stop signal is the second logic signal. A clock signal control circuit that generates and outputs a signal corresponding to the fixed output switching signal as the register control signal when it is a value;
The first data signal, the register control signal, and the clock stop signal are input, the clock stop signal is the second logical value, and the register control signal is derived from the second logical value. A synchronization circuit that generates and outputs a signal corresponding to the first data signal when transitioning to a first logic value, and holds a previous output value otherwise;
An output switching signal generating circuit for generating a logic signal that repeats the first and second logic values at a sufficiently longer period than the clock signal as the fixed output switching signal;
A semiconductor device. The semiconductor device according to claim 1 or 4,
The clock signal control circuit includes:
A first AND circuit that generates and outputs an AND signal of the clock signal and the clock stop signal;
A first inverting circuit that generates and outputs an inverted signal of the clock stop signal;
A first logical sum circuit that generates and outputs a logical sum signal of the clock signal and the output signal of the first inversion circuit;
A second AND circuit for generating and outputting a logical product signal of the output signal of the first AND circuit and the fixed output switching signal;
A second inverting circuit for generating and outputting an inverted signal of the fixed output switching signal;
A third AND circuit that generates and outputs a logical product signal of the output signal of the first logical sum circuit and the output signal of the second inversion circuit;
A second logical sum circuit that generates and outputs a logical sum signal of the output signal of the second logical product circuit and the output signal of the third logical product circuit;
Outputting an output result of the second OR circuit as the register control signal;
A semiconductor device. A clock signal that periodically repeats the first logic value and the second logic value, a first clock stop signal for stopping the output of the clock signal, and an output signal when output as a fixed value A fixed output switching signal for switching a value, and when the first clock stop signal is the first logic value, a signal corresponding to the clock signal is generated and output as a first register control signal; A first clock signal control circuit that generates and outputs a signal corresponding to the fixed output switching signal as the first register control signal when the first clock signal has a second logic value;
The first register control signal, the first clock stop signal, and a second clock stop signal for stopping the output of the clock signal are input, and the first clock stop signal and the second clock stop signal are input. When both of the clock stop signals are at the first logic value, a signal corresponding to the first register control signal is generated and output as a second register control signal, and the first clock stop signal is output as the second register control signal. A second clock signal control circuit that generates and outputs a fixed value as the second register control signal when it is a logical value;
A synchronization circuit for updating an output in synchronization with the second register control signal;
An output switching signal generating circuit that generates a logic signal that repeats the first and second logic values at a sufficiently longer period than the clock signal as the fixed output switching signal;
A semiconductor device. The semiconductor device according to claim 6.
The synchronization circuit has the first data signal and the second register control signal as inputs, and the second register control signal transitions from the second logic value to the first logic value. A semiconductor device that generates and outputs a signal corresponding to the first data signal, and holds a previous output value in other cases. The semiconductor device according to claim 6.
The synchronization circuit receives the first data signal and the second register control signal as input, and corresponds to the first data signal when the second register control signal is the first logic value. Generate and output a signal, otherwise hold the previous output value,
A semiconductor device. The semiconductor device according to claim 6.
The first clock signal control circuit includes:
A first AND circuit that generates and outputs an AND signal of the clock signal and the first clock stop signal;
A first inverting circuit that generates and outputs an inverted signal of the first clock stop signal;
A first logical sum circuit that generates and outputs a logical sum signal of the clock signal and the output signal of the first inversion circuit;
A second AND circuit for generating and outputting a logical product signal of the output signal of the first AND circuit and the fixed output switching signal;
A second inverting circuit for generating and outputting an inverted signal of the fixed output switching signal;
A third AND circuit that generates and outputs a logical product signal of the output signal of the first logical sum circuit and the output signal of the second inversion circuit;
A second logical sum circuit that generates and outputs a logical sum signal of the output signal of the second logical product circuit and the output signal of the third logical product circuit;
Outputting an output result of the second OR circuit as the first register control signal;
A semiconductor device.

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