JP2006108695A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To decrease the amount of electric charges injected into a floating gate region, by constituting the floating gate region using quantum thin lines of nanometer size and arranging it, such that it intersects with the arrangement direction of the source region and the drain region. <P>SOLUTION: At substantially the center of a region 143 of the shape of a rectangle formed on a silicon substrate 141, in a substantially the right-angle direction relative to the longitudinal direction of the region 143, a quantum thin line 145 of nanometer size is formed and set as a floating gate region. Then, a nonvolatile memory, in which the floating gate region between a channel region 150 and a gate electrode 147 is constituted using the quantum thin line 145, is formed by forming the gate electrode 147, a source region 148, and a drain region 149. At this time, the quantum thin line 145 is arranged, such that it intersects at substantially a right-angle with the source region 148 and the drain region 149. Accordingly, it is possible to reduce the stored electric charges in the floating gate region and implement a nonvolatile memory having very low power dissipation, ultra-high density, and large capacity. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device using a quantum wire made of a metal or a semiconductor that is minute enough to produce a quantum size effect formed on an insulating substrate or a semiconductor substrate via an insulating layer.

  Nowadays, large-scale integrated circuits (LSIs) that have supported the advancement of electronics, which has become the backbone of the industry, have dramatically improved performance such as large capacity, high speed, and low power consumption by miniaturization. However, when the element size is 0.1 μm or less, it is considered that the limit of the operation principle of the conventional element is reached, and research on new elements based on the new operation principle is actively conducted. As this new device, there is a device having a fine structure called a nanometer-sized quantum dot or quantum wire. The nanometer-sized quantum dots are actively studied for application to single-electron devices using the Coulomb blockade phenomenon together with various quantum effect devices. The nanometer-sized quantum wires are expected to be applied to ultrahigh-speed transistors using the quantum effect.

  In particular, in the nanometer-sized quantum wires, the degree of freedom of the electrons is limited by confining electrons in a semiconductor layer having a width similar to the wavelength of electrons in the semiconductor crystal (de Broglie wavelength). Attempts have been made to fabricate semiconductor quantum devices based on a new operating principle using the resulting quantization phenomenon. That is, since the wavelength of electrons in the semiconductor layer is about 10 nm, if the electrons are confined in a semiconductor thin wire (quantum thin wire) having a width of about 10 nm, the electrons can move in the thin wire without being scattered. Furthermore, it has been theoretically derived that the mobility of electrons increases.

  Therefore, by creating a conductive layer with a large number of quantum wires arranged on a plane as described above and controlling the number of electrons in this conductive layer by the action of the gate electrode, it is superior in speed compared to conventional transistors. Thus, a quantum wire transistor can be manufactured. Also, by incorporating a large number of quantum wires as described above into the light emitting layer of the laser, it is possible to obtain a highly efficient semiconductor laser device having a sharp spectrum even with a small injection current and excellent in high frequency characteristics.

Conventionally, methods described in the following documents (1) to (3) have been proposed as methods for forming the quantum wires.
(1) Ishiguro et al., 1996 Spring Society of Applied Physics, Lecture No. 28a-PB-5, Proceedings p-798 and Lecture No. 26p-ZA-12, Proceedings p-64 (Non-patent Document 1)
FIG. 15 shows “a method for producing uniform Si quantum wires on a SIMOX (separation by implanted oxygen) substrate using anisotropic etching” disclosed in Non-Patent Document 1 of (1) above. It is process drawing shown.

In FIG. 15, first, as shown in FIG. 15A, silicon nitride (Si ₃ N) is formed on a (100) SIMOX substrate composed of a silicon substrate 1, an oxide film 2 and an SOI (silicon-on-insulator) film 3. After depositing ₄ ), patterning is performed to form the silicon nitride film 4. Next, as shown in FIG. 15B, anisotropic etching is performed with TMAH (tetra-metal-ammonium-hydroxide) using the silicon nitride film 4 as a mask to have a (111) plane at the pattern edge. An SOI film 5 is formed.

  Next, as shown in FIG. 15C, with the silicon nitride film 4 as a mask, the (111) plane of the sidewall of the SOI film 5 is selectively oxidized to form an oxide film 6. Then, as shown in FIG. 15D, after the silicon nitride film 4 is removed, anisotropic etching is performed again with TMAH using the oxide film 6 as a mask to form Si quantum wires 7.

  The width of the Si quantum wire 7 is determined by the thickness of the SOI film 3 and is about 10 nm. In the quantum wire MOSFET (metal oxide semiconductor field effect transistor) formed using the Si quantum wire 7 formed as described above as a channel region, Coulomb blockade oscillation, which is a characteristic of the quantization phenomenon, is observed.

(2) Japanese Patent Laid-Open No. 6-77180 (Patent Document 1)
FIG. 16 is a process diagram showing “a quantum wire forming method using a thin wire-like etching mask formed by a sidewall method” disclosed in Patent Document 1 of (2) above.

In FIG. 16, first, as shown in FIG. 16 (a), a resist 12 is formed by patterning on a substrate to be etched 11 made of GaAs, and a 50 nm thick SiO 2 film is formed thereon by plasma vapor deposition (PCVD). _{2 The} coating 13 is formed. Next, as shown in FIG. 16B, reactive ion etching is performed to form SiO ₂ side walls 14 on both side walls of the patterned resist 12.

Finally, as shown in FIG. 16C, after removing the resist 12, the substrate to be etched 11 made of GaAs is patterned by reactive ion etching using the SiO ₂ sidewalls 14 as a mask, and made of GaAs. A thin line is formed.

(3) JP-A-8-288499 (Patent Document 2)
FIG. 17 is a process diagram showing “a method for forming a quantum wire using an etching mask by bonding two Si wafers and forming a sidewall” disclosed in Patent Document 2 of (3) above.

  In FIG. 17, first, as shown in FIG. 17A, a convex portion 22 is formed on the Si substrate 21 by dry etching. Subsequently, as shown in FIG. 17B, a SiOx insulating film 23 is formed to flatten the entire substrate. Next, as shown in FIG. 17C, the entire surface of the flattened substrate is reversed and bonded to another Si substrate 24 while bringing the SiOx insulating film 23 side into contact therewith. Next, as shown in FIG. 17D, the Si substrate 21 is polished by a CMP (chemical mechanical polishing) method until the SiOx insulating film 23 is exposed. As a result, the island-like Si layer 25 remains with a thickness of about 10 nm while being embedded in the SiOx-based insulating film 23. Then, after forming an impurity-containing polysilicon layer having a thickness of about 10 nm by a thermal CVD (chemical vapor deposition) method, anisotropic etching is performed through a resist mask (not shown), thereby the vicinity of the center of the island-like Si layer 25. Then, a polysilicon pattern 26 having a processed end face is formed.

  Next, as shown in FIG. 17E, a thermal oxide film (SiOx) 27 having a film thickness of 1 nm to 10 nm is formed on the Si exposed portions 25 and 26 by thermal oxidation. Next, as shown in FIG. 17 (f), etch back is performed to form a sidewall 28 leaving the thermal oxide film 27 on the processed end face of the polysilicon 26. Next, as shown in FIG. 17G, a wet process is performed on the island-like Si layer 25 under conditions that can ensure a selection ratio, and the polysilicon pattern 26 is removed. Subsequently, the island-like Si layer 25 is etched under the condition that a selection ratio with respect to the SiO x forming the sidewall 28 can be secured, thereby forming the quantum wire 29.

  However, the conventional quantum wire forming methods described in Non-Patent Document 1, Patent Document 1, and Patent Document 2 have the following problems. That is, Non-Patent Document 1 described above is a method that is effective only when the substrate is SOI and cannot be applied to a conventionally used Si substrate. The SOI substrate is 10 to 20 times more expensive than the Si substrate, and in order to further reduce the cost, it is desirable that the quantum wire can be formed using the Si substrate.

  Moreover, in the said patent document 1, the sidewall which determines the width | variety of a quantum wire is formed by CVD and reactive ion etching. However, it is necessary to control the width of the quantum wire from 1 nm to 10 nm, and there is a problem that it is very difficult to control the thickness of the film formed by PCVD and sidewall etching in the range of 1 nm to 10 nm.

Further, in Patent Document 2, two Si substrates 21 and 24 for bonding are required, and a special substrate forming technique of bonding the two Si substrates 21 and 24 via the insulating layer 23 is required. It becomes. Further, the height of the formed quantum wire 29 is determined by the depth when the Si substrate 21 is dry-etched through the resist mask, but it is extremely difficult to control the depth of the dry etching in this case with a nanometer size. There is a problem that it is difficult. Further, since the width of the quantum wire 29 is determined by the width of the sidewall 28, there is a problem that it is difficult to control.
JP-A-6-77180 JP-A-8-288499 Ishiguro et al., 1996 Spring Society of Applied Physics, Lecture No. 28a-PB-5, Proceedings p-798 and Lecture No. 26p-ZA-12, Proceedings p-64

  Accordingly, an object of the present invention is to provide a semiconductor device using a nanometer-sized quantum wire that can be formed by using a semiconductor substrate such as a Si substrate or a GaAs substrate and using a general film forming technique, a lithography technique, and an etching technique. There is.

In order to solve the above problems, the semiconductor element of the present invention is
A source region, a drain region, a channel region between the source region and the drain region, a gate region for controlling a channel current flowing in the channel region, and a floating gate positioned between the gate region and the channel region In a semiconductor device having a region, a first insulating film between the floating gate region and the gate region, and a second insulating film between the channel region and the floating gate region,
The floating gate region is composed of nanometer-sized quantum wires, and extends in a direction intersecting the arrangement direction of the source region and the drain region, and is arranged in parallel with the channel region. It is characterized by that.

  According to the above configuration, the floating gate region is configured by the nanometer-sized quantum wires arranged to intersect with the arrangement direction of the source region and the drain region. Therefore, the accumulated charge in the floating gate region is reduced, and the amount of charge injected into the floating gate region is reduced. Thus, a high-density and large-capacity nonvolatile memory with low power consumption can be obtained.

In the semiconductor device of one embodiment,
The cross-sectional shape of the floating gate region is such that the width measured in the extending direction of the first insulating film on the surface facing the channel region through the first insulating film is in the extending direction of the first insulating film. The shape is narrower than the measured maximum width.

  According to this embodiment, the nanometer-sized quantum wires constituting the floating gate region have a cross-sectional shape in which the width of the surface facing the channel region is narrower than the maximum width. Therefore, the probability that electrons trapped in the floating gate region (quantum wire) escape to the channel region side (that is, the substrate side) is reduced, and charge retention is improved.

In the semiconductor device of one embodiment,
At least the source region, drain region, channel region, and floating gate region are formed of Si.

  According to this embodiment, the source region, drain region, channel region, and floating gate region are formed of Si. Therefore, it becomes possible to mount a non-volatile memory having a quantum wire, which is the basis of a single electronic device, on the same substrate as the Si LSI.

The semiconductor element of the present invention is
A source region, a drain region, a channel region between the source region and the drain region, a gate region for controlling a channel current flowing in the channel region, and a gate insulating film between the channel region and the gate region. In a semiconductor device having
The channel region is characterized by being composed of nanometer-sized quantum wires.

  According to the above configuration, the channel region is composed of quantum wires. Therefore, the channel region is quantized in a direction perpendicular to the longitudinal direction to exhibit one-dimensional conduction. As a result, a transistor capable of ultra-high speed operation is obtained.

In the semiconductor device of one embodiment,
The source region and the drain region are formed on both sides of the channel region in the quantum wire constituting the channel region.

  According to this embodiment, the source region and the drain region are formed by implanting impurity ions into one quantum wire using the gate region as a mask to form the source region and the drain region in the quantum wire. The channel region can be formed in one step.

In the semiconductor device of one embodiment,
At least the source region, drain region, and channel region are formed of silicon.

  According to this embodiment, the source region, drain region and channel region are formed of Si. Therefore, it becomes possible to mount the transistor having the quantum wire that is the basis of the single-electron device on the same substrate as the Si LSI.

  As is apparent from the above, the semiconductor device of the present invention includes a source region, a drain region, a channel region, a gate region, a floating gate region, and a first insulation between the floating gate region and the gate region. In a semiconductor device having a film and a second insulating film between the channel region and the floating gate region, the floating gate region is formed of nanometer-sized quantum wires, and the source region and the drain region are arranged Since it is arranged so as to intersect with the direction, the amount of charge injected into the floating gate region can be reduced, and a low-power consumption, high-density and large-capacity nonvolatile memory can be obtained.

  Furthermore, if the nanometer-sized quantum wire constituting the floating gate region has a cross-sectional shape in which the width of the surface facing the channel region is narrower than the maximum width, it is trapped in the floating gate region (quantum wire). The probability that electrons escape to the substrate side is reduced, and charge retention can be improved.

  Further, the semiconductor element of the present invention is a semiconductor element having a source region, a drain region, a channel region, a gate region, and a gate insulating film, and the channel region is composed of nanometer-sized quantum wires. The region is quantized in a direction perpendicular to the longitudinal direction to show one-dimensional conduction. Therefore, according to the present invention, it is possible to obtain a transistor capable of operating at an ultra high speed.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

<First embodiment>
FIG. 1 is a cross-sectional view of a substrate at each step in the quantum wire manufacturing method of the present embodiment. In FIG. 1, first, as shown in FIG. 1A, the surface of a silicon substrate 31 is oxidized to form a first oxide film 32 having a thickness of 10 nm, and then a first oxide film having a thickness of 100 nm is formed by a CVD method or the like. A nitride film 33 is formed. In this case, the first nitride film 33 has a sufficient film thickness with respect to the alignment accuracy when forming the photoresist pattern 37 for patterning the third nitride film 36 in a later step.

  Next, as shown in FIG. 1B, the first nitride film 33 is patterned by anisotropic etching through a resist mask (not shown). Next, as shown in FIG. 1C, a second nitride film 34 having a thickness of 10 nm is formed by a CVD method or the like. Subsequently, the surface of the second nitride film 34 is oxidized to form a second oxide film 35 having a thickness of 5 nm. Next, as shown in FIG. 1D, a third nitride film 36 having a thickness of 100 nm is formed by a CVD method or the like.

  Next, as shown in FIG. 1 (e), a photoresist pattern 37 is formed so that its end face is located at a stepped portion of the third nitride film 36. In that case, as described above, the end face of the photoresist pattern 37 can be positioned at the step portion of the third nitride film 36 by using the accuracy of alignment of the end face of the photoresist pattern by the conventional LSI technology. The film thickness of the first nitride film 33 is set to be thick. Therefore, the resist pattern 37 can be formed by a conventional LSI exposure technique without using a special exposure technique using electron beam lithography or AFM (atomic force microscope).

  Next, as shown in FIG. 1F, using the resist pattern 37 as a mask, the portion of the third nitride film 36 located on the first nitride film 33 is removed by anisotropic etching. In that case, a portion of the third nitride film 36 below the photoresist pattern 37 remains without being etched, and the third nitride film 36 between the photoresist pattern 37 and the first nitride film 33 is like a sidewall. Shape. Further, since the end face of the photoresist pattern 37 is located in the vicinity of the stepped portion (see FIG. 1D) of the third nitride film 36, the deepest etched portion in the shape of the sidewall is the third. The second oxide film 35 under the nitride film 36 does not reach.

  Next, as shown in FIG. 1G, after removing the resist pattern 37, dry etching of the oxide film is performed. By this dry etching, a portion of the second oxide film 35 on the first nitride film 33 and a portion extending in a direction perpendicular to the silicon substrate 31 and sandwiched between the second nitride film 34 and the third nitride film 36 Is removed. Next, as shown in FIG. 1H, the second oxide film 35 extending in the vertical direction is removed by dry etching of the oxide film in FIG. By etching the second nitride film 34 and the first oxide film 32 therebelow, a groove 38 for exposing the Si substrate 31 is formed. That is, the width of the groove 38 is set by the film thickness (5 nm) of the second oxide film 35.

Next, as shown in FIG. 1I, the first nitride film 33, the second nitride film 34 extending in the vertical direction, and the third nitride film 36 are removed by dry etching or wet etching. Subsequently, the entire substrate is placed in a reaction chamber equivalent to a high vacuum CVD apparatus. After evacuating the reaction chamber to a vacuum of about 10 ⁻⁸ Torr, the substrate temperature is set to about 550 ° C. to 600 ° C., and silane (SiH ₄ ) gas or disilane (Si ₂ H ₆ ) gas is supplied. Then, by controlling the gas partial pressure to be 10 ⁻² Torr or less, the Si thin wire 39 is epitaxially grown on the portion where the Si substrate 31 is exposed. In that case, since it is necessary to separate the Si thin wire 39 from the Si substrate 31 later by oxidation, the Si thin wire 39 is grown wider than the width of the groove 38. Here, in the epitaxial growth, the raw material gas partial pressure is set to 10 ⁻² Torr or less. Therefore, it is prevented that the film growth starts promptly on the entire surface of the insulating thin film, and the Si thin wire 39 is selectively vapor-grown only in the groove 38 where the Si substrate 31 is exposed.

Prior to the epitaxial growth of the Si thin wire 39, a sacrificial oxide film is formed on the surface of the exposed portion of the Si substrate 31 in order to remove damage caused by etching of the portion where the Si substrate 31 is exposed, and wet etching is performed for an appropriate time. You may go. Further, the evacuation in the reaction chamber is not limited to 10 ⁻⁸ Torr and may be 10 ⁻⁶ Torr or less.

  Next, as shown in FIG. 1J, the first oxide film 32, the second nitride film 34, and the second oxide film 35 are removed by wet etching such as hydrofluoric acid and phosphoric acid. Finally, as shown in FIG. 1 (k), oxidation is performed to form a third oxide film 40 under the Si thin wire 39 and on the surface of the Si substrate 31. Thus, the Si thin wire 39 and the Si substrate 31 are separated by the third oxide film 40, and the quantum thin wire 39 is formed.

  As described above, in the present embodiment, the second nitride film 34, the first nitride film 34, the first nitride film 34, and the second nitride film 34 are formed on the Si substrate 31 through the first oxide film 32 by using a normal film forming technique, a photolithography technique, and an etching technique. A second oxide film 35 extending in a direction perpendicular to the upper surface of the Si substrate 31 is formed between the stacked body of the second oxide film 35 and the third nitride film 36 and the first nitride film 33. Then, by etching, the second oxide film 35 extending in the vertical direction, the second nitride film 34 therebelow and the first oxide film 32 therebelow are removed, and the groove 38 exposing the Si substrate 31 is removed. Form. Thereafter, the second nitride film 34 and the third nitride film 36 extending in the direction perpendicular to the first nitride film 33 are removed, and the first oxide film 32, the first oxide film 32, the second nitride film 34, and the second oxide film 36 are removed. Si thin wires 39 are epitaxially grown on the exposed portion of the Si substrate 31 between the laminated body of the films 35. Then, the first oxide film 32, the second nitride film 34, and the second oxide film 35 are removed, and the Si thin line 39 and the Si substrate 31 are separated by the third oxide film 40 formed by oxidation. To form.

  Therefore, according to the present embodiment, the quantum wire 39 has a width that extends in a direction perpendicular to the upper surface of the Si substrate 31 and exposes the Si substrate 31, that is, the second nitride film 34. It can be determined by the thickness of the second oxide film 35 obtained by oxidizing. The groove 38 can be formed using a general film forming technique, a lithography technique, and an etching technique. Therefore, the quantum wire 39 can be formed without using a special fine processing technique. That is, according to the present embodiment, it is possible to reduce the manufacturing cost and realize a quantum wire manufacturing method suitable for mass production with high yield and high productivity.

  Further, the width of the groove 38 at that time can be controlled by controlling the film thickness of the second oxide film 35 formed by oxidizing the surface of the second nitride film 34. Therefore, the width of the groove 38, that is, the width of the quantum wire 39 can be precisely controlled in nanometer units, and the quantum wire 39 having a complete electron confinement region can be obtained. Further, since the Si thin wire 39 is formed by epitaxial growth on the exposed portion of the Si substrate 31 in the groove 38, the quantum thin wire 39 having excellent crystallinity and excellent uniformity in size and density and reproducibility can be formed. Further, since the quantum wire 39 and the Si substrate 31 are separated by the third oxide film 40, the bottom surface side of the quantum wire 39 is not in contact with the Si substrate 31, and electrons can be completely confined.

<Second Embodiment>
In the first embodiment, the end face of the photoresist pattern 37 for patterning the third nitride film 36 needs to be positioned at the step portion of the third nitride film 36. That is, in FIG. 2A, the end face of the photoresist pattern 47 needs to be within the position control margin a of the end face of the photoresist pattern. Therefore, in the first embodiment, the end face of the photoresist pattern can be positioned within the position control margin a by using the alignment accuracy of the end face of the photoresist pattern in the normal LSI technology. The film thickness of the first nitride film 33 is made sufficiently thick. In the present embodiment, the position control margin of the end face of the photoresist pattern 47 is about twice that in the first embodiment.

  In the present embodiment, first, similarly to FIGS. 1A to 1E in the first embodiment, a first oxide film (10 nm) 42 and a first nitride film are formed on the Si substrate 41. A (100 nm) pattern 43, a second nitride film (10 nm) 44, a second oxide film (5 nm) 45, and a third nitride film (100 nm) 46 are formed. Further, the photoresist pattern 47 is formed so that the end surface thereof is located at the step portion of the third nitride film 46. Thus, the state shown in FIG.

  Here, when the end face of the photoresist pattern 47 is formed on the right side of the position control margin “a” shown in FIG. 2A, the photoresist pattern 47 is formed to pattern the third nitride film 46. When dry etching is performed as a mask, as shown in FIG. 2B, the deepest etched portion in the shape of the sidewall reaches the second oxide film 45, and outside the first nitride film pattern 43, A second oxide film exposed portion 53 where the second oxide film 45 is exposed is formed. Therefore, if the steps after FIG. 1G are performed according to the first embodiment, a portion where the Si substrate 41 is exposed is also formed in the second oxide film exposed portion 53.

  Therefore, in the present embodiment, as shown in FIG. 2C, after the photoresist pattern 47 is removed, a fourth nitride film 51 having a thickness of 100 nm is formed. In that case, the unevenness of the surface after the formation of the fourth nitride film 51 can be reduced by appropriately changing the thickness of the fourth nitride film 51 in accordance with the width of the second oxide film exposed portion 53. Next, as shown in FIG. 2D, the fourth nitride film 51 is etched back so that a portion of the second oxide film 45 on the first nitride film 43 is exposed. Then, by dry etching of the oxide film, as shown in FIG. 2 (e), the second oxide film 45 extends in a direction perpendicular to the portion on the first nitride film 43 and the Si substrate 41. Thus, the portion sandwiched between the second nitride film 44 and the third nitride film 46 is removed. Subsequently, the second oxide film 45 extending in the vertical direction by the dry etching of the oxide film is removed, the second nitride film 44 below the groove formed, and the first oxide film 42 therebelow. Is etched to form a groove 48 exposing the Si substrate 41. By performing the subsequent steps in the same manner as in FIG. 1 (i) to FIG. 1 (k), Si quantum wires can be formed.

  According to the second embodiment, the distance between the end face of the first nitride film 43 and the end face of the photoresist pattern 47 exceeds the position control margin a, and the second oxide film is exposed outside the first nitride film pattern 43. When the portion 53 is formed, it can be covered with the fourth nitride film 51. Therefore, as compared with the first embodiment, the position control margin a of the end face of the photoresist pattern 47 can be approximately doubled, and the workability and accuracy of the position control can be improved.

<Third Embodiment>
In the second embodiment, the groove 48 exposing the Si substrate 41 is formed by performing oxide film etching / nitride film etching / oxide film etching in FIG. However, the aspect ratio of the groove 48 exposing the Si substrate 41 is expected to be very large, and in that case, it is considered very difficult to form the narrow groove 48 by etching. Therefore, in the present embodiment, the aspect ratio when forming the groove for exposing the Si substrate is reduced to facilitate the groove formation by etching.

  FIG. 3 is a cross-sectional view of the substrate in the quantum wire manufacturing method of the present embodiment. In the present embodiment, first, similarly to FIGS. 1A to 1E in the first embodiment, a first oxide film (10 nm) 62 and a first nitride film are formed on the Si substrate 61. A (100 nm) pattern 63, a second nitride film (10 nm) 64, a second oxide film (5 nm) 65, and a third nitride film (100 nm) 66 are formed. Further, the photoresist pattern is formed so that the end surface thereof is located at the step portion of the third nitride film 66.

  Next, in the same manner as in FIGS. 2B to 2D in the second embodiment, after performing dry etching using the photoresist pattern as a mask, the photoresist pattern is removed, and the fourth nitride film is removed. After forming 70, etch back is performed to expose the second oxide film 65 on the first nitride film 63.

  Thus, when the fourth nitride film 70 is etched back until the second oxide film 65 on the first nitride film 63 is exposed, the first nitride film 63 on the first nitride film 63 is etched back as shown in FIG. The 2 nitride film 64 and the second oxide film 65 are removed by wet etching. Next, as shown in FIG. 3B, the first nitride film 63, the third nitride film 66, and the fourth nitride film 70 are etched back by 60 nm to project the second oxide film 65 extending in the vertical direction. Let After that, as shown in FIG. 3C, an oxide film etch / nitride film etch / oxide film etch is performed to form a groove 68 exposing the Si substrate 61.

  In this case, since the aspect ratio at the time of etching is small, the etching becomes easy. Then, Si quantum wires can be formed by performing the subsequent steps in the same manner as in FIGS. 1 (i) to 1 (k).

<Fourth embodiment>
FIG. 4 is a cross-sectional view of the substrate in each step in the quantum wire manufacturing method of the present embodiment. In FIG. 4, first, as shown in FIG. 4A, the surface of the silicon substrate 71 is oxidized to form a first oxide film 72 having a thickness of 10 nm, and then the first oxide film having a thickness of 100 nm is formed by CVD or the like. A nitride film 73 is formed. In this case, the first nitride film 73 has a sufficient film thickness with respect to the alignment accuracy when forming the photoresist pattern 76 for patterning the second nitride film 75 in a later step.

  Next, as shown in FIG. 4B, the first nitride film 73 is patterned by anisotropic etching through a resist mask (not shown). Next, as shown in FIG. 4C, a 10 nm thick second oxide film 74 is formed by CVD or the like. Next, as shown in FIG. 4D, the second nitride film 75 having a thickness of 100 nm is formed by a CVD method or the like.

  Next, as shown in FIG. 4E, a photoresist pattern 76 is formed so that its end face is located at a step portion of the second nitride film 75. In that case, as described above, the end face of the photoresist pattern 76 can be positioned at the stepped portion of the second nitride film 75 using the accuracy of alignment of the end face of the photoresist pattern by the conventional LSI technology. The film thickness of the first nitride film 73 is set thick. Therefore, the photoresist pattern 76 can be formed by a conventional LSI exposure technique without using a special exposure technique using electron beam lithography, AFM, or the like.

  Next, as shown in FIG. 4F, the portion of the second nitride film 75 located on the first nitride film 73 is removed by anisotropic etching using the photoresist pattern 76 as a mask. In that case, the portion under the photoresist pattern 76 in the second nitride film 75 remains as it is without being etched, and the second nitride film 75 between the photoresist pattern 76 and the first nitride film 73 is like a sidewall. Shape. Further, since the end face of the photoresist pattern 76 is located in the vicinity of the step portion (see FIG. 4D) of the second nitride film 75, the deepest etched portion in the shape like the sidewall is the first. The second oxide film 74 under the nitride film 73 does not reach.

  Next, as shown in FIG. 4G, after the photoresist pattern 76 is removed, the oxide film is dry etched. By this dry etching, the portion of the second oxide film 74 on the first nitride film 73 and the portion extending in the direction perpendicular to the silicon substrate 71 and sandwiched between the first nitride film 73 and the second nitride film 75 Then, the first oxide film 72 underneath is removed. Thus, as shown in FIG. 4H, a groove 77 exposing the Si substrate 71 is formed. That is, the width of the groove 77 is set by the film thickness (10 nm) of the second oxide film 74.

Next, as shown in FIG. 4H, the first nitride film 73 and the second nitride film 75 are removed by dry etching or wet etching. Subsequently, the entire substrate is placed in a reaction chamber equivalent to a high vacuum CVD apparatus. After evacuating the reaction chamber to a vacuum of about 10 ⁻⁸ Torr, the substrate temperature is set to about 550 ° C. to 600 ° C., and silane (SiH ₄ ) gas or disilane (Si ₂ H ₆ ) gas is supplied. By controlling the gas partial pressure to be 10 ⁻² Torr or less, the Si thin wire 78 is epitaxially grown on the exposed portion of the Si substrate 71 as shown in FIG. In that case, since it is necessary to separate the Si thin wire 78 from the Si substrate 71 later by oxidation, the Si thin wire 78 is grown wider than the width of the groove 77. Prior to the epitaxial growth of the Si thin line 78, a sacrificial oxide film is formed on the surface of the exposed portion of the Si substrate 71 and wet etching is performed for an appropriate time in order to remove damage caused by etching of the portion where the Si substrate 71 is exposed. May be.

  Next, as shown in FIG. 4J, the first oxide film 72 and the second oxide film 74 are removed by wet etching such as hydrofluoric acid. Finally, as shown in FIG. 4 (k), oxidation is performed to form a third oxide film 79 below the Si thin wire 78 and on the surface of the Si substrate 71, and the Si thin wire 78 and the Si substrate 71 are third oxidized. Separated by a membrane 79. Thus, the Si thin line 78 is formed.

  According to the present embodiment, in order to form the second oxide film 74 related to the control of the width of the quantum wire 78 by CVD, the surface of the second nitride film 34 in the first embodiment is oxidized to provide a second. The film thickness accuracy is inferior to the film thickness control in the case where the oxide film 35 is formed. However, there is an advantage that the process is simplified by reducing the number of times of forming the nitride film by one.

<Fifth embodiment>
FIG. 5 is a cross-sectional view of the substrate in the quantum wire manufacturing method of the present embodiment. In the present embodiment, as in the second embodiment, the position control margin of the end face of the photoresist pattern 76 when patterning the second nitride film 75 in the fourth embodiment is approximately doubled. It is.

  In the present embodiment, first, similarly to FIGS. 4A to 4E in the fourth embodiment, a first oxide film (10 nm) 82 and a first nitride film are formed on the Si substrate 81. A (100 nm) pattern 83, a second oxide film (10 nm) 84, and a second nitride film (100 nm) 85 are formed. Further, the photoresist pattern 86 is formed so that the end surface thereof is located at the step portion of the second nitride film 85. Thus, the state shown in FIG.

  Here, when the end face of the photoresist pattern 86 is formed on the right side of the position control margin “b” shown in FIG. 5A, the photoresist pattern 86 is formed to pattern the second nitride film 85. When dry etching is performed as a mask, as shown in FIG. 5B, the deepest etched portion in the shape of the sidewall reaches the second oxide film 84, and outside the first nitride film pattern 83, A second oxide film exposed portion 90 in which the second oxide film 84 is exposed is formed. Therefore, if the steps after FIG. 4G are performed according to the fourth embodiment as it is, a portion where the Si substrate 81 is exposed is also formed in the second oxide film exposed portion 90.

  Therefore, in the present embodiment, as shown in FIG. 5C, after removing the photoresist pattern 86, a third nitride film 91 having a thickness of 100 nm is formed. In that case, the unevenness of the surface after the formation of the third nitride film 91 can be reduced by appropriately changing the film thickness of the third nitride film 91 according to the width of the second oxide film exposed portion 90. Next, as shown in FIG. 5D, the third nitride film 91 is etched back so that the portion of the second oxide film 84 on the first nitride film 83 is exposed. Then, by performing dry etching of the oxide film, as shown in FIG. 5 (e), the first oxide film is delayed from the second oxide film 84 on the first nitride film 83 and the surface of the Si substrate 81 with a first delay. The portion sandwiched between the nitride film 83 and the second nitride film 85 and the first oxide film 82 thereunder are removed. Thus, the groove 27 for exposing the Si substrate 81 is formed.

  Si quantum wires can be formed by performing the subsequent steps in the same manner as in FIGS. 4 (h) to 4 (k). According to the fifth embodiment, the position control margin b of the end face of the photoresist pattern 86 can be approximately doubled as compared with the fourth embodiment, and the workability and accuracy of the position control are improved. It can be done.

<Sixth embodiment>
In the fifth embodiment, the groove 87 exposing the Si substrate 81 is formed by performing oxide film etching in FIG. However, the aspect ratio of the groove 87 exposing the Si substrate 81 is expected to be very large, and in that case, it is considered very difficult to form the narrow groove 87 by etching. Therefore, in the present embodiment, the aspect ratio when forming the groove for exposing the Si substrate is reduced to facilitate the groove formation by etching.

  FIG. 6 is a cross-sectional view of a substrate in the quantum wire manufacturing method of the present embodiment. In the present embodiment, first, as in FIGS. 4A to 4E in the fourth embodiment, a first oxide film 102 and a first nitride film are formed on the oxidized Si substrate 101. A pattern 103, a second oxide film 104, and a second nitride film 105 are formed. Further, the photoresist pattern is formed so that the end surface thereof is located at the step portion of the second nitride film 105.

  Next, in the same manner as in FIGS. 5B to 5D in the fifth embodiment, dry etching is performed using the photoresist pattern as a mask to form a second oxide film exposed portion. A nitride film 111 is formed and etched back to expose the second oxide film 104 on the first nitride film 103.

  Thus, when the second oxide film 104 on the first nitride film 103 is exposed, as shown in FIG. 6A, the second nitride film 104 on the first nitride film 103 is removed by wet etching. Next, as shown in FIG. 6B, the first nitride film 103, the second nitride film 105, and the third nitride film 111 are etched back by 60 nm to project the second oxide film 104 extending in the vertical direction. Let After that, as shown in FIG. 6C, an oxide film is etched to form a groove 107 that exposes the Si substrate 101.

  Then, the Si quantum wires can be formed by performing the subsequent steps in the same manner as in FIGS. 4 (h) to 4 (k). According to this embodiment, since the aspect ratio at the time of etching is small, the etching becomes easy. Therefore, the narrow groove 107 can be easily formed, and thus a thinner quantum wire can be formed.

<Seventh embodiment>
The present embodiment relates to a method for manufacturing a quantum wire in which the formation of the photoresist pattern 37 used for patterning the third nitride film 36 on the first nitride film 33 in the first embodiment is omitted.

  FIG. 7 is a cross-sectional view of the substrate at each step in the present embodiment. In FIG. 7, first, as shown in FIG. 7A, the surface of the silicon substrate 121 is oxidized to form a first oxide film 122 having a film thickness of 10 nm, and then a first film having a film thickness of 50 nm is formed by CVD or the like. A nitride film 123 is formed.

  Next, as shown in FIG. 7B, the first nitride film 123 is patterned by anisotropic etching through a resist mask (not shown). Next, as shown in FIG. 7C, a second nitride film 124 having a thickness of 10 nm is formed by a CVD method or the like. Next, the surface of the second nitride film 124 is oxidized to form a second oxide film 125 having a thickness of 5 nm. The film thickness of this second oxide film 125 is the width of a groove to be formed later. Next, as shown in FIG. 7D, a third nitride film 126 is formed by a CVD method or the like. In that case, the film thickness of the third nitride film 126 is set to such a film thickness that a step caused by the patterning of the first nitride film 123 is eliminated. For example, if the interval between adjacent patterns of the first nitride film 123 is 0.2 μm, the thickness of the third nitride film 126 is 3/4 times or more, that is, 0.15 μm or more.

  Next, as shown in FIG. 7E, the third nitride film 126 is etched back to expose the second oxide film 125 on the first nitride film 123. Next, as shown in FIG. 7F, the oxide film is etched. By this etching, a portion of the second oxide film 125 on the first nitride film 123 and a portion extending in a direction perpendicular to the silicon substrate 121 and sandwiched between the second nitride film 124 and the third nitride film 126 are formed. Removed. Next, as shown in FIG. 7G, the second oxide film 125 extending in the vertical direction by the etching of the oxide film in FIG. The trench 128 exposing the Si substrate 121 is formed by etching the second nitride film 124 and the first oxide film 122 therebelow.

Next, as shown in FIG. 1H, the first nitride film 123, the second nitride film 124 extending in the vertical direction, and the third nitride film 126 are removed by dry etching or wet etching. Subsequently, the entire substrate is placed in a reaction chamber equivalent to a high vacuum CVD apparatus. After evacuating the reaction chamber to a vacuum of about 10 ⁻⁸ Torr, the substrate temperature is set to about 550 ° C. to 600 ° C., and silane (SiH ₄ ) gas or disilane (Si ₂ H ₆ ) gas is supplied. Then, by controlling the gas partial pressure to be 10 ⁻² Torr or less, the Si thin wire 129 is epitaxially grown on the portion where the Si substrate 121 is exposed. In that case, since it is necessary to separate the Si thin wire 129 from the Si substrate 121 later by oxidation, the Si thin wire 129 is grown wider than the width of the groove 128. Prior to the epitaxial growth of the Si thin wire 129, a sacrificial oxide film is formed on the surface of the exposed portion of the Si substrate 121 and wet etching is performed for an appropriate time in order to remove damage caused by etching of the portion where the Si substrate 121 is exposed. May be.

  Next, as shown in FIG. 7I, the first oxide film 122, the second nitride film 124, and the second oxide film 125 are removed by wet etching such as hydrofluoric acid and phosphoric acid. Finally, as shown in FIG. 7 (j), oxidation is performed to form a third oxide film 130 below the Si thin wire 129 and on the surface of the Si substrate 121, and the quantum thin wire 129 and the Si substrate 121 are third oxidized. Separated by membrane 130. Thus, the Si quantum wire 129 is formed.

  According to the present embodiment, the step of forming a photoresist pattern (corresponding to the photoresist pattern 37 in the first embodiment) for patterning the third nitride film 126 as compared with the first embodiment. do not need. Therefore, as compared with the first embodiment, the process can be simplified and the cost can be reduced.

<Eighth embodiment>
FIG. 8 is a cross-sectional view of the substrate at each step in the method of manufacturing a quantum wire according to the present embodiment. In FIG. 8, first, as shown in FIG. 8A, the surface of the silicon substrate 131 is oxidized to form a first oxide film 132 having a film thickness of 10 nm, and then a first film having a film thickness of 50 nm is formed by CVD or the like. A nitride film 133 is formed.

  Next, as shown in FIG. 8B, the first nitride film 133 is patterned by anisotropic etching through a resist mask (not shown). Next, as shown in FIG. 8C, a second oxide film 134 having a thickness of 10 nm is formed by a CVD method or the like. Next, as shown in FIG. 8D, a second nitride film 135 is formed by a CVD method or the like. In that case, the thickness of the second nitride film 135 is set such that a step caused by the patterning of the first nitride film 133 is eliminated. For example, when the interval between adjacent patterns of the first nitride film 133 is 0.2 μm, the thickness of the second nitride film 135 is 3/4 times or more, that is, 0.15 μm or more.

  Next, as shown in FIG. 8E, the second nitride film 135 is etched back to expose the second oxide film 134 on the first nitride film 133. Next, as shown in FIG. 8F, the oxide film is etched. By this etching, a portion of the second oxide film 134 on the first nitride film 133 and a portion extending in a direction perpendicular to the Si substrate 131 and sandwiched between the first nitride film 133 and the second nitride film 135, Then, the first oxide film 132 thereunder is removed. Thus, a groove 137 for exposing the Si substrate 131 is formed.

Next, as shown in FIG. 8G, the first nitride film 133 and the second nitride film 135 are removed by dry etching or wet etching. Subsequently, the entire substrate is placed in a reaction chamber equivalent to a high vacuum CVD apparatus. After evacuating the reaction chamber to a vacuum of about 10 ⁻⁸ Torr, the substrate temperature is set to about 550 ° C. to 600 ° C., and silane (SiH ₄ ) gas or disilane (Si ₂ H ₆ ) gas is supplied. By controlling the gas partial pressure to be 10 ⁻² Torr or less, the Si thin wire 138 is epitaxially grown on the portion where the Si substrate 131 is exposed, as shown in FIG. Prior to the epitaxial growth of the Si thin wire 138, a sacrificial oxide film is formed on the surface of the exposed portion of the Si substrate 131 and wet etching is performed for an appropriate time in order to remove damage caused by etching of the portion where the Si substrate 131 is exposed. May be.

  Next, as shown in FIG. 8I, the first oxide film 132 and the second oxide film 134 are removed by wet etching such as hydrofluoric acid. Finally, as shown in FIG. 8 (j), oxidation is performed to form a third oxide film 139 below the Si thin wire 138 and on the surface of the Si substrate 131, and the quantum thin wire 138 and the Si substrate 131 are third oxidized. Separated by membrane 139. Thus, the Si quantum wire 138 is formed.

  According to the present embodiment, in order to form the second oxide film 134 related to the control of the width of the quantum wire 138 by CVD, the surface of the second nitride film 124 in the seventh embodiment is oxidized to form the second oxide film 134. The accuracy of the film thickness is inferior to the film thickness control when the oxide film 125 is formed. However, there is an advantage that the process is simplified by reducing the number of times of forming the nitride film by one. Further, as compared with the case of the fourth embodiment, a step of forming a photoresist pattern (corresponding to the photoresist pattern 76 in the fourth embodiment) for patterning the second nitride film 135 is not required. Therefore, as compared with the fourth embodiment, the process can be simplified and the cost can be reduced.

<Ninth Embodiment>
The present embodiment relates to a semiconductor element using a quantum wire formed by any of the first to eighth embodiments. FIG. 9A is a plan view of a nonvolatile memory (such as a flash EEPROM (electrically erasable / writable random access memory)) as the semiconductor element. Moreover, FIG.9 (b) is CC sectional view taken on the line in Fig.9 (a).

  As shown in FIGS. 9A and 9B, in the nonvolatile memory, a rectangular region 143 surrounded by an element isolation region 142 is formed on a silicon substrate 141. Then, a nanometer-sized quantum wire 145 is formed in the approximate center of the region 143 in a direction substantially perpendicular to the longitudinal direction of the region 143 by any one of the first to eighth embodiments. The third oxide film formed on the silicon substrate 141 is used as the tunnel oxide film 144, and the quantum wire 145 is used as the floating gate region. Thereafter, a control gate insulating film 146 having a thickness of 10 nm is formed on the tunnel oxide film 144 and the quantum wire 145 by the CVD method. Next, after forming a gate electrode 147 on the control gate insulating film 146, impurities are ion-implanted using the gate electrode 147 as a mask to form a source region 148 and a drain region 149. In addition, a channel region 150 is formed between the source region 148 and the drain region 149. Thus, a non-volatile memory in which the floating gate region between the channel region 150 and the gate electrode 147 is configured by the quantum wire 145 is configured.

  FIG. 9 (c) is a cross-sectional view taken along the line DD in FIG. 9 (a). In the present embodiment, the quantum wires 145 are arranged so as to intersect the source region 148 and the drain region 149 shown in FIG. Therefore, by using the quantum wire 145 as the floating gate region, the accumulated charge in the floating gate region can be reduced. Therefore, it is possible to realize an ultra-high-density and large-capacity nonvolatile memory with extremely low power consumption.

  That is, according to the present embodiment, since the quantum wire 145 can be formed of silicon using a general film formation technique, a lithography technique, and an etching technique, the yield is low, the yield is high, and the productivity is high. Therefore, a nonvolatile memory suitable for the above can be realized. The quantum wire 145 is not limited to silicon, but may be other semiconductor materials or metal materials.

<Tenth embodiment>
FIG. 10A is a plan view of a MOSFET as the semiconductor element. 10 (b) is a cross-sectional view taken along the line EE in FIG. 10 (a), and FIG. 10 (c) is a cross-sectional view taken along the line FF in FIG. 10 (a).

  As shown in FIGS. 10A to 10C, in the MOSFET according to the present embodiment, an insulating layer (described above) is formed on the silicon substrate 151 according to any one of the first to eighth embodiments. (Third oxide film) 152 and quantum wire 153 are formed. Thereafter, a gate insulating film 154 having a thickness of 30 nm is formed on the insulating layer 152 and the quantum wire 153 by a CVD method. Then, after forming the gate electrode 155 on the gate insulating film 154, impurity ions are implanted using the gate electrode 155 as a mask to form the source region 156 and the drain region 157 in the quantum wire 153. In that case, a channel region 158 is formed between the source region 156 and the drain region 157 in the quantum wire 153.

  In the above structure, the width of the quantum wire 153 can be formed to 10 nm or less by using a general film forming technique, a lithography technique, and an etching technique. Therefore, the channel region 158 can be quantized in the width direction of the quantum wire 153 to show one-dimensional conduction. That is, according to the present embodiment, it is possible to obtain an ultrahigh-speed MOSFET suitable for mass production with low cost and good yield and high productivity.

<Eleventh embodiment>
FIG. 11 shows a cross section of a light-emitting element as the semiconductor element. In the light-emitting element shown in FIG. 11, an insulating layer (the third oxide film) 162 and a plurality of pieces having a diameter of 10 nm or less are formed on a silicon substrate 161 using any one of the first to eighth embodiments. The quantum wire 163 is formed. Then, a gate insulating film 164 having a film thickness of 30 nm is formed on the insulating layer 162 and the quantum wire 163 by a CVD method, and a transparent gate electrode 165 is formed on the gate insulating film 164 with ITO (Indium Tin Oxide) or the like. To do.

  In the above configuration, since the quantum wire 163 has a diameter of 10 nm or less, it has a direct transition type band structure due to the quantum confinement effect. Then, by applying a voltage between the gate electrode 165 and the silicon substrate 161, a tunnel current flows between the insulating film 162 and the gate insulating film 164, and electrons are injected into the quantum wire 163 by the tunnel current, The quantum wire 163 emits light due to the transition of electrons. That is, according to this embodiment, a light-emitting element having a high efficiency and excellent high-frequency characteristics having a sharp spectrum even with a small injection current can be obtained.

  In that case, the quantum wire 163 is formed of silicon by using a general film formation technique, a lithography technique, and an etching technique. Therefore, a light-emitting element suitable for mass production with low cost, high yield, and high productivity can be realized.

<Twelfth embodiment>
FIG. 12A shows a cross section of a light emitting element as the semiconductor element. In the light emitting device shown in FIG. 12A, an insulating layer (the third oxide film) 172 and a diameter of several tens of nanometers are formed on a silicon substrate 171 according to any one of the first to eighth embodiments. The following quantum wires 173 are formed. Then, an insulating film 174 having a thickness of 30 nm is formed on the insulating layer 172 and the quantum wire 173 by a CVD method. Further, an N-type impurity region 175 is formed by ion-implanting an N-type impurity into a part of the quantum wire 173 using a photoresist mask (not shown). Similarly, a P-type impurity region 176 is formed by implanting P-type impurity ions into regions other than the N-type impurity region 175 in the same quantum wire 173.

  In the above configuration, since the quantum wire 173 has a diameter of several tens of nm or less, it has a direct transition type band structure due to the quantum confinement effect, and is located in the boundary region between the N-type impurity region 175 and the P-type impurity region 176. A PN junction is formed. Accordingly, a band structure of a PN junction as shown in FIG. 12B is formed, and by applying a voltage between the N-type impurity region 175 and the P-type impurity region 176, the arrow (G) As shown in FIG. 8, recombination of electrons 180 and holes 181 occurs, and light 177 is emitted. In FIG. 12B, 178 is a conduction band and 179 is a valence band.

  In that case, the quantum wire 173 is formed of silicon by using a general film forming technique, a lithography technique, and an etching technique. Therefore, a light-emitting element suitable for mass production with low cost, high yield, and high productivity can be realized.

<13th Embodiment>
FIG. 13 is a plan view showing a procedure for producing a light emitting element as the semiconductor element. In FIG. 13, first, as shown in FIG. 13 (a), the Si substrate 191 is subjected to the steps described in any of the first to eighth embodiments in FIG. 4 (h). As shown, a groove 192 is formed which is sandwiched between the oxide film and nitride film stack and the oxide film to expose the Si substrate 191. In that case, portions other than the groove 192 on the surface of the Si substrate 191 are covered with an insulating layer. Then, the top of the Si substrate 191 including a part of the groove 192 is covered with a first nitride film 193.

  Next, as shown in FIG. 13B, a trench 192 that is not covered with the first nitride film 193 by the quantum wire growth process described in any of the first to eighth embodiments. The Si thin wire 194 is grown on the portion. Next, as shown in FIG. 13C, the first nitride film 193 is removed to expose the portion of the groove 192 covered by the first nitride film 193, while covering the Si thin wire 194 portion. A 2 nitride film 195 is formed.

Next, as shown in FIG. 13 (d), monosilane (SiH ₄ ) and monogermane (raw material gas) are formed by the quantum wire growth process described in any of the first to eighth embodiments. Using GeH ₄ ), a SiGe thin wire 196 is grown in the portion of the groove 192 not covered with the second nitride film 195. Next, as shown in FIG. 13E, after the second nitride film 195 is removed, the SiGe thin line 196, the Si thin line 194a on the left side of the SiGe thin line 196, and the right side of the SiGe thin line 196 in the figure. Appropriate ions are implanted into each of the Si thin wires 194b. In this way, this light emitting element is obtained.

  FIG. 14 shows a band structure of the light-emitting element having the above structure. Since SiGe has a smaller band gap than Si, it has a double heterostructure, and electrons 203 and holes 204 are concentrated on the SiGe thin wire 196. Therefore, recombination of the electrons 203 and the holes 204 indicated by the arrow (H) is performed efficiently, and the light 205 is emitted. In FIG. 14, 201 is a conduction band, and 202 is a valence band.

  In that case, the Si thin wire 194 and the SiGe thin wire 196 are formed of SI or SiGe using a general film forming technique, a lithography technique, and an etching technique. Therefore, a highly efficient light-emitting element suitable for mass production with low cost, high yield, and high productivity can be realized.

In the first to thirteenth embodiments, the Si substrate is used as the semiconductor substrate. However, the present invention is not limited to this, and a semiconductor substrate other than Si may be used. In addition, although disilane (Si ₂ H ₆ ) is used as a source gas when the quantum wires are formed of silicon, monosilane (SiH ₄ ), trisilane (Si ₃ H ₈ ), dichlorosilane (SiH ₂ Cl ₂ ) and tetra Any one of chlorosilane (SiCl ₄ ) may be used. When the quantum wires are formed of germanium, any one of monogermane (GeH ₄ ), digermane (Ge ₂ H ₆ ), or germanium tetrafluoride (GeF ₄ ) may be used as a source gas. Good. When the quantum wires are formed of silicon germanium, the raw material gas is monosilane (SiH ₄ ), disilane (Si ₂ H ₆ ), trisilane (Si ₃ H ₈ ), dichlorosilane (SiH ₂ Cl ₂ ) or A mixed gas of any one of tetrachlorosilane (SiCl ₄ ) and any one of monogermane (GeH ₄ ), digermane (Ge ₂ H ₆ ), or germanium tetrafluoride (GeF ₄ ) may be used. . When the quantum wires are formed of aluminum, organic aluminum such as DMAH ((CH ₃ ) ₂ AlH) may be used as a raw material.

  Further, the material of the quantum wire is not limited to silicon, germanium or silicon germanium as the semiconductor and aluminum as the metal. In addition, the present invention can be applied to high-density LSI wiring because it can form ultrafine fine wires made of a conductive material without using a special fine processing apparatus. In addition, the quantum effect device manufactured by the present invention and the semiconductor element having the quantum wire that is the basis of the single electron device can be mounted on the same substrate as the Si LSI, and this semiconductor element can be applied to a light emitting element or a photoelectric conversion element. By doing so, the electronic circuit and the optical communication circuit can be fused.

It is board | substrate sectional drawing which shows the manufacturing method of the quantum wire used for the semiconductor element of this invention. It is board | substrate sectional drawing which shows the manufacturing method of the quantum wire different from FIG. It is board | substrate sectional drawing which shows the manufacturing method of the quantum wire different from FIG. 1 and FIG. It is board | substrate sectional drawing which shows the manufacturing method of the quantum wire different from FIGS. It is board | substrate sectional drawing which shows the manufacturing method of the quantum wire different from FIGS. It is board | substrate sectional drawing which shows the manufacturing method of the quantum wire different from FIGS. It is board | substrate sectional drawing which shows the manufacturing method of the quantum wire different from FIGS. It is board | substrate sectional drawing which shows the manufacturing method of the quantum wire different from FIGS. It is a figure which shows the non-volatile memory as a semiconductor element of this invention. It is a figure which shows MOSFET as a semiconductor element different from FIG. It is a figure which shows the light emitting element as a semiconductor element different from FIG. 9 and FIG. It is a figure which shows the light emitting element as a semiconductor element different from FIGS. 9-11, and its band structure. It is a figure which shows the preparation procedure of the light emitting element as a semiconductor element different from FIGS. It is a figure which shows the band structure of the light emitting element shown in FIG. It is process drawing which shows the manufacturing method of Si quantum wire | line using the conventional anisotropic etching. It is process drawing which shows the quantum wire formation method using the mask formed with the conventional sidewall method. It is process drawing which shows the quantum wire formation method by the past two Si wafer bonding.

Explanation of symbols

31, 41, 61, 71, 81, 101, 121, 131, 141, 151, 161, 171, 191 ... silicon substrate,
32, 42, 62, 72, 82, 102, 122, 132 ... the first oxide film,
33,43,63,73,83,103,123,133,193 ... first nitride film,
34, 44, 64, 75, 85, 105, 124, 135, 195 ... second nitride film,
35, 45, 65, 74, 84, 104, 125, 134 ... second oxide film,
36, 46, 66, 91, 111, 126 ... third nitride film,
37, 47, 76, 86 ... Photoresist pattern,
38,48,68,77,87,107,128,137,192 ... groove,
39,78,129,138,194 ... Si thin wire,
40, 79, 130, 139 ... third oxide film,
51, 70 ... the fourth nitride film,
53, 90 ... second oxide film exposed portion,
142 ... element isolation region,
144: Tunnel oxide film,
145, 153, 163, 173 ... quantum wires,
146: Control gate insulating film,
147, 155, 165 ... gate electrodes,
148,156 ... source region,
149,157 ... drain region,
150, 158 ... channel region,
152,162,172,174 ... insulating layer,
154, 164 ... gate insulating film,
175... N-type impurity region,
176 ... P-type impurity region,
196 ... SiGe fine wire.

Claims (6)

A source region, a drain region, a channel region between the source region and the drain region, a gate region for controlling a channel current flowing in the channel region, and a floating gate positioned between the gate region and the channel region In a semiconductor device having a region, a first insulating film between the floating gate region and the gate region, and a second insulating film between the channel region and the floating gate region,
The floating gate region is composed of nanometer-sized quantum wires, extends in a direction intersecting with the arrangement direction of the source region and the drain region, and is arranged in parallel with the channel region. The semiconductor element characterized by the above-mentioned. The semiconductor device according to claim 1,
The cross-sectional shape of the floating gate region is such that the width measured in the extending direction of the first insulating film on the surface facing the channel region through the first insulating film is in the extending direction of the first insulating film. A semiconductor element characterized by a shape narrower than the measured maximum width. The semiconductor device according to claim 1,
At least the source region, the drain region, the channel region, and the floating gate region are formed of silicon. A source region, a drain region, a channel region between the source region and the drain region, a gate region for controlling a channel current flowing in the channel region, and a gate insulating film between the channel region and the gate region. In a semiconductor device having
The channel region is composed of nanometer-sized quantum wires. The semiconductor device according to claim 4,
The semiconductor element, wherein the source region and the drain region are formed on both sides of the channel region in a quantum wire constituting the channel region. The semiconductor device according to claim 4,
A semiconductor element, wherein at least the source region, the drain region, and the channel region are formed of silicon.

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