JP2006107628A - Ferroelectric memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric memory device which has less imprint effects. <P>SOLUTION: This ferroelectric memory device has a memory cell to store the predetermined data, plate lines and bit lines connected to the memory cell, a plate line control circuit to supply the 1st pulses to the plate lines, and a write circuit to supply the 2nd pulses to the bit lines, and a timing control circuit to control the timing where the write circuit supplies the 2nd pulses to the bit lines against the timing the plate line control circuit supplies the 1st pulses to the plate lines based on the data to store in the memory cell. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a ferroelectric memory device. The present invention particularly relates to a ferroelectric memory device that is less likely to cause an imprint phenomenon.

  A conventional semiconductor memory device is disclosed in Japanese Patent Laid-Open No. 11-134874 (Patent Document 1). In the conventional semiconductor memory device disclosed in Patent Document 1, in the conventional semiconductor memory device, at the time of reading and rewriting, the polarization state is inverted so that the hysteresis characteristic of the ferroelectric capacitor goes around at least once. Thus, the occurrence of the imprint effect is suppressed.

Japanese Patent Laid-Open No. 11-134874

  However, in the conventional semiconductor memory device, when new data is written to the ferroelectric capacitor based on the write data supplied from the outside, the inversion phenomenon of the polarization state is not performed, so an imprint phenomenon occurs. There was a problem that it would end up. In particular, in a semiconductor memory device used for an LCD driver, an operation of continuously writing “0” data as write data frequently occurs, and the occurrence of an imprint phenomenon is remarkable.

  Therefore, an object of the present invention is to provide a ferroelectric memory device that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  To achieve the above object, according to the first aspect of the present invention, a memory cell that stores predetermined data, a plate line and a bit line connected to the memory cell, and a first pulse is supplied to the plate line. A plate line control circuit, a write circuit for supplying a second pulse to the bit line, and a write circuit for timing at which the plate line control circuit supplies the first pulse to the plate line based on stored data stored in the memory cell. There is provided a ferroelectric memory device comprising a timing control circuit for controlling a timing of supplying a second pulse to a bit line.

  In the above embodiment, the timing of the pulses supplied to the plate line and the bit line can be relatively shifted according to the data to be stored in the memory cell. That is, in the above embodiment, when data is stored in the memory cell, there are both a timing at which the plate line has a higher potential than the bit line and a timing at which the bit line has a higher potential than the plate line. The timing control circuit can control these timings based on the stored data stored in the memory cell. Therefore, according to the above configuration, when storing the storage data in the memory cell, both the storage data and its complementary data can be written, so that the imprint phenomenon can be suppressed. In the above embodiment, the writing circuit and the timing control circuit may be provided separately or may be provided as one configuration.

  In the ferroelectric memory device, the timing control circuit includes a plate line control circuit and a plate line control circuit, so that a period during which the first pulse is supplied to the plate line overlaps a part of a period during which the second pulse is supplied to the bit line. It is preferable to control at least one of the writing circuits.

  In the above embodiment, the period during which the first pulse is supplied to the plate line overlaps with the period during which the second pulse is supplied to the bit line. Therefore, according to the above embodiment, the imprint phenomenon can be suppressed and the stored data can be written into the memory cell at high speed.

  In the ferroelectric memory device, the timing control circuit is configured such that when the stored data is “1”, the timing at which the first pulse is supplied to the plate line is earlier than the timing at which the second pulse is supplied to the bit line. When the stored data is “0”, the timing at which the first pulse is supplied to the plate line is delayed from the timing at which the second pulse is supplied to the bit line. It is preferable to control at least one.

  In the ferroelectric memory device, the first pulse has a first edge and a second edge delayed from the first edge, and the ferroelectric memory device has a first timing earlier than the first edge, And a first timing signal whose voltage changes at a second timing between the first edge and the second edge, a third timing between the first edge and the second edge, and a second timing later than the second edge. A timing signal generation unit that generates a second timing signal whose voltage changes at four timings, and the timing control circuit selects the first timing signal or the second timing signal based on the stored data, and the writing circuit Preferably, the second pulse is generated based on the selected first timing signal or second timing signal and supplied to the bit line.

  In the above embodiment, the timing for supplying the second pulse to the bit line relative to the timing for supplying the first pulse to the plate line is controlled by selecting the first timing signal or the second timing signal. Therefore, according to the above embodiment, both the stored data and its complementary data can be written with a very simple operation of selecting a signal based on the stored data to be written in the memory cell, thereby suppressing the imprint phenomenon. be able to.

  The ferroelectric memory device includes a plurality of bit lines, a plurality of write circuits and a plurality of timing control circuits provided on each of the plurality of bit lines, and the timing signal generation unit includes a plurality of timing control circuits. The first timing signal and the second timing signal are supplied to the plurality of timing control circuits, and the plurality of timing control circuits respectively select one of the first timing signal and the second timing signal supplied from the timing signal generation unit, and The writing circuit may generate the second pulse based on the first timing signal and the second timing signal selected by the corresponding timing control circuit and supply the second pulse to the corresponding bit line.

The ferroelectric memory device includes a plurality of bit lines and a plurality of write circuits respectively provided on the plurality of bit lines, and the timing control circuit includes a first timing signal and a second timing signal generated by the timing signal generation unit. One of the timing signals is selected, and each of the plurality of write circuits generates a second pulse based on the first timing signal or the second timing signal selected by the timing control circuit and supplies the second pulse to the corresponding bit line. Is preferred.
In the above embodiment, since it is not necessary to provide the timing control circuit for each of the plurality of write circuits, the chip area of the ferroelectric memory device can be reduced. The timing control circuit is provided, for example, in the data input / output circuit portion of the ferroelectric memory device or in the vicinity thereof.

  In the above ferroelectric memory device, the write circuit is connected to one end of the bit line and writes stored data to the memory cell, and the ferroelectric memory device is connected to the other end of the bit line and writes to the memory cell. It is preferable to further include a read circuit for reading the stored data.

  In the above embodiment, for example, even when the ferroelectric memory device is used as a multi-port memory such as a TFT driver that easily writes one data continuously, the imprint effect can be suppressed. it can.

  In addition, “one end” and “the other end” do not refer to only the physical end of the bit line, but when the write circuit and / or the read circuit are not connected to the physical end of the bit line. Even in such a case, the case where the write circuit and / or the read circuit is connected to the bit line in a predetermined region or an end of a predetermined configuration is included.

  According to the second aspect of the present invention, the voltage of the plate line is determined based on the memory cell storing predetermined data, the bit line and the plate line connected to the memory cell, and the storage data stored in the memory cell. There is provided a ferroelectric memory device comprising a control unit that controls a timing at which a voltage of a bit line changes with respect to a changing timing and stores the stored data in a memory cell.

  According to a third aspect of the present invention, there is provided a ferroelectric memory device having a memory cell connected to a bit line, the write circuit being connected to one end of the bit line and writing stored data in the memory cell; A read circuit connected to the other end of the bit line and reading stored data written in the memory cell, the write circuit writes complementary data of the stored data into the memory cell, and further writes the stored data, There is provided a ferroelectric memory device characterized in that the memory data is stored in the memory cell.

  Hereinafter, the present invention will be described through embodiments of the invention with reference to the drawings. However, the following embodiments do not limit the invention according to the claims, and are described in the embodiments. Not all combinations of features are essential to the solution of the invention.

  FIG. 1 is a diagram showing a first embodiment of a ferroelectric memory device 100 according to the present invention. The ferroelectric memory device 100 includes a plurality of memory cells MC, a plurality of word lines WL0 to m (m is a positive integer), plate lines PL0 to m, bit lines BL0 to n and / BL0 to n (n Is a positive integer), a word line control circuit 120, a plate line control circuit 130, a write circuit 140, a timing signal generation circuit 142, and a read circuit 150.

  Memory cells MC are arranged in an array and are connected to word lines WL0 to m, plate lines PL0 to m, bit lines BL0 to n, and bit lines / BL0 to n. In the present embodiment, the memory cell MC has a 2T2C type structure including two n-type MOS transistors TR1 and TR2 and two ferroelectric capacitors C1 and C2, and the ferroelectric capacitors C1 and C2 include Are complementary to each other.

  In the n-type MOS transistor TR1, one of the source and the drain is connected to the bit lines BL0 to BLn, and the other is connected to one end of the ferroelectric capacitor C1. In the n-type MOS transistor TR2, one of the source and the drain is connected to bit lines / BL0 to n which are complementary to the bit lines BL0 to BLn, and the other is one end of the ferroelectric capacitor C2. It is connected to the.

  The n-type MOS transistors TR1 and TR2 have gates connected to the same word lines WL0 to m, and one ends of the ferroelectric capacitors C1 and C2 are connected to the bit line BL0 based on the voltage of the word lines, respectively. .. To n and bit lines / BL0 to n are switched. The other ends of the ferroelectric capacitors C1 and C2 are connected to the same plate lines PL0 to PLm.

  The word line control circuit 120 controls the voltage supplied to the word lines WL0 to m based on the X decode signal, and connects one ends of the ferroelectric capacitors C1 and C2 to the bit lines BL0 to BLn and the bit line, respectively. Control whether to connect to / BL0-n.

  The plate line control circuit 130 controls the voltage supplied to the plate lines PL0-m based on the plate line selection signal, thereby controlling the voltage at the other end of the ferroelectric capacitors C1 and C2. In the present embodiment, the plate line control circuit 130 supplies a first pulse to one of the plate lines PL0 to PL0 to select the plate line PL.

  The timing signal generation circuit 142 is a timing signal A and B that is an example of a first timing signal and a second timing signal that indicate timings at which the write circuit 140 changes the voltages of the bit lines BL0 to n and the bit lines / BL0 to n. Is generated. Details of the timing signals A and B will be described later.

  The write circuit 140 controls the voltages of the bit lines BL0 to BL to write storage data in the memory cell MC. The write circuit 140 is connected to one end of the bit lines BL0 to n and the bit lines / BL0 to n, and the plate line control circuit 130 is based on the stored data indicated by the data signals propagating through the data buses DB and / DB. Controls the timing of changing the voltages of the bit lines BL0 to n and the bit lines / BL0 to n with respect to the timing of changing the voltages of the plate lines PL0 to PL, and writes the storage data in the memory cell MC.

  Specifically, the write circuit 140 supplies the second pulse to the bit lines BL0 to n and the bit lines / BL0 to n to write the storage data in the memory cell MC, but based on the value of the storage data Thus, the timing signal A or B supplied from the timing signal generation circuit 142 is selected and supplied as the second pulse to the bit lines BL0 to n and bit lines / BL0 to n.

  The read circuit 150 is connected to the other ends of the bit lines BL0 to n and bit lines / BL0 to n, and reads the storage data stored in the memory cell MC. The read circuit 150 preferably supplies the read storage data to another data bus (not shown) different from the data buses DB and / DB.

  FIG. 2 is a diagram illustrating an example of the configuration of the write circuit 140. The write circuit 140 has a configuration connected to the bit lines BL0 to BLn (upper configuration in the figure; hereinafter referred to as an upper configuration) and a configuration connected to the bit lines / BL0 to BLn (lower configuration in the figure. In this example, both configurations have the same configuration except that the data bus DB or / DB is connected to the input.

  The write circuit 140 includes a driver 210 and a timing control circuit 220. The timing control circuit 220 generates a timing for supplying the second pulse to the bit lines BL0 to n and the bit lines / BL0 to n, and the driver 210 generates a bit line BL0 to n and the bit line / BL0 based on the timing. The second pulse is supplied to the bit lines BL0 to n and the bit lines / BL0 to n by changing the voltage to n.

  The timing control circuit 220 includes inverters 222 and 228, transmission gates 224 and 226, and a NAND circuit 230. The inverter 222 receives a data signal propagating through the data bus DB or / DB as an input, and uses the inverted signal as the gate of the n-type MOS transistor constituting the transmission gate 224 and the gate of the p-type MOS transistor constituting the transmission gate 226. To supply.

  Each of the transmission gates 224 and 226 receives the timing signals A and B generated by the timing signal generation circuit 142 as inputs, and supplies an output to the inverter 228. A data signal propagating through the data bus DB or / DB is supplied to the gate of the p-type MOS transistor constituting the transmission gate 224 and the gate of the n-type MOS transistor constituting the transmission gate 226. And 226 supply the timing signal A or B to the inverter 228 based on the voltage of the data signal. In other words, the transmission gates 224 and 226 select the timing signal A or B according to the value of the stored data indicated by the data signal and supply it to the inverter 228.

  The inverter 228 generates an inverted signal of the timing signal A or B supplied from the transmission gate 224 or 226 and supplies the inverted signal to the NAND circuit 230. The NAND circuit 230 receives the Y selection signal YSEL and the inverted signal as inputs, and supplies a negative logical product of them to the driver 210.

  The driver 210 includes a p-type MOS transistor 212 and n-type MOS transistors 214 to 218. In the p-type MOS transistor 212, the drive voltage VCC is supplied to the source, and the drain is connected to the drain of the n-type MOS transistor 214, the bit lines BL0 to BLn, and the bit lines / BL0 to BLn. The n-type MOS transistor 216 has a source grounded and a drain connected to the bit lines BL0 to BLn and the bit lines / BL0 to n via the n-type MOS transistor 214. Further, the output of the NAND circuit 230 is supplied to the gates of the p-type MOS transistor 212 and the n-type MOS transistor 216. Depending on the voltage of the output, either the p-type MOS transistor 212 or the n-type MOS transistor 216 is supplied. Either one is configured to be turned on.

  The source of the n-type MOS transistor 214 is connected to the drain of the n-type MOS transistor 216. Based on the voltage of the signal S supplied to the gate, the n-type MOS transistor 214 converts the bit lines BL0-n and the bit lines / BL0-n to n. Whether to connect to the drain of the type MOS transistor 218 is switched. For example, when the n-type MOS transistor 216 is turned on, the n-type MOS transistor 214 floats the bit lines BL0 to BLn and the bit lines / BL0 to n from the n-type MOS transistor 216. Thus, when the bit lines BL0-n and the bit lines / BL0-n are not selected, the bit lines BL0-n and the bit lines / BL0-n are selected to be in a floating state or fixed to 0V. Can do.

  In the n-type MOS transistor 218, the source is grounded, and the drain is connected to the output of the driver 210, that is, the bit lines BL0 to n and / BL0 to n. The n-type MOS transistor 218 is turned on when the signal BLD is supplied to the gate and the signal BLD indicates H logic, and grounds the bit lines BL0-n and / BL0-n.

  FIG. 3 is a timing chart showing the operation of the ferroelectric memory device 100. With reference to FIGS. 1 to 3, as an example of the operation of the ferroelectric memory device 100 of the first embodiment, data is stored in the ferroelectric capacitor C1 connected to the bit line BL0, the word line WL0, and the plate line PL0. A case will be described in which “1” is written and data “0” is written to the ferroelectric capacitor C2 connected to the bit line / BL0, the word line WL0, and the plate line PL0.

  In the following example, each signal is a digital signal indicating L logic or H logic. In the following example, the voltage of the signal when each signal indicates L logic is the ground voltage, and the voltage of the signal when each signal indicates H logic is the drive voltage of the ferroelectric memory device 100. VCC, VDD, or VPP. The voltage of each signal is not limited to this, and it is sufficient that the voltage of the signal when indicating H logic is higher than the voltage of the signal when indicating L logic.

  First, an address signal Address indicating the address of the memory cell MC connected to the bit lines BL0 and / BL0, the word line WL0, and the plate line PL0 is supplied from the outside of the ferroelectric memory device 100. Accordingly, the word line control circuit 120 changes the voltage of the word line WL0 from 0V to VCC based on the address signal, and one ends of the ferroelectric capacitors C1 and C2 are connected to the bit lines BL0 and / BL0, respectively. Is done.

  Further, the voltage of the Y selection signal YSEL0 changes from 0V to VCC. As a result, the write circuit 140 connected to the bit lines BL0 and / BL0 is connected to the data buses DB and / DB. At this time, the data signals propagating through the data buses DB and / DB are L logic and H logic, respectively, and the upper configuration transmission gate 224 and the lower configuration transmission gate 226 are turned on in the timing control circuit 220.

  Next, the data signal propagating through the data buses DB and / DB changes based on the data to be written to the ferroelectric capacitors C1 and C1. Specifically, since the data written to the ferroelectric capacitor C1 in this example is “1”, the data signal propagating through the data bus DB changes from L logic to H logic, and data propagating through the data bus / DB. The signal changes from H logic to L logic. Thereby, in the upper configuration of FIG. 2, the transmission gate 224 is turned off and the transmission gate 226 is turned on, so that the timing signal B is supplied to the inverter 228. In the lower configuration, since the transmission gate 224 is turned on and the transmission gate 226 is turned off, the timing signal A is supplied to the inverter 228.

  In the present embodiment, the timing signal generation circuit 142 generates a signal including a first pulse having a first edge and a second edge delayed from the first edge as the timing signal A, and a third signal as the timing signal B. A signal including a second pulse having an edge and a fourth edge delayed from the third edge is generated. The timing signal A is a signal in which the period between the first edge and the second edge is L logic, and the timing signal B is in the period between the third edge and the fourth edge. Signal. The timing signal generation circuit 142 generates the timing signals A and B so that the first pulse of the timing signal A overlaps a part of the second pulse of the timing signal B. That is, the period in which the timing signal A indicates L logic overlaps with a part of the period in which the timing signal B indicates L logic.

  Next, when the signal BLD changes from H logic to L logic and the signal S changes from L logic to H logic, the n-type MOS transistor 218 is turned off, but the n-type MOS transistor 214 is turned on, Since the output of the NAND circuit 230 is H logic and the n-type MOS transistor 216 is turned on, the bit line BL0 and the bit line / BL0 remain grounded.

  Next, the timing signal generation circuit 142 changes the voltage of the timing signal A before the timing at which the plate line control circuit 130 supplies the first pulse to the plate line PL0. Specifically, the timing signal generation circuit 142 changes the timing signal A from H logic to L logic at a timing earlier than the rising edge of the first pulse supplied to the plate line PL0.

  When the timing signal A changes from H logic to L logic, both inputs of the NAND circuit 230 become H logic in the lower configuration of FIG. 2, and therefore the gates of the p-type MOS transistor 212 and the n-type MOS transistor 216 in the driver 210. Becomes L logic, the p-type MOS transistor 212 is turned on, and the n-type MOS transistor 216 is turned off. Therefore, the voltage of the bit line / BL changes from 0V to VCC, the supply of the second pulse to the bit line / BL0 is started, and the voltage at one end of the ferroelectric capacitor C2 becomes VCC.

  At this time, since the voltage of the plate line PL0 is 0V, a voltage of −VCC is applied to the ferroelectric capacitor C2 with respect to the bit line / BL0, and therefore, the ferroelectric capacitor C2 has the ferroelectric capacitor C2 applied thereto. Data “1” which is data opposite to the data to be written to is written. On the other hand, the voltage of the bit line BL0 is 0V, and the voltage applied to the ferroelectric capacitor C1 remains 0V.

  Next, the plate line control circuit 130 changes the voltage of the plate line PL0 from 0 V to VCC, and starts supplying the first pulse to the plate line PL0. As a result, the voltage at the other end of the ferroelectric capacitors C1 and C2 becomes VCC. At this time, since the voltage of the bit line BL0 is 0V, a voltage of + VCC is applied to the ferroelectric capacitor C1 with reference to the bit line BL0, and thus the ferroelectric capacitor C1 is written in the ferroelectric capacitor C1. Data “0” which is data opposite to the data to be written is written.

  Next, the timing signal generation circuit 142 changes the voltage of the timing signal B before the timing when the plate line control circuit 130 changes the voltage of the plate line PL0 from VCC to 0V. Specifically, the timing signal generation circuit 142 changes the timing signal B from H logic to L logic at a timing earlier than the falling edge of the first pulse supplied to the plate line PL0.

  When the timing signal B changes from H logic to L logic, both inputs of the NAND circuit become H logic in the upper configuration of FIG. 2, so that the gates of the p-type MOS transistor 212 and the n-type MOS transistor 216 in the driver 210 are The logic becomes L, the p-type MOS transistor 212 is turned on, and the n-type MOS transistor 216 is turned off. Accordingly, the voltage of the bit line BL0 changes from 0V to VCC, the supply of the second pulse to the bit line BL0 is started, and the voltage at one end of the ferroelectric capacitor C1 becomes VCC.

  At this time, since the voltage of the plate line PL0 is VCC, the voltage applied to the ferroelectric capacitor C1 becomes 0V, and the “0” data written in the ferroelectric capacitor C1 is held as it is.

  Next, the timing signal generation circuit 142 changes the voltage of the timing signal A before the timing when the plate line control circuit 130 changes the voltage of the plate line PL0 from VCC to 0V. Specifically, the timing signal generation circuit 142 changes the timing signal A from L logic to H logic at a timing earlier than the falling edge supplied to the plate line PL0.

  When the timing signal A changes from L logic to H logic, one of the inputs of the NAND circuit 230 becomes L logic in the lower configuration of FIG. 2, so that the gates of the p-type MOS transistor 212 and the n-type MOS transistor 216 in the driver 210. Becomes H logic, the p-type MOS transistor 212 is turned off, and the n-type MOS transistor 216 is turned on. Therefore, the voltage of the bit line / BL0 changes from VCC to 0V, the supply of the second pulse to the bit line / BL0 is completed, and the voltage at one end of the ferroelectric capacitor C2 becomes 0V.

  At this time, since the voltage of the plate line PL0 is VCC, a voltage of + VCC is applied to the ferroelectric capacitor C2 with reference to the bit line / BL0, and therefore, the ferroelectric capacitor C2 is connected to the ferroelectric capacitor C2. Data “0”, which is data to be written, is written.

  Next, the plate line control circuit 130 changes the voltage of the plate line PL0 from VCC to 0V, and the supply of the first pulse to the plate line PL0 is completed. As a result, the voltage at the other end of the ferroelectric capacitors C1 and C2 becomes 0V. At this time, since the voltage of the bit line BL0 is VCC, the voltage of -VCC is applied to the ferroelectric capacitor C1 with reference to the voltage of the bit line BL0, and therefore, the ferroelectric capacitor C1 includes the ferroelectric capacitor. Data “1”, which is data to be written to C1, is written.

  Next, the timing signal generation circuit 142 changes the timing signal A from L logic to H logic. 2, one of the inputs of the NAND circuit 230 becomes L logic in the upper configuration of FIG. 2, so that the gates of the p-type MOS transistor 212 and the n-type MOS transistor 216 in the driver 210 become H logic. Is turned off and the n-type MOS transistor 216 is turned on. Therefore, the voltage of the bit line BL0 changes from VCC to 0V, the supply of the second pulse to the bit line / BL0 is completed, and the voltage at one end of the ferroelectric capacitor C1 becomes 0V. As a result, the voltages applied to the ferroelectric capacitors C1 and C2 are both 0V, and the written data “1” and data “0” are held in the ferroelectric capacitors C1 and C2, respectively.

  FIG. 4 is a diagram showing hysteresis characteristics of the ferroelectric capacitors C1 and C2. With reference to FIG. 3 and FIG. 4, a change in the hysteresis characteristics of the ferroelectric capacitors C1 and C2 in the present embodiment will be described. In FIG. 4, the horizontal axis indicates the voltage applied to the ferroelectric capacitors C1 and C2, and the vertical axis indicates the polarization amount of the ferroelectric capacitors C1 and C2. In the following description, the voltage applied to the ferroelectric capacitors C1 and C2 is the voltage of the bit line BL0 and the bit line / BL0 rather than the voltage of the plate line PL0, that is, the voltage at the other end of the ferroelectric capacitors C1 and C2. That is, when the voltages of the ferroelectric capacitors C1 and C2 are high, it is represented by plus.

  First, the hysteresis characteristic of the ferroelectric capacitor C1 in which “1” is written as stored data in the present embodiment will be described. When the stored data previously stored in the ferroelectric capacitor C1 is “1”, the hysteresis characteristic is at the point D in the initial state. When the stored data is “0”, the hysteresis characteristic is at point A in the initial state.

  When the voltage of the plate line PL0 changes from 0V to VCC, the voltage applied to the ferroelectric capacitor C1 becomes + VCC. Therefore, when the stored data is "1", the hysteresis characteristic is the point D From point A to point F, the point moves to point F, and when it is “0”, the point A moves to point F.

  Next, when the voltage of the bit line BL0 changes from 0V to VCC, the voltage applied to the ferroelectric capacitor C1 becomes 0V, and the hysteresis characteristic moves from the F point to the A point. When the voltage of the plate line PL0 changes from VCC to 0V, the voltage applied to the ferroelectric capacitor C1 becomes −VCC, and the hysteresis characteristic moves from the A point to the B point through the B point. When the voltage of the bit line BL0 changes from VCC to 0V, the voltage applied to the ferroelectric capacitor C1 becomes 0V, and the hysteresis characteristic moves from the C point to the D point.

  Therefore, in the present embodiment, when the storage data “1” is written to the ferroelectric capacitor C1, polarization inversion occurs regardless of the data stored in the initial state, and therefore, the occurrence of the imprint phenomenon can be suppressed. . The same applies when the stored data “1” is written to the ferroelectric capacitor C2.

  Next, the hysteresis characteristic of the ferroelectric capacitor C2 to which the stored data “0” is written in the present embodiment will be described. When the stored data previously stored in the ferroelectric capacitor C2 is “1”, the hysteresis characteristic is at the point D in the initial state. When the stored data is “0”, the hysteresis characteristic is at point A in the initial state.

  When the voltage of the bit line / BL0 changes from 0V to VCC, the voltage applied to the ferroelectric capacitor C2 becomes −VCC. Therefore, when the stored data is “1”, the hysteresis characteristic is as follows: When the point moves from the point D to the point C and is “0”, the point A moves from the point A to the point B through the point B.

  Next, when the voltage of the plate line PL0 changes from 0V to VCC, the voltage applied to the ferroelectric capacitor C2 becomes 0V, and the hysteresis characteristic moves from the C point to the D point. When the voltage of the bit line / BL0 changes from VCC to 0V, the voltage applied to the ferroelectric capacitor C2 becomes + VCC, and its hysteresis characteristic moves from the D point to the E point through the E point. When the voltage of the plate line PL0 changes from VCC to 0V, the voltage applied to the ferroelectric capacitor C2 becomes 0V, and the hysteresis characteristic moves from the F point to the A point.

  Therefore, in the present embodiment, when the storage data “0” is written to the ferroelectric capacitor C2, polarization inversion occurs regardless of the data stored in the initial state, and therefore, the occurrence of the imprint phenomenon can be suppressed. . The same applies when the stored data “0” is written to the ferroelectric capacitor C1.

  FIG. 5 is a diagram illustrating a second embodiment of the ferroelectric memory device 100. In the following, the ferroelectric memory device 100 according to the second embodiment will be described focusing on differences from the first embodiment. In addition, about the structure which attached | subjected the code | symbol same as 1st Embodiment, it has a function similar to 1st Embodiment. The operation of the ferroelectric memory device 100 of this embodiment is the same as that of the ferroelectric memory device 100 of the first embodiment whose operation timing is shown in FIG.

  In the present embodiment, the timing control circuit 220 provided for each write circuit 140 in the first embodiment is configured to supply data signals to the plurality of write circuits 140. The ferroelectric memory device 100 includes write data buses WD and / WD instead of the data buses DB and / DB, and the timing control circuit 220 uses the write data bus WD based on a data signal indicating stored data. The write data signal and its inverted signal are supplied to / WD.

  The timing control circuit 220 according to this embodiment includes an inverter 250 instead of the NAND circuit 230 according to the first embodiment. The inverter 228 supplies the output as a write data signal to the write data bus WD. The inverter 250 receives the output of the inverter 228 as an input, that is, the write data signal, and supplies the inverted signal as an output to the write data bus / WD.

  FIG. 6 is a diagram illustrating an example of the configuration of the write circuit 140 according to the second embodiment. In the present embodiment, the write circuit 140 has the configuration of the driver 210 of the first embodiment, and further includes an n-type MOS transistor 262 and p-type MOS transistors 264 and 266.

  The n-type MOS transistor 262 has a drain connected to the write data buses WD and / WD, and a source connected to the gates of the p-type MOS transistor 212 and the n-type MOS transistor 216. The n-type MOS transistor 262 is supplied with the Y selection signal YSEL at its gate, and when YSEL indicates H logic, the n-type MOS transistor 262 transmits the data signal propagating through the write data buses WD and / WD to the p-type MOS transistor 212 and This is supplied to the n-type MOS transistor 216.

  In the p-type MOS transistor 264, VCC is supplied to the source, and the drain is connected to the p-type MOS transistor 212 and the n-type MOS transistor 216. The p-type MOS transistor 264 is supplied with VCC to the gates of the p-type MOS transistor 212 and the n-type MOS transistor 216 when YSEL is supplied to the gate and YSEL indicates L logic. That is, when YSEL indicates L logic, the n-type MOS transistor 216 is turned on with VCC supplied to the gate. Thus, the driver 210 and the write data buses WD and / WD can be connected by the n-type MOS transistor 262, so that the parasitic capacitance applied to the timing control circuit 220 can be reduced.

  In the p-type MOS transistor 266, VCC is supplied to the source, and the drain is connected to the p-type MOS transistor 212 and the n-type MOS transistor 216. That is, the p-type MOS transistor 266 is provided in parallel with the p-type MOS transistor 264. The gate of the p-type MOS transistor 266 is connected to the drains of the p-type MOS transistor 212 and the n-type MOS transistor 214. That is, the p-type MOS transistor 266 has a gate connected to the bit lines BL0-n and / BL0-n, and when the voltages of the bit lines BL0-n and / BL0-n are 0V, the p-type MOS transistor 212 VCC is supplied to the gate of the n-type MOS transistor 216. That is, the p-type MOS transistor 266 can function as a pull-up transistor. As a result, the output of the driver 210 can be latched, so that the selected bit line can be prevented from floating.

  FIG. 7 is a diagram illustrating another example of the configuration of the write circuit 140 according to the second embodiment. In the following, the writing circuit 140 of this example will be described focusing on differences from the writing circuit 140 of FIG. Note that the configuration denoted by the same reference numeral as that of the writing circuit 140 in FIG. 6 has the same configuration and function as the configuration.

  The write circuit 140 of this example is different from the write circuit 140 described in FIG. 6 in that p-type MOS transistors 264 and 266 are provided in series. Specifically, the write circuit 140 of this example is different from the write circuit 140 described in FIG. 6 in that the drain of the p-type MOS transistor 266 is connected to the source of the p-type MOS transistor 264. As a result, when the bit line is selected, that is, when YSEL is H logic, the current flowing through the p-type MOS transistor 266 can be cut off, so that when WD or / WD is L logic, VDD Can prevent an increase in the L logic level of WD or / WD due to a through current flowing through p-type MOS transistors 266 and 264 and n-type MOS transistor 262. When YSEL is L logic, the bit line is not selected, and the gate voltage of the n-type MOS transistor 216 is set to H logic by the p-type MOS transistor 266 using the ground potential of the bit line as a gate input. Even if the BLD signal is not always maintained as H logic, the bit line level can be fixed to the ground potential by the n-type MOS transistor 216. Further, since the source or drain of the n-type MOS transistor 262 is connected to each of the bit lines to WD and / WD, the wiring load of WD and / WD can be reduced. Therefore, since the write circuit 140 can be immediately connected to the write data buses WD and / WD when the bit line is selected, the write data signal can be propagated at high speed.

  The examples and application examples described through the embodiments of the present invention can be used in combination as appropriate according to the application, or can be used with modifications or improvements, and the present invention is limited to the description of the above-described embodiments. It is not a thing. It is apparent from the description of the scope of claims that the embodiments added with such combinations or changes or improvements can be included in the technical scope of the present invention.

1 is a diagram showing a first embodiment of a ferroelectric memory device 100 of the present invention. 2 is a diagram illustrating an example of a configuration of a write circuit 140. FIG. 3 is a timing chart showing the operation of the ferroelectric memory device 100. It is a figure which shows the hysteresis characteristic of the ferroelectric capacitors C1 and C2. 3 is a diagram showing a second embodiment of a ferroelectric memory device 100. FIG. It is a figure which shows an example of a structure of the write circuit 140 in 2nd Embodiment. It is a figure which shows the other example of a structure of the write circuit 140 in 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Ferroelectric memory device, 120 ... Word line control circuit, 130 ... Plate line control circuit, 130 ... Plate line control circuit, 140 ... Write circuit, 142 ... Timing signal Generation circuit, 150... Readout circuit, 210... Driver, 220.

Claims (9)

A memory cell for storing predetermined data;
A plate line and a bit line connected to the memory cell;
A plate line control circuit for supplying a first pulse to the plate line;
A write circuit for supplying a second pulse to the bit line;
Controlling the timing at which the write circuit supplies the second pulse to the bit line with respect to the timing at which the plate line control circuit supplies the first pulse to the plate line based on the stored data stored in the memory cell A ferroelectric memory device comprising a timing control circuit.   The timing control circuit includes the plate line control circuit and the write circuit such that a period during which the first pulse is supplied to the plate line overlaps a part of a period during which the second pulse is supplied to the bit line. 2. The ferroelectric memory device according to claim 1, wherein at least one of the circuits is controlled.   In the timing control circuit, when the stored data is “1”, the timing at which the first pulse is supplied to the plate line is earlier than the timing at which the second pulse is supplied to the bit line. The plate line control circuit is configured such that when the stored data is "0", the timing at which the first pulse is supplied to the plate line is later than the timing at which the second pulse is supplied to the bit line. 3. The ferroelectric memory device according to claim 1, wherein at least one of the write circuit and the write circuit is controlled. The first pulse has a first edge and a second edge delayed from the first edge,
The ferroelectric memory device is
A first timing signal whose voltage changes at a first timing earlier than the first edge, and a second timing between the first edge and the second edge, and the first edge and the second edge; A timing signal generator for generating a second timing signal whose voltage changes at a third timing between the second timing and a fourth timing later than the second edge;
Further comprising
The timing control circuit selects the first timing signal or the second timing signal based on the stored data;
4. The write circuit according to claim 1, wherein the write circuit generates the second pulse based on the selected first timing signal or second timing signal and supplies the second pulse to the bit line. 5. 2. A ferroelectric memory device according to 1. A plurality of the bit lines;
A plurality of the write circuits and a plurality of the timing control circuits provided in each of the plurality of bit lines;
With
The timing signal generator supplies the first timing signal and the second timing signal to the plurality of timing control circuits;
Each of the plurality of timing control circuits selects one of the first timing signal and the second timing signal supplied from the timing signal generation unit;
The plurality of write circuits generate the second pulse based on the first timing signal and the second timing signal selected by the corresponding timing control circuit, and supply the second pulse to the corresponding bit line. 5. The ferroelectric memory device according to claim 4, wherein: A plurality of the bit lines;
A plurality of the write circuits provided respectively on the plurality of bit lines;
The timing control circuit selects one of the first timing signal and the second timing signal generated by the timing signal generation unit,
Each of the plurality of write circuits generates the second pulse based on the first timing signal or the second timing signal selected by the timing control circuit, and supplies the second pulse to the corresponding bit line. The ferroelectric memory device according to claim 4. The write circuit is connected to one end of the bit line and writes stored data to the memory cell,
6. The ferroelectric memory device according to claim 1, further comprising a read circuit that is connected to the other end of the bit line and reads the stored data written in the memory cell. The ferroelectric memory device according to the item. A memory cell for storing predetermined data;
A bit line and a plate line connected to the memory cell;
A control unit that controls the timing at which the voltage of the bit line changes relative to the timing at which the voltage of the plate line changes based on the storage data stored in the memory cell, and stores the storage data in the memory cell; A ferroelectric memory device comprising: A ferroelectric memory device having memory cells connected to a bit line,
A write circuit connected to one end of the bit line and writing storage data into the memory cell;
A read circuit connected to the other end of the bit line and reading the stored data written in the memory cell;
The ferroelectric memory device, wherein the write circuit writes complementary data of the storage data to the memory cell, and further writes the storage data to store the storage data in the memory cell.

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