JP2006107614A - Memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the overhead when the RDRAM memory controller issues a burst refresh instruction. <P>SOLUTION: The refresh bank address generating means has a function to sequentially generate bank addresses in advance before burst issuing a refresh command. A page management means issues an NAPExit command and compares those bank addresses with the bank addresses on the page opened. When it detects a contention, it outputs the address information of this contention page with a conflict detection signal. A command issue means issues a command to close this page based on the page address information output when there is a contention, and burst issues a refresh command after finishing the NAPExit. At this time, the refresh bank address generating means again generates the addresses from the first refresh bank address. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device in an information processing apparatus, and more particularly to a method for controlling a DRAM.

  The improvement of the processing power of the central processing unit in the computer system is not known until now, and its basic operation clock frequency has exceeded 1GHz. On the other hand, the speed of the semiconductor memory device constituting the main memory has not improved so much, and the gap between the two has been widening.

  For this reason, it has been attempted to buffer the speed gap by providing a memory (cache memory) having a low capacity but a higher speed between the CPU and the main memory, and hierarchizing the storage devices (for example, Patent Document 1). reference). This is because the locality of reference when the CPU accesses the memory is high, and it is configured so that almost all accesses are made to the small-capacity and high-speed cache memory, thereby reducing the operation speed of the main memory. It is something to hide. Computer systems with two or more levels of cache memory are not uncommon today.

  However, the loss when an access misses in the cache increases relatively as the storage hierarchy increases and the main memory and CPU speeds increase. In recent years, as the number of applications that handle stream-type data such as moving images has increased, the locality of data access has decreased relatively, which reduces the effect of caching and improves the performance of a single CPU. It has become difficult to improve the performance of the entire system.

  The essential solution to this problem is to increase the operating speed of the main memory. However, it is difficult to increase the device speed of DRAM, which constitutes the main memory of most computer systems today, as much as the CPU. Therefore, it is necessary to improve the effective operation speed by devising the peripheral circuit architecture centered on the DRAM device. Conventionally, various types of DRAMs have been devised based on this concept. Typical examples that have been put into practical use in recent years include EDO-DRAM, SDRAM, and DDR-SDRAM. Among them, DirectRDRAM (DRDRAM) uses a high clock frequency for the interface part, performs access by a packet unit protocol, and realizes a high effective transfer rate by deep pipeline processing.

  FIG. 2 shows the configuration of a memory system using DRDRAM. In DRDRAM, CTM / CTMN, CFM / CFMN, RQ [7: 0] {ROW [2: 0], COL [4: 0]}, DQA [8: 0], DQB [8: 0] Communication is performed with the memory controller via a total of 33 signal lines, SCK, CMD, and SIO.

  A command composed of a packet synchronized with CFM / CFMN is given to each DRDRAM from the memory controller on the RQ [7: 0] signal line. Packets are divided into ROW packets that use ROW [2: 0] and COL packets that use COL [4: 0] on the RQ signal line, and the device address, bank address, and row address (ROW packet) of the target device. ) Or column address (COL packet). When the command is a write command, write data is subsequently sent on the DQA / DQB signal line. If it is a read command, read data is subsequently returned from the target device onto the DQA / DQB signal line.

  FIG. 3 shows the detailed structure of the ROW packet and FIG. 4 shows the COL packet.

  Next, the basic operation when the memory controller accesses the DRDRAM device will be described. First, one page (corresponding to one row address) in the target bank of the target device is activated by the ROW packet. The command issuing means in the memory controller must write the COL packet (WR command) after the tRCD time and write to the position address (column address) in the target page of the target device when the access is write. To be notified. At this time, in the auto precharge mode, it indicates simultaneously that precharge is automatically performed after tRTP (WRA command). Then, write data is sent to DQA / DQB as a packet with an interval of tCWD. FIG. 5 shows a timing chart at the time of writing.

  Similarly, when the access is a read, a COL packet (RD command) is issued after the tRCD time to notify that the read is performed from the position address (column address) in the target page of the target device. At this time, in the auto precharge mode, it indicates that precharge is automatically performed after tRDP (RDA command). The target device sends the read data as a packet to DQA / DQB with an interval of tCAC. Actually, since a propagation delay of one clock cycle or more is allowed from the memory controller to each device on the channel, each device sends read data onto the channel at a timing that takes that into consideration. FIG. 6 shows a timing chart at the time of reading as viewed from the position of the memory controller.

  These read and write operations can be performed in a pipeline of up to four stages as long as the device / bank address / page (row) address do not conflict. FIG. 7 shows a timing chart when reading and writing are performed in the pipeline.

  The above is the case where a closed page policy that opens (activates) or closes (precharges) a page for each access is applied, but when accessing the same page continuously, the page is temporarily stored in one ROW packet. After opening, COL packets are issued continuously as many times as necessary, and the page is closed at the end (open page policy). The bandwidth can be greatly improved. For this purpose, page management means for managing information on pages opened in the memory controller is provided, and the page corresponding to the newly accessed address is already open (page hit) or conflicts (page miss). Bank conflict), and issue a command according to the result.

  FIG. 8 shows a timing chart when the open page policy is applied at the time of reading.

  Since the internal storage part of DRDRAM has the same structure as normal DRAM, a refresh operation is required. The refresh is performed for each page, but an operation instruction is given to each device by a pair of a device address (usually broadcast), a REFA (activate) specifying a bank address, and a REFP (precharge) command by a ROW packet. Each device manages the row address internally.

  The interval between this REFA command and the REFP command for a certain bank address is tRAS, and the interval between the REFA command and the next REFA command is tRC. However, as with read and write accesses, these commands can be issued in a pipeline manner as long as the bank addresses do not conflict, and the refresh overhead can be greatly reduced.

  For this reason, the memory controller has a means for generating a refresh bank address so that the bank addresses of consecutive refresh commands do not conflict. For example, when the refresh bank address generating means has a DRDRAM bank configuration of 32 banks sharing a sense amplifier between adjacent banks, (0, 2, 4, 8, 10, 12, 14, 16, ..., Bank addresses are generated in the order of 30,1,3, .... 29,31).

  FIG. 9 shows a timing chart when the REFA / REFP command is issued in bursts.

  Issuing burst refresh commands is particularly important when performing power management using the NAP mode. DRDRAM has six power modes as shown in FIG. Among these, the low power consumption modes are the NAP mode and the Powerdown mode. Since DRDRAM uses a high frequency clock for the interface part, it consumes a large amount of power during operation.

  Therefore, particularly when there are a large number of devices on the channel, in order to reduce the power consumption of the system, it is necessary to set a device that does not perform access to the low power consumption mode. However, since the Powerdown mode takes too much time to return to the normal mode, the NAP mode that uses a relatively short time to return to the normal mode when an access occurs is used while the system is operating. However, since the NAP mode stops the clock of the interface part, the device cannot be kept in the NAP mode for a long time due to the necessity of maintaining the synchronization, and there is a limitation of, for example, 10 us at the longest. Also, REFA / REFP commands cannot be received when in the NAP state.

Therefore, when using the NAP mode, all devices are returned to the normal mode every 10us, refreshed by the REFA / REFP command, and then the mode is switched to the NAP mode again except for those that were originally in the normal mode. . If refresh is performed on average, the number of refreshes required in 10us is multiple. At this time, the refresh overhead can be reduced by issuing a refresh burst as described above.
JP-A 61-269296

  However, when the above-described open page policy is applied, it may happen that a page existing in a bank to be refreshed is already opened. In that case, the page must first be closed prior to refresh. If three refresh commands are issued and the bank addresses do not conflict with any open page, three refreshes can be issued in bursts as described above. However, if it conflicts with any page, it must first be closed and then a refresh command issued. FIG. 13 shows a conventional flow for performing refresh. First, issue a NAP Exit command to return the device in the NAP state to normal mode. This is done using signals SCK, CMD, SIO and DQA [5: 0]. This takes about 100ns or more. In DQA [5: 0], the device address to be restored from NAP is specified, but here broadcast is specified. In this case, the NAP Exit command is ignored for devices not in the NAP state. Next, the output from the refresh bank address generation means is compared with the bank address of the page currently held by the page management means. If they seem to compete, close the page in advance. For this, the PRER command of the ROW packet is used. Since there can be multiple competing pages, this is done until all competing pages are closed. Next, a REFA command for the bank is issued. Since all devices are refreshed simultaneously by broadcasting, a tRP interval is required between the PRER command and the REFA command.

  Next, the refresh bank address generation means is made to update the bank address. This is repeated for the number of refresh bursts issued.

  FIG. 11 shows a timing chart when one page competes for each of the three refresh commands.

  When the open page policy is applied in this way, there is a problem that a conflicting page has to be closed at the time of refresh, and the refresh overhead increases.

  In order to solve such a problem, in the present invention, a function for sequentially generating bank addresses in advance is added to the refresh bank address generating means in the memory controller prior to issuing a refresh command burst. After issuing the NAP Exit command, these bank addresses are input to the page management unit, and the page management unit compares the bank address of the page that is currently open with the bank address that is sequentially input, and detects a conflict. In this case, the address information of the contention page is output together with the contention detection signal. The command issuing means inputs the contention detection signal, and issues a command for closing the page based on the page address information output in the case of contention. By repeating this for the number of bursts, all pages competing for the bank address of the refresh command issued in burst are closed, so that the refresh command is issued in burst after the NAP Exit is completed. At this time, the refresh bank address generating means generates again from the first refresh bank address.

  Since these page close command and NAP Exit can be performed in parallel, the overhead associated with refresh can be reduced as compared with the conventional case.

  As described above, according to the present invention, it is possible to reduce the overhead when issuing a burst refresh when the open page policy is applied, thereby improving the effective bandwidth of the memory system.

(Embodiment 1)
In order to describe the above-described embodiment of the present invention in more detail, an example of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram for explaining the configuration of an embodiment of a memory controller according to the present invention. In FIG. 1, 101 is a system bus interface circuit, and 102 is a memory interface circuit, which are circuits for interfacing with the outside. Write / read requests to / from the memory are commanded to the memory controller via the system bus 200 and transmitted to the memory via the channel 300. Command issuing means 103 generates a write, read command or refresh command in response to the request, and provides it to the memory interface unit 102. The memory interface unit 102 converts this into a command packet as described above and sends it to the channel 300. 104 is a page management means, which holds address information of the currently opened page, compares it with a new address, determines page hits, misses, bank conflicts, etc., and sends them to the command issuing means. . Reference numeral 105 denotes refresh timing generation means for notifying the command generation means of the timing for refreshing based on a preset time. Reference numeral 106 denotes refresh bank address generation means for sequentially generating addresses such that consecutive bank addresses do not conflict with each other. In addition, the address generation sequence can be restored as necessary. For example, after four bank addresses are generated sequentially, the same four addresses are generated again in order from the first address, and then the next address can be transferred. Reference numerals 107 and 108 denote a write data buffer and a read data buffer, respectively for temporarily storing write and read data and outputting them at a necessary timing.

  Now, assume that there is a write request to addresses A and B and a read request from address C through the system bus 200 in a state where there is no open page. In this embodiment, the address A is assigned to the device address da, the bank address ba, and the row address ra to the column address ca. This is expressed as {da, ba, ra, ca}. Similarly, address B is assigned to {db, bb, rb, cb}, and address C is assigned to {dc, bc, rc, cc}. These addresses A, B, and C exist on different pages that do not conflict with each other. That is, da, db, and dc are different from each other, or even in the same device, ba, bb, and bc are not the same as each other and do not share a sense amplifier. Further, the refresh bank address generation means 106 generates addresses successively in the order of ba + 1, bb and bc-1, and the refresh bank address generation means 106 now outputs the bank address ba + 1.

  Then, when the open page policy is applied, these three pages are opened when these three accesses are completed. At this time, if the refresh timing generation means 105 notifies that the burst refresh period has been reached, then refresh is performed in the order of the bank addresses ba + 1, bb, bc-1, but ba and ba + 1, bc And bc-1 compete with each other, the three pages that are currently open compete with these refresh bank addresses.

  FIG. 14 is a flowchart for refreshing according to an embodiment of the present invention. In the present invention, unlike the flow in the conventional example described above, after starting the NAP Exit first, the process proceeds to the next step without waiting for the end. In the next step, the output of the refresh bank address generation means 106, ie ba + 1, is compared with the bank address of the currently open page held by the page management means 104, ie ba, bb, bc. As a result, it is found that the page having the address A with the bank address ba conflicts, and the page is closed. For this, the PRER command of the ROW packet is used. Since there is no other page competing with the bank address ba + 1, the bank address of the refresh bank address generation means 106 is then updated to become bb. Since this conflicts with a page having an address B whose bank address is bb, the page is closed by a PRER command. Since there are no other pages competing with the bank address bb, the bank address of the refresh bank address generation means 106 is updated to bc-1. Since this conflicts with a page having an address C having a bank address bc, the page is closed by a PRER command.

  If the number of refresh bursts issued is 3, the bank address of the refresh bank address generation means 106 is returned to the initial address, that is, ba + 1.

  Thereafter, since there is no longer any open page that conflicts with refresh, burst refresh is issued to the bank addresses ba + 1, bb, and bc-1 after the NAP Exit is completed.

  As described above, in the present invention, by closing the page that competes with the refresh in advance with the start of the NAP Exit, it is possible to reduce the overhead related to the refresh when the open page policy is applied.

  While the invention has been illustrated and described with respect to specific embodiments, it will be appreciated that other modifications and improvements are possible. For example, in this embodiment, only one set of the refresh bank address generation means is provided, but two sets of the refresh bank address generation means are provided, the generation of an address for comparison with the opened page address, and the address at the time of issuing the refresh command The generation may be performed by individual means.

  In this embodiment, after all the conflicting pages are closed, the output address of the refresh bank address generating means is returned to the start state before the NAP Exit end determination step. Needless to say good things.

  Accordingly, the invention is not intended to be limited to the specific forms shown, but is intended to cover all modifications within the scope of the appended claims which do not depart from the spirit and scope of the invention. Should be understood.

The block diagram which shows the structure of one Embodiment of this invention. The figure explaining the structure of the memory subsystem using RDRAM. The figure which shows the structure of a ROW packet. The figure which shows the structure of a COL packet. The figure which shows the timing of the signal on the channel at the time of write-in operation | movement. The figure which shows the timing of the signal on the channel at the time of read-out operation | movement. The figure explaining the pipeline operation | movement on a channel. The figure explaining the timing of the read-out operation at the time of an open page. The figure explaining the timing in the case of issuing a refresh command burst. The figure explaining the power mode of RDRAM. The figure which shows the timing at the time of the refresh in a prior art example. The figure which shows the timing at the time of the refresh in one Example of this invention. The figure explaining the operation | movement flow at the time of the refresh in a prior art example. The figure explaining the operation | movement flow at the time of the refresh in one Example of this invention.

Explanation of symbols

101 System bus interface circuit
102 Memory interface circuit
103 Command issuing means
104 Page management means
105 Refresh timing generation means
107 Write data buffer
108 Read data buffer
200 system bus
300 channels
400 memory controller
410-440 RDRAM
450 channels
460 Termination terminal
470 clock oscillator

Claims (1)

In response to a write / read request from the outside, if there is no request in response to the write / read request and the request is a write to a plurality of storage devices, the data received from the outside is written to the storage device. In the case where the request is read, the storage device control device outputs data read from the storage device to the outside,
The storage device is a dynamic semiconductor memory,
A function of giving a plurality of instructions to perform a memory holding operation in the dynamic semiconductor memory at a time;
The semiconductor memory is composed of a plurality of parts,
Each of the plurality of parts can take a unique state,
Means for determining in advance whether or not the state in the plurality of portions of the semiconductor memory and the plurality of storage holding operations compete with each other;
In accordance with the result of the determination means, prior to performing the plurality of storage holding operations, an instruction is given to change the state in the plurality of portions of the semiconductor memory so as not to compete with the plurality of storage holding operations. It has a function.

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