JP2006107206A - Semiconductor integrated circuit design method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit design method that can reduce a clock skew by deterring the influence of variations such as variations in transistor characteristics. <P>SOLUTION: According to cell placement information, a plurality of flip-flops connected to the same clock net are divided into first groups of a circuit scale and shape in which a clock skew can be expected to converge at a predetermined threshold or lower. Grouping buffers for driving FFs are added to the groups respectively to generate first clock trees. Delay elements are inserted before the grouping buffers and hard macros respectively. Signal connections are examined among the first groups and others. First groups, or first groups and hard macros are grouped in descending order of signal connection degree into second groups. Relay buffers for driving a cell supplying a clock are added before the second groups to generate a second clock tree between a clock source of the clock net and the delay elements of the first groups. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit design method, and more particularly to a clock tree generation method for a large-scale semiconductor integrated circuit such as an ASIC (Application Specified Integrated Circuit) or a system LSI (Large Scale Integration).

  With the progress of process miniaturization, semiconductor integrated circuits have become possible to realize very large-scale products. In addition, the performance of the automatic placement and routing tool used for designing the layout of a semiconductor integrated circuit has been dramatically improved, and a larger scale circuit can be handled. Therefore, it is becoming more important to establish a layout design method for a larger scale semiconductor integrated circuit.

  2. Description of the Related Art Recent semiconductor integrated circuits perform a synchronous design in which a hard macro such as a flip-flop (hereinafter abbreviated as FF), an SRAM (Static Random Access Memory), a ROM (Read Only Memory), or the like is synchronized with one clock. A lot is happening. In the synchronous circuit, the difference in propagation delay time of the clock signal from the clock source to each FF, that is, the large clock skew, causes malfunctions and hinders speeding up. In the process of miniaturization, there is a high possibility that a malfunction of the semiconductor integrated circuit occurs due to variations in transistor characteristics in manufacturing. This is even more noticeable especially when the clock line is susceptible to variations. Therefore, in a larger-scale semiconductor integrated circuit, clock line design that takes into account the reduction of clock skew and the prevention of malfunction caused by fluctuations in clock skew due to variations in transistor characteristics becomes very important.

  As a layout method for reducing clock skew, a method of generating a clock tree is generally used. The normal clock tree generation will be described below.

  First, the FF group is divided so that the load capacity, that is, the sum of the input capacity and the wiring capacity of the FF becomes equal, and a relay buffer that drives them is added to each divided cluster. The arrangement position of the relay buffer is determined at the center of gravity of the FF so that the loads from the added relay buffer to each FF are equal. Next, cluster processing and insertion of the relay buffer are repeated for the added relay buffer in the same manner, and a clock path is generated in a tree shape from the clock source to the FF.

  Since the generated clock tree divides the load capacity equally in each layer, if the same cell is used for the relay buffer in the same layer, the delay time of all the relay buffers in that layer will be equal, so the clock skew is reduced. It becomes possible to reduce.

  In order to actually reduce clock skew during layout design, it is considered necessary to take measures such that the load capacitance becomes a desired value after detailed wiring is performed. In addition, when it is difficult to make the load capacity uniform, a method using a relay buffer with a driving capacity corresponding to the load can be considered, but in this case as well, after carrying out detailed wiring, the load capacity and the driving capacity can be balanced. Need to be. If these cannot be realized, in a larger-scale semiconductor integrated circuit, the difference in delay time of each layer is accumulated in the clock line, so that the clock skew eventually becomes large.

  In Patent Document 1, as a first example for reducing clock skew, a basic gate portion is divided and arranged in an FF region and a logic gate region other than FF, and only FFs are regularly arranged in a lattice shape in the FF region. The tree synthesis is applied only to the FF clock line in the FF region. If this method is used, it is easy to divide the FF so that the load is uniform and insert a buffer at the center of gravity, and the clock skew can be reduced without being affected by the circuit scale or chip size. .

  As a second example, in Patent Document 2, a branch point of a binary tree-like clock wiring path is set once, and then a sibling branch point having a common parent branch point is connected, and an RC delay is set on the actual wiring path. A place where balance is achieved is updated as a new parent branch point position, and this is repeated bottom-up to determine a detailed wiring path. In addition, after the buffer cell detailed arrangement position is determined, a detour portion is included in the route in the vicinity of the buffer cell so as to equalize the delay in the same layer. In addition, the cells that are not allowed to pass through the detailed wiring path are changed to positions that do not intersect with the detailed wiring path of the clock. In this method, the delay time is optimized for each layer, the load capacity of the detailed wiring is easily uniformed, and the propagation delay time of the clock line can be reduced and the clock skew can be reduced.

  As a third example, in Patent Document 3, in order to reduce clock skew, at least one dummy element is added to a clock net in addition to a predetermined functional element, and the load capacity and wiring length of each clock net match. Alternatively, the values are close to each other. Since this method also tends to make the load uniform, the clock skew can be reduced.

  In designing a semiconductor integrated circuit in a recent miniaturization process, it is important to consider the influence of variations in transistor characteristics within a chip. The timing analysis considering the variation will be briefly described below.

  FIGS. 6A and 6B are diagrams for explaining timing analysis in a conventional method for designing a semiconductor integrated circuit. In the figure, clocks input from a clock input terminal 64 are input to FF51 and FF61. It is input via the relay buffers 63a to 63d. The clocks input from the clock input terminal 64 are input to the FFs 52 and FF62 through the relay buffers 63a and 63e to 63g. The data of FF51 is input to FF52, and the data of FF61 is input to FF62 via Logic65. T1 is the transmission delay time of the clock path on the data sending side, T2 is the transmission delay time of the data path on the data sending side, and T3 is the transmission delay time of the clock path on the data receiving side.

In FIG. 6A, when the hold time of the FF 52 is verified by a normal timing verification method, when the hold time of the input pin D of the FF 52 is H, the hold time margin at the input pin D of the FF 52 is
Hold time margin = T1 + T2-T3-H (Formula 1)
It is expressed. If the hold time margin ≧ 0, no malfunction occurs.

In the timing analysis considering the variation in transistor characteristics (hereinafter referred to as on-chip variation), the hold time margin 'of the FF 52 is
Hold time margin '= (T1 + T2) * [coefficient 1] -T3 * [coefficient 2] -H (Formula 2)
It is expressed. Here, the coefficient 1 is set to 1.00 and the coefficient 2 is set to 1.10 so that the propagation delay times of the clock line and the data path are varied. In this case, 10% is weighted. If the hold time margin '≧ 0, no malfunction occurs.

Next, in FIG. 6B, the setup margin of the FF 62 is the same as that in FIG. 6A using the same reference symbol, the clock cycle is TP, and the setup time of the FF 62 is S
Setup margin = TP + T3- (T1 + T2) -S (Formula 3)
It is expressed. If the setup margin ≧ 0, no malfunction occurs.

In addition, the setup margin of FF62 in the on-chip fluctuation analysis is
Setup margin '= TP + T3 * [coefficient 4]-(T1 + T2) * [coefficient 3] -S (Formula 4)
It is expressed. Here, the coefficient 3 is set to 1.10 and the coefficient 4 is set to 1.00, and the propagation delay time of the clock line and the data path is varied. In this case, 10% is weighted. If the setup margin '≧ 0, no malfunction occurs.

As can be seen from Equations 2 and 4, the longer the distance from the clock line branch point to the clock input terminal of the FF that transmits and receives data, the larger the values of T1 and T3. Any of the setup margins will be disadvantageous. Therefore, it is considered that reducing the propagation delay time of the clock signal is effective as a countermeasure for variation. If the circuit scale is large and it is difficult to reduce the propagation delay time of the clock signal, set an upper limit on the number of FFs and create a netlist in advance to divide the clock into functional blocks within that range. A way to do this is conceivable.
Japanese Patent No. 2850945 Japanese Patent No. 2695078 JP-A-5-206414

  However, in the normal clock tree generation as described above, the larger the circuit scale and the more complicated the cell arrangement area, the more difficult it is to perform cluster processing so that the load is uniform. There is a problem that it becomes impossible to reduce this.

  Further, according to the method described in Patent Document 1 regarding clock skew reduction, FFs can only be arranged in a grid in a predetermined area, and logic cells other than FFs can be arranged only in another dedicated area. Therefore, the distance between the FF and the logic cell is increased, and the delay of the data signal of the FF is increased. For this reason, it is considered that the timing constraint may not be satisfied.

  Further, since signals between FFs and signals between FFs and logic cells are gathered in the FF region, there is a possibility that wiring congestion may occur, and securing a wiring region for that purpose leads to an increase in chip area. .

  Further, the method disclosed in Patent Document 2 has a problem that wiring congestion may occur because the clock wiring is bypassed in order to equalize the load capacity of each relay buffer.

  Further, as shown in Patent Document 3, if a method of adding a dummy element is used in order to equalize the load capacity of the buffer that drives the clock net, an area for arranging the dummy element is required. In addition, there is a possibility that wiring congestion may occur due to the addition of wiring for connecting the dummy element and the buffer, resulting in an increase in chip area.

  Also, in order to alleviate the effects of variations in transistor characteristics within a chip, in a large-scale semiconductor integrated circuit, a netlist is created in advance so that clocks are divided for each functional block, and then a layout method is used. When automatic placement is actually performed using timing constraints, among FF groups of functional blocks having the same input clock, FFs having a small timing margin with other functional blocks are used to transmit / receive data. It may be placed near the FF of the functional block, and if the FFs in the same functional block with the same input clock are distributed and placed, the clock skew of the functional block may increase, which may be a problem. .

  The present invention has been made to solve the above-described problems, and is a semiconductor that is less susceptible to variations in transistor characteristics, wiring capacitance, wiring resistance, and the like and can reduce clock skew. An object is to provide an integrated circuit design method.

  The method for designing a semiconductor integrated circuit according to the present invention includes a step of setting a threshold value of a clock skew, and a circuit scale and a shape estimated that the clock skew converges below the set threshold value based on cell arrangement information. The plurality of flip-flops connected to the same clock net are divided into a plurality of first groups, and a grouping buffer is added to the preceding stage of the grouped flip-flops for each first group. A first grouping step, a first clock tree generating step for generating a clock tree between the grouping buffer and the flip-flop, and a delay element inserting step for inserting a delay element in the previous stage of the grouping buffer; , Examining the connection of signals excluding the clock between the first groups, and examining the connection of the signals. Based on the obtained signal connection information, a combination of the plurality of first groups is determined in descending order of the signal connection degree, and a group obtained by the combination is set as a second group in the next hierarchy. , Adding a relay buffer for driving a cell supplying a clock to the second group to the previous stage, and adding the relay buffer to the second group and the preceding stage for the added relay buffer Is repeated, and a second clock tree generation step of generating a clock tree between the clock source of the clock net and the delay element of the first group is provided.

  In the semiconductor integrated circuit design method, the second clock tree generation step includes the hierarchical group corresponding to the degree of signal connection based on signal connection information excluding the clock between the first groups. A layer number setting step that considers signal connection and sets the number of relay buffer stages to be added by adding a relay buffer having the number of stages set by the layer number setting step according to the degree of signal connection. Based on the arrangement information of the relay buffer added to the lower layer group, the second clock is set so that the clock skew between the clock source of the clock net and the relay buffer added to the lowermost group is minimized. A clock tree is generated.

  In the semiconductor integrated circuit design method, the hierarchy corresponding to the degree of signal connection based on signal connection information excluding the clock between the first groups in the step of generating the second clock tree. In target grouping, the grouping target is limited to adjacent groups in the next higher hierarchy.

  The semiconductor integrated circuit design method further includes a step of examining a timing margin of a signal excluding the clock between the first groups, and based on timing margin information obtained by the step of examining the timing margin, A combination of a plurality of the first groups is determined in ascending order of timing margin, and a group obtained by the combination is set as a second group in the next hierarchy.

  Further, in the semiconductor integrated circuit design method, in the first grouping step, the signal connection and timing margin excluding the clock between the flip-flops are examined, and based on the signal connection information and timing margin information, The first group is determined so that flip-flops with many signal connections and flip-flops with a small timing margin are in the same group.

  In the semiconductor integrated circuit design method, the number of clock tree buffers generated between the grouping buffer and the flip-flop is set to be within a predetermined range, and the clock source of the clock net is used. A stage number setting step for setting the total number of cell stages up to all flip-flops to be within a predetermined range is provided.

  In the semiconductor integrated circuit design method, a part of the flip-flop is replaced with a circuit element.

  In the semiconductor integrated circuit design method, the circuit element is a latch or a hard macro.

  In the semiconductor integrated circuit design method, the circuit elements are singly formed into a first group.

  In the semiconductor integrated circuit design method, when the circuit element includes a hard macro and a flip-flop or a latch exists in the hard macro, from the clock input terminal of the hard macro to the flip-flop or latch in the hard macro The propagation delay time and the number of buffer stages are identified.

  The semiconductor integrated circuit design method may further include a step of setting a limit value of a load capacity of the relay buffer in the second clock tree generation step.

  In the semiconductor integrated circuit design method, the flip-flop group constituting one scan chain is limited to the flip-flops included in the first group, or the flip-flop constituting one scan chain. A scan chain connection changing step for continuously connecting all the flip-flops in the first group and changing the connection so that the same first group does not pass a plurality of times when the group extends over a plurality of groups. In the first group, when the connection order of the flip-flops is changed based on the cell arrangement information so that the wiring length of the scan chain is shortened, the number of clock tree stages from the clock branch point to the flip-flops is For flip-flops that are less than or equal to the preset value, A scan chain optimization process for determining the connection order as continue, in which as and a.

  According to the present invention, based on the cell arrangement information, the flip-flops connected to the same clock net are assigned to the first group of circuit scale and shape that can be estimated that the clock skew converges to a predetermined threshold value or less. It is divided. Therefore, it is possible to increase the possibility that the divided first group can be finally suppressed to the target clock skew. In addition, a grouping buffer that drives FF is added for each group, and a delay element is inserted before the grouping buffer, so the clock skew from the clock source to all FFs is the delay value of the added delay element. There is an effect that can be reduced by adjusting.

  Further, according to the present invention, when generating a clock tree between the clock source and the delay element, the degree of connection of signals excluding the clock is checked between the first groups, and the order of the degree of signal connection is as follows. Combine multiple groups and make the resulting group the second group in the next layer, add a relay buffer to the previous stage of the group, and then repeat the same grouping process for the added relay buffer As a result, for the FFs between the groups having signal connections, the distance from the branch point of the clock signal to the FFs can be kept short in the second clock tree. Therefore, there is an effect that signals between groups with a high degree of signal connection can be made less susceptible to variations in transistor characteristics.

  Further, according to the present invention, since the range of the number of stages of the relay buffer constituting the clock tree is set in the first and second clock tree generation, the number of stages of the buffer from the clock source to all the FFs is predetermined. Within the limits, each propagation delay time can be relatively close. Therefore, when adjusting the propagation delay time to all FFs, the delay value of each delay element can be adjusted even if a close value is set, and the effect of being less susceptible to variations in wiring capacitance and wiring resistance. There is.

  Also, according to the present invention, the second clock tree generation step is based on the hierarchical grouping according to the degree of signal connection based on connection information of signals excluding the clocks between the first groups. A step of setting the number of layers of the relay buffer to be added, and a step of setting the number of layers in consideration of signal connection, adding a relay buffer of the number of steps set by the step of setting the number of layers according to the degree of connection of the signal, Based on the arrangement information of the relay buffer added to the group, the clock skew between the clock source of the clock net and the relay buffer added to the lowermost group is minimized by the conventional clock tree generation method. As described above, since the second clock tree is generated, the second clock tree in the previous period does not have an unnecessarily complicated configuration. It can be controlled to.

  Further, according to the present invention, in the second clock tree generation step, the second clock tree can be simplified by limiting the second grouping target to adjacent groups in the next higher hierarchy. It becomes possible to control so that it becomes a simple structure.

  Further, according to the present invention, when generating a clock tree between a clock source and a delay element, a timing margin of a signal excluding a clock is checked between the first groups, and a plurality of timing margins are arranged in ascending order. The first group is grouped, and the group obtained by this is set as the second group in the next hierarchy, the relay buffer is added to the previous stage of the group, and the same grouping process is repeatedly performed. For FFs between small groups, the distance from the branch point of the clock signal to the FFs can be kept short in the second clock tree. Therefore, there is an effect that signals between groups having a small timing margin can be made less susceptible to variations in transistor characteristics.

  Further, according to the present invention, in the first grouping step, the signal connection and timing margin excluding the clock between the FFs are examined, and the signal connection is determined based on the connection information of the signal and the timing margin information. Since the first group is determined so that many FF groups and FF groups with a small timing margin belong to the same group, the same FF groups that are likely to cause timing constraint violations due to variations in transistor characteristics. There is a high possibility that the first grouping is performed so as to exist in the first group. Therefore, these FF groups have an effect that the distance from the clock branch point to the cell becomes shorter, so that the FF group is less affected by variations in transistor characteristics.

  In addition, according to the present invention, a part of the plurality of FFs can be replaced with circuit elements such as latches and hard macros, so that the present invention can be applied to a system LSI including the previous circuit elements.

  According to the present invention, when the circuit element includes a hard macro and an FF or a latch exists in the hard macro, a propagation delay time from the clock input terminal of the hard macro to the FF or latch in the hard macro Therefore, even in a complicated system LSI including a hard macro, there is an effect that the clock lines from the clock source to all the cells can be configured symmetrically.

  According to the present invention, the FF group constituting one scan chain is limited to the FFs included in one first group, or a plurality of flip-flop groups constituting one scan chain are provided. When all the FFs in the first group are connected continuously and the scan chain is changed in connection so as not to pass through the same first group multiple times, When the FF connection order is changed so that the scan chain wiring length is shortened based on the cell arrangement information, the number of clock tree stages from the clock branch point to the FF is less than or equal to a preset value. In order to perform scan chain optimization that determines the connection order so that connections are preferentially connected, it is affected by variations in transistor characteristics, There is an effect that the timing constraint violation was easily scan chain generator for hold margin can be changed in less susceptible configure the influence of variation in transistor characteristics.

(Embodiment 1)
FIG. 1 is a flowchart showing a semiconductor integrated circuit design method according to Embodiment 1 of the present invention.
FIG. 3 is a diagram for explaining a state before grouping of netlists for explaining the semiconductor integrated circuit design method according to the first embodiment of the present invention. A clock inputted from clock input terminal 9 is a memory. An example of a semiconductor integrated circuit input to the hard macros 10 to 15 and the plurality of FFs 20 is shown. In the first embodiment, a case where a plurality of FFs 20 are arranged will be described. However, the present invention can also be applied to a case where a latch is arranged instead of an FF.

  4 (a) and 4 (b) are diagrams showing a first grouping of circuits for explaining the semiconductor integrated circuit design method according to the first embodiment of the present invention. The same reference numerals denote the same or corresponding parts.

  FIG. 5 is a diagram showing a second grouping of circuits for explaining the semiconductor integrated circuit design method according to the first embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 3 denote the same or corresponding parts. Is shown.

  FIG. 2 is a diagram showing the placement positions of the hard macros determined by the floor plan information for explaining the semiconductor integrated circuit design method according to the first embodiment of the present invention. In the figure, the same reference numerals as those in FIG. The same or corresponding parts are shown.

  Hereinafter, the semiconductor integrated circuit design method according to the first embodiment of the present invention will be described with reference to FIGS. 1, 2, 3, 4 (a), 4 (b), and 5. First, in the first step S101, information necessary for layout design such as a net list of a semiconductor integrated circuit and timing constraints, physical library information, floor plan information and the like as shown in FIG. 3 is input to an automatic placement and routing tool of the semiconductor integrated circuit. To do. In step S102, scan chain connection information that is not necessary for the automatic placement processing in the next step S103 is deleted.

  Next, in step S103, automatic layout is performed by the layout design apparatus using the input netlist and timing constraints. When the floor plan information is input in step S101, as shown in FIG. 2, since the arrangement positions of the hard macros 10 to 15 are determined, only the arrangement of the logic cells is executed here.

  In step S104, the target value of the clock tree skew generated in step S107 and the maximum and minimum values of the number of tree stages are set. The number of tree stages may be set uniquely. In step S106, based on the arrangement information of the FF 20 arranged in step S103, the FF group is divided into a plurality of circuit sizes and shapes estimated to converge to the target value of the clock skew set in step S102. Let them be the first group. In the first embodiment, the FF group is divided into first groups 1 to 8 as shown in FIG. In order to reduce the clock skew, it is considered that the arrangement area has a shape that is nearly symmetrical in the vertical and horizontal directions. However, depending on the created floor plan, it may not be possible to do so. Here, it is assumed that data on a shape that can easily reduce clock skew is prepared in advance, and the shape is determined with reference to the data. Further, an upper limit value of the number of FFs of the group to be created, a prohibited shape, and the like may be set in advance.

  In step S106, the netlist is changed so that the first grouping buffer 21 is added to the preceding stage of the FF 20 of each determined group. In step S107, for each of the determined groups 1 to 8, the conventional technique is used. A plurality of relay buffers 23 are added by the normal clock tree method as described to generate a tree shown in FIG. Then, the propagation delay time of the clock signal is provisionally calculated for the generated clock line using the wiring capacity and the wiring resistance obtained from the Manhattan length or the result of the schematic wiring. In step S108, it is checked whether the clock skew of each group 1 to 8 has converged to the target value from the result of the provisional calculation. If the clock skew of all the groups 1 to 8 is less than the target value, the process proceeds to step S109. If there is something exceeding the target value, the process proceeds to step S104. In step S109, as shown in FIG. 4A, the delay element 22 is inserted in the previous stage of the first grouping buffer, and the process proceeds to step S110.

  As described above, first, based on the arrangement information, the first grouping process, the clock tree generation of the first groups 1 to 8 and the clock delay calculation are performed until the clock skew becomes below the target value, and the clock skew is calculated. Judgment is made. When the group is determined so that the clock skew is equal to or less than the target value, the delay element 22 is inserted. Thus far, the generation of the first clock tree has been described.

  Next, the second clock tree generation will be described. In step S110, signal connections and timing margins other than the clock signals between the created first groups and between the first group and the hard macro are examined.

  In step S111, a limit value of the number of buffer stages in the tree in the second clock tree generation in step S113 is set. At this time, in addition to the limit value, the total number of cell stages from the clock source of the clock net to all flip-flops and hard macros may be set to be within a predetermined range.

  In step S112, the number of hierarchies is set in consideration of signal connection and timing margin between the first groups 1 to 8 and the hard macros 10 to 15. For example, a combination of a plurality of first groups 1 to 8 and the hard macros 10 to 15 is determined in ascending order of timing margin, and a group obtained by the combination is set as a second group in the next hierarchy. Similarly, the grouping process is executed hierarchically, and the number of stages for adding the relay buffer is set.

  In step S113, as shown in FIG. 5, based on the information on the degree of signal connection checked in step S110, the plurality of first groups 1 to 8 and hard macros 10 to 15 are arranged in descending order of signal connection. The combination is determined so as to be put together, and is set as the second group in the next hierarchy. Alternatively, a combination of the plurality of first groups 1 to 8 and the hard macros 10 to 15 is determined in ascending order of timing margin, and a group obtained by the combination is determined as a second group in the next hierarchy. You may make it do. Note that this grouping target may be limited to the first groups 1 to 8 or the hard macros 10 to 15 that are adjacent to each other in the next higher hierarchy. Next, the relay buffer 24 for driving the cell supplying the clock is added to the preceding stage. The added relay buffer 24 is arranged near the center of gravity of the cell to be driven so that the load is evenly applied to the cell to be driven. When determining the second group, a limit value of the load capacity of the relay buffer is set in advance, and the number of groups to be combined is determined so that the load of the relay buffer 24 to be driven does not increase. . Furthermore, the arrangement position of the delay element may be moved as necessary so that the clock path is shortened. Thereafter, the same grouping process is repeated for the added relay buffer 24 to generate a second clock tree between the clock source and the delay element.

  Here, in consideration of the degree of signal connection between the groups, the number of stages for performing the grouping process in a hierarchical manner is set in step S112. Therefore, after the grouping process for the set number of hierarchies is performed, the second clock tree is further added. When it is necessary to add a relay buffer, the processing is performed by the normal clock tree method shown in the prior art.

  Next, in step S114, it is determined whether the number of stages of the generated clock tree satisfies the set limit value. If it is within the limit range, the process proceeds to step S115, and if it is out of the range, the process proceeds to step S111.

  In step S115, the scan chain deleted in step S102 is reconnected. At this time, the FF group constituting one scan chain is limited to the FFs included in one first group, or the FF group constituting one scan chain spans a plurality of first groups. In this case, all the FFs in the first group are connected continuously, and the scan chain is changed in connection so that it does not pass through the same first group multiple times. The connection order of the FFs is changed so that the wiring length of the scan chain is shortened based on the arrangement information.

  FIG. 7A shows the connection before the scan chain optimization, and FIG. 7B shows the connection after the scan chain optimization. 7A and 7B, the same reference numerals as those in FIG. 2 denote the same or corresponding parts, SI1 to SI6 denote scan input terminals, and SO1 to SO6 denote scan output terminals. F indicates a flip-flop. In FIG. 7B, the connection change is performed so that all the FFs belonging to the same first group are continuously connected. Further, in the first group, when the FF connection order is changed so that the scan chain wiring length is shortened based on the cell arrangement information, the number of clock tree stages from the clock branch point to the FF is previously set in step S115. For the FFs below the set value, the scan order may be optimized by determining the connection order so that the FFs are successively connected preferentially.

  In step S116, detailed wiring of the first clock tree is executed, in step S117, detailed wiring of the second clock tree is executed, and in step S118, detailed wiring of signals other than the clock is executed.

  In step S119, the delay calculation of the layout data completed up to the detailed wiring is executed to obtain the propagation delay time of the clock signal from the clock source to all the cells, and the average value is the same for each first group and each hard macro. As described above, the delay elements added to the first stage and the preceding stage of the hard macro are adjusted. For example, the delay element may be the same cell as the relay buffer added to the clock line arranged in a line, or a cell with a small delay value is created so that the delay time can be easily adjusted, and the delay adjustment cells are arranged. It may be configured. When step S119 is completed, all the processes are completed.

  In the present invention, when an FF or latch exists in the hard macro, the clock tree is identified by identifying the propagation delay time from the hard macro clock input terminal to the FF or latch in the hard macro and the number of buffer stages. Consider these in the generation.

  As described above, in the first embodiment, based on the cell arrangement information, the FFs connected to the same clock net can be estimated to have the circuit scale and shape that can be estimated that the clock skew converges to a predetermined threshold value or less. It is divided into one group. Therefore, it is possible to increase the possibility that the divided first group can be finally suppressed to the target clock skew. In addition, a grouping buffer that drives FF is added for each group, and a delay element is inserted in front of the grouping buffer and hard macro, so clock skew from the clock source to all FFs and hard macro is added. It is possible to reduce by adjusting the delay value of the delay element.

  Further, when generating a clock tree between delay elements from the clock source, the degree of connection of signals other than the clock or the timing margin between the first group and between the first group and the hard macro is examined, A plurality of groups and hard macros are grouped together in descending order of the degree of connection or in ascending order of timing margin to form a second group in the next hierarchy, and a relay buffer is added in the preceding stage of the group. Thereafter, the same grouping process is repeatedly performed on the added relay buffer. Therefore, for the FF and the hard macro between the groups having a large signal connection or a small timing margin, the FF, The distance to a cell such as a hard macro is kept short in the second clock tree. Therefore, there is an effect that the structure can be hardly affected by variations in transistor characteristics.

  In addition, in the first and second clock tree generation, since the range of the number of stages of the relay buffer constituting the clock tree is set, the number of buffer stages from the clock source to all the cells such as FFs and hard macros has a predetermined limit. The propagation delay time tends to be relatively close. Therefore, when adjusting the propagation delay time to all cells, it is possible to adjust the delay value of each delay element to a value close to that of the delay element, making it difficult to be affected by variations in wiring capacitance and wiring resistance. There is an effect that can.

  Further, when the FF group constituting one scan chain is limited to the FFs included in one first group, or when the FF group constituting one scan chain spans a plurality of first groups Since all the FFs in the first group are connected in succession and the scan chain is changed so as not to pass through the same first group multiple times, the cells from the clock branch point in the scan chain Thus, the scan chain is prevented from being affected by variations in wiring capacitance and wiring resistance.

(Embodiment 2)
FIG. 8 is a flowchart showing a semiconductor integrated circuit design method according to the second embodiment of the present invention. The difference from the first embodiment is that the signal connection other than the clock between the FFs and the timing margin are examined in step S105, and the first grouping is performed based on the information in step S106a. is there. 8, the same reference numerals as those in FIG. 1 denote the same or corresponding parts.

  FIGS. 9 and 10 are diagrams showing processing for performing the first grouping based on the information obtained in step S105 in step S106a of FIG. 8, and the same reference numerals as those in FIG. The part to do is shown. The FF groups 101 to 107 are created by collecting FFs having many signal connections. Areas 201 to 203 and area 205 are areas with a large timing margin. An area 204 is an area with a small timing margin.

  The semiconductor integrated circuit design method according to the second embodiment of the present invention will be described below with reference to FIGS. In addition, in process S101-S103 and the process after process S107, since it processes similarly to Embodiment 1, description here is abbreviate | omitted.

  In step S105, first, the timing margin for the connection between the FFs in the netlist input in step S101 or between the FF and the hard macro and the timing constraint is checked. Next, in step S106a, based on the information obtained in step S105, FF divided regions are determined so that FFs with many connections or FFs with a small timing margin belong to the same first group as much as possible, and As in the first embodiment, the FF group is adjusted to the circuit scale and shape estimated to converge to the target value of the clock skew set in step S102 based on the arrangement information of the FF 20 arranged in step S103. The first grouping is performed. For example, in FIG. 9, FFs with many connections are grouped into FF groups 101 to 107 based on connection information between FFs obtained in step S <b> 105. In the second embodiment, on the basis of the area of the FF groups 101 to 107, a clock skew is set to a predetermined value by combining an FF with a large timing margin considered to be hardly affected by on-chip fluctuation with another FF group. The divided areas of the FFs are adjusted as follows, and the first groups 1 to 8 are determined as shown in FIG. The first group 2 in FIG. 10 is created by combining the FF group 102 in FIG. 9 and the area 201 including the FFs having a large timing margin in the FF group 101. Similarly, the first group 3 in FIG. 9 is created from the FF group 103 in FIG. 9 and the region 202 including the FF having a large timing margin in the FF group 101. The first group 4 in FIG. 10 includes the FF group 104 in FIG. 106 are created respectively from the areas 203 including FFs having a large timing margin in 106. Further, the first group 1 in FIG. 10 is an area obtained by removing the areas 201 and 202 from the FF group 101 in FIG. The first groups 5 and 7 are created by dividing the FF group 105 of FIG. 10 into a region 204 with a small timing margin and a region 205 with a large timing margin.

  As described above, in the second embodiment, the timing margin with respect to the connection and the timing constraint between the FFs in the input netlist or between the FF and the hard macro is checked, and the FFs with many connections are obtained based on the obtained information. Alternatively, the first grouping is performed by adjusting the division region of the FFs so that the FFs having a small timing margin belong to the same first group. Therefore, the FF of a data path with many connections or a small timing margin has an effect of suppressing the occurrence of timing constraint violation due to the influence of on-chip variation because the distance from the clock branch point to the cell is shortened.

  The semiconductor integrated circuit design method according to the present invention is capable of generating a clock tree having a small clock skew and being hardly affected by variations in transistor characteristics, and is capable of generating a large-scale semiconductor integrated circuit such as an ASIC or a system LSI. This is useful as a circuit layout design method.

3 is a flowchart of a semiconductor integrated circuit design method according to the first embodiment of the present invention. 2 is a floor plan of a semiconductor integrated circuit for explaining the semiconductor integrated circuit design method according to the first embodiment of the present invention; It is a figure which shows the structure before grouping of the circuits for demonstrating the semiconductor integrated circuit design method which concerns on Embodiment 1 of this invention. It is a figure which shows the 1st grouping of the circuit for demonstrating the semiconductor integrated circuit design method which concerns on Embodiment 1 of this invention. It is a figure which shows the 1st grouping of the circuit for demonstrating the semiconductor integrated circuit design method which concerns on Embodiment 1 of this invention. It is a figure which shows the 2nd grouping of a circuit for demonstrating the semiconductor integrated circuit design method which concerns on Embodiment 1 of this invention. It is a figure for demonstrating the conventional semiconductor integrated circuit design method. It is a figure for demonstrating the conventional semiconductor integrated circuit design method. It is a figure which shows the connection of a scan chain for demonstrating the semiconductor integrated circuit design method which concerns on Embodiment 1 of this invention. It is a figure which shows the connection of a scan chain for demonstrating the semiconductor integrated circuit design method which concerns on Embodiment 1 of this invention. It is a flowchart of the semiconductor integrated circuit design method which concerns on Embodiment 2 of this invention. It is a figure which shows the structure before grouping of the circuit for demonstrating the semiconductor integrated circuit design method which concerns on Embodiment 2 of this invention. It is a figure which shows the 1st grouping of the circuit for demonstrating the semiconductor integrated circuit design method which concerns on Embodiment 2 of this invention.

Explanation of symbols

1-8 First group 9, 64 Clock input terminals 10-15 Hard macro 20 Flip-flop 21 Relay buffer 22 Delay element 23 Relay buffer 24 Relay buffers SI0-SI6 Scan input terminals SO0-SO6 Scan output terminals

Claims (12)

Setting a clock skew threshold;
Based on the input arrangement information, a plurality of flip-flops connected to the same clock net are connected to a plurality of flip-flops so that the clock scale has a circuit scale and shape estimated to converge below the set threshold value. A first grouping step of dividing the group into one group and adding a grouping buffer to the preceding stage of the grouped flip-flops for each of the first groups;
A first clock tree generation step of generating a clock tree between the grouping buffer and the flip-flop;
A delay element insertion step of inserting a delay element in a preceding stage of the grouping buffer;
Examining the connection of signals excluding the clock between the first groups;
Based on the signal connection information obtained in the step of examining the signal connection, a combination of the plurality of first groups is determined in descending order of the degree of signal connection, and the group obtained by the combination is determined as follows. And a relay buffer that drives a cell that supplies a clock to the second group is added to the previous stage, and the second grouping and its And a second clock tree generation step of generating a clock tree between the clock source of the clock net and the delay element of the first group by repeatedly performing the process of adding the relay buffer to the previous stage. A method for designing a semiconductor integrated circuit. The second clock tree generation step includes:
Based on connection information of signals excluding the clock between the first groups, setting the number of relay buffers to be added by the hierarchical grouping according to the degree of signal connection, setting the number of layers considering signal connection With a process,
Add a relay buffer of the number of stages set by the hierarchy number setting step according to the degree of connection of the signal,
Based on the arrangement information of the relay buffer added to the lowest layer group, the second clock signal skew between the clock source of the clock net and the relay buffer added to the lowest layer group is minimized. 2. The semiconductor integrated circuit design method according to claim 1, wherein the clock tree is generated. In the hierarchical grouping according to the degree of connection of the signals, based on connection information of signals excluding the clock between the first groups in the step of generating the second clock tree,
3. The method of designing a semiconductor integrated circuit according to claim 2, wherein the grouping target is limited to a group adjacent in the hierarchy one level higher. Examining the timing margin of signals excluding the clock between the first groups,
Based on the timing margin information obtained by the step of examining the timing margin, the combination of the plurality of first groups is determined in ascending order of the timing margin, and the group obtained by these combinations is determined as 2. The semiconductor integrated circuit design method according to claim 1, wherein the second group in the hierarchy is used.   In the first grouping step, the connection of the signals other than the clocks between the flip-flops and the timing margin are examined, and the flip-flops having a large number of signal connections and the timing margin based on the connection information of the signals and the timing margin information 2. The semiconductor integrated circuit design method according to claim 1, wherein the first group is determined so that the flip-flops having a small degree are in the same group.   The number of stages of the clock tree buffer generated between the grouping buffer and the flip-flop is set to be within a predetermined range, and the total number of stages of cells from the clock source of the clock net to all flip-flops 6. The method of designing a semiconductor integrated circuit according to claim 1, further comprising a step number setting step for setting the step number so as to be within a predetermined range.   2. The semiconductor integrated circuit design method according to claim 1, wherein a part of the plurality of flip-flops is replaced with a circuit element.   8. The method of designing a semiconductor integrated circuit according to claim 7, wherein the circuit element is a latch or a hard macro.   8. The method of designing a semiconductor integrated circuit according to claim 7, wherein the circuit elements are independently made into the first group. Including a hard macro as the circuit element,
8. A propagation delay time from a clock input terminal of a hard macro to a flip-flop or a latch in the hard macro and the number of buffer stages are identified when a flip-flop or a latch exists in the hard macro. 10. A method for designing a semiconductor integrated circuit according to any one of items 9 to 9.   2. The method for designing a semiconductor integrated circuit according to claim 1, further comprising a step of setting a limit value of a load capacity of the relay buffer in the second clock tree generation step. When flip-flop groups constituting one scan chain are limited to flip-flops included in one first group, or when flip-flop groups constituting one scan chain span a plurality of groups A scan chain connection changing step of continuously connecting all the flip-flops in the first group and changing the connection so as not to pass through the same first group multiple times;
In the first group, when the connection order of the flip-flops is changed based on the input arrangement information so that the wiring length of the scan chain is shortened, the number of clock tree stages from the clock branch point to the flip-flops is 2. The semiconductor integrated circuit according to claim 1, further comprising: a scan chain optimizing step for determining a connection order so that flip-flops having a predetermined value or less are connected preferentially continuously. Design method.

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