JP2006107022A - Inter-module communication method and device by hierarchized ring - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To maintain the high speed access of a module to be accessed at a high speed even when the number of modules is large in a system where a plurality of modules are connected like a ring. <P>SOLUTION: When the number of modules is large, those modules are classified into the modules to be accessed at a high speed and the modules to be accessed at a low speed, and the ring connection is divided into a plurality of hierarchies, and a slave module to be accessed at a high speed is connected to a first ring, and a slave module to be accessed at a low speed is connected to a second ring so that when the slave module connected to the first ring is accessed, the slave module can be accessed at a high speed regardless of the number of the modules connected to the other ring. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to communication between modules in an LSI of an information processing apparatus, and more particularly to communication in which each module is connected on a ring.

  Conventionally, there has been a technique for performing communication by connecting a plurality of modules in a ring shape (see, for example, Patent Document 1). In such a method, an instruction sent to a module is analyzed by the module, and when it is determined that the instruction is for itself, the instruction is executed and the instruction is transferred to the next module. If it is determined that it is not a command for itself, the command is transferred to the next module without performing the command. Here, in the case of an instruction for itself, there are techniques that do not transfer the instruction to the next module, and techniques that process and transfer the instruction.

  However, in such a method, it takes a certain amount of processing time from receiving an instruction to determining the instruction and transferring it to the next module, and it often takes several to tens of cycles.

In such a system connected in a ring shape, when the number of modules increases, an instruction transfer time increases accordingly, and the time is greatly influenced by the processing time required for each module.
JP-A-6-77973

  However, in general, there are both modules that can be accessed at a high speed and modules that can be accessed at a low speed in a system. Modules that may be accessed are accessed at the same time, and the time is proportional to the number of modules in the ring, and becomes longer as the number of modules increases.

  Therefore, an object of the present invention is to make it possible to maintain high-speed access to a module that is desired to be accessed at high speed even when the number of modules increases.

In the invention according to the present application, there is one main master module in the LSI, there are a plurality of slave modules accessed from the master module, and the plurality of slave modules are included in a ring shape including the master module. In a system having a first ring to be connected, a second ring for connecting other slave modules in a ring shape, and a layered ring in which the first ring and the second ring are connected by a bridge, Every module connected in the ring has a master interface that issues transactions to the next connected module and a slave interface that receives transactions from the previously connected module, and the master module is another module connected to the ring Access to A means for issuing a command transaction from the master interface to the bridge, the bridge receiving a command transaction from a previously connected module in the first ring, and a next connected module in the first ring A master interface that issues transactions to the next connected module in the second ring, and a slave interface that receives command transactions from previously connected modules in the second ring. Means for issuing a command transaction received from the first ring to the second ring as necessary, and a transaction received from the second ring. Has a means for issuing a first ring according to necessity, other modules that the slave has a means for processing according to the command transactions received from the slave interface,
The slave module has means for forwarding the command transaction received from the slave interface from the master interface to the next connected module, and is included in the transaction to determine whether the command transaction is an access to itself. Means for decoding the address to be transmitted in parallel with forwarding the transaction, and means for issuing a return transaction from the master interface when it is determined that the command transaction is an access to itself. The command transaction received from the master interface is forwarded to the next connected module in the first ring. Means for decoding the address included in the transaction in parallel with forwarding the transaction in order to determine whether the command transaction is an access to itself, and the command transaction accessing the self If it is determined that the command transaction is issued from the master interface to the second ring, and when a return transaction is received from a previously connected module in the second ring, the first ring Next has a means to forward from the master interface to the connected module,
The slave module and the bridge have a buffer for holding the received transaction without forwarding when the next connected module is not ready to receive a transaction, and the next connected module Has a means to send as soon as it is ready to receive transactions,
The bridge has a slave interface in which the master interface of the bridge is the starting point, the end point of the second ring in which the modules are connected in order is finally connected, and the command transaction issued from the bridge finally returns, And a means for determining an error when a return transaction cannot be received for a certain period of time.

  As described above, according to the present invention, even if the number of slave modules increases, the ring connection is divided into a plurality of layers by classifying them into those that access at high speed and those that access at low speed. By connecting a slave module that accesses the ring at high speed to the second ring and a slave module that accesses at low speed to the second ring, the slave module connected to the first ring is accessed at high speed. It is possible.

<Embodiment 1>
In order to describe the above-described embodiment of the present invention in more detail, an example of the present invention will be described in detail with reference to the drawings.

  FIG. 2 shows a diagram in which a portion of the first register access ring 111 is extracted from the system of FIG. Here, it is assumed that the second register access ring 121 does not exist.

  First, the communication method will be described in detail below, focusing on the register access ring, using this figure.

  Reference numeral 400 is equivalent to the ring access interface portion of the system bridge 101 in FIG. 1, and is a master module serving as a master of the first register access ring 111 in this configuration. Reference numerals 401 to 403 are equivalent to ring access interface portions such as modules 0 and 2 and the memory controller 105 in FIG. 1, and are slave modules serving as slaves of the first register access ring 111.

  Each module has a master interface and a slave interface for communication between the modules.

  The master interface of the master module 400 and the slave interface of the slave module 0 401 are connected via a communication path 0. The master interface of the slave module 0 401 and the slave interface of the slave module 1 402 are connected via the communication path 1. The master interface of the slave module 1 402 and the slave interface of the slave module 2 403 are the communication path 2 and the slave module 2. The master interface 403 and the slave interface of the master module 400 are connected via the communication path 3.

  In the ring configured as described above, the direction in which the command / return transaction is transferred is determined, and is transferred only in the direction of the master module 400 → slave module 0 401 → slave module 1 402 → slave module 2 403 → master module 400. Is possible.

Each communication path is composed of the following signals.

Tsp Transaction Start Master I / F> Slave I / F
Rsp Return Start Master I / F> Slave I / F
Tbsyp Transaction Busy Master I / F> Slave I / F
uaddr_midp [5: 0] Upper Address / Master ID Master I / F> Slave I / F
laddr_datap [15: 0] Lower Address / Data Master I / F> Slave I / F
rd_not_wr Read (H) / Write (L) Master I / F> Slave I / F
errorp Error Master I / F> Slave I / F
srdyp Slave Ready Slave I / F> Master I / F

Each signal will be described below.

Tsp transaction Start Master I / F> Slave I / F
The master interface confirms that srdyp from the communicating slave interface is asserted, asserts for one cycle, and starts a command transaction.

The master can start the next transaction after detecting that tbsyp is high. In other words, there is always at least one cycle between transactions.

Rsp Return Start Master I / F> Slave I / F
Signal that initiates a return transaction from the slave module. The slave module asserts this signal when writing is completed or read data is ready, and starts a return transaction. Assert conditions are the same as tsp.

Tbsyp Transaction Busy Master I / F> Slave I / F
Asserted while a command / return transaction is in progress. Since a transaction takes 3 cycles, it is always asserted for 3 cycles. When this signal is deasserted, the communication path is in an idle state.

uaddr_midp [5: 0] Upper Address / Master ID Master I / F> Slave I / F
Multiplex signal of Upper Address and Master ID (MID).

  Upper Address is entered in the 1st beat, and Master ID is entered in the 2nd beat. The third beat is Don't Care.

  Address [23:18] is entered for the upper address of the 1st beat.

  MID [3: 0] is entered in uaddr_midp [3: 0] for the 2nd beat Master ID. The upper 2 bits are Don't Care.

MID has no effect on the sequence. Each slave module simply forwards the MID received from the master interface to the next.

laddr_datap [15: 0] Lower Address / Data Master I / F> Slave I / F
Lower Address and Data multiplex signal.

  The lower address is in the first beat, the 16 bits on the MSB side of the data in the second beat, and the 16 bits on the LSB side of the data in the third beat.

  Address [17: 2] is entered for Lower Address of the 1st beat.

  Data [31:16] is entered for the second beat of data.

Data [15: 0] is entered for the 3rd beat of data.

rd_not_wr Read (H) / Write (L) Master I / F> Slave I / F
Indicates transfer read / write.

Asserted while tbsyp is asserted. The period must not change.
High: Lead
Low: Light

Errorp Error Master I / F> Slave I / F
Notify master module of errors. If an error occurs, the slave module asserts this signal while tbsyp is asserted during a return transaction.

Srdyp Slave Ready Slave I / F> Master I / F
Indicates that the slave interface receiving the transaction is ready to receive a transaction from the master interface sending the transaction. If this signal is asserted, the master interface can start a transaction at any time and the slave interface must accept the transaction.

  When srdyp receives a transaction, it is deasserted once. The slave module decodes the command transaction, and if it hits its own range of addresses, it must continue to deassert srdyp to prevent receipt of the next transaction.

  If no hit is found and the received transaction can be forwarded to the next module, srdyp is asserted to prepare to receive the next transaction.

  Decoding should be completed during the command transaction.

  If there is a hit, issue a return transaction and then assert srdyp again.

  The above signals are common to the communication paths 0 to 3, and the signal names in the respective communication paths are added with numbers 0 to 3 at the end of the signal names, and are as follows.

Communication path 0 signal
tsp0, rsp0, tbsyp0, uaddr_midp0 [5: 0], laddr_datap0 [15: 0], rd_not_wr0, errorp0, srdyp0
Communication path 1 signal
tsp1, rsp1, tbsyp1, uaddr_midp1 [5: 0], laddr_datap1 [15: 0], rd_not_wr1, errorp1, srdyp1
Communication path 2 signal
tsp2, rsp2, tbsyp2, uaddr_midp2 [5: 0], laddr_datap2 [15: 0], rd_not_wr2, errorp2, srdyp2
Communication path 3 signal
tsp3, rsp3, tbsyp3, uaddr_midp3 [5: 0], laddr_datap3 [15: 0], rd_not_wr3, errorp3, srdyp3
Write and read command transactions are issued by the master module, and each slave module forwards it to the next slave module. The slave module forwards to the next slave module regardless of whether the received command transaction is an access to itself, so that the command transaction finally returns to the master module.

  The slave module decodes the address at the same time as forwarding the command transaction, and if it hits its own address, it does not receive the subsequent command transaction and performs a write or read operation on the register managed by itself. .

  When it finishes, the slave module issues a return transaction.

  This return transaction is also forwarded by each subsequent slave module, and finally reaches the master module.

  The slave module that issued the return transaction resumes receiving the command transaction that was temporarily stopped.

  When a master module issues a command transaction, it always expects to receive that command transaction and a return transaction for that command transaction.

  Even when issuing multiple command transactions, the master module should always receive command transactions and return transactions alternately.

  If there is an error in the command transaction address and no slave module has responded, no return transaction is returned to the master module. Thus, the master module can know that there is an error in the command transaction.

  A command transaction is first issued by the master module. The slave module receives it and immediately forwards it to the subsequent slave module. Command transactions can be issued only when tbsyp = 0 and srdyp = 1.

  The command transaction finally reaches the master module.

  The slave module decodes the address at the same time as it forwards the command transaction.

  At the time of writing, write data is sent to the data signal. Not sent when reading.

  Regardless of write / read, the transaction takes 3 beats. The first beat is the address transfer, the second beat is the master ID and data transfer, and the third beat is the data transfer. At the time of reading, the data part is Don't Care.

  The slave module receives the command transaction. If the slave module hits its own address, the slave module temporarily stops receiving subsequent command transactions, and performs a write or read operation on a register managed by the slave module.

  When it finishes, the slave module issues a return transaction. This is always issued both at the time of writing and at the time of reading.

  The return transaction is unconditionally forwarded by each subsequent slave module, and finally reaches the master module. No code is performed at the address of the return transaction.

  The master module determines that the command has been completed normally by receiving this return transaction.

  Read data is sent to the return transaction at the time of reading. No data is sent when writing.

  If the master module detects an error and cannot process it immediately, it issues a command transaction with errorp asserted at the same timing as tbsyp. The slave module must not respond to command transactions for which errorp is asserted. The error is processed when the command transaction returns to the master module again.

  If the slave module detects an error, it asserts errorp at the same timing as tbsyp when a return transaction is issued.

  If an address error occurs, no slave module will respond to the command transaction. Therefore, no return transaction occurs.

  This needs to be detected by the master module.

  When receiving a transaction, the master module can determine that an error has occurred when a command transaction is continuously received.

  Further, when a command transaction is received and counted by a time-out counter, and a return transaction is not received within a certain period of time, it can be similarly determined as an error.

  Next, the transaction sequence will be described in detail.

  FIG. 5 shows a sequence of command transactions. Since the communication path is in the idle state (tbsyp = Low) in cycle 1 and the slave interface is in the ready state (srdyp = High), the master interface can assert tsp high in cycle 2 and start a command transaction. Since this command is a write, rd_not_wr is asserted low. The slave interface detects the start of the command transaction by asserting tsp, and deasserts srdyp to low in cycle 3. The deassertion timing of srdyp is to prevent subsequent command transactions from being issued, so it can be any time until the transaction ends.

  In uaddr_midp [5: 0] and laddr_datap [15: 0], addresses, master IDs, and write data determined from the first beat to the third beat are placed. In cycle 4, the command transaction ends. In cycle 5, tbsyp is deasserted to Low, and the communication path returns to the idle state.

  In cycle 9, srdyp is asserted high, and the slave interface returns to the ready state again. Upon detecting this, the master interface asserts tsp to High in cycle 10 and starts a read command transaction. Since it is a read here, rd_not_wr is asserted High. Also, no data is placed on the second and third beats of laddr_datap [15: 0].

  FIG. 6 shows a sequence when the slave module 0 401 receiving the write command transaction issued from the master module 400 from the communication path 0 forwards the write command transaction to the communication path 1 and issues a return transaction to the communication path 1. Is shown.

  The sequence of the write command transaction on the communication path 0 described above is as described above. The slave module 0 forwards the transaction sent from the communication path 0 to the communication path 1. If srdyp1 of communication path 1 is asserted High, the transaction is forwarded to communication path 1 with a one-cycle delay. Generally, in order to forward a command transaction, it is necessary to wait for the address decoding to end in order to forward the command transaction to the next path when the address decoding is completed and it is determined that it is not an access to itself. As a result, it was difficult to forward with a one-cycle delay. In the present invention, the protocol for always forwarding command transactions is used regardless of the result of address decoding, so there is no need to wait for the end of decoding, and the forward delay can be suppressed to one cycle. Thereby, it is possible to minimize the deterioration of the latency, which is the greatest drawback of the ring connection.

  The slave module 0 401 decodes the address while deasserting srdyp0 to prevent reception of the next transaction. If it is not an access to itself, it may assert srdyp0 and accept the next transaction. .

  When the slave module 1 402 cannot receive a transaction, srdyp1 of the communication path 1 is deasserted to Low. In this case, since the slave module 0 401 cannot forward the received transaction, the transaction is stored in the internal buffer and forwarded again when srdyp1 is asserted.

  In the case of FIG. 6, the command transaction is forwarded with a delay of one cycle. Also, as a result of decoding, the access is for itself, so a return transaction is issued to the communication path 1 while srdyp0 is deasserted.

  Since the communication path 1 is idle in cycle 9 and the slave module 1 402 is ready, slave module 0 401 asserts rsp high in cycle 10 and starts a return transaction. The sequence is the same as the command transaction, except that tsp is asserted and rsp is asserted. Also, in a return transaction for a write command, the part where data is placed may be Don't Care.

  The return transactions issued in this way are forwarded one after another through the communication path in the same way as the command transaction, and finally return to the master module. When each slave module receives a return transaction, it does not decode the address, and is forwarded to the next communication path in the same manner as a command transaction that did not hit.

  As described above, the command transaction issued from the master module 400 is issued as a return transaction by the target slave module. When returning to the master module 400, the return transaction is always sent after the command transaction.

  After issuing the command transaction, the master module 400 can issue the next command transaction before the command transaction and the return transaction are returned. This makes it possible to issue transactions in a pipeline manner in the ring.

  FIG. 7 shows a sequence when the slave module 1 that has received the read command transaction issued from the master module 400 from the communication path 0 forwards the read command transaction to the communication path 1 and issues a return transaction to the communication path 1. Show.

  The sequence is almost the same as a write command transaction. The only difference is that rd_not_wr is inverted and that the data part of the read command transaction is Don't Care and the read data is put on the data part of the return transaction.

  In the above, paying attention to the register access ring, the communication method has been described in detail.

  FIG. 3 is a diagram in which portions of the first register access ring 111 and the second register access ring 121 are extracted from the system of FIG. Hereinafter, the communication method will be described in detail with a focus on the hierarchized register access ring, using FIG. The communication protocol of the communication path between modules is the same as described above.

  The master module 400, slave module 0 401, slave module 2 403, and communication paths 0 to 3 are the same as those in FIG. The slave module 3 411, the slave module 3 412, and the slave module 4 413 are also equivalent to the slave module 0 401.

  A ring bridge 410 is connected to the master interface of the slave module 0 401 via the communication path 1 and is connected to the slave interface of the slave module 2 403 via the communication path 2. Further, the ring bridge 410 is connected to the slave interface of the slave module 3 411 through the communication path 10, and is connected to the master interface of the slave module 5 413 through the communication path 13.

  The communication path 11 connects the master interface of the slave module 3 411 and the slave interface of the slave module 4 412, and the communication path 12 connects the master interface of the slave module 4 412 and the slave interface of the slave module 5 413.

  The ring configured by communication path 0 → communication path 1 → communication path 2 → communication path 3 is the first register access ring 111, and is configured by communication path 10 → communication path 11 → communication path 12 → communication path 13. The ring is a second register access ring 121.

  The signals on the communication paths in the second register access ring 121 are equivalent to the communication paths 0 to 3, and the signal names on the respective communication paths are as follows.

Signal of communication path 10
tsp10, rsp10, tbsyp10, uaddr_midp10 [5: 0], laddr_datap10 [15: 0], rd_not_wr10, errorp10, srdyp10
Communication path 11 signal
tsp11, rsp11, tbsyp11, uaddr_midp11 [5: 0], laddr_datap11 [15: 0], rd_not_wr11, errorp11, srdyp11
Communication path 12 signal
tsp12, rsp12, tbsyp12, uaddr_midp12 [5: 0], laddr_datap12 [15: 0], rd_not_wr12, errorp12, srdyp12
Communication path 13 signal
tsp13, rsp13, tbsyp13, uaddr_midp13 [5: 0], laddr_datap13 [15: 0], rd_not_wr13, errorp13, srdyp13
The addresses assigned to each slave module are as follows.

Assigned address slave module 0 401 0x001000 to 0x001FFF
Slave module 2 403 0x002000 to 0x002FFF
Slave module 3 411 0x011000 to 0x011FFF
Slave module 4 412 0x012000 to 0x012FFF
Slave module 5 413 0x013000 to 0x013FFF
Here, the ring bridge 410 includes addresses assigned to all the slave modules connected to the second register access ring 121 branched from the ring bridge 410 and assigned to other slave modules. It is necessary to assign an address that does not include the address. In this case, the address assigned to the ring bridge 410 needs to include 0x011000 to 0x013FFF, and actually 0x010000 to 0x01FFFF is assigned.

  The ring bridge 410 has a bridge function, and when receiving a command transaction for an address assigned to the ring bridge 410 from the communication path 1, has a function of forwarding it to the second register access ring.

  When the ring bridge 410 does not hit its own address, the ring bridge 410 behaves in the same manner as the slave module described above and forwards the command transaction to the communication path 2.

  Hereinafter, the bridge function of the ring bridge 410 will be described in detail.

  When the ring bridge 410 receives a command transaction from the communication path 1, it immediately forwards it to the communication path 2 as it is. Of course, slave module 2 403 needs to be ready to accept transactions and srdyp2 must be asserted in order to forward. A command buffer 420 that temporarily stores commands exists in the ring bridge 410, and is forwarded to the communication path 2 and simultaneously stored in the command buffer 420.

  The ring bridge 410 decodes the address while deasserting srdyp1 to prevent reception of the next transaction, and if it is not an access to itself, it may assert srdyp1 and accept the next transaction.

  As described above, as long as the slave modules in the first register access ring 111 are accessed, the modules in the first register access ring 111 do not depend on the number of slave modules in the second register access ring 121 or the like. Since the communication speed is determined by the number, high-speed communication is possible.

  If the result of the decoding is an access to itself, the command transaction 420 stored in the command buffer 420 is forwarded to the communication path 10 while srdyp0 is deasserted. The command transaction forwarded to the communication path 10 in this manner flows through the second register access ring 121 in the same manner as when flowing through the first register access ring 111.

  The command transaction goes around the second register access ring 121 and returns to the ring bridge 410. This is stored in the command buffer 420 and a return transaction is awaited. If the command transaction is for the slave module 4 412, the slave module 4 412 issues a return transaction to the communication path 12 after the command processing is completed. This reaches the ring bridge 410 via the slave module 5 413 and the communication path 13. When the ring bridge 410 receives the return transaction, it forwards it to the communication path 2 of the first register access ring 111, asserts srdyp0, and waits for the next transaction from the communication path 1.

  The ring bridge 410 has a built-in timeout counter 421, which counts after receiving a command transaction from the communication path 13, and determines that an error occurs if no return transaction is received within a certain period of time. A return transaction is created based on the command transaction stored in 420 and issued to the communication path 2. At this time, errorp2 is asserted at the same timing as tbsyp2. As a result, an error can be detected in the second register access ring 121 when there is no slave module that responds to the command transaction.

  If there are two slave modules that respond to the command transaction in the second register access ring 121, the return transaction that has reached the ring bridge 410 earlier causes the ring bridge 410 to return a packet as in the normal state. Is issued to the communication path 2. Thereafter, when a further return transaction is received from the communication path 13, the return transaction is forwarded to the communication path 2 while asserting errorp2.

  In order to keep the order of return transactions with respect to command transactions in-order, the ring bridge 410 issues a command transaction to the second register access ring 121, and then returns from the communication path 1 until the return transaction for the command transaction returns. As a result, there is always only one command transaction in the second register access ring 121.

  In this embodiment, the slave module in the second register access ring 121 is the same as the slave module in the first register access ring 111, and the transaction protocol is also the same. Since the slave modules in 121 are always ready to accept transactions, the srdyp signal is not necessary.

  Therefore, the second register access ring 121 can omit the srdyp signal.

  Although the present invention has been shown and described with respect to particular embodiments, further modifications and improvements will be possible. For example, the communication path signals described herein may have other names but perform the same basic functions. The bit width of each signal and other values can be varied depending on the design. Any number of slave modules can be connected to the ring.

  Further, if the design is such that no error occurs, the error signal can be omitted.

  The system bus for data transfer that connects each module does not need to be connected to each module by one bus, and may be hierarchized via a bus bridge between them, or separated by a separate bus. May be connected. Furthermore, the connection may be in any shape such as multiplex bus or star connection.

When there is only one master in the system, the ring connection of the present invention is not limited to register access, but can be used for all communications in place of the system bus.
Furthermore, in this embodiment, addresses and data are multiplexed to reduce the number of signal lines, but the number of stages in the multiplex may be any number. For example, a single signal line can be used to send addresses and data as in serial communication. Conversely, if all signal lines are prepared, there is no need to perform multiplexing. In this case, the transaction is completed in one cycle, and high speed can be realized.

  Further, as shown in FIG. 4, a system configuration in which two or more subordinate register access rings exist and a configuration in which the ring hierarchy is multistage can be easily considered.

  Accordingly, the invention is not intended to be limited to the specific forms shown, but is intended to cover all modifications within the scope of the appended claims which do not depart from the spirit and scope of the invention. Should be understood.

The block diagram which shows the structure of embodiment of this invention. The figure which extracted the part of the 1st register access ring from the system of FIG. The figure which extracted the part of the 1st register access ring and the 2nd register access ring from the system of FIG. The figure in case the 2nd and 3rd register access rings are subordinate to the 1st register access ring. A sequence of command transactions. A sequence when the slave module 1 that has received a write command transaction issued from the master module from the communication path 0 forwards the write command transaction to the communication path 1 and issues a return transaction to the communication path 1. A sequence when the slave module 1 that has received the read command transaction issued from the master module from the communication path 0 forwards the read command transaction to the communication path 1 and issues a return transaction to the communication path 1.

Explanation of symbols

100 CPU
101 System bus bridge 102 Slave module 0 subject to register access
104 Slave module 2 to be accessed by the register
105 memory controller 106 system memory 110 system bus connecting each module in LSI 111 first register access ring connecting each module in a ring shape 120 ring bridge 121 second register access ring connecting each module in a ring shape 122 Slave module 3 subject to register access
123 Slave module 4 subject to register access
124 Slave module 5 subject to register access
400 Master module serving as master of first register access ring 401 Slave module 0 serving as slave of first register access ring
402 Slave module 1 serving as slave of first register access ring
403 Slave module 2 serving as a slave of the first register access ring
410 Ring bridge 411 Slave module 3 serving as a slave of the second register access ring
412 Slave module 4 serving as a slave of the second register access ring
413 Slave module 5 serving as a slave of the second register access ring

Claims (6)

  In the LSI, there is one main master module, a plurality of slave modules accessed from the master module, including the master module, and a first ring that connects the plurality of slave modules in a ring shape; In a system with a second ring that connects other slave modules in a ring and a layered ring in which the first ring and the second ring are connected by a bridge, all the rings connected by the ring The module has a master interface that issues transactions to the next connected module and a slave interface that receives transactions from the previously connected module, so that the master module has access to other modules connected to the ring To master Interface to issue command transactions from the interface, and the bridge issues transactions to the slave interface that receives command transactions from previously connected modules in the first ring and to the next connected module in the first ring A master interface that issues a transaction to the next connected module in the second ring, and a slave interface that receives a command transaction from a previously connected module in the second ring. A means for issuing a command transaction received from the ring to the second ring as necessary, and a transaction received from the second ring as required by the first It has a means for issuing a grayed, other modules as a slave to a communication method and apparatus and performs processing according to the command transactions received from the slave interface.   The communication method and the communication apparatus according to claim 1, wherein a plurality of rings are connected to the first ring by a plurality of bridges.   In addition to having multiple modules inside an LSI and connecting each module via a system bus, there is a communication path that connects each module in a ring that is hierarchized by a first ring and a second ring. 3. The communication method and apparatus according to claim 1, wherein when the CPU performs register access or the like, communication is performed using a hierarchical ring-shaped communication path.   The slave module has means for forwarding the command transaction received from the slave interface from the master interface to the next connected module, and is included in the transaction to determine whether the command transaction is an access to itself. Means for decoding the address to be transmitted in parallel with forwarding the transaction, and means for issuing a return transaction from the master interface when it is determined that the command transaction is an access to itself. The command transaction received from the master interface is forwarded to the next connected module in the first ring. Means for decoding the address included in the transaction in parallel with forwarding the transaction in order to determine whether the command transaction is an access to itself, and the command transaction accessing the self If it is determined that the command transaction is issued from the master interface to the second ring, and when a return transaction is received from a previously connected module in the second ring, the first ring 4. The communication method and apparatus according to claim 1, further comprising means for forwarding from a master interface to a connected module.   The slave module and the bridge have a buffer for holding the received transaction without forwarding when the next connected module is not ready to receive a transaction, and the next connected module 5. The communication method and apparatus of claim 4, further comprising means for transmitting as soon as it is ready to receive a transaction.   The bridge has a slave interface in which the master interface of the bridge is the starting point, the end point of the second ring in which the modules are connected in order is finally connected, and the command transaction issued from the bridge finally returns, 6. The communication method and apparatus according to claim 5, further comprising means for determining an error when a return transaction cannot be received for a predetermined time.

Images