JP2006101250A - Electronic device and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce an electromagnetic noise generated from a digital circuit effectively. <P>SOLUTION: By sampling a signal applied to an input terminal according to timing, which is given by a reference clock of operation of a digital circuit as an electromagnetic noise source, the signal level of a fundamental wave of a clock frequency included in the input signal and its harmonic factor can be restricted. By using a synchronization type frequency removing filter for generating an output signal at an output terminal, the electromagnetic noise factor of the digital circuit mixed into the high frequency signal can be reduced, and superior communication characteristics or measurement performance can be obtained. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for suppressing noise generated by a digital IC chip present in an electronic device.

  The frequency elimination filter is used for the purpose of removing electromagnetic noise mixed from other electronic circuits in addition to a desired frequency component in the electronic device, and making the device function such as good radio performance work well.

  For example, in a mobile phone or the like, it is common to provide an amplifier circuit or a detection circuit in order to receive an original weak radio signal and extract communication information.

  However, in recent years, IC chips equipped with digital circuits such as high-speed CPUs and DSPs for multimedia support are mounted in the same device, and electromagnetic noise generated by the digital circuits is mixed into the high-frequency circuits, resulting in deterioration of communication characteristics. There is a problem to do.

  As a method of removing noise, a method of mounting a filter that removes only a specific noise frequency component or shielding a digital circuit that is an electromagnetic noise source has been taken.

  One example thereof is described in JP-A-62-116095 (Patent Document 1).

JP-A-62-116095

  However, the conventional method is intended to remove only a specific noise frequency component, and noise suppression is not performed in consideration of driving characteristics of the noise generation source.

  Therefore, noise could not be suppressed efficiently.

  An object of the present invention is to efficiently suppress noise of a signal processed in an electronic device.

  As described above, the present inventors pay attention to the fact that a high-speed digital IC chip such as a CPU or DSP is a large noise generation source. Settled.

  The representative means distributes the clock signal input to the other digital IC chip to the filter circuit that suppresses the fundamental frequency and harmonic signal of the clock based on the input clock signal. And a circuit for inputting data.

  The filter circuit can be mounted as a circuit in another IC chip, mixed in a circuit in an IC chip that has become a noise signal source, or a plurality of elements and wiring on a mounting circuit board. There is a form that consists of.

  According to the present invention, noise can be efficiently suppressed.

  A specific aspect of a method for using the driving characteristics of a digital IC chip, which has been conceived as a result of paying attention to the fact that a high-speed digital IC chip such as a CPU or DSP, is a large noise generation source, as follows is shown below.

  FIG. 1 is a functional block diagram of the electronic apparatus according to the first embodiment.

  In this embodiment, the electronic device 100 is a mobile phone. This mobile phone includes a high frequency amplifier 101, a CPU 102, a memory 103, a baseband signal processing circuit 104, a clock generator 106, a display 105, and a sample hold circuit (filter) 200.

  The radio wave is received by an antenna (not shown), and is input as a signal to the high-frequency amplifier 101 whose input terminal is connected to the antenna. The high frequency amplifier 101 amplifies the signal and outputs it from the output terminal.

  The amplified signal is input to the input terminal of the sample and hold circuit 200. The sample hold circuit 200 suppresses noise and outputs the suppressed signal from the output terminal.

  The signal in which noise is suppressed is input to the input terminal of the baseband signal processing circuit 104. The baseband signal processing circuit 104 demodulates the input signal and outputs the demodulated data signal from the output terminal.

  Information (signal) is transmitted to the liquid crystal display unit 105 based on the data signal representing information such as sound and image output here.

  These processes are performed by the CPU 102 in cooperation with other devices including the memory 103. Therefore, the sample hold circuit 200 includes an input terminal for a clock signal, and the clock generator 106, the input terminal for the clock signal, and the clock generator 106 are connected by wiring.

  The function of the sample and hold circuit 200 will be described with reference to FIGS.

  FIG. 3 shows an electromagnetic noise generation principle, FIG. 2 shows a block diagram of the sample hold circuit 200, and FIG. 4 shows a filter circuit diagram of the sample hold circuit.

  FIG. 3 shows an example in which a CPU 102 that operates with a clock signal of 40 MHz is mounted inside a mobile phone using a wireless signal of 900 MHz band.

  When a clock signal is input from the clock generator 106 to the CPU 102, electromagnetic noise is generated in the data signal or power supply wiring of the CPU 102 by driving the internal circuits and elements of the CPU 102. These electromagnetic noises propagate in the housing through the air or via the ground pattern of the wiring board, power supply wiring, etc., and are mixed into the signal of the high-frequency amplifier 101. At this time, the frequency spectrum of the in-device electromagnetic noise is as shown in FIG. 2, and a harmonic component 20 times as high as 40 MHz cannot be distinguished from a signal in the 900 MHz band, and the radio function is deteriorated. Specifically, the sensitivity is reduced, or data corruption due to noise mixing occurs.

  The sample and hold circuit 200 suppresses the mixed noise.

  As shown in FIG. 2, the high frequency signal amplified by the high frequency amplifier 101 and the same clock signal 201 from the clock generator 106 that supplies the clock signal 201 to the CPU 102 are input to the sample hold circuit 200, and noise is generated. A suppressed output signal is output.

  Specifically, as shown in FIG. 4, one is connected between the signal input terminal and the output terminal, the other is connected to the other, and the capacitor 202 is provided between them, and the capacitor 202 and the connection are connected to each other. A switch 203 for switching between them, and a clock signal 201 is input to the switch 203, and the switch 203 is controlled by the clock signal.

  Although the control of the switch 203 is not shown, the fundamental frequency and harmonic components of the clock signal 201 are extracted, and the connection between the capacitor and the circuit between the input terminal and the output terminal is turned on at the fundamental frequency and the harmonic frequency. And control to turn off at other timings.

  Thus, in the controlled sample and hold circuit 200, the switch is turned on at the fundamental frequency and the harmonic frequency of the clock signal, and the current flows so as to charge the capacitor, so that the current flowing to the output terminal The value becomes smaller and noise can be suppressed.

  FIG. 5 is a circuit block diagram in which a high frequency amplifier is provided with a sample hold function.

  The high-frequency amplifier 210 includes a first-stage amplifier 211, an AGC (Auto Gain Control) amplifier 212 for avoiding saturation due to an excessive signal, a switch 203, and a capacitor 202.

  The high-frequency amplifier 210 of the present embodiment has a clock input terminal 201, and removes harmonic components of the clock frequency f1 by sampling and holding using the switch 203 and the capacitor 202 in synchronization with the clock 201 inside. There is in point to do.

  The high-frequency amplifier 210 is used in place of the high-frequency amplifier 101 in FIG. 1, and the output terminal of the high-frequency amplifier 101 is connected to the input terminal of the baseband signal processing circuit 104 without using the sample hold circuit 200 in FIG. .

  Even in this form, it is possible to configure a good radio circuit free from problems caused by electromagnetic noise inside the apparatus.

FIG. 1 is a functional block diagram of an electronic apparatus according to the first embodiment. FIG. 2 is a block diagram of the sample and hold circuit 200. FIG. 3 is a diagram showing the generation principle of electromagnetic noise. FIG. 4 is a schematic diagram of the sample and hold circuit. FIG. 5 is a circuit block diagram in which a high frequency amplifier is provided with a sample hold function.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Antenna, 2 ... Frequency spectrum of electromagnetic noise in apparatus, 100 ... Electronic device, 101 ... High frequency amplifier, 102 ... CPU (IC chip), 103 ... Memory, 104 .. Baseband signal processing circuit (IC chip), 105... Liquid crystal display unit, 106... Clock generation circuit, 200... Sample hold circuit, 201. ···switch

Claims (5)

An electronic device including an IC chip including a digital circuit,
An electronic apparatus comprising a circuit for performing processing for suppressing a fundamental frequency of a clock frequency of the IC chip and a signal level of a harmonic thereof as a circuit outside the IC chip. In claim 1,
A circuit that performs processing for suppressing the signal level is:
An electronic device that receives a clock signal having the same clock frequency as that of the IC chip and digitally processes the signal in accordance with a timing given by the clock signal. In claim 1,
A circuit that performs processing for suppressing the signal level is:
A sampling circuit that samples the input signal input to the signal input terminal according to the timing given by the clock signal input from the clock input terminal, and the fundamental frequency of the clock frequency included in the input signal and the signal level of its harmonic component An electronic device comprising: a circuit that suppresses noise. The electronic device according to claim 1,
The electronic device is characterized in that the circuit for performing the processing for suppressing the signal level is constituted by an IC chip different from the IC chip. In a semiconductor device that amplifies a signal input terminal, a signal output terminal, and a signal input to the input signal terminal and outputs the amplified signal to the output terminal.
Has a clock signal input terminal,
A semiconductor device comprising a circuit that suppresses a signal level of a fundamental frequency of a clock signal input to a clock signal input terminal and a harmonic component thereof.

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