JP2006098190A - Photon detector module and imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a radar imaging system having a circuit speed and a density necessary for attaining a range resolution, and having sensitivity necessary for designating a small target surface fluctuation based on a flying difference in a picosecond in a laser echo. <P>SOLUTION: This photon detector module has a photon source for generating photon reflection from a target, a detector array for generating a detector array output signal by being reacted with the photon reflection, and a laminated processing module for receiving the detector array output signal. The processing module has at least two laminates, and each laminate has at least one integrated circuit chip for receiving detector array output signal processing. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a photon detector module and an imaging device, and more particularly to a radar (laser radar) imaging technique, and more particularly partially blurred or camouflaged with high resolution and sensitivity. The present invention relates to an apparatus that enables three-dimensional laser imaging of a target.

  Current laser imaging is generally detected by a photon detector such as a photon (also called laser echo) focal plane array reflected by scanning a target with a laser. The target range is determined by calculating the time required for the laser echo to return from the target to the photon detector. The detector output signal is processed electronically to reveal the surface body on the three-dimensional object. Such imaging capability is valuable, for example, if the vehicle is blurred or camouflaged by leaves or the imaging sensor can only obtain a limited or angular image of the target in an urban environment. is there.

  In general, current radar imaging systems include a laser source, appropriate optical elements associated with the detector array, processing circuitry for processing the detector array output into a usable form, post-processing circuitry, and processed detection. Software that obtains the child array output and converts it to a usable form such as an image on an electronic display.

  In operation of the system, one or more laser pulses are directed to the desired target. Laser echoes from the target surface are received and imaged in the detectors in the detector array by appropriate optical elements. Since the flight time of the returning laser echo changes according to the distance between the detector array surface and the surface body from which the echo is received, a three-dimensional image can be calculated based on the relative echo delay.

  When the laser echo delay is 1 nanosecond, the target surface variation is about 15 cm, and when the laser echo delay is 500 picoseconds, the target surface variation is about 8 cm. As is apparent from these short time periods, very high detector signal processing and timing circuit speeds are desirable for resolving target surface bodies with centimeter-level depth resolution. Unfortunately, current radar imaging systems lack the ability to obtain the required circuit speed and resolution and sensitivity in the very high (eg cm) range.

  Instead, conventional passive visual sensors such as CCD video sensors provide the viewer with easily read information. Nevertheless, if accurate scene information in a complex video environment (ie camouflaged or partially blurred target) is an important factor in observer decision making, these types of sensors are It is not desirable.

  In view of the state of the art as described above, the object of the present invention is to clarify the small target surface variation based on the circuit speed and density necessary to achieve the range resolution and the picosecond flight difference in the laser echo. It is to provide a radar imaging system having the sensitivity necessary for the above.

  Another object of the present invention is to provide a radar detector system with reliability, high speed, and high circuit density, and an apparatus with range resolution and sensitivity at the centimeter level.

  Therefore, a first technical idea of the present invention relates to a photon detector module, which module generates a detector array output signal in response to a photon input, and a detector array output signal. Receiving and electrically connected stacked processing modules, the processing module having at least two stacks, and processing at least one stack received detector array output signal At least one integrated circuit chip, each integrated circuit chip has an amplifier circuit for amplifying the detector array output signal, and a differential for differentiating the detector array output signal A circuit is electrically connected to the amplifier circuit, and a comparator circuit for comparing the detector array output signal with a predetermined threshold is electrically connected to the differentiating circuit. An analog / digital conversion circuit that converts the output signal into a digital value is electrically connected to the comparison circuit, and a FIFO register that receives the digital value is electrically connected to the conversion circuit for further processing. The gist of the invention is that the output means for outputting the FIFO register data is electrically connected to the FIFO register.

  A second technical idea of the present invention relates to an image device, which includes a photon source that generates photon reflection from a target, and a detector array that generates a detector array output signal in response to the photon reflection. A stack processing module for receiving the detector array output signal, the processing module having at least two stacks, each stack having at least one for receiving detector array output signal processing. The gist of the present invention is to have an integrated circuit chip.

  According to the present invention, high imaging ability can be obtained. This is due in part to the use of stacks with ROIC circuits. This increases the detector output processing circuit density, while minimizing circuit conductor length and associated capacitance.

  As a result of the lamination of the ROIC circuits, a large detector array (for example, 128 × 128 or more) with a dedicated detector read circuit can be integrated. Amplifiers, threshold detectors, sampling circuits, digital-to-analog converters (DACs), first-in first-out (FIFOs), register range bins, etc. are all very small modules.

  The module thus obtained achieves the circuit speed and density required to resolve a small three-dimensional target based on one or more laser echoes detected by each detector pixel on the detector array. The At the same time, a dedicated processing channel is provided for each detector on the detector array.

The multi-layer ROIC processing module preferably comprises a stack, the stack having thin integrated circuit chips, each layer having one or more receive channels. Based on the reception of photons reflected from the imaged target surface, each channel has a circuit that detects the laser flight time from T ₀ (start of laser pulse or user-assigned T ₀ point) to photon return time. Have.

  The laser echo time of flight information is processed and converted into digital bits stored in a FIFO register consisting of range bins on the ROIC. A high bit in a range bin can be designated as indicating, for example, the arrival time of a laser echo based on its location within a group of range bins. The range bin data is multiplexed from the ROIC module to an external circuit, which translates the data, converts it into a usable form such as a 3D point cloud, and displays it as an electronic image on the display.

  FIG. 1 is a block diagram of an arrangement of the present invention in which a photon source such as a laser 1 generates a beam 5 that is directed through a beam shaping optical element 10 to a scene or target 7.

  In the preferred embodiment, laser 1 is 1064 nm and is mechanically aligned and is a 300 microjoule seed YAG laser, which can generate 500 picosecond wide pulses. A beam amplifier (not shown) such as a master oscillator power amplifier may be provided, and a seed beam is supplied to the amplifier. The seed beam passes through a Faraday rotator and enters a four-pass thermal control amplifier with two pump YAG diodes.

  In the preferred embodiment, the beam shaping optical element 10 is a beam shaping holographic lens and is suitable for projecting a square beam region onto a target. The square beam region optimizes the ability of the detector array to receive and process reflected photons in its field of view.

  The beam 5 is preferably amplified to produce a photon reflection from a detectable target and has a reflectivity of 10% at 100 m.

  A converging optical element 20 is provided, preferably a 75 mm, F1.4 lens, with an appropriate spectral filter for optimizing the laser pulse wavelength. The converging optical elements 20 are arranged to receive photons reflected from the imaging target 7 (ie, intensive blur, subject and background) and imaged on the detector array of the present invention as described below. The

  After the beam is applied, the beam 5 is selectively pre-aligned with the detector array of the present invention by rotating the beam 5 through a Risley prism (not shown) and aiming at the detector array. Is done. The parallax error is minimized for the two optical subassemblies in the beam shaping optical element 10 in close proximity to the converging optical element 20.

  The detector unit 30 includes a sensor array or detector array 40 and a stacked processing readout electronic module 50.

  The detector array 40 is generally a focal plane array of individual photo detectors suitable for detecting reflected photons from the target and generating signals in response thereto. In the preferred embodiment, an InGaAs detector array is used. Irvine Sensors presents a 128 × 128 InGaAs detector array with a 40 μ active detector on the 50 μ center in this invention. There, 128 × 8 sets of detectors on the array are accessed.

  2 and 3, the processing module 50 has a stack of two or more layers 60, each layer having one or more readout electronics 70. These are preferably integrated circuit chips and process the signals received from the detector array 40. Each readout electronic circuit 70 includes one or more channels 75 and includes an electronic circuit that processes the electronic signals from the detector array 40.

  The individual layers 60 are such that the input, output, power and read ground paths of the electronic circuit 70 are connected to one or more edges of each layer 60 using metal traces 73 to form one or more access conductors 80. Is formed.

  Layers 60 are bonded together using a known adhesive 62 and are processed (eg, grounded or wrapped) to expose access leads 80. Layer 60 is optionally thinned and packaged by known methods in the field of semiconductor processing. The thinned active layer is embedded in a silicon cap chip for convenience of handling.

  Appropriate conductive connection pads 90 are formed on one or more sides of the processing module 50 to form one or more “T-connections” 80 to connect the access leads 80 to the detector array 40 and external image processing electronics. To connect to.

  Shown in FIG. 3 is a T-connection 85 between the bump bond on the detector array 40 and the metal access lead 80. The T-connection structure allows the high density stack to be connected to the detector array 40 and external circuits outside the processing module.

  In one embodiment of the present invention, pads 90 are formed on one or more processing module side surfaces to enable bump bonding, such as indium bump bonding, of the detector array 40. After bump bonding of the detector array 40, the volume occupied by the detector array 40 arranged vertically on the processing module 50 is minimized, and the length of the detector-readout circuit conductor is optimized and the speed is increased. However, the parasitic capacitance is reduced. Such a connection structure takes advantage of the high circuit density of the processing module and provides the very short circuit path required for high speed laser range resolution.

  Returning to FIG. 1, an external electronic circuit 100 that receives and processes the output of the processing module 50 can be connected to a connection pad 90 on the accessible surface of the processing module 50 through a wire bond.

  In operation of the system, the beam 5 extends outward from the beam shaping optics 10 and is imaged onto the desired target. Photons from the pulse beam that are not absorbed or specularly reflected by the target return to the converging optics 20 from the various target surfaces. Since the distance between the target surface and the converging optical element varies, the time for which the reflected photon is received by the detector unit also varies. Each detector in the detector array demonstrates multiple signals returning from photon reflections from the scene surface at different distances from the detector array.

  Beam 5 is swept across the target area being scanned to obtain 256 vertical samples. The laser is pulsed at 94 Hz to obtain 256 horizontal samples and the channel data is stored in a 1024 FIFO range bin. The 256X256X1024 data is stored as frames, multiple frames are registered and merged into a 3D point cloud and displayed as a 3D image for target object classification.

The flight time of the reflected photons emitted from the laser 1 and returning to the surface of the detector array 40 depends on the speed of light (c = 3 × 10 ⁸ m / s) and the physical characteristics of the light guide medium, depending on the distance of the target surface. ,fluctuate.

An example of a channel on the ROIC chip is shown in FIG. As shown in FIGS. 1 and 4, each channel 75 can function as a dedicated detector signal input circuit and has a circuit that receives the T ₀ trigger signal (initial laser pulse trigger) and performs a FIFO. The register is given a reference for the arrival time of the laser echo in the detector array 40. The laser pulse is preferably short compared to the capture interval (eg -500 picoseconds vs. 500 nanoseconds), and multiple returns can be detected by a single detector pixel.

  Each channel 75 preferably has an analog portion that operates at a very large bandwidth, and further has a digital portion that operates at up to 2 GHz while the FIFO register is filled with data. The channel 75 includes a digital-to-analog converter and further includes a circuit that allows the user to adjust the threshold value of the comparator. Each ROIC can include multiple channels (eg, 128 channels) that are multiplexed into a single output signal for image processing by the external circuit 100.

  The received laser echo is collected and filtered by the channel during the acquisition period. The integrated signal is amplified and differentiated. As a result, the signal is converted back to a pulse having an amplified signal intensity, which is large enough to be detected by the comparator. The comparator detects whether the pulse is above or below a predetermined programmable threshold. In one embodiment, the output of the comparator is sampled at a rate of 2 GHz, resulting in a 1-bit analog to digital conversion signal.

In one embodiment, each channel 75 has a 1024 deep, FIFO register that stores a history of output from the comparator from T ₀ to T ₀ + about 50 nanoseconds. The high bit in the FIFO register can be defined as the arrival time of the laser echo with respect to the T ₀ signal, as determined by the location of the bit in the register. When the FIFO is clocked at 2 GHz, each stage of the register bin represents 500 picoseconds of time history, which is considered equivalent to 7.5 cm of range history. The timing of the T ₀ trigger signal can be varied, thereby increasing the return time of the laser echo returning from the farther target.

  After the FIFO 1024 stage is filled, the ROIC reads data (MUX) to the external circuit 100 using a conventional frame and a line signal at a 20 MHz rate. The MUX data can be processed using an appropriate external circuit to generate a 3D point cloud defined by the target and further processed to generate a 3D electronic image.

It is a block diagram which shows the structure of this invention. It is a perspective view which shows each layer and lamination | stacking of this invention. It is sectional drawing of the processing module of this invention. It is a circuit diagram of the integrated circuit of this invention.

Explanation of symbols

1: Laser 5: Beam 7: Target 10, 20: Optical element 30: Detector unit 40: Detector array 50: Processing module 100: External electronic circuit

Claims (20)

A photon detector array that generates a detector array output signal in response to the photon input; and
A stack processing module that receives the detector array output signal and is electrically connected, the processing module having at least two stacks, and detecting at least one stack received At least one integrated circuit chip for processing the child array output signal, each integrated circuit chip having an amplifier circuit for amplifying the detector array output signal, A differentiation circuit for differentiating is electrically connected to the amplification circuit, a comparison circuit for comparing the detector array output signal with a predetermined threshold value is electrically connected to the differentiation circuit,
An analog / digital conversion circuit that converts the detector array output signal into a digital value is electrically connected to the comparison circuit, and a FIFO register that receives the digital value is electrically connected to the converter for further processing. Therefore, the photon detector module is characterized in that the output means for outputting the FIFO register data is electrically connected to the FIFO register.   2. A module according to claim 1, wherein the output means comprises at least one multiplex circuit.   The module of claim 1, further comprising at least one T-connector for electrical connection of the detector array.   The module according to claim 1, wherein the digital value is a 1-bit digital value.   The module of claim 1, wherein the predetermined threshold is programmable by external program means.   The module of claim 1, wherein the detector array comprises at least one 8X128 array of detector pixels.   The module of claim 1, wherein the detector array comprises at least one 128X128 array of detector pixels.   The module of claim 1, wherein the detector array is an InGaAs detector array.   A photon source that generates photon reflection from the target, a detector array that generates a detector array output signal in response to the photon reflection, and a stacked processing module that receives the detector array output signal. An imaging device, wherein the processing module has at least two stacks, each stack having at least one integrated circuit chip for receiving detector array output signal processing.   10. The apparatus of claim 9, wherein the processing module has at least one T-connection structure formed thereon, which electrically connects the detector to an external electronic device. .   10. The apparatus of claim 9, further comprising circuit means for converting the processed detector array output signal into an electronic image.   The apparatus of claim 9, wherein the circuit means converts the processed detector array output signal into a three-dimensional electronic image.   The apparatus of claim 9, wherein the photon source is a laser.   The apparatus according to claim 9, wherein the photon source is a pulsed laser.   The apparatus of claim 9, further comprising a beam shaping optical element for imaging the photon source on the target.   10. The apparatus of claim 9, further comprising a converging optical element for imaging the reflected photons on the detector array.   The apparatus of claim 9, wherein the detector array is an InGaAs detector array.   The apparatus of claim 9, wherein the detector array is bump bonded to the processing module by at least one T-connection.   The apparatus of claim 9, wherein the detector array output signal is compared to a predetermined threshold by a comparator.   The apparatus of claim 9, wherein the external electronic device is a detector array.

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