JP2006094365A - Nonlinear amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonlinear amplifier circuit using a source follower circuit and capable of obtaining super linear characteristics without changing its simple circuit configuration as much as possible. <P>SOLUTION: A feedback circuit reduces a channel current of an input MOS transistor and reduces a gate-source voltage of the input MOS transistor as a source voltage of the input MOS transistor of a source follower circuit increases. Since an output voltage is approximately corresponding to a voltage subtracting the gate-source voltage from an input voltage, the output voltage becomes higher as the gate-source voltage is reduced. Therefore, the non-linear amplifier circuit is designed to superlinearly reduce the gate-source voltage with respect to increase of the input voltage, thereby obtaining superlinear characteristics without complicating circuit configuration. It may be enough therefor to appropriately select an element dimension or impurity concentration of the input MOS transistor and to use a range of superlinearly increasing the the channel current with respect to increase of the gate-source voltage. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an amplifier circuit whose input / output characteristics are nonlinear (hereinafter referred to as a nonlinear amplifier circuit). In particular, the present invention relates to a non-linear amplifier circuit that is configured using MOS transistors and whose gain increases as the input signal increases.

  In an electric circuit for processing an analog signal, some information may be included in a signal level such as an output voltage. In that case, the relationship between the signal level and the information value (for example, the luminance value indicated by the video signal) indicated by the signal level may be nonlinear. For example, (information value) / (signal level) may increase as the signal level increases, and this is hereinafter referred to as a “super linear characteristic signal”. On the other hand, as the signal level increases, (information value) / (signal level) may decrease, and this is hereinafter referred to as “sub-linear characteristic signal”. A nonlinear amplifier circuit is used as one means for linearly correcting the nonlinear relationship between the signal level and the information value (see, for example, Patent Document 1 and Patent Document 2).

  The non-linear amplifier circuit has, for example, any of the following input / output characteristics. One is that the input / output ratio (gain) decreases as the input signal rises. In this specification, this input / output characteristic is referred to as “sub-linear characteristic”, or “the output becomes sub-linear as the input increases. "Increase". The other is that the input / output ratio increases as the input signal rises. In this specification, this input / output characteristic is referred to as the “super linear characteristic” or “the output becomes super linear as the input increases. "Increase".

In Patent Document 1, a bipolar transistor whose collector current increases exponentially with respect to the base-emitter voltage is used, the collector current is detected as a voltage by a resistor, and this voltage is used as a correction signal. That is, an attempt is made to cancel the nonlinearity of the input signal and correct it linearly by a portion where the collector current exhibits super linear characteristics.
JP 2002-320112 A Japanese Patent Publication No. 6-20251

  When linearly correcting a signal having super linear characteristics without performing positive / negative inversion or the like, a non-linear amplifier circuit having input / output characteristics of sub-linear characteristics may be used. On the contrary, when linearly correcting a signal having a sub-linear characteristic, a nonlinear amplifier circuit having an input / output characteristic having a super linear characteristic may be used, and it has been desired to realize such a circuit with a source follower circuit. This is because the source follower circuit is excellent in that it has a high input impedance and a low output impedance, and a gain of about 1 can be obtained without any other ancillary elements.

The source follower circuit is often used for a buffer amplifier or the like because of the above-described advantages. However, the gain is not determined by an attached element but utilizes the property that the voltage between the gate and the source of the MOS transistor is constant. Therefore, in the source follower circuit, it is difficult to adjust the gain, and it is further difficult to make the input / output characteristic to be a super linear characteristic.
An object of the present invention is to provide a non-linear amplifier circuit that uses a source follower circuit and has an input / output characteristic of a super linear characteristic without complicating its simple circuit configuration.

  Another object of the present invention is to enhance the super linear characteristic in a non-linear amplifier circuit suitable for the above-described purpose, that is, to increase the gain increase rate with respect to the increase of the input signal.

  According to a first aspect of the present invention, the nonlinear amplifier circuit includes a source follower circuit having an N-channel input MOS transistor and a load MOS transistor, and a feedback circuit. The input MOS transistor has a drain connected to the positive voltage line and receives an input signal at the gate. The load MOS transistor has a drain connected to the source side of the input MOS transistor and receives a gate voltage and a source voltage so that a constant channel current flows. The feedback circuit decreases the channel current of the input MOS transistor as the source voltage of the input MOS transistor is higher. In this specification, the current flowing from the drain to the source in the N-channel MOS transistor and the current flowing from the source to the drain in the P-channel MOS transistor are both expressed as “channel current”. .

  The invention according to claim 2 is the nonlinear amplifier circuit according to claim 1, characterized by the following points. First, the feedback circuit includes a current mirror circuit having two P-channel MOS transistors, and an N-channel adjustment MOS transistor whose gate is connected to the source side of the input MOS transistor. Second, the channel current of one P-channel MOS transistor and the channel current of the input MOS transistor are supplied as the channel current of the load MOS transistor, and the other P-channel MOS transistor The circuit elements are connected so that the channel current is supplied as the channel current of the adjustment MOS transistor. Third, the nonlinear amplifier circuit according to the present invention outputs the source voltage of the input MOS transistor.

  The invention according to claim 3 is the nonlinear amplifier circuit according to claim 1, characterized by the following points. First, the feedback circuit includes a current mirror circuit having two P-channel MOS transistors, and an N-channel adjustment MOS transistor whose gate is connected to the source side of the input MOS transistor. Second, the channel current of one P-channel MOS transistor and the channel current of the input MOS transistor are supplied as the channel current of the load MOS transistor, and the other P-channel MOS transistor The circuit elements are connected so that the channel current is supplied as the channel current of the adjustment MOS transistor. Third, the non-linear amplifier circuit according to the present invention has a resistance element connected between the drain of one P-channel type MOS transistor and the source of the input MOS transistor, The drain voltage of the MOS transistor is output.

  According to a fourth aspect of the present invention, in the nonlinear amplifier circuit according to the third aspect, "the resistance element is a channel resistance of an N channel type MOS transistor receiving a positive constant voltage at a gate".

  In the present invention, the feedback circuit reduces the channel current of the input MOS transistor and the gate-source voltage of the input MOS transistor as the source voltage of the input MOS transistor of the source follower circuit is higher. Since the output voltage substantially corresponds to a voltage obtained by subtracting the gate-source voltage from the input voltage, the output voltage increases as the gate-source voltage decreases. Accordingly, when the input voltage rises at a constant rate, if the gate-source voltage of the input MOS transistor is designed to decrease in a super linear manner, a super linear characteristic can be obtained without complicating the circuit configuration. . For this purpose, the element size, impurity concentration, and the like are selected appropriately, and the channel current characteristic of the input MOS transistor may be in a range in which the channel current increases in a super linear manner as the gate-source voltage increases.

[Description of Principle of the Present Invention]
FIG. 1 is a circuit diagram showing the principle of the present invention. As shown in the figure, the nonlinear amplifier circuit 8 includes a constant voltage source 12 that supplies a positive constant voltage Vcc, an N-channel depletion type MOS transistor NM1, an N-channel depletion type MOS transistor NM2, and a voltmeter 16. The control type current source 20 and the output terminal 24 are included. In the figure, G, S, D, and B represent the gate, source, drain, and bulk (substrate) of the MOS transistors NM1 and NM2, respectively, and GND represents a ground line (voltage 0 V).

  MOS transistor NM1 receives input voltage Vin at its gate terminal and positive constant voltage Vcc at its drain terminal. The MOS transistor NM2 has a gate terminal and a source terminal fixed to the voltage of the ground line GND so that the channel current is constant, and functions as a load. That is, the MOS transistor NM1 and NM2 constitute a one-stage source follower circuit, and the source voltage of the MOS transistor NM1 (drain voltage of NM2) becomes the output voltage Vout.

  The voltmeter 16 detects the output voltage Vout. The control type current source 20 supplies a current Ics corresponding to the output voltage Vout detected by the voltmeter 16. In the above circuit configuration, the MOS transistors NM1 and NM2 respectively correspond to the input MOS transistor and the load MOS transistor. The voltmeter 16 and the control type current source 20 correspond to the feedback circuit described in the claims.

Here, the gate-source voltage of the MOS transistor NM1 is assumed to be Vgsnm1 (hereinafter simply referred to as Vgsnm1). At this time, the following equation holds.
Vout = Vin−Vgsnm1 (1)
That is, if Vgsnm1 is constant, the output voltage Vout changes linearly with respect to the input voltage Vin. As shown in the figure, the current supplied from the voltage source 12 is Ivcc, and the channel currents of the MOS transistors NM1 and NM2 are Inm1 and Inm2, respectively. Further, if the output terminal 24 is connected to the gate of the transistor in the subsequent circuit, and the outflow current from the output terminal 24 can be ignored, the following equation is established.

Inm2 = Inm1 + Ics = Ivcc (2)
The main feature of the present invention is that the control type current source 20 increases the current Ics as the output voltage Vout detected by the voltmeter 16 increases. As described above, in view of the fact that the channel current Inm2 of the MOS transistor NM2 is constant and the equation (2), when the current Ics increases as the output voltage Vout increases, the channel current Inm1 is equal to the current Ics. Decreases by the increment.

  At this time, in the MOS transistor NM1, the gate-source voltage decreases as the channel current decreases, so that when the current Ics increases as the output voltage Vout increases, Vgsnm1 decreases. Therefore, when the input voltage Vin increases from the relationship of the expression (1), the increase amount of the output voltage Vout becomes larger than the increase amount of the input voltage Vin by the decrease amount of Vgsnm1. Therefore, if the manner of decreasing Vgsnm1 is appropriately controlled, the input / output characteristics become super linear characteristics. Specifically, when the input voltage Vin increases at a constant rate, Vgsnm1 may be decreased so that the amount of decrease increases as the input voltage Vin increases. That is, Vgsnm1 may be reduced in a super linear manner with respect to the increase of the input voltage Vin.

  FIG. 2 shows which range of the channel current characteristic of the MOS transistor NM1 should be used to obtain the super linear characteristic, that is, to reduce Vgsnm1 in a super linear manner with respect to the increase of the input voltage Vin. It is explanatory drawing. FIG. 2A schematically shows the relationship between Vgsnm1 and channel current Inm1 in the MOS transistor NM1.

  In the present invention, the MOS transistor NM1 is operated in a saturation region (a range in which the channel current Inm1 hardly changes even when the drain-source voltage is changed). In general, the channel current Inm1 exhibits a substantially square characteristic with respect to a value obtained by subtracting the threshold voltage Vth from Vgsnm1. That is, the channel current Inm1 increases super linearly in a certain range of Vgsnm1, but the present invention uses this range.

  In addition, the scales 1, 2, and 3 of the alternate long and short dash line in FIG. 2A are shown for reference so that it can be understood that they have super linear characteristics. As shown in the figure, when Vgsnm1 increases from 1 to 2, the channel current Inm1 increases only by about 0.5 (from about 1 to about 1.5), but when Vgsnm1 increases from 2 to 3. The channel current Inm1 is increased about three times (by about 1.5). Therefore, it can be said that the range indicating the scale (the “large bend range” in the figure) exhibits a large super linear characteristic.

  FIG. 2B is a schematic diagram in which input / output characteristics are compared between a normal source follower circuit and the present invention, where the horizontal axis indicates the input voltage Vin and the vertical axis indicates the output voltage Vout. The thick line in the figure is a virtual straight line where Vin = Vout. In a normal source follower circuit, that is, in the configuration in which the voltmeter 16 and the control type current source 20 are opened in FIG. 1, Vgsnm1 is operated substantially constant. In this case, the input / output characteristics are obtained by shifting a constant voltage downward from a straight line of Vin = Vout in almost the entire range of the input voltage Vin, and are linear as shown by a thin line in the figure.

  On the other hand, in the present invention, the current Ics is increased as the output voltage Vout increases. Here, since the output voltage Vout increases only when the input voltage Vin rises, increasing Ics as the output voltage Vout increases is equivalent to increasing the current Ics as the input voltage Vin increases. is there. In the present invention, as the range of Vgsnm1 corresponding to the range that the input voltage Vin can take, a portion where the super linear characteristic of the channel current Inm1 appears greatly (for example, “a large bending range” in FIG. 2A). Use. This is possible if the dimensions, impurity concentration, etc. of the MOS transistors NM1, NM2 are appropriately selected. By doing so, when the input voltage Vin increases, Vgsnm1 decreases in a super linear manner, so that the input / output characteristics become super linear characteristics as shown by the dotted line in FIG.

  Here, as the range of Vgsnm1 corresponding to the range that the input voltage Vin can take, a range in which the relationship between Vgsnm1 and the channel current Inm1 is almost linear (for example, “a small bend range” in FIG. 2A) is used. Think about the case. In this case, if the channel current Inm1 is linearly reduced as the output voltage Vout increases, the Vgsnm1 decreases almost linearly. Therefore, the input / output characteristic in this case is merely a larger slope than that of a normal source follower circuit as indicated by a one-dot chain line in FIG.

  For the above reasons, the range of Vgsnm1 in the range that can be taken by the input voltage Vin needs to be a range in which the channel current Inm1 increases in a super linear manner as Vgsnm1 increases. The present invention is based on such a principle. Hereinafter, first to third embodiments in which the functions of the voltmeter 16 and the control type current source 20 of FIG. 1 are realized by MOS transistors or the like will be described. In addition, in each figure, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

[First Embodiment]
FIG. 3 is a circuit diagram of the nonlinear amplifier circuit 40 according to the first embodiment of the present invention. The first embodiment corresponds to claims 1 and 2. As shown in the figure, the non-linear amplifier circuit 40 includes a constant voltage source 12, MOS transistors NM1, NM2, P-channel enhancement type MOS transistors PM1, PM2, N-channel enhancement type MOS transistor NM3, and an output terminal 24. It consists of and.

  The MOS transistors PM1 and PM2 constitute a current mirror circuit, and the MOS transistor NM3 corresponds to the adjustment MOS transistor described in the claims. All the MOS transistors NM1, NM2, NM3, PM1, and PM2 are operated in the saturation region. Therefore, the constant voltage Vcc is, for example, about 5 V, the input voltage Vin is, for example, 2 V to 3 V, and the output voltage Vout is, for example, 2 V to 3 V. Here, as shown in the figure, if the channel currents of the MOS transistors PM1 and PM2 are Ipm1 and Ipm2, respectively, and the channel current of the MOS transistor NM3 is Inm3, the following equation is established.

Ipm2 = Ipm1 = Inm3 (3)
Vout = Vin−Vgsnm1 (4)
If the outflow current from the output terminal 24 can be ignored, the following equation is established.
Inm2 = Inm1 + Ipm2 (5)
In the MOS transistor NM3, the gate voltage is equal to the output voltage Vout, and the source terminal is grounded. That is, the gate-source voltage of the MOS transistor NM3 is equal to the output voltage Vout. Therefore, when the output voltage Vout rises due to the rise of the input voltage Vin, the gate current-source voltage of the MOS transistor NM3 rises, so that the channel current Inm3 increases. At this time, the channel currents Ipm1 and Ipm2 of the MOS transistors PM1 and PM2 also increase from the relationship of the expression (3).

  Since the MOS transistor NM2 is biased so that the channel current Inm2 becomes constant, the channel current Inm1 of the MOS transistor NM1 decreases by the increase of the channel current Inm3 from the relationship of the equation (5). That is, when the output voltage Vout increases as the input voltage Vin increases, the channel current Inm1 decreases and Vgsnm1 decreases. Therefore, if the design is such that Vgsnm1 decreases in a super linear manner as the input voltage Vin increases as described above, the input / output characteristics become super linear characteristics.

Here, a method for further enhancing the super linear characteristics from another point, not only from the characteristics of Vgsnm1 and the channel current Inm1 of the MOS transistor NM1 described above, will be considered.
In a range where the channel current Inm1 increases in a super linear manner with respect to the increase in Vgsnm1, when the channel current Inm1 decreases linearly, the Vgsnm1 decreases in a super linear manner. This can be seen, for example, by looking at the “bending range” in FIG. That is, the decrease amount of Vgsnm1 when the channel current Inm1 decreases from 3 to 2 is about 0.5, but the decrease amount of Vgsnm1 when the channel current Inm1 decreases from 2 to 1 is about three times. I understand. Therefore, if the channel current Inm1 decreases in a super linear manner as the input voltage Vin increases, the Vgsnm1 decreases further in a super linear manner than the channel current Inm1, and the super linear characteristic becomes stronger.

  In order to decrease the channel current Inm1 in a super linear manner with respect to the increase in the input voltage Vin, from the relationship of the equations (3) and (5), if the channel current Inm3 is increased in a super linear manner with respect to the increase in the input voltage Vin. Good. Therefore, in order to enhance the super linear characteristic, the channel current Inm3 may increase in a super linear manner in the range where the output voltage Vout (that is, the gate-source voltage of the MOS transistor NM3) takes the minimum value to the maximum value. desirable. In order to do so, the size, impurity concentration, etc. of each part of the MOS transistor NM3 may be appropriately selected.

  Although the channel current Inm2 of the MOS transistor NM2 is constant, as shown in the equations (3) and (5), the channel currents Inm3, Ipm1, and Ipm2 of the MOS transistors NM3, PM1, and PM2 are the same as those of the MOS transistor NM2. It is always smaller than the channel current Inm2. Therefore, it is necessary to select dimensions, impurity concentrations, and the like of each part of the MOS transistors NM2, PM1, and PM2 so that the channel currents Inm3, Ipm1, and Ipm2 are smaller than the channel current Inm2 within the range that the input voltage Vin can take.

[Second Embodiment]
FIG. 4 is a circuit diagram of a nonlinear amplifier circuit 60 according to the second embodiment of the present invention. The second embodiment corresponds to claims 1 and 3. The nonlinear amplifier circuit 60 of the second embodiment includes a resistor R between the connection node of the drain terminal and the output terminal 24 of the MOS transistor PM2 and the source terminal of the MOS transistor NM1 in the nonlinear amplifier circuit 40 of the first embodiment. Are connected in series. Other configurations are the same as those of the first embodiment.

  Here, the current flowing out from the output terminal 24 is negligible, and the voltage drop (absolute value) at the resistor R is Vr. At this time, the channel current Ipm2 of the MOS transistor PM2 flows through the resistor R in the direction from the output terminal 24 side to the MOS transistor NM2 side. Therefore, the output voltage Vout becomes higher than the source voltage (Vin−Vgsnm1) of the MOS transistor NM1 by the voltage drop at the resistor R as shown in the following equation.

Vout = Vin−Vgsnm1 + Vr (6)
As described in the first embodiment, the channel currents Inm3, Ipm1, and Ipm2 of the MOS transistors NM3, PM1, and PM2 increase super linearly as the input voltage Vin increases. For this reason, the voltage drop Vr at the resistor R through which the channel current Ipm2 flows also increases super linearly as the input voltage Vin increases.

  Accordingly, in the nonlinear amplifier circuit 60 of the second embodiment, the super linear characteristic is stronger than that of the first embodiment by the amount that the voltage drop Vr at the resistor R increases super linearly. Note that the gate terminal of the MOS transistor NM3 may be connected not to the connection node between the MOS transistor NM1 and the resistor R but to the connection node between the resistor R and the output terminal 24. Also in this case, the gate voltage of the MOS transistor NM3 increases as the input voltage Vin increases, so that the same effect as described above can be obtained.

[Third Embodiment]
FIG. 5 is a circuit diagram of a nonlinear amplifier circuit 80 according to the third embodiment of the present invention. The third embodiment corresponds to claims 1, 3, and 4. In the nonlinear amplifier circuit 80 of the third embodiment, the resistance R of the nonlinear amplifier circuit 60 of the second embodiment is replaced with the channel resistance of an N-channel depletion type MOS transistor NM4, and the gate terminal of the MOS transistor NM4 is replaced with a voltage. This is connected to the positive electrode of the source 12. Other configurations are the same as those of the second embodiment.

  The MOS transistors NM1 to NM4, PM1, and PM2 are operated in the saturation region. Therefore, the constant voltage Vcc is, for example, about 5 V, the input voltage Vin is, for example, 2 V to 3 V, and the output voltage Vout is, for example, 2 V to 3 V. Since the bulk voltage of the MOS transistor NM4 is fixed at 0V, when the input voltage Vin increases, the source voltages of the MOS transistors NM1 and NM4 increase, and the source-bulk voltage of the MOS transistor NM4 increases. In general, a MOS transistor has a channel resistance that increases as the source-bulk voltage increases. Therefore, the channel resistance of the MOS transistor NM4 increases as the input voltage Vin increases.

Here, assuming that the resistance value of the channel of the MOS transistor NM4 is Rch and the outflow current from the output terminal 24 can be ignored, the output voltage Vout in the third embodiment is expressed by the following equation.
Vout = Vin−Vgsnm1 + (Rch × Ipm2) (7)
In view of the above equation and the increase in the channel resistance Rch described above, the second embodiment and the third embodiment are compared.

  In the expression (6) of the second embodiment, the voltage drop Vr at the resistor R is a product of a fixed resistance value and Ipm2 that increases in a super linear manner with respect to the input voltage Vin. In Expression (7), the term corresponding to Vr in Expression (6) is the product of the channel resistance Rch that increases as the input voltage Vin increases and Ipm2 that increases superlinearly with respect to the input voltage Vin. That is, compared with the second embodiment in which the resistance value of the resistor R is fixed, the third embodiment has a super linear characteristic that is increased by an increase in the channel resistance Rch. In order to obtain stronger super linear characteristics, it is desirable that the channel resistance Rch increases super linearly with respect to the source-bulk voltage.

  However, even if the channel resistance Rch increases sub-linearly as the source-bulk voltage increases, the super linear characteristic is stronger than in the second embodiment as long as the channel current Ipm2 increases as the input voltage Vin increases. Furthermore, in the third embodiment, since the channel of the MOS transistor NM4 is used as a resistor, a larger resistance can be obtained with a smaller area than when the resistor R is formed by diffusion or polysilicon in the second embodiment.

The gate terminal of the MOS transistor NM3 may be connected to the connection node between the MOS transistor NM4 and the output terminal 24 instead of the connection node between the MOS transistors NM1 and NM4. Also in this case, the gate voltage of the MOS transistor NM3 increases as the input voltage Vin increases, so that the same effect as described above can be obtained.
Further, the MOS transistors NM2 and NM4 need to be depletion type. This is because the channel current Ipm2 supplied from the current mirror circuit needs to flow regardless of the input current Vin and the output voltage Vout. Since the MOS transistor NM1 must flow the channel current Inm1 regardless of the input voltage Vin, the depletion type is desirable in consideration of the threshold voltage, but the enhancement type may also be used. The MOS transistors PM1, PM2, and NM3 may be of a depletion type.

[Additional matters of the present invention]
As described above, the variations of the present invention have been described as the first to third embodiments in the order of increasing super linear characteristics. For example, depending on how much super linear characteristics are required, for example, first to third implementations. Any one of the forms may be used. For example, when a weak super linear characteristic is required, the circuit configuration of the first embodiment may be used. Conversely, when a weak super linear characteristic is required, the circuit configuration of the third embodiment may be used. .

  Further, in each of the first to third embodiments, the strength of the super linear characteristic can be finely adjusted, for example, by using any part of the channel current characteristics in the MOS transistors NM1 and NM3. In particular, in the second embodiment, the super linear characteristic can be finely adjusted by the resistance value of the resistor R, and a variable resistor may be used as the resistor R. In the third embodiment, the channel resistance Rch can be finely adjusted according to the impurity concentration in the channel region.

  Hereinafter, the nonlinear amplifier circuit of the present invention and the correction circuit of FIG. The correction circuit of Patent Document 1 uses a portion where super linear characteristics appear in one element (collector current of the transistor Q1) in order to obtain nonlinear input / output characteristics. On the other hand, in the present invention, if the dimensions, impurity concentration, etc. of each element are appropriately selected, the super linear characteristics of the plurality of elements such as MOS transistors NM1, NM3, NM4 are overlapped to enhance the super linear characteristics. Can do.

  Further, in the correction circuit of Patent Document 1, when the input voltage Sin increases, the base-emitter voltage of the transistor Q1 decreases, and the collector current and the current amount of the entire circuit decrease. Therefore, when the input voltage increases rapidly, the increase in output voltage is delayed. On the other hand, in the present invention, the current flowing through the entire circuit in FIGS. 3, 4 and 5, that is, the current Ivcc supplied from the voltage source 12 is expressed by the following equation.

Ivcc = Inm1 + Ipm1 + Ipm2 = Inm2 + Ipm1 (8)
In the present invention, since the operation is performed so that Inm2 is constant, when the input voltage Vin rises, Ipm1 rises due to the rise of the output voltage Vout, and Ivcc rises. Therefore, in the present invention, the response speed when the input rises is fast.

  As described above in detail, the nonlinear amplifier circuit of the present invention can be used as a signal processing circuit that requires super linear characteristics, and can adjust the strength of the super linear characteristics.

It is a circuit diagram which shows the principle of the nonlinear amplifier circuit of this invention. It is explanatory drawing which shows which range of channel current characteristic should be used in order to obtain a super linear characteristic. 1 is a circuit diagram of a nonlinear amplifier circuit according to a first embodiment of the present invention. FIG. 4 is a circuit diagram of a nonlinear amplifier circuit according to a second embodiment of the present invention. It is a circuit diagram of the nonlinear amplifier circuit which concerns on the 3rd Embodiment of this invention.

Explanation of symbols

8, 40, 60, 80 Nonlinear amplifier circuit 12 Constant voltage source 16 Voltmeter 20 Control type current source 24 Output terminals NM1, NM2, NM3, NM4 N channel type MOS transistors PM1, PM2 P channel type MOS transistors R Resistance

Claims (4)

An N-channel input MOS transistor having a drain connected to the positive voltage line and receiving an input signal at the gate, a drain connected to the source side of the input MOS transistor, and a constant channel current A source follower circuit having a load MOS transistor that receives a gate voltage and a source voltage so as to flow,
And a feedback circuit that reduces the channel current of the input MOS transistor as the source voltage of the input MOS transistor is higher. The nonlinear amplifier circuit according to claim 1,
The feedback circuit includes a current mirror circuit having two P-channel MOS transistors, and an N-channel adjustment MOS transistor whose gate is connected to the source side of the input MOS transistor,
The channel current of one P-channel MOS transistor and the channel current of the input MOS transistor are supplied as the channel current of the load MOS transistor, and the other P-channel MOS transistor Each circuit element is connected so that the channel current is supplied as the channel current of the adjustment MOS transistor,
A nonlinear amplifier circuit characterized in that the source voltage of the input MOS transistor is used as an output. The nonlinear amplifier circuit according to claim 1,
The feedback circuit includes a current mirror circuit having two P-channel MOS transistors, and an N-channel adjustment MOS transistor whose gate is connected to the source side of the input MOS transistor,
The channel current of one P-channel MOS transistor and the channel current of the input MOS transistor are supplied as the channel current of the load MOS transistor, and the other P-channel MOS transistor Each circuit element is connected so that the channel current is supplied as the channel current of the adjustment MOS transistor,
A resistor element connected between the drain of one of the P-channel MOS transistors and the source of the input MOS transistor;
A non-linear amplifier circuit characterized in that the drain voltage of one of the P-channel MOS transistors is output. The nonlinear amplifier circuit according to claim 3, wherein
The non-linear amplifier circuit, wherein the resistance element is a channel resistance of an N-channel MOS transistor that receives a positive constant voltage at a gate.

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