JP2006093676A - Imaging device and imaging system provided with it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device capable of performing precise readout of signal charge. <P>SOLUTION: The peripheral region of a photoelectric conversion region 400 in which a photoelectric conversion element is formed has common output line formation regions 401a and 401b in which common output lines for transmitting electric signals from the photoelectric conversion element are formed. In an in-layer lens formation region 402 including the photoelectric conversion region 400 and the peripheral region, a plurality of in-layer lenses are formed at constant pitches. The plurality of in-layer lenses located at the outer peripheral portion of the in-layer lens formation region 402 do not overlap the common output line. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an imaging device used for a scanner, a video camera, a digital still camera, and the like.

  In recent years, a solid-state imaging device called a CMOS sensor using a CMOS process has attracted attention. The CMOS sensor is expected to be used particularly for a portable information device because of easy mounting of peripheral circuits and low voltage driving. On the other hand, the performance required for the solid-state imaging device is also advanced, and the increase in the number of pixels and the reduction in size are regarded as indispensable issues in development.

  In a solid-state imaging device, when the number of pixels is increased, the pixel size must be reduced. When the pixel size is reduced, the amount of light incident on the pixel is reduced, resulting in a decrease in sensitivity. When the sensitivity is lowered, the SN ratio is deteriorated and the image quality is deteriorated. For this reason, when reducing the pixel size, how to maintain high sensitivity becomes a problem. As a technique for maintaining high sensitivity, a method of forming an on-chip microlens above (more specifically, the uppermost part) above a light receiving part (photodiode) that constitutes a pixel is known.

  However, with further miniaturization of pixels, it is necessary to further improve sensitivity. It is difficult to obtain sufficient light collection efficiency only by forming the above-described on-chip microlens on the top. Therefore, in order to further improve the light collection efficiency, an in-layer lens structure has been proposed in which a lens is formed not only at the uppermost part of the laminated structure but also inside (see Patent Documents 1 and 2). This intralayer lens is formed in the interlayer film immediately above the light receiving portion where photoelectric conversion is performed. Similar to the on-chip microlens, incident light is refracted at the interface on the upper surface side or lower surface side of the in-layer lens and guided to the light receiving section. When the in-layer lens and the on-chip microlens are used in combination, the light collected by the on-chip lens can be further collected by the in-layer lens, and the light collection efficiency of the entire solid-state imaging device can be further increased. .

  FIG. 13 shows a schematic configuration of a MOS type sensor to which a solid-state imaging device including the above-described intralayer lens is applied. This MOS type sensor includes the following configuration. Reference numeral 100 denotes a sensor array in which a plurality of photoelectric conversion elements 110 are two-dimensionally arranged. Reference numeral 120 denotes a vertical shift register circuit that selects the photoelectric conversion elements 110 in units of rows. A line memory 130 includes a signal component holding capacitor Cts and a reset component holding capacitor Ctn for holding the signal component (S) and the reset (noise) component (N) of the photoelectric conversion element 110 selected by the vertical shift register circuit 120, respectively. Circuit. Reference numeral 140 denotes a horizontal shift register circuit that selects two pieces of data simultaneously from one row of signal data held in the line memory circuit 130. Reference numerals 150a and 150b denote S-N readout circuits that amplify and output a difference signal (hereinafter referred to as S-N) between the signal component (S) and the reset component (N) for the data simultaneously selected by the horizontal shift register circuit 140. .

  In the S-N read circuit 150a, the S-common output line Ch1s is connected to one input, and the N-common output line Ch1n is connected to the other input. The S-N readout circuit 150b has one input connected to the S-common output line Ch2s and the other input connected to the N-common output line Ch2n. The N-common output lines Ch1n and Ch2n and the S-common output lines Ch1s and Ch2s are common output lines 160.

  The S-common output line Ch1s is connected in common to a line including the storage capacitor Cts of the odd-numbered photoelectric conversion elements 110. A line including the storage capacitor Ctn of the photoelectric conversion elements 110 in the odd-numbered columns is commonly connected to the N-common output line Ch1n. The S-common output line Ch2s is commonly connected to a line including the storage capacitor Cts of the even number of photoelectric conversion elements 110. A line including the storage capacitor Ctn of the photoelectric conversion elements 110 in the even columns is connected in common to the N− common output line Ch2n.

Reading of data from the line memory circuit 130 to the common output line 160 is determined by the following capacity relationship. One is a wiring capacitance generated between the holding capacitor Ct included in the line memory circuit 130 and the common output line 160 mainly to the ground point. The other is a capacitance Ch that is a capacitance between the source and gate and between the source and back gate of the MOS switch connected to the common output line 160. Then, reading is performed according to a gain determined by these capacity division ratios (Ct / (Ct + Ch)). In each of the S-N read circuits 150a and 150b, the signal charge (S) is read to the S-common output line according to the capacitance division ratio gain. Similarly, the reset component (N) is read out to the N-common output line according to the capacitance division ratio gain, and these differential signals (A × (Cts / (Cts + Chs) Vs−Ctn / (Ctn + Chn) Vn)) are output. The Here, A represents the amplification factor of the amplifier. According to this S-N reading, the noise component (fixed pattern noise generated in the pixel) included in the signal charge is canceled by taking the differential signal.
: US 5796154 : US 6030852

  However, the solid-state imaging device having the above-described conventional intralayer lens has the following problems.

14A to 14C show the procedure for forming the inner lens. The intralayer lens is generally formed by the following procedure. First, the element isolation region 201, the photodiode region 202, the insulating film 203, and the light shielding film 204 are formed in a predetermined order on the semiconductor substrate 200, and the surface (the upper surface of the insulating film 203) is planarized. Subsequently, an in-layer lens material film 205 made of SiN, SiON, or SiO ₂ is formed on the planarized surface by a CVD method (chemical vapor deposition method), and an etching mask 206 is further formed thereon by a photolithography process. (See FIG. 14A). This etching mask 206 is a mask for forming an inner lens in the inner lens material film 205, and is arranged in an island shape so that the mask portion is located immediately above each photodiode region 202.

Subsequently, the etching mask 206 is reflowed by heat treatment so that the mask portion has a convex lens shape 206a having substantially the same shape as that of the target intralayer lens (see FIG. 14B). Then, an etching gas such as CF ₄ , CHF ₃ , O ₂ , Ar, and He is introduced and gas etching is performed on the entire inner lens forming film 205, so that the convex lens shape 206 a of the etching mask 206 is formed into the inner lens material. It transfers to the film | membrane 205 (refer FIG.14 (c)). In this way, the in-layer lens 207 is obtained. Thereafter, a planarizing film (insulating film) is formed, and a color filter layer and a microlens are appropriately formed thereon.

  In the above-described intra-layer lens formation process, the intra-layer lens is formed on each photoelectric conversion element 110 of the sensor array 100. Therefore, the intra-layer lens formation film 205 is the region of the sensor array 100 (photoelectric conversion region). ) Formed throughout. In the vicinity of the outer periphery of the inner lens forming film 205 (near the boundary with the region where the inner lens is not formed), there are variations in the conditions during gas etching. Therefore, the size and dielectric constant of the intralayer lens formed in the vicinity of the outer periphery may be different. For example, in the vicinity of the outer peripheral portion of the in-layer lens forming film 205, the supply of the etching gas becomes non-uniform and the size of the convex lens shape varies. Further, the plasma density is different between the vicinity of the outer peripheral portion and the central portion of the inner lens forming film 205. As a result, the plasma damage differs between the vicinity of the outer peripheral portion and the central portion, and the dielectric constant varies. Thus, when there is variation in the size and dielectric constant of the in-layer lens, the light condensing efficiency to the photoelectric conversion element 110 (photodiode region 202) varies depending on the location, resulting in variation in light output and reduction in sensitivity. .

  In addition, the problem of the above-mentioned variation in light output and reduction in sensitivity is that the in-layer lens material film is arranged so that the in-layer lens near the outer periphery that causes variations in the size and dielectric constant of the lens deviates from the photoelectric conversion region. This can be solved by widening the formation range of 205. Specifically, the formation range of the in-layer lens material film 205 is expanded from the photoelectric conversion region to the peripheral portion. The widening width is 1 pixel or more, more desirably about 5 to 10 pixels. According to this configuration, the intralayer lens formed in the periphery of the photoelectric conversion region is treated as a simple intralayer lens that is not intended to collect light, so there is no problem even if the lens size or the dielectric constant varies. Never become. Further, in the photoelectric conversion region, an intra-layer lens having substantially the same size and dielectric constant can be formed, and a desired light collection efficiency can be achieved. However, in this case, the following problems occur.

  In the MOS sensor shown in FIG. 13, since the common output line 160 is usually provided in the periphery of the photoelectric conversion region, the dummy inner lens may be located immediately above or directly below the common output line. Here, consider a case where a dummy inner lens is formed on a common output line. FIG. 15 is a conceptual plan view of a CMOS area sensor when a dummy inner lens is formed on a common output line, and FIG. 16 is a schematic sectional view taken along line AA of FIG.

  Referring to FIG. 15, common output line formation regions 301 a and 301 b are arranged on both sides of the photoelectric conversion region 300 where the photoelectric conversion elements 110 of the sensor array 100 are formed. The common output line formation regions 301a and 301b are connected to both inputs of the S-N read circuit 150b and the S-common output line Ch1s and the N-common output line Ch1n respectively connected to the input of the SN read circuit 150a. An S common output line Ch2s and an N common output line Ch2n are formed. The inner lens forming region 302 where the inner lens and the dummy inner lens are formed is formed over the entire region of the photoelectric conversion region 300 and its peripheral region, and the outer peripheral portion of the inner lens forming region 302. Overlaps regions 301a and 310b where common output lines are formed.

  As shown in FIG. 16, in the photoelectric conversion region 300, an intralayer lens 207 is formed immediately above the photodiode region 202. In an area other than the photoelectric conversion area 300, that is, in the dummy area, the dummy inner lens 207a is formed at the same pitch as the inner lens 207, and the common output line Ch1s is formed in an area corresponding to the common output line forming area 301a. , Ch1n respectively corresponding to wiring layers 208a and 208b are formed. Another wiring layers 209a and 209b are further formed below the wiring layers 208a and 208b. Although not shown in FIG. 16, wirings corresponding to the common output lines Ch2s and Ch2n are also formed in the region corresponding to the common output line formation region 301a of the dummy region.

  In the case of the above configuration, electric lines of force e as shown in FIG. 17 are generated between the wiring layers 208a and 208b. The pitch of the wiring layers 208a and 208b is set regardless of the pitch of the dummy inner lens 207a. Therefore, the overlapping area of the dummy inner lens 207a and the wiring layer 208a is different from the overlapping area of the dummy inner lens 207a and the wiring layer 208b. For this reason, the coupling capacitance (density of electric lines of force e) generated between the wiring layer 208a and other wiring differs from the coupling capacity (density of electric lines of force e) generated between the wiring layer 208b and other wirings. . This is because the electric lines of force are amplified by the dummy intra-layer lens having a high dielectric constant, but the ratio of amplification is also different because the pitch is different.

  A wiring layer 208a (common output line Ch1s) which is an S-common output line corresponding to the signal component (S), and a wiring layer 208b (common output line Ch1n) which is an N-common output line corresponding to the reset component (N); In some cases, the coupling capacities for the other wiring layers are different. Then, the level of noise at the input of the SN read circuit 150a differs between the S-common output line and the N-common output line. For this reason, it becomes impossible to completely cancel the noise appearing on the S-common output line and the noise appearing on the N-common output line. For this reason, noise is included in the output of the SN read circuit 150a. A similar noise problem occurs in the SN read circuit 150b.

  The coupling capacitance is also a problem in other readout circuits other than the SN readout circuit. Specifically, the signal component (S) from each photoelectric conversion element is provided with a plurality of common output lines supplied in units of columns, and is configured to amplify the signal component (S) supplied to each common output line. In this case, the read circuit is provided. In this case, when the coupling capacitance occurs, the signal level output through each common output line varies, and as a result, the signal component (S) cannot be read out accurately.

  The coupling capacitance causes attenuation of the output of the readout circuit. Specifically, when a coupling capacitance is generated between the common output wiring and another wiring, the capacitance Ch increases, and as a result, the capacitance division ratio (Ct / (Ct + Ch)) decreases, and the SN reading is performed. The output of the circuit (signal component (S)) is attenuated. If the attenuation of the output is large, it is difficult to accurately read out the signal component (S), and high sensitivity cannot be maintained.

  An object of the present invention is to solve the above-described problems and provide an imaging apparatus capable of accurately reading a signal component (S) and an imaging system using the imaging apparatus.

To achieve the above object, the present invention is arranged in a photoelectric conversion region including a plurality of pixels arranged on a semiconductor substrate, a peripheral circuit region for reading a signal from the photoelectric conversion region, and the peripheral circuit region, a common output line for transmitting signals from said plurality of pixels, said common output line on the layer containing a layer lens disposed through an insulating film, a color filter disposed on said layer lens And the micro lens disposed on the color filter, the intra-layer lens is disposed so as not to overlap the common output line, and the color filter is disposed also on the peripheral circuit region. It is characterized by being.

  According to the present invention, since the effect of the existing structure of improving the light collection efficiency by arranging the intralayer lens is maintained, there is no influence that the coupling capacity of each common output line is different. SN reading can be performed, and the noise removal rate is improved.

  Next, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a conceptual plan view of a solid-state imaging device according to a first embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view taken along line AA of FIG. FIG. 3 is a schematic configuration diagram of the solid-state imaging device of the present embodiment.

  The solid-state imaging device of the present embodiment is basically the same as that shown in FIG. 13 except that the line memory circuit and the readout circuit are different. In FIG. 3, the same components as those shown in FIG. 13 are denoted by the same reference numerals.

  The line memory circuit 132 includes a holding capacitor Cts and a holding capacitor Ctn that hold the signal component (S) and the reset component (N) of the photoelectric conversion element 110 selected by the vertical shift register circuit 120, respectively. The horizontal shift register circuit 140 selects data one by one from the signal data for one row held in the line memory circuit 13. The SN read circuit 150 amplifies and outputs a difference signal (hereinafter referred to as SN) signal between the signal component (S) and the reset component (N) for the data selected by the horizontal shift register circuit 140.

  An S-common output line Ch1s is connected to one input of the SN read circuit 150, and an N-common output line Ch1n is connected to the other input. A line including the storage capacitor Cts of the photoelectric conversion element 110 in each column is connected in common to the S-common output line Ch1s. A line including the storage capacitor Ctn of the photoelectric conversion element 110 in each column is commonly connected to the N-common output line Ch1n.

  In the solid-state imaging device according to the present embodiment, the inner lens near the outer periphery that causes variations in the size and dielectric constant of the lens is formed as a dummy inner lens in the periphery of the photoelectric conversion region of the sensor array 100. ing. In addition, the dummy inner lens does not overlap the common output line 160. The specific structure will be described below with reference to FIGS.

  As shown in FIG. 1, common output line formation regions 401a and 401b are arranged on both sides of a photoelectric conversion region 400 where the photoelectric conversion elements 110 of the sensor array 100 are formed. The interval between each of the common output line formation regions 401a and 401b and the photoelectric conversion region 400 is approximately on the order of 10 to several hundred μm although it varies depending on the design conditions. In the common output line formation regions 401a and 401b, an S-common output line Ch1s and an N-common output line Ch1n respectively connected to the input of the SN read circuit 150 are formed.

  In the in-layer lens formation region 402, in-layer lenses are formed at a constant pitch (same as the pixel pitch). The size of the in-layer lens is usually on the order of 1 to 10 μm. The in-layer lens formation region 402 covers a range including the entire region of the photoelectric conversion region 400 and its peripheral region. However, it does not overlap with the common output line formation regions 401a and 410b. The intralayer lens formed on the peripheral region is a dummy intralayer lens.

  As shown in FIG. 2, in the photoelectric conversion region 400, an intralayer lens 207 is formed immediately above the photodiode region 202. In an area other than the photoelectric conversion area 400, that is, in the dummy area, dummy inner lenses 207a are formed at the same pitch as the inner lenses 207. Wiring layers 208a and 208b corresponding to the common output lines Ch1s and Ch1n are formed in the area corresponding to the common output line formation area 401a. Another wiring layers 209a and 209b are further formed below the wiring layers 208a and 208b.

  According to the above structure, since the dummy inner lens 207a does not overlap the wiring layers 208a and 208b, there is no variation in coupling capacitance that occurs between the wiring layers 208a and 208b and other wirings. For this reason, the difference in noise at the input of the SN read circuit 150 is small between the S-common output line and the N-common output line, and appears in the S-common output line and the N-common output line. Noise can be canceled appropriately. Therefore, at the output terminal of the SN reading circuit 150, a signal can be efficiently obtained out of the signal and noise (reset component) generated by the photoelectric conversion element 110, and accurate SN reading can be performed. it can. Here, “non-overlapping” means an intra-layer lens and a common output line. The intra-layer lens located above the semiconductor substrate in the stacking direction is arranged on the same plane as the plane on which the common output line is arranged. When projected from the vertical direction, the projection of the in-layer lens does not overlap the common output line. As shown in FIG. 2, when viewed in a cross-sectional view, the inner lens 207a does not overlap when moved in a direction perpendicular to the surface on which the common output line is arranged. The vertical relationship between the in-layer lens and the common output line may be reversed. In the following embodiments, “does not overlap” refers to such a state.

  When a coupling capacitance amplified by the dummy inner lens 207a is generated between the common output wiring and the other wiring, the capacitance Ch increases, and as a result, the capacitance division ratio (Ct / (Ct + Ch)) decreases. , The output (signal charge (S)) of the SN read circuit 150 is attenuated. In the present embodiment, since the coupling capacitance is not amplified by the dummy intra-layer lens, such signal charge (S) is not attenuated, so that high sensitivity can be maintained.

(Embodiment 2)
The solid-state imaging device according to the second embodiment of the present invention uses the wiring layers 209a and 209b as common output lines Ch1s and Ch1n, respectively, instead of the wiring layers 208a and 208b in the structure shown in FIG. The layers in which the inner lens 207 and the dummy inner lens 207a are formed are divided into a layer including the wiring layers 208a and 208b (first wiring layer) and a layer including the wiring layers 209a and 209b (second wiring layer). It forms so that it may be located between. Thus, the dummy inner lens 207a is formed so as not to overlap the wiring layers 209a and 209b. In this case, the first wiring layer may be used as a light shielding film outside the photoelectric conversion region. This structure also has the same effects as the above-described accurate SN reading and maintaining high sensitivity.

  In order to make the effects of the solid-state imaging device of this embodiment easier to understand, as a comparative example, FIG. 4 shows a common output when the second wiring layer is a common output line and a dummy inner lens is arranged on the common output line. A coupling capacitance generated between a line and another wiring is schematically shown. In FIG. 4, wiring layers 209a and 209b, which are the second wiring layers, are the same as those shown in FIG. In the comparative example, a dummy inner lens 207b is formed so as to overlap with the wiring layers 209a and 209b, and a wiring layer 208 as a first wiring layer is formed above the dummy inner lens 207b. Exists. In addition, an insulating layer exists between each of the first wiring layer, the dummy inner lens 207b, and the second wiring layer.

  In the structure shown in FIG. 4, the pitch of the wiring layers 209a and 209b is set regardless of the pitch of the dummy inner lens 207b. Therefore, the overlapping area of the dummy inner lens 207b and the wiring layer 209a is different from the overlapping area of the dummy inner lens 207b and the wiring layer 209b. For this reason, the coupling capacitance (density of electric lines of force e) generated between the wiring layer 209a and other wirings is different from the coupling capacity (density of electric lines of force e) generated between the wiring layer 209b and other wirings. It will be. As a result, the noise level at the input of the S-N readout circuit differs between the S-common output line (wiring layer 209a) and the N-common output line (wiring layer 209b), and noise remains. There is.

  On the other hand, in the solid-state imaging device of the present embodiment, the dummy inner lens does not overlap with the wiring layers 209a and 209b. Therefore, in the S-common output line and the N-common output line, The coupling capacitance is not affected by the dummy inner lens. Therefore, accurate SN reading can be performed.

(Embodiment 3)
FIG. 5 is a cross-sectional view in the vicinity of the common output line of the solid-state imaging device according to the third embodiment of the present invention. In the solid-state imaging device, in the structure shown in FIG. 2, instead of the wiring layers 208a and 208b that are the first wiring layers, the wiring layers 209a and 209b that are the second wiring layers are used as the common output lines Ch1s and Ch1n, respectively. The wiring layers 209a and 209b and the wiring layers 208a and 208b located above the wiring layers 209a and 209b are structured so as not to overlap (a structure in which the first wiring layer is opened immediately above the wiring layers 209a and 209b). This structure also has the same effect of accurate SN reading and maintaining high sensitivity.

  In order to make the effects of the solid-state imaging device of the present embodiment easier to understand, as a comparative example, FIG. 6 shows a common output when the second wiring layer is a common output line and a dummy intra-layer lens is arranged on the common output line. The electric lines of force produced between a line and other wiring are shown typically. In FIG. 6, wiring layers 208a and 208b which are first wiring layers and wiring layers 209a and 209b which are second wiring layers are the same as those shown in FIG. In the comparative example, a dummy inner lens 207b is formed on the upper layer of the first wiring layer so as to overlap the wiring layers 209a and 209b. An insulating layer exists between each of the first wiring layer, the dummy inner lens 207b, and the second wiring layer.

  In the structure shown in FIG. 6, the pitch of the wiring layers 209a and 209b is set regardless of the pitch of the dummy inner lens 207b. For this reason, the overlapping area of the dummy inner lens 207b and the wiring layer 209a is different from the overlapping area of the dummy inner lens 207b and the wiring layer 209b. For this reason, the coupling capacitance (density of electric lines of force e) generated between the wiring layer 209a and other wirings is different from the coupling capacity (density of electric lines of force e) generated between the wiring layer 209b and other wirings. . As a result, the noise level at the input of the S-N readout circuit differs between the S-common output line (wiring layer 209a) and the N-common output line (wiring layer 209b), and the noise is completely canceled. You will not be able to.

  On the other hand, in the solid-state imaging device of the present embodiment, the dummy inner lens does not overlap with the wiring layers 209a and 209b. Therefore, in the S-common output line and the N-common output line, The coupling capacitance is not affected by the dummy inner lens. Therefore, accurate SN reading can be performed.

(Embodiment 4)
FIG. 7 is a conceptual plan view of a solid-state imaging device according to the fourth embodiment of the present invention, and FIG. 8 is a schematic cross-sectional view taken along line AA of FIG.

  The solid-state imaging device according to the present embodiment is applied to the circuit configuration shown in FIG. 3, and the intra-layer lens near the outer periphery that causes variations in the size and dielectric constant of the lens is a dummy layer. The inner lens is formed around the photoelectric conversion region of the sensor array 100. The dummy inner lens overlaps the common output line 160. The specific structure will be described below with reference to FIGS. 3, 7 and 8. FIG.

  As shown in FIG. 7, common output line formation regions 401 a and 401 b are arranged on both sides of the photoelectric conversion region 400 where the photoelectric conversion elements 110 of the sensor array 100 are formed. In the common output line formation regions 401a and 401b, an S-common output line Ch1s and an N-common output line Ch1n respectively connected to the input of the SN read circuit 150 are formed.

  In the in-layer lens formation region 403, in-layer lenses are formed at a constant pitch (same as the pixel pitch). The size of the in-layer lens is usually on the order of 1 to 10 μm. The in-layer lens formation region 403 extends over the entire region of the photoelectric conversion region 400 and its peripheral region, and overlaps the common output line formation regions 401a and 410b. The intralayer lens formed on the peripheral region is a dummy intralayer lens.

  As shown in FIG. 8, in the photoelectric conversion region 400, the inner lens 207 is formed at a constant pitch a (corresponding to the pitch of the photodiode region 202) immediately above the photodiode region 202. In the dummy area around the photoelectric conversion area 400, dummy inner lenses 207c are formed at the same pitch a as the inner lenses 207. In the region corresponding to the common output line formation region 401a, wiring layers 208a and 208b corresponding to the common output lines Ch1s and Ch1n, respectively, are formed at the same pitch a as the dummy inner lens 207c. Another wiring layers 209a and 209b are further formed below the wiring layers 208a and 208b.

  According to the above structure, the dummy inner lens 207c and the wiring layers 208a and 208b overlap each other. Since the pitch of the dummy inner lens 207c and the pitch of the wiring layers 208a and 208b are the same, the overlapping area of the dummy inner lens 207c and the wiring layer 208a is the overlapping area of the dummy inner lens 207c and the wiring layer 208a. Will be the same. For this reason, the noise level at the input of the S-N readout circuit 150 is the same between the S-common output line and the N-common output line, and the noise that appears on the S-common output line and the noise that appears on the N-common output line. Can be preferably canceled. Therefore, at the output terminal of the SN read circuit 150, a signal can be efficiently obtained out of the signal and noise generated in the photoelectric conversion element 110, and accurate SN read can be performed.

  As described in the problem, in the vicinity of the outer peripheral portion of the intra-layer lens forming region 403, the size of the intra-layer lens and the dielectric constant vary due to variations in conditions during gas etching. For this reason, if an intra-layer lens (dummy intra-layer lens) that has a difference in size and dielectric constant is formed on the common output line, the overlapping area of the dummy intra-layer lens 207c and the wiring layer 208a is as follows. This is different from the overlapping area of the dummy inner lens 207c and the wiring layer 208a. This makes it impossible to perform accurate SN reading as described above. In order to reduce this, it is necessary to make the inner lens formation region 403 sufficiently wide so that the inner lens that causes a difference in size and dielectric constant is located further outside the common output line formation regions 401a and 401b. is there. The distance from the both sides of the common output line formation regions 401a and 401b to the edge of the inner lens formation region 403 is one pixel or more, more desirably about 5 to 10 pixels.

(Embodiment 5)
In the solid-state imaging device according to the fifth embodiment of the present invention, in the structure shown in FIG. 8, instead of the wiring layers 208a and 208b, the wiring layers 209a and 209b are common output lines Ch1s and Ch1n, respectively. The layer in which the inner lens 207 and the dummy inner lens 207c are formed is between a layer including the wiring layers 208a and 208b (first wiring layer) and a layer including the wiring layers 209a and 209b (second wiring layer). It is formed so that it may be located. In this case, the first wiring layer may be used as a light shielding film outside the photoelectric conversion region. Even in this structure, as in the case of the fourth embodiment, accurate SN reading can be performed.

(Embodiment 6)
FIG. 9 is a cross-sectional view of the vicinity of the common output line of the solid-state imaging device according to the sixth embodiment of the present invention. In the solid-state imaging device, in the structure shown in FIG. 8, instead of the wiring layers 208a and 208b that are the first wiring layers, the wiring layers 209a and 209b that are the second wiring layers are used as the common output lines Ch1s and Ch1n, respectively. The wiring layers 209a and 209b and the wiring layers 208a and 208b located above the wiring layers 209a and 209b are structured so as not to overlap (a structure in which the first wiring layer is opened immediately above the wiring layers 209a and 209b). Even in this structure, as in the case of the fourth embodiment, accurate SN reading can be performed.

(Embodiment 7)
FIG. 18 is a cross-sectional view of an imaging apparatus according to the seventh embodiment of the present invention. In the present embodiment, the arrangement of the layer including the inner lens, the color filter layer, and the microlens layer will be described.

  1800 is a semiconductor substrate on which a photoelectric conversion unit is arranged, and 1802 is a photoelectric conversion unit. For example, as a photoelectric conversion unit, there is a photodiode configured to include a P-type semiconductor region and an N-type semiconductor region. In addition, an amplifying configuration in which an amplifying element is provided for each pixel and for each of a plurality of pixels can be employed.

  Reference numeral 1803 denotes an interlayer film for insulating the wiring from the semiconductor substrate or between the wirings. Reference numeral 1804 denotes a wiring arranged in the pixel region.

  Reference numeral 1807 denotes an in-layer lens. This intra-layer lens is provided corresponding to the photoelectric conversion portion in the pixel region, and is disposed on the layer including the common output line via an insulating layer.

  Reference numerals 1808a and 1808b are common output lines. One functions as an S-common output line for transmitting a signal corresponding to a signal component, and the other functions as an N-common output line. Reference numerals 1809a and 1809b denote wirings, for example, wirings for driving MOS transistors arranged in the peripheral circuit region. 1810 is a planarizing film, 1811 is a color filter, 1812 is a planarizing film, and 1813 is a microlens. Reference numeral 1814 denotes a pixel region, and reference numeral 1815 denotes a peripheral circuit region for reading a signal from the pixel region.

  Here, the lens material layer for forming the intra-layer lens is arranged including the peripheral circuit region, and forms a convex lens shape with respect to incident light in the pixel region by the formation method described above. . In the peripheral circuit region, the film thickness (lens height) of the in-layer lens is made thinner by the etching process after the resist described above is processed into a lens shape when forming the in-layer lens. Since this film thickness is reduced simultaneously by etching when processing into a lens shape, the film thickness is substantially equal to the lens material layer disposed around the inner lens in the pixel region.

In the color filter, each color is arranged corresponding to each photoelectric conversion unit in the pixel region. Also in the peripheral circuit region, color filters are arranged as dummy patterns. In FIG. 18 , the dummy pattern is composed of one color, but it can be composed of a plurality of colors. Since the color filter has a dummy pattern on the peripheral circuit region, the sagging of the microlens pattern is reduced in the region close to the peripheral circuit region of the pixel region, and the same optical characteristics as in the vicinity of the center are obtained at the end of the pixel region. It becomes possible. Similarly, the microlens is also arranged as a dummy pattern in the peripheral circuit region. Even in the in-layer lens, it is conceivable to arrange a dummy pattern in the same manner as the pixel region. However, as described above, since it affects the capacitance variation between the common output lines or between the common output line and other wirings, In the peripheral circuit region, a lens material layer having a substantially uniform film thickness remains, but is not processed into a lens shape. In addition, by leaving the lens material layer having a substantially uniform film thickness in this way, it becomes possible to reduce the film thickness of the flattening film formed after that, and the dummy pattern of the color filter and the micro lens is preferably used. Can be formed.

  The first to seventh embodiments have been described by taking the case where they are applied to the circuit configuration shown in FIG. 3 as an example, but can be applied to other circuit configurations. For example, the structure of each embodiment can be applied to the configuration of an S-N readout circuit having a plurality of S-common output lines and a plurality of N-common output lines as shown in FIG. In this case, wiring layers corresponding to the plurality of S-common output lines and the plurality of N-common output lines are formed in the common output line formation regions 401a and 401b. When the structures of the first to third and seventh embodiments are applied, accurate SN reading is performed by preventing the dummy inner lens from overlapping the wiring layer of any common output line. In addition, similar effects such as maintaining high sensitivity can be achieved. In addition, there is an effect that variation in output between the common output lines (variation in output between channels) is also reduced. When the structures of the fourth to sixth embodiments are applied, the pitch of the dummy inner lens and the pitch of the wiring layer of each common output line are made the same, so that the effect of accurate SN reading is achieved. And the effect of reducing variations in output between channels.

  Furthermore, the first to seventh embodiments can also be applied to a configuration having no SN read circuit as shown in FIG. This circuit is a MOS type sensor and is basically the same as that shown in FIG. 3 except that the line memory circuit and the readout circuit are different. The line memory circuit 133 includes a storage capacitor Cts that stores the signal component (S) of the photoelectric conversion element 110 selected by the vertical shift register circuit 120. The horizontal shift register circuit 140 selects two pieces of data simultaneously from one row of signal data held in the line memory circuit 133. The readout circuit includes gain amplifiers 152a and 152b that amplify and output data (signal component (S)) signals simultaneously selected by the horizontal shift register circuit 140, respectively. A common output line Ch1s is connected to the input of the gain amplifier 152a, and a common output line Ch2s is connected to the input of the gain amplifier 152b. The common output line Ch1s is commonly connected to a line including the storage capacitor Cts of the odd-numbered photoelectric conversion elements 110. The common output line Ch2s is commonly connected to a line including the storage capacitor Cts of the even number of photoelectric conversion elements 110.

  In the case of the circuit configuration shown in FIG. 10, wiring layers corresponding to the common output lines Ch1s and Ch2s are formed in the common output line formation regions 401a and 401b. When the structures of the first to third and seventh embodiments are applied, the signal component (S) of the signal component (S) can be obtained by preventing the dummy inner lens from overlapping the wiring layer of any common output line. Accurate readout can be performed and high sensitivity can be maintained. Even when the structures of the fourth to sixth embodiments are applied, the pitch of the dummy inner lens and the pitch of the wiring layer of each common output line are made the same so that the signal component (S) can be accurately detected. Reading can be performed.

  In the circuit configuration shown in FIG. 10, when a coupling capacitance is generated between the common output line and other wirings, the output between the gain amplifiers 152 a and 152 b varies, and therefore, based on the output of the solid-state imaging device. When displaying an image, a problem of color mixing occurs. When the structures of the first to third embodiments are applied, since no coupling capacitance is generated, the problem of color mixing can be prevented. When the structures of the fourth to sixth embodiments are applied, the coupling capacitance in each common output line can be made the same, and in this case as well, the problem of color mixing can be prevented.

  The first to third and seventh embodiments can also be applied to a circuit configuration as shown in FIG. This circuit is basically the same as that shown in FIG. 13 except for the line memory circuit and the readout circuit. The line memory circuit 131 holds the signal component (S) of the photoelectric conversion element 110 selected by the vertical shift register circuit 120. The horizontal shift register circuit 140 selects data one by one from the signal data for one row held in the line memory circuit 130. The readout circuit includes a gain amplifier 151 that amplifies and outputs the data signal (signal component (S)) selected by the horizontal shift register circuit 140. The output of the photoelectric conversion element 110 is connected in column units to a common output line 161 connected to the input of the gain amplifier 151.

  In the case of the circuit configuration shown in FIG. 11, a wiring layer corresponding to the common output line 161 is formed in the common output line formation regions 401a and 401b. By preventing the dummy inner lens from overlapping the wiring layer of the common output line, the signal component (S) can be read accurately and high sensitivity can be maintained.

  As described above, the solid-state imaging device of the present invention described in the first to seventh embodiments can be applied to a solid-state imaging system such as a scanner, a video camera, and a digital still camera. Hereinafter, the configuration and operation of a solid-state imaging system including the solid-state imaging device of the present invention will be described in detail.

  FIG. 12 is a block diagram illustrating a schematic configuration of a solid-state imaging system including the solid-state imaging device of the present invention. This solid-state imaging system includes a barrier 1, a lens 2, an aperture 3, a solid-state imaging device 4, an imaging signal processing circuit 5, an A / D converter 6, a signal processing unit 7, a timing generation unit 8, an overall control / calculation unit 9, The memory unit 10 includes a recording medium control interface unit 11, a recording medium 12, and an external interface (I / F) unit 13.

  The barrier 1 doubles as a lens switch and a main switch. The lens 2 forms an optical image of the subject on the solid-state imaging device 4. The diaphragm 3 is for changing the amount of light passing through the lens 2. The solid-state imaging device 4 is for capturing the subject imaged by the lens 2 as an image signal, and includes the structure of the solid-state imaging device according to any one of the first to sixth embodiments.

  The imaging signal processing circuit 5 performs various correction, clamping, and other processes on the image signal output from the solid-state imaging device 4. The A / D converter 6 performs analog-digital conversion of the image signal output from the solid-state imaging device 4. The signal processing unit 7 performs various corrections on the image data output from the A / D converter 6 and compresses the data. The timing generation unit 8 supplies various timing signals to the solid-state imaging device 4, the imaging signal processing circuit 5, the A / D converter 6, and the signal processing unit 7. The imaging signal processing circuit 5, A / D converter 6, signal processing unit 7, and timing generation unit 8 may be formed on the same chip as the solid-state imaging device 4.

  The overall control / calculation unit 9 controls various computations and the entire system. The memory unit 10 is for temporarily storing image data. The recording medium control interface unit 11 performs recording or reading on the recording medium 12. The recording medium 12 is a detachable recording medium such as a semiconductor memory. The external I / F unit 13 communicates with an external computer or the like.

  Next, the operation of the present solid-state imaging system will be described. When the barrier 1 is opened, the main power supply, the power supply for the control system, and the power supply for the imaging system circuits such as the A / D converter 6 are sequentially turned on. When the power is turned on, the overall control / calculation unit 9 opens the diaphragm 3 in order to control the exposure amount. The signal output from the solid-state imaging device 4 is supplied to the A / D converter 6 via the imaging signal processing circuit 5, where it is A / D converted. The A / D converted signal is supplied to the signal processing unit 7. The signal processing unit 7 calculates the exposure based on the supplied signal through the overall control / calculation unit 9. Photometry is performed by this operation, and the brightness is determined based on the result. Then, the overall control / calculation unit 9 controls the diaphragm according to the determination result.

  Next, the overall control / calculation unit 9 extracts a high-frequency component based on the signal output from the solid-state imaging device 4 and calculates the distance to the subject. Thereafter, the overall control / calculation unit 9 drives the lens 2 to determine whether or not it is in focus. When it is determined that the subject is not in focus, the overall control / calculation unit 9 drives the lens 2 again to perform distance measurement.

  After the in-focus state is confirmed, the main exposure starts. When the main exposure is completed, the image signal output from the solid-state imaging device 4 is corrected and the like in the imaging signal processing circuit 5 and then A / D converted by the A / D converter 6. The A / D converted image signal is stored in the memory unit 10 by the overall control / calculation 9 via the signal processing unit 7. Thereafter, the data stored in the memory unit 10 is recorded on a removable recording medium 12 such as a semiconductor memory through the recording medium control I / F unit 11 under the control of the overall control / calculation unit 9. Further, the image processing may be performed by directly inputting to an external computer or the like through the external I / F unit 13.

1 is a schematic plan view of a solid-state imaging device that is a first embodiment of the present invention. It is a schematic sectional drawing in the AA of FIG. 1 is a schematic configuration diagram of a solid-state imaging device according to a first embodiment of the present invention. It is a schematic diagram which shows the coupling capacitance in the comparative example of the solid-state imaging device which is the 2nd Embodiment of this invention. It is sectional drawing of the vicinity of a common output line of the solid-state imaging device which is the 3rd Embodiment of this invention. It is a schematic diagram which shows the coupling capacitance in the comparative example of the solid-state imaging device which is the 3rd Embodiment of this invention. It is a plane conceptual diagram of the solid-state imaging device which is the 4th Embodiment of this invention. It is a schematic sectional drawing in the AA of FIG. It is sectional drawing of the vicinity of a common output line of the solid-state imaging device which is the 6th Embodiment of this invention. It is a block diagram which shows an example of the circuit structure which can apply the structure of the solid-state imaging device of this invention. It is a block diagram which shows the other example of the circuit structure which can apply the structure of the solid-state imaging device of this invention. It is a block diagram which shows an example of a solid-state imaging system provided with the solid-state imaging device of this invention. It is a block diagram which shows an example of the MOS type sensor to which a solid-state image sensor provided with an in-layer lens is applied. (A)-(c) is process sectional drawing for demonstrating the formation procedure of the lens in a layer. It is a plane conceptual diagram of the conventional CMOS area sensor in which the dummy inner lens was formed on the common output line. It is a schematic sectional drawing in the AA of FIG. It is a schematic diagram which shows the coupling capacity | capacitance in the conventional solid-state image sensor provided with an in-layer lens. It is a schematic block diagram of the solid-state imaging device which is the 7th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Sensor array 110 Photoelectric conversion element 120 Vertical shift register circuit 130 Line memory circuit 140 Horizontal shift register circuit 150 SN reading circuit 160 Common output line 400 Photoelectric conversion area 401a, 401b Common output line formation area 402 Intra-layer lens formation area

Claims (6)

A photoelectric conversion region including a plurality of pixels disposed on a semiconductor substrate;
A peripheral circuit region for reading a signal from the photoelectric conversion region;
A common output line disposed in the peripheral circuit region for transmitting signals from the plurality of pixels;
An intra-layer lens disposed on the layer including the common output line via an insulating film;
A color filter disposed on the in-layer lens;
A microlens disposed on the color filter,
The image pickup apparatus, wherein the inner lens is disposed so as not to overlap the common output line, and the color filter is also disposed on the peripheral circuit region.   The signal includes a first signal component corresponding to an image signal and a second signal component corresponding to a noise signal, and the common output line transmits a first signal component to which the first signal component is transmitted. The imaging apparatus according to claim 1, further comprising: a common output line and a second common output line through which the second signal component is transmitted.   The imaging device according to claim 2, wherein the intralayer lens has a convex shape with respect to incident light.   The imaging device according to claim 3, wherein a lens material layer that forms the intra-layer lens is disposed on the peripheral circuit region with a substantially uniform film thickness.   A lens material layer having a substantially uniform film thickness is provided around the inner lens in the pixel region, and the lens material layer disposed in the pixel region is a lens material disposed on the peripheral circuit region. The imaging device according to claim 4, wherein the imaging device has substantially the same film thickness as the layer. An imaging device according to claim 1;
A lens that forms an optical image of a subject on the light receiving surface of the solid-state imaging device;
An image pickup system comprising: a signal processing unit that obtains an image signal of the subject from an output of the solid-state image pickup device.

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