JP2006092561A - Design method of interface - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a design method for composing an interface for semiconductor integrated circuit, and a bus structure or database used for the design. <P>SOLUTION: Libraries that are operation models describing operations in adaptation of a von Neumann CPU (bus structure), a Harvard CPU (bus structure) and a directional separating CPU (bus structure) are registered for each of applications A and B. In a performance table of each library, a performance index of each library is expressed as a function of a parameter such as processing capability, bus width, command quantity, or memory quantity. Software parts (hatching parts) and parts made to hardware (blank parts) in the operations are also registered. Each application A, B, etc. is successively substituted by each library, and operation simulation is performed thereto, whereby the performance of a semiconductor integrated circuit can be evaluated, and an optimum interface can be composed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a bus structure in a semiconductor integrated circuit device such as a system LSI, an interface design method, and a database for use in interface design.

  Conventionally, a portion called an interface connecting a CPU of a semiconductor circuit and a circuit controlled thereby is an important portion in performing communication between the CPU and each circuit. The central part of this interface is a signal line called a “bus”, and when sending data, a system for controlling the input and output of data such as how to acquire access rights to this bus is important. It is. In other words, the interface including the bus structure is a factor that greatly affects the performance of the final device.

  Here, as shown in FIG. 1, as a conventional bus structure, a Neumann bus structure used for a Neumann processor and a Harvard bus structure used for a Harvard processor are known. The Neumann bus structure is a structure in which only an address and data are distinguished, and the address and data are expressed by one line, or the address and data are expressed by two lines. As a Neumann bus structure, there are a multiplexer type in which addresses and data are distributed through a common bus, and a demultiplexer type in which addresses and data are separately distributed through separate buses, that is, an address bus and a data bus. Are known.

  The Harvard processor is a structure for separating the control data and the actual transfer file data from the data. The Harvard bus structure that has been developed in the past is that the address bus is further divided into an IO address bus and a memory address bus, and the data bus is divided into a control data bus and a transfer data bus. Is known).

  The multiplexer-type bus structure is a bus structure used for sequentially processing address and data control and transfer. When this is used, the processing capacity is relatively low, but the area occupied by the bus (bandwidth) Is small. The demultiplexer-type bus structure is a bus structure used for parallel processing of address control and transfer and data control and transfer. When this is used, parallel processing is possible, so the processing speed is Get higher.

In addition, the information-separated bus structure, which is a conventional Harvard bus structure, is a bus structure that is used to process both control and transfer in parallel for both address and data. The processing capacity is even higher.
US Pat. No. 5,907,698 US Pat. No. 5,541,849 US Pat. No. 6,493,351 US Pat. No. 6,516,379

  However, the present situation is that an appropriate method has not yet been established as to how to construct the interface structure when constructing a large-scale device such as a conventional system LSI. That is, the bus structure alone has advantages and disadvantages of various bus structures, and a method for uniformly evaluating these bus structures in relation to the operation of each circuit has not yet been established.

  In addition, when the scale of a semiconductor integrated circuit device becomes large and, for example, a device combining a plurality of semiconductor circuits called a system LSI is designed, a bus structure such as the conventional one described above is used when designing an interface. There is also a problem that the structure cannot be used flexibly.

  An object of the present invention is to provide a design method for constructing an interface of a large-scale semiconductor device such as a system LSI, and a bus structure and database for use in the design.

  The interface design method of the present invention uses a database storing a plurality of libraries as an operation model for each of a plurality of applications and a plurality of bus structures, and uses a control function unit of the semiconductor integrated circuit and a plurality of applications. A plurality of main parameters for finally evaluating the value of the semiconductor integrated circuit, and a plurality of subparameters that influence the main parameters are set. Step (a) for setting, step (b) for selecting the library group satisfying the target value of the main parameter by evaluating the main parameter by the sub-parameter of each library for each of the main parameter, and the above selected Evaluate multiple main parameters determined for each library group, and optimize library group By choosing, and a step (c) to determine the interface.

  By this method, it is possible to select an optimal library group by a more unified method and finally determine an optimal interface as compared to evaluating performance from all parameters at once.

  In the interface design method, before the step (a), the plurality of libraries are sequentially used as the operation models of the plurality of applications, and an operation simulation for each of the libraries is performed. The interface can be determined. Specific methods of this method include the following methods.

  For example, in the step (a), three main parameters are set, three sub parameters are set for each main parameter, and in the step (b), a three-dimensional coordinate system having the three sub parameters as coordinate axes. And a library group in which the area of the triangle determined by the values of the sub-parameters is equal to or smaller than the target value is selected, and in the step (c), a three-dimensional coordinate system having three main parameters as coordinate axes is configured, The interface can be determined from the library group having the smallest triangular area determined by the value of the main parameter obtained from the selected library group.

  In addition, after step (a) and before step (b), paying attention to a specific subparameter among the plurality of subparameters, a library group in which the specific subparameter satisfies the target value is selected, and In step (b), a library group in which the main parameters excluding the specific main parameter among the plurality of main parameters satisfy the target value is selected, and in step (c), the library in which the specific main parameter is minimized. A group can also be selected as an optimal library group.

Further, in step (a), an influence coefficient of a plurality of subparameters for the main parameter is set, and in step (b), a library that satisfies the target value of each main parameter based on the influence coefficient and the value of the subparameter. In step (b), a group is selected, and a plurality of main parameters obtained from the selected library group are weighted, and then an operation for determining the library group can be performed.

  According to the interface design method of the present invention, an interface for connecting a control function unit of a semiconductor integrated circuit and a plurality of applications using a database storing a plurality of libraries serving as operation models for each application and bus structure. As a method of designing a system, an interface for constructing a system with the performance required by the designer is synthesized by performing an operation simulation for analyzing the degree of bus congestion or evaluating the performance of the entire system. Can do.

(First embodiment)
FIG. 1 is a block diagram schematically showing structural differences between a conventional Neumann bus structure, a conventional Harvard bus structure, and a Harvard bus structure of the present embodiment.

  The Harvard bus structure in this embodiment should be a “direction separation type bus structure”, and can be said to further separate and process transfer data in the information separation type bus structure. In this direction separation type bus structure, the direction in which transfer data is sent when the target resource (controlled circuit) is arranged with the processor (control circuit) as the center is divided into “upstream” and “downstream”. Furthermore, the controlled circuit for transfer data may be divided into memory data and IO data. Here, the control data is information having control information such as recognition and response. Transfer data refers to a collection of data such as image file data.

  FIG. 2A shows a conventional bus structure. As shown in the figure, in the conventional bus structure, only one bus is provided between the CPU and the target resource (here, the primary station IO).

  On the other hand, in the direction separation type bus structure of the present embodiment, as shown in FIGS. 2B and 2C, communication between the processor (CPU) and the primary station is also performed between the upstream bus and the downstream side. It is configured to be divided into buses. Here, FIG. 2B is a diagram showing a direction-separated bus structure in the case where there are a secondary station and a tertiary station that communicate with the CPU with the primary station interposed therebetween, respectively. (C) is a diagram showing a direction separation type bus structure when the tertiary station in FIG. 2 (b) does not exist.

  3A to 3D show, in order, addresses in a Neumann multiplexer bus structure, a Neumann demultiplexer bus structure, a Harvard information separation bus structure, and a direction separation bus structure (direction type). FIG. 5 is a diagram illustrating data processing on a time axis.

  As shown in FIG. 3A, the multiplexer bus structure is a bus structure for processing addresses and data serially on one line. For example, when generating some command for the target resource A, the control address of the target resource A is specified, the control data of the target resource A is sent, the address for transfer to the target resource A is sent, and then to A Send the transfer data. When a command for “B” is generated, processing by the same procedure is performed sequentially (serially).

As shown in FIG. 3B, the demultiplexer type bus structure is a bus structure for processing addresses and data in parallel. For example, when any command is generated for the target resource A, the control data of A is sent while designating the control address of the target resource A, and the address to the target resource A is sent while the address to be transferred to A is being sent. Send transfer data. When generating a command for the target resource B, the same procedure is performed in parallel.

  As shown in FIG. 3C, the information separation type bus structure is a bus structure for processing a control address, a transfer address, control data, and transfer data in parallel. For example, when any command is generated for the target resource A, the control address of the target resource A is specified, the control data is transmitted to the target resource A, the address is transferred to the target resource A, the target The transmission of the transfer data to the resource A is processed in parallel. When generating a command for the target resource B, the same procedure is performed in parallel.

  As shown in FIG. 3D, the information separation type bus structure processes the control address, the transfer address, the control data, and the transfer data in parallel. This is a bus structure that is divided into downstream and performed in parallel. For example, when any command is generated for the target resources A, B, and C, the control addresses of the target resources A, B, and C are specified, and the upstream address and the downstream address are also specified. When an upstream address is specified, transmission of an upstream transfer address and transfer data (for example, for the target resources A and C) is transmitted via the upstream bus. When a downstream address is specified, a downstream bus is specified. Can be used to transmit the downlink transfer address and transfer data (for example, for the target resources B and A). In other words, transmission of the transfer address and transmission of the transfer data can be performed irrespective of designation of the control address and transmission of the control data.

  For example, in the case of the bus structure shown in FIG. 2B, it is assumed that the primary station IO1 is the target resource A, the primary station IO2 is the target resource B, and the secondary station is the target resource C. At this time, even when the address of the target resource A (primary station IO1) is specified, the specification of the address of the target resource A (primary station IO1) is not input to the target resource B (primary station IO2). Therefore, while the transfer address A is specified and the transfer data is transferred to the target resource A, the transfer data can be specified and sent to the target resource B. When data is input (upstream), it is possible to output data (downstream) immediately.

  FIG. 4 is a block diagram showing a resource-separated bus structure when the target resource A is a memory and the target resources B and C are IO. An operation of receiving data from the target resource C (IO2) and transferring the data to the target resource B (IO1) while simultaneously storing the data in the target resource A (memory) can be performed.

  As a result, when the conventional information separation type bus structure is used, the time required for data transfer is as follows: data transfer A, data transfer B, data transfer C and data transfer A as shown in FIG. The required time is serially added (transfer A, B, C, and A address times are the same), but when the direction separation type bus structure of this embodiment is used, it is shown in FIG. Will be shortened. That is, by dividing into an upstream bus and a downstream bus, transmission of an upstream transfer address and transfer data to the target resources A and C, and transmission of a downstream transfer address and transfer data to the target resources B and A This is because it is possible to perform the above simultaneously.

(Second Embodiment)
Next, a second embodiment relating to an IF design method including a bus structure will be described. Here, a procedure for designing an optimum IF will be described.

-Data to prepare-
Here, data (library model) necessary for performance analysis will be described first. It is necessary to create an operation model for each single application, but as one method of creating the operation model, it is basically created with software, some are created with hardware, and others are separated. The part up to is decided to be performed by hardware. The single application defines the input / output relationship of one application, and does not define the size of the range. For example, as an example of a single application, there are print data transfer operation using IrDA, mouse position data transfer using USB, and still image data compression / decompression operation using JPEG. Here, when using an application for data transfer using infrared communication called “IrDA”, for example, data to be printed must be processed in advance on the computer side. For example, in order to compress a still image, an infrared communication is performed in which data is sent after performing a process of compressing with JPEG and performing format conversion for expressing the data as infrared rays. In this case, the single application here means only the part that defines the input and output of an application called IrDA, except for the process before performing infrared communication (IrDA). .

  Here, the processing time differs depending on whether the behavior model is created by hardware or software. In the present embodiment, whether the operation model is created by hardware or software is divided at a part where each layer is clearly separated to some extent in one protocol expression.

  FIGS. 5A and 5B are diagrams showing examples of libraries and performance tables in the single applications A and B stored in the design database. For example, if there are libraries A and B of the specification level for the applications A and B, the Neumann type is used as the CPU (bus structure) for each of the applications A and B at the operation level as shown in FIG. A library serving as an operation model describing operations when a CPU (bus structure), a conventional Harvard CPU (bus structure), and a direction separation type CPU (bus structure) are employed is registered. In the performance table of each library, the performance index of each library is expressed as a function of variables (parameters) such as processing capacity (P), bus width (B), instruction amount (M), and memory amount (E). ing.

  5A and 5B, the hatched portion of the portion describing the operation of the library indicates the portion realized by software, and the white portion indicates the portion realized by hardware. For example, in the application A, if all the functions are realized by software and the performance index becomes 100, when realizing 40% by hardware and the remaining 60% by software, for example, the performance index becomes 50, When 60% is realized by hardware, the figure of merit becomes 10. In this way, a performance table is prepared for how many percent of the software can be replaced by hardware and what the performance index is.

Here, among the functions of the operation model, “FLOW” means a layer describing a flow of processing such as “perform processing b after processing a” when there is processing such as a and b, for example. Say. “MANG” refers to, for example, a layer describing a method for managing communication between applications such as a data exchange multiplexer required for each of file transfer applications connected to each other. “LINK” is a layer that defines a connection procedure in which, for example, one information data is recognized as data in a range surrounded by a series of data such as a synchronization bit, control data, MAC data, and termination. Say. “PHY” is an actual coding method, for example, when “1” is expressed, all are “1” in a certain pulse width, or “1” in the center of a certain pulse width.
"CAL" indicates, for example, in the case of arithmetic processing, whether arithmetic processing (multiplication) is performed by hardware or software. Refers to the layer.

  In addition, it is necessary to keep in mind that although high performance is required when performed by software, the performance is often low due to the presence of some hardware. The performance tables as shown in FIGS. 5A and 5B are prepared for a large number of applications, but only the applications A and B are illustrated in FIGS. 5A and 5B. .

-Operation simulation-
FIG. 6 is a block diagram illustrating an example of a method for performing an operation simulation using a plurality of applications. Here, assuming that 100% softwareized library is used for application A, 20% hardware library is used for application B, and 40% hardened library is used for application C. Assume that the performance analysis of the transfer process is performed.

  Here, in the connection relationship shown in FIG. 6, a part for counting input and output (input / output counting part) and a part for counting instruction processing (instruction processing counting part) are described in an operation analysis simulation. deep. For example, when the applications A, B, and C are connected to the transfer processing aisle (system operation control), the input / output count unit is assumed to perform the transfer processing without taking any action. Counts the number of times input / output with each device collides with each other (bus transaction collision). That is, the degree of bus congestion is measured. In addition, the number of instruction processes occurring is counted including the collision.

  FIG. 7 is a diagram showing a display method of transaction analysis in this performance analysis. As shown in the figure, for each application A, B, and C, a Neumann type bus structure (demultiplexer type) library is adopted, and a conventional Harvard type bus structure (information separation type) library is adopted. In the case of adopting the direction separation type bus structure library, the transaction density between the applications A and B, between the applications B and C, and between the applications A and C measured by the input / output count unit is summarized in the direction of the processing time axis. . In FIG. 7, it is assumed that the number of collisions increases as the hatching density increases. It can be seen that when the Neumann bus structure is employed, collisions inevitably increase when parallel processing is performed. On the other hand, when the direction separation type bus structure is adopted, the number of collisions is relatively small because the parallel processing is easy. Then, a FIFO is inserted at a location where the number of collisions is large. For example, when the Neumann bus structure is adopted, k stages (for example, 10 stages) of FIFOs are inserted between A and B, and 1 stage (for example, 8 stages) of FIFOs are inserted between B and C. Insert 1 stage of FIFO between them. Further, when the conventional Harvard bus structure (information separation type) is adopted, 1 stage of FIFO is inserted between A and B, m stages (for example, 6 stages) of FIFO are inserted between B and C, and A Insert m stages of FIFO between -C. When the direction separation type bus structure is adopted, n stages (for example, 4 stages) of FIFOs are inserted between A and B, n stages of FIFOs are inserted between B and C, and FIFOs are also inserted between A and C. N stages. While the CPU is processing, it is necessary to store information in the FIFO, but the number of FIFO stages is analyzed in accordance with the degree of bus congestion. Of course, the smaller the number of bus transaction collisions, the smaller the number of FIFO stages to be inserted. In this way, the number of FIFOs to be inserted is analyzed according to the structure of each bus structure, that is, the structure of the bus connected to the CPU.

Next, FIG. 8 is a diagram showing a display method of instruction processing analysis in the performance analysis. As shown in the figure, for applications A, B, and C, a Neumann type bus structure (demultiplexer type) library is adopted, and a conventional Harvard type bus structure (information separation type) library is adopted. In the case of using a library having a direction-separated bus structure, the simultaneous instruction density between the applications A and B, between the applications B and C, and between the applications A and C measured by the instruction processing count unit is indicated in the direction of the processing time axis. To summarize. FIG. 8 shows that the higher the density of hatching, the greater the number of simultaneous instructions and the higher the processing capacity of the entire system. It can be seen that the number of simultaneous instructions is small when the Neumann bus structure is adopted. On the other hand, when the direction separation type bus structure is adopted, the number of simultaneous instructions is relatively large. When the number of simultaneous instructions is large, the processing time is shortened and the response speed is increased, but on the other hand, there is a problem that the load factor of the CPU increases and the instantaneous current value also increases.

  FIGS. 9A and 9B are diagrams showing a part of the bus structure in the case where a cross bus is provided at a location where there are many simultaneous instructions. As shown in FIG. 9 (a), when the CPU function has sufficient capacity, the transfer function of the application B is provided in a portion not normally used, and the switching of the cross bus is controlled by the CPU. To do. Alternatively, as shown in FIG. 9B, when the CPU has no remaining capacity, a DMA is arranged. This DMA (direct memory access) has a transfer function that allows data to be directly exchanged between the input / output controller and the main memory without going through the CPU. In other words, by using a function called DMA and providing a cross bus having a switching function instead of performing everything by the CPU, for example, switching is performed such that application A is processed by the CPU and application B is processed by the DMA. This is to reduce the load factor of the CPU and to distribute the current value. The newly arranged device only needs to have a transfer function, but it goes without saying that a CPU may be arranged instead of the DMA. Then, paying attention to the part with the largest number of simultaneous instructions, depending on the maximum number of simultaneous instructions when that type of CPU is adopted, there is no cross bus, a single cross bus, or a double cross bus. Select whether to provide.

-Analysis index-
Next, a method for determining the optimum performance among the performances obtained from the above analysis results will be described. In the analysis method of the present embodiment, the most important parameter that determines the value of the system is used as the main parameter. Here, the performance, power, and area are the main parameters. Then, the three sub-parameters that affect these main parameters are combined, a library group in which each main parameter falls within the target range is first selected, and based on the value of the main parameter of each selected library, This is a method of selecting the optimal library group.

Hereinafter, specific methods will be described in order.
1. Method for Selecting the Minimum Crossing Area FIGS. 10A to 10D are diagrams showing the procedure of a method for selecting the minimum crossing area among those satisfying the parameters.

First, as shown in FIG. 10A, three sub-parameters such as the number of bus transaction collisions, the processing amount, and the response time are set as sub-parameters that affect the common main parameter “performance”. Create a three-dimensional coordinate system with parameters as coordinate axes. The values of these three sub-parameters are obtained from analysis results obtained by performing an operation simulation using each library that is an operation model of each application. For example, whether the configuration of the single application A, B, C connected to the CPU adopts a Neumann bus structure, a conventional Harvard bus structure, or a direction separation type bus structure, Furthermore, it is uniquely determined by how the hardware ratio in the operation of each application is set. For example, the number of bus transaction collisions and the processing time can be obtained from the analysis results shown in FIGS. At this time, the worst value or average value of the number of transaction collisions between the IOs, or the overall average value, the average value of a certain section, or the like can be used as the point of the transaction T. The response time R is an execution (simulation) time when the data analysis shown in FIGS. 7 and 8 is performed. The processing amount E is an execution processing amount (total value) when the analysis shown in FIGS. 7 and 8 is performed.

  Since the performance of the system LSI is higher as the bus transaction T is smaller, the processing amount E is smaller, and the response time R is shorter, one of the main parameters of performance is better as the intersection area in the three-dimensional coordinate system is smaller. Become. Therefore, a library group is selected in which the intersection area of the plane formed by connecting the points (sub-parameter values) on the coordinate axes in the coordinate system and the coordinate axes is a target value or less. Then, this intersection area may be a relative value of “performance”.

  Also, as shown in FIG. 10B, the processing amount E, the hardware rate H, and the simultaneous active density A are set as three sub parameters that affect the common main parameter “power”. Then, a three-dimensional coordinate system having these three sub-parameters as coordinate axes is created. The hardware ratio H is a ratio of hardware in the library model shown in FIG. The simultaneous active density A is a ratio of buses that are simultaneously active in the analysis shown in FIGS. At this time, the smaller the processing amount E, the smaller the hardwareization rate H, and the smaller the simultaneous active density A, the smaller the electric power. Therefore, the smaller the intersection area in the three-dimensional coordinate system, the better the main parameter of power is. Become. Therefore, a library group is selected in which the intersection area of the plane formed by connecting the points (sub-parameter values) on the coordinate axes in the coordinate system and the coordinate axes is a target value or less. The crossing area may be relatively set to the value of “electric power”. However, in this method, there are two methods of evaluating with the maximum value (peak value) of power or evaluating with the average value of power, and either method may be used.

  Furthermore, as shown in FIG. 10 (c), the necessary bus width B and the required memory amount M must be inserted as three sub-parameters affecting the common main parameter “area (cost)”. A FIFO amount F that must be set is set, and a three-dimensional coordinate system having the sub-parameters as coordinate axes is created. The bus width B is the total bus width in the bus structure in the model shown in FIG. The memory amount M is the amount of memory used in the library model shown in FIG. The FIFO amount F is the total number of FIFO stages required as a result of the analysis shown in FIGS. At this time, the smaller the bus width B, the smaller the memory amount M, and the smaller the FIFO amount F, the better the main parameter of area. Therefore, a library group is selected in which the intersection area of the plane formed by connecting the points (sub-parameter values) on the coordinate axes in the coordinate system and the coordinate axes is a target value or less. The intersection area may be relatively set as the “area” value.

Then, as shown in FIG. 10 (d), a three-dimensional coordinate system is created with the main parameters, that is, performance, power, and area as coordinate axes. Then, main parameter values determined by the library groups selected by the processes of FIGS. 3A to 3C, that is, performance, power, and area values (intersections of FIGS. 10A to 10C). A library group that minimizes the intersection area (triangular area) between the plane formed by connecting each point on the coordinate axis indicating (area) and the coordinate axis is selected, and an interface determined by this library group is selected as an optimal interface. decide.
2. Method of selecting with emphasis on specific parameters For example, from the analysis results shown in FIG. 7 and FIG. 8, the bus transaction that is the secondary parameter is less than or equal to the predetermined value in the library group that satisfies the target response time that is the secondary parameter. Of the libraries that satisfy the target response time that is the secondary parameter, the processing amount that is the secondary parameter is less than the predetermined value, and the secondary parameter that satisfies the target memory amount that is the secondary parameter The bus width that is the sub-parameter and the bus width that is the sub-parameter is selected from the library group that satisfies the target FIFO amount that is the sub-parameter.

  Next, from the ones selected by the above processing, those that are considered to be optimal in total are determined according to the following criteria. This process includes the following methods according to the type of design object.

  The first is to select a library group in which the main parameters of performance and maximum power satisfy the target minimum performance and target maximum power from the selected library group. In this method, a library group having the smallest area as a main parameter is selected.

  Second, the library group selected from the selected library group is one in which main parameters of performance and power satisfy the target minimum performance and target maximum power. In this method, a library group having a minimum average power as a main parameter is selected.

  Thirdly, the library group in which the main parameters of area and maximum power satisfy the target maximum area and target maximum power is selected from the selected library group. In this method, a library group having the smallest performance as the main parameter is selected.

Fourth, the library group selected from the selected library group is one whose main parameters of area and maximum power satisfy the target maximum area and target maximum power. In this method, the library having the smallest average power as the main parameter is selected.
3. Method of performing indexing by weighting As shown in FIGS. 11A to 11D, this method is based on performance index x for performance as a main parameter and average power index yav (or maximum power for power as a main parameter). The index ymx) and the area index z with respect to the area as the main parameter are added after weighting a, b and c, respectively, and the one with the smallest optimum index as the added value is selected.

Here, the performance index x is calculated by the following procedure. That is, as shown in FIG. 11 (a), and calculates the response time R and its performance influence coefficient l _x, a bus transaction T and its performance influence coefficient m _x, throughput E and its performance influence coefficient n _x , Following formula Performance index x = Rl _x × Tm _x × En _x
To calculate a performance index x. However, the performance influence coefficient l _x of the response time is, for example, “1” when it is 1 sec. That is, when the response time is 3 sec, the performance influence coefficient l _x of the response time is “3”. The performance influence coefficient m _x of the bus transaction is “1” when there are 10 collisions. That is, when there are 20 collisions, the performance impact coefficient of the bus transaction is “2”. Performance influence coefficient n _x amount of processing, when the 10 MIPS (1 MIPS mean that the number of instructions million times) and "1". That is, when the 50MIPS, the performance impact factor n _x of the processing amount becomes "5".

The power index y is calculated according to the following procedure. That is, as shown in FIG. 11 (b), the average throughput Eav (or the maximum throughput Emx) and its power influence coefficient l _y, and the hard ratio H and its power influence coefficient m _y, mean simultaneous active ratio Aav (or the maximum concurrent active ratio Amx) and calculates its power influence coefficient n _y, the following equation electric power index _{y = Eavl y × Hm y ×} Aavn y
_{or = Emxl y × Hm y ×} Amxn y
Thus, the power index y is calculated. However, power influence coefficient l _y average throughput (or the maximum throughput) is, for example, "1" when the 10 MIPS. Power influence coefficient m _y hard ratio is set to "1" at 20%. That is, when the hardening rate is 40%, the power influence coefficient of the hardening rate is “2”. Power influence coefficient n _y average concurrent active factor (or the maximum concurrent active ratio) is set to "1" at 25%. That is, when it is 10%, the power influence coefficient n _y of the average simultaneous active rate is “0.5”.

The area index z is calculated by the following procedure. That is, as shown in FIG. 11B, the memory amount M and its area influence coefficient l _z , the FIFO amount F and its area influence coefficient m _z , the bus width B and its area influence coefficient _nz are calculated. , the following equation area index _{z = Ml z × Fm z ×} Bn z
To calculate the area index z. However, the area influence coefficient l _z of the memory amount is set to “1” when it is 1 kByte, for example. In other words, the area influence coefficient l _z of the memory amount is 10 at 10 kByte. The area influence coefficient m _z of the FIFO amount is “1” when it is 128 bytes. That is, when the memory amount is 256 bytes, the area influence coefficient of the memory amount is “2”. The area influence coefficient _nz of the bus width is “1” when 16 bits. That is, in the case of 8 bits, the area influence coefficient _nz of the bus width is “0.5”.

Then, as shown in FIG. 11 (d), the determination of the analysis index is performed for the performance index x, power index y, and area index z calculated by the above-described processing, with respective influence coefficients (weighting coefficients) a, b, c is determined, and the value obtained by adding c is determined as the optimum exponent. That is, the following formula Optimal index Op = ax + by + cz
Based on the above, the optimal index Op is calculated. Then, the one having the smallest optimum index Op is finally selected.

-Optimal IF synthesis-
FIG. 12 is a block diagram showing the structure of the optimum IF synthesized using the above-described processing. In the bus structure selected based on the analysis index described above, a FIFO structure is inserted at a place where the FIFO needs to be inserted, and a bus structure capable of simultaneous processing is generated. In the figure, a portion surrounded by a one-dot chain line excluding DMA is an IF (interface) portion. That is, the bus structure including the data bus, control bus, cross bus, etc. and the inserted FIFO, the hardware of the libraries A, B, and C, the CPU (operation model), and the storage device (RAM, ROM, etc.) An IF for connecting is configured.

  FIG. 13 is a flowchart showing the procedure of system design including the synthesis of the optimal IF described in the present embodiment.

  First, as data verses, the libraries A, B, and C shown in FIG. 5, the Harvard bus structure, the Neumann bus structure (demultiplexer type), the direction separation type bus structure, etc. described in the first embodiment are stored. Keep it.

  In step ST1, a bus structure is selected for the selected library, and in step ST2, a system connection diagram, a transfer processing file, a new library, and the like are input.

  Next, in step ST3, transaction and instruction processing are analyzed. At this time, the operation simulation shown in FIG. 6 is performed, the transaction analysis shown in FIG. 7 and the instruction processing analysis shown in FIG. 8 are performed, and the number of FIFO stages to be inserted and the necessary cross bus arrangement are performed.

  In step ST4, for example, the analysis index is determined by the above-described three methods (see FIG. 10, FIG. 11, etc.). The processes of steps ST1 to ST4 are repeatedly performed to select a system having the minimum optimum index Op. In steps ST3 and ST4, performance evaluation (HW / SW performance evaluation) is performed by combining hardware and software.

Next, in steps ST5 to ST7, the optimum system is divided into hardware and software. That is, the optimum IF is synthesized in step ST5, and a system connection diagram as shown in FIG. 12 is generated in step ST6. On the other hand, in step ST7, selection (condition setting) of software such as an application, flow control (FLOW), and OS (operation system) is performed.

  Finally, in step ST8, hardware / software cooperative verification is performed. In other words, the hardware is used to verify whether the software functions well.

  According to the interface design method of the present embodiment, an operation simulation is performed using a library that is an operation model registered for each bus structure for an application, and based on the sub-parameters and main parameters obtained from the result of the operation simulation, The performance of the entire system connected by the interface can be accurately evaluated in an environment close to actual operation. And based on this evaluation, the interface most suitable for a designer's request can be selected, and it can use for construction of the whole system.

  An interface design method according to the present invention uses a database storing a plurality of libraries as operation models for each application and bus structure, and uses an interface for connecting a control function unit of a semiconductor integrated circuit and a plurality of applications. As a design method, it is possible to synthesize an interface for building a system with the performance desired by the designer by performing an operation simulation to analyze the degree of congestion of the bus or evaluating the performance of the entire system. This is effective as a design method for an interface related to a semiconductor integrated circuit device such as a system LSI.

It is a block diagram which shows roughly the structural difference of the conventional Neumann bus structure, the conventional Harvard bus structure, and the Harvard bus structure of the first embodiment of the present invention. (A)-(c) is a figure which shows in order the example of the conventional bus structure and the direction separation type | mold bus structure (when there is a tertiary station) of 1st this embodiment. (A) to (d) show, in order, the address and data processing in the Neumann type multiplexer type, demultiplexer type, Harvard type information separation type and the direction separation type bus structure of the first embodiment on the time axis. FIG. It is a block diagram which shows the resource isolation | separation type | mold bus structure in case the target resource A in 1st Embodiment is a memory, and the target resources B and C are IO. (A), (b) is a figure which shows the example of the library and performance table in the single application A and B memorize | stored in the database for design in 2nd Embodiment. It is a block diagram which shows the example of the method of performing operation | movement simulation using the some application in 2nd Embodiment. It is a figure which shows the display method of the transaction analysis of the performance analysis in 2nd Embodiment. It is a figure which shows the display method of the instruction processing analysis of the performance analysis in 2nd Embodiment. (A), (b) is a figure which shows a part of bus structure at the time of providing a cross bus in the location with many simultaneous instructions in 2nd Embodiment. (A)-(d) is a figure which shows the procedure of the method of selecting the thing with the minimum crossing area in the library in which each parameter satisfy | fills target value. (A) to (d) are methods in which the performance index, the average power index (or maximum power index), and the area index are respectively weighted and added, and the optimal index that is the added value is the minimum. . It is a block diagram which shows the structure of optimal IF synthesize | combined using the design method of the interface of 2nd Embodiment. It is a flowchart figure which shows the procedure of the system design including the synthesis | combination of optimal IF in 2nd Embodiment.

Claims (5)

Designing an interface for connecting a control function unit of a semiconductor integrated circuit and a plurality of applications by using a database storing a plurality of libraries as operation models for each of a plurality of applications and a plurality of bus structures. A method,
Setting a plurality of main parameters for finally evaluating the value of the semiconductor integrated circuit, and setting a plurality of subparameters affecting the main parameters;
For each of the main parameters, the step (b) of evaluating the main parameter by the sub-parameter of each library and selecting a library group satisfying the target value of the main parameter;
A method for designing an interface, including a step (c) of determining an interface by evaluating a plurality of main parameters determined for each selected library group and selecting an optimal library group. The interface design method according to claim 1,
Before the step (a), the step of analyzing the sub-parameters of each of the libraries is further performed by performing an operation simulation on each of the libraries by sequentially using the plurality of libraries as an operation model of the plurality of applications. An interface design method characterized by including. The interface design method according to claim 1 or 2,
In step (a) above, three main parameters are set, three sub parameters are set for each main parameter,
In the step (b), a three-dimensional coordinate system having three sub-parameters as coordinate axes is configured, and a library group having a triangular area determined by the values of each sub-parameter and having a target value or less is selected.
In the step (c), a three-dimensional coordinate system having three main parameters as coordinate axes is constructed, and an interface is defined from a library group having the smallest triangular area determined by the value of the main parameter obtained from the selected library group. A method of designing an interface characterized by determining. The interface design method according to claim 1 or 2,
After step (a) and before step (b), paying attention to a specific subparameter among the plurality of subparameters, a library group in which the specific subparameter satisfies the target value is selected,
In the step (b), a library group in which main parameters excluding a specific main parameter among the plurality of main parameters satisfy a target value is selected,
In the step (c), the interface design method is characterized in that a library group having the minimum specific main parameter is selected as an optimum library group. The interface design method according to claim 1 or 2,
In step (a) above, the influence coefficients of a plurality of subparameters with respect to the main parameter are set,
In the step (b), a library group satisfying the target value of each main parameter is selected based on the influence coefficient and the value of the sub parameter,
In the step (b), an interface design method is characterized in that a plurality of main parameters obtained from a selected library group are weighted and then an operation for determining the library group is performed.

Images