JP2006092259A - Logic equivalence verification system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a logic equivalence verification system having high verification efficiency in which information collection applied to an evaluation verification tool and the collection of HDL files configuring a logical hierarchy for executing verification for a largely scaled LSI are automated, and divided into verifiable units, thus verification is automatically executed. <P>SOLUTION: The logic equivalence verification system is provided with a logic synthesis processing part 301 for performing the logic synthesis of a plurality of HDL files to generate a gate circuit and a logic equivalence verification processing part 302 for comparing a reference logic circuit constituted of the plurality of HDL files with a comparison object logic circuit constituted of a gate circuit formed by performing the logic composition of the plurality of HDL files, and for verifying logic equivalence. The logic equivalence verification processing part 302 is operated while being interlocked with the logic composition processing part 301 to receive in real time the information of a logical hierarchy whose logic change or addition has been performed by the logic synthesis processing part 301, and assembles the logic hierarchy by retrieving the HDL files necessary for the reference logic circuit, and divides and executes the logic equivalence verification with the comparison object logic circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a logical equivalence verification system for performing logical equivalence verification between a circuit logic described in HDL (Hardware Description Language) and a gate level netlist obtained by logically synthesizing the circuit logic.

  In recent years, with the advance of semiconductor technology, the logical scale integrated in one LSI has been increasing. When designing a circuit for such a large-scale LSI, the logic of the LSI is described using a hardware description program language called HDL, which is RTL (Register Transfer Level), and software called a logic synthesis tool is described. A design method is generally used to synthesize a logic description into an actual gate circuit.

  At this time, HDL logic (hereinafter referred to as HDL file) described by the designer is used as a reference logic circuit, and a Gate level gate circuit (hereinafter referred to as netlist) synthesized by a logic synthesis tool is used as a comparison target logic circuit. The design process that guarantees that both are logically equivalent is called logical equivalence verification. This logical equivalence verification is executed by software called an equivalence verification tool.

  The equivalence verification tool reads the HDL file and a netlist obtained by logically synthesizing the HDL file, recognizes the circuit structure of both, associates verification points (output ports, flip-flops, etc.), and is arranged in the preceding stage. Equivalence is verified by generating a cone called a logic cone as a logic, a logical expression in the HDL file, and a combinational circuit in the netlist.

  Moreover, even if the HDL file described by the designer is mechanically synthesized with respect to the logic synthesis tool, the circuit structure of the netlist intended by the designer is not necessarily obtained including the layout.

  Therefore, conventionally, the designer performs various settings or manual intervention on the logic synthesis tool, and outputs the circuit structure intended by the designer to the netlist.

  In addition, since logic synthesis is performed using an HDL file that is not intended by the designer due to data management failure of the HDL file, there is a possibility that the logic failure proceeds to the subsequent design process. Therefore, it is effective to guarantee the logical equivalence of circuits by performing logical equivalence verification.

  Further, when designing a large-scale LSI, the LSI is logically designed by dividing the LSI into several hierarchical parts.

  Specifically, a lower layer component that describes the actual circuit operation is designed, an HDL file is described, several combinations are created to create an upper layer component, and this is repeated and assembled as one LSI logic. Go. When logical design is performed by such a method, the HDL file has a huge hierarchical structure as a result.

  Similarly, logic synthesis in large-scale LSI design uses a technique called hierarchical logic synthesis to synthesize HDL files from a lower hierarchy into a netlist and combine them to create a netlist for the entire LSI. Is common. Similarly to the HDL file, the netlist is generated with a huge hierarchical structure.

  However, the hierarchical structure of the netlist does not necessarily correspond to the HDL file on a one-to-one basis due to the setting of the designer at the time of logic synthesis of the HDL file.

  When performing equivalence verification between an HDL file and a netlist designed by such a method, conventionally, the equivalence verification tool has been manually set to verify.

  Further, it has been a conventional general logic equivalence verification method that performs batch verification from the highest layer of LSI and verifies the logical equivalence without being aware of the hierarchical difference between the HDL file and the netlist.

  However, the conventional general verification method has the following two problems.

  The first problem is that in order to perform logical equivalence verification, it is necessary to provide the equivalence verification tool with information such as specially configured settings for the logic synthesis tool and manually intervening parts. .

  As a first representative example, assume that a variable defined as A in the HDL file is mapped to a register defined as A in the netlist. The equivalence verification tool performs verification by automatically associating a variable defined with the same A with a register. However, if the register defined as A in the netlist is intentionally replaced with a register defined as B, the equivalence verification tool may not be able to associate.

  A second representative example is to add a group hierarchy considering the physical layout to the gate circuit of the netlist in order to reduce the timing delay. Since this is a hierarchy that is newly added by logic synthesis, it does not exist in the HDL file, so the equivalence verification tool may not be able to automatically associate.

  In other words, if it is changed or added in the process of logic synthesis from the HDL file to the netlist and the equivalence verification tool cannot automatically handle it, it must be provided manually as information separately. Such manual setting addition not only deteriorates verification efficiency, but also reduces verification accuracy due to manual error.

  The second problem is that when the LSI HDL file and netlist are collectively verified from the highest level, the capacity of the equivalent verification tool may be exceeded due to the large logical scale. The capacity refers to the program capacity of the equivalent verification tool, the memory usage of the computer that executes this, and the verification time.

  In such a case, the equivalence verification tool and the method of verifying the logical equivalence with the load on the computer minimized by dividing and verifying the HDL file and the netlist are used.

  In this split verification, when the logic is changed or added to a part of the logic hierarchy of the LSI, the entire LSI can be verified without using the entire LSI, and can be verified with the difference. It is effective in terms of verification efficiency against frequent logic changes.

  However, in order to perform division verification, it is necessary to accurately grasp the hierarchical structure of both the HDL file and the netlist, and to give the changed and added hierarchy as information to the equivalence verification tool.

  In particular, the HDL file is generally divided into lower parts and upper parts, and manually selecting an HDL file necessary for performing division verification reduces verification efficiency and causes poor file management. Cause a decrease in verification accuracy.

  Therefore, an object of the present invention is to perform logical equivalence verification on a large-scale LSI using an HDL file described in RTL as a reference logic circuit and a gate-level netlist obtained by logically synthesizing the HDL file as a comparison target logic circuit. Automates the collection of information given to the equivalence verification tool and the collection of HDL files that make up the logical hierarchy for performing verification, and provides a logical equivalence verification system with high verification efficiency that is automatically divided into units that can be verified. There is to do.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A logical equivalence verification system according to the present invention includes a logical input terminal for inputting a logically described hardware description program language file, a plurality of hardware description program language files, and a plurality of hardware description program language files. A storage device for storing information of the synthesized gate circuit, a logic synthesis means for generating a gate circuit by logically synthesizing a plurality of hardware description program language files stored in the storage device, and for a plurality of hardware descriptions Comparing the reference logic circuit by the program language file with the logic circuit to be compared by the gate circuit obtained by logically synthesizing the program language files for hardware description, and equipped with a logic equivalence verification means for verifying the logic equivalence, and the logic equivalence The property verification means can change or add logic more than the logic synthesis means. It receives information of a logical hierarchy, assembling a logical hierarchy to find a hardware description program language files necessary criteria logic circuit, and executes by dividing the logical equivalence checking the comparison logic.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The first effect of the present invention is that the logic equivalence verification means performs logic equivalence verification in conjunction with the logic synthesis means, so that the number of work steps can be reduced.

  In addition, the second effect of the present invention is to search the logical hierarchy of the hardware description program language file and perform logical hierarchy division verification, thereby improving verification efficiency and reducing verification mistakes when logic is added or changed. Is possible.

  The third effect of the present invention is that the hardware description program language under design and the unverified hardware description program language are stored in a high-speed storage device, and the hardware description program language that has been verified is stored at a low speed. Since the data is stored in a mass storage device, design data management with high cost performance is possible.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

<Configuration of logical equivalence verification system>
With reference to FIG. 1, the configuration of a logical equivalence verification system according to an embodiment of the present invention will be described. FIG. 1 is a configuration diagram showing a configuration of a logical equivalence verification system according to an embodiment of the present invention.

  In FIG. 1, the logical equivalence verification system includes a logic input terminal 10, a logic input server 20, a logic synthesis server 30, and an external storage device 50 for storing design data.

  The logic input terminal 10, the logic input server 20, and the logic synthesis server 30 are connected by a local area network 60, and the logic input server 20, the logic synthesis server 30 and the design data storage external storage device 50 are a storage area network. 40 is connected.

  The logic input terminal 10 is a terminal for a designer to create an HDL file, or to input settings and information at the time of logic synthesis, and a plurality of logic input terminals 10 can be created by a plurality of designers. One logical input terminal 10 is provided.

  The logical input server 20 receives the HDL file input from the logical input terminal 10 and stores it as an HDL file group 501 in the external storage device 50 for storing design data.

  The logic synthesis server 30 includes a logic synthesis processing unit 301 that is a logic synthesis unit and a logic equivalence verification processing unit 302 that is a logic equivalence verification unit.

  The logic synthesis processing unit 301 performs logic synthesis on the HDL file group 501 stored in the design data storage external storage device 50 to generate an LSI netlist 502.

  The logical equivalence verification processing unit 302 verifies the logical equivalence between the HDL file group 501 and the net list 502 obtained by logically synthesizing the HDL file group 501.

<Hierarchical structure of HDL files and netlist>
Next, the hierarchical structure of the HDL file group and netlist of the logical equivalence verification system according to the embodiment of the present invention will be described with reference to FIGS. 2 is a schematic diagram of the logical hierarchy of the HDL file group (reference logic circuit) of the logical equivalence verification system according to the embodiment of the present invention, and FIG. 3 is the logical equivalence verification according to the embodiment of the present invention. FIG. 4 is a schematic diagram showing a verification target hierarchy of the logical equivalence verification system according to the embodiment of the present invention.

  In FIG. 2, an HDL file group 201 is created by, for example, a plurality of designers, and when the connection information of each HDL file in the HDL file group 201 is traced, a logical hierarchy diagram shown at 202 in FIG. In a large-scale LSI design, the hierarchical structure becomes huge.

  In FIG. 3, the internal structure of the netlist 311 has a hierarchical structure as indicated by 312 in FIG. 3. In the case of designing a large-scale LSI like the HDL file group 201, the hierarchical structure is huge.

  4, in the logical equivalence verification of the hierarchical structure 401 of the reference logic circuit (HDL file group) and the hierarchical structure 402 of the comparison target logic circuit (net list), the hierarchy indicated by the broken line in FIG. Yes, it is an object of split verification when performing logical equivalence verification of a huge hierarchical structure.

<Operation of logical equivalence verification of logical equivalence verification system>
Next, the operation of logical equivalence verification of the logical equivalence verification system according to the embodiment of the present invention will be described with reference to FIG. FIG. 5 is a flowchart showing the logical equivalence verification operation of the logical equivalence verification system according to the embodiment of the present invention.

  As shown in FIG. 5, the logical equivalence verification operation of the present embodiment automatically performs logical equivalence verification in conjunction with the logic synthesis processing unit 301, and is necessary for logical equivalence verification. Automatic collection of information and reflection to the equivalence verification tool, and automatic collection of HDL files for constructing a hierarchy for performing division verification.

  First, as soon as the HDL file group 501 is synthesized by the logic synthesis processing unit 301 to generate the LSI netlist 502, the logic equivalence verification processing unit 302 is executed. At this time, the logic synthesis information 60 including the hierarchy information and the synthesis information obtained by the logic synthesis at the time of the logic synthesis is delivered from the logic synthesis processing unit 301 to the logic equivalence verification processing unit 302.

  In step 101, the logic equivalence verification processing unit 302 acquires the logic synthesis information 60 from the logic synthesis processing unit 301.

  In step 102, the second hierarchy is extracted from the hierarchy information of the logic synthesis information 60 received from the logic synthesis processor 301 as viewed from the LSI highest hierarchy that is the hierarchy to be verified. There may be a plurality of second hierarchies serving as verification target hierarchies, and the logical scale below these second hierarchies is a scale that can be verified by the equivalent verification tool.

  In step 103, the HDL file hierarchy search processing unit is used to collect each of the HDL files constituting the second hierarchy and below to be verified.

  In step 104, the equivalence verification processing unit 1 is used to perform logical equivalence verification of the verification target hierarchy, and this is repeated for the number of verification target hierarchies.

  When the verification of the second hierarchy is completed in step 105, in step 106, the second hierarchy of the HDL file and the netlist are all empty boxes (black boxes) using the equivalence verification processing unit 2. Verify the equivalence of the connection relation.

<Operation of HDL file hierarchy search processing unit>
Next, the operation of the HDL file hierarchy search processing unit in the logical equivalence verification processing unit of the logical equivalence verification system according to the embodiment of the present invention will be described with reference to FIGS.

  FIG. 6 is a hierarchical diagram of an HDL file group having only the third hierarchy used in the HDL file hierarchy search processing unit of the logical equivalence verification system according to the embodiment of the present invention, and FIG. 7 is an embodiment of the present invention. FIG. 8 is a hierarchy diagram of an HDL file group including an intermediate hierarchy used in the HDL file hierarchy search processing unit of the logical equivalence verification system according to FIG. 8, and FIG. 8 is a logical equivalence verification of the logical equivalence verification system according to the embodiment of the present invention. FIG. 9 is a flowchart showing the operation of the HDL file hierarchy search processing unit in the processing unit, and FIG. 9 shows the operation of the HDL file first search processing unit in the HDL file hierarchy search processing unit of the logical equivalence verification system according to the embodiment of the present invention. FIG. 10 is a flowchart showing the second HDL file search in the HDL file hierarchy search processing unit of the logical equivalence verification system according to the embodiment of the present invention. FIG. 11 is a flowchart showing the operation of the processing unit, and FIG. 11 shows the operation of the lower level search processing unit in the HDL file first search processing unit and the HDL file second search processing unit of the logical equivalence verification system according to the embodiment of the present invention. It is a flowchart to show.

  First, as a premise, the HDL file group 501 serving as the reference logic circuit is such that the third hierarchy below the second hierarchy as shown in FIG. 6 is described in one HDL file as shown in FIG. There is an intermediate hierarchy below the second hierarchy, and it is roughly divided into those having the lowest hierarchy described in the function below the intermediate hierarchy.

  Naming rules are determined in advance for the file names of the HDL file group 501 and are named with the name “<identifier> _ <hierarchy name>”. However, there are cases where different HDL files exist with the same <hierarchy name>, and identifiers such as “<identifier 1> _ <hierarchy name A>” and “<identifier 2> _ <hierarchy name A>” are used. Differentiated. In the logic synthesis processing unit, the same hierarchy name A included in the latest HDL file is the logic synthesized in the netlist.

  The operation of the HDL file search processing unit shown in FIG. 8 will be described using the HDL file group shown in FIG. 7 as an example.

  As shown in FIG. 8, the operation of the HDL file search processing unit in step 103 in FIG. 5 first creates an HDL file list 70 in which the creation date is arranged in the order of creation date for the files in the HDL file group 501 in step 701. In step 702, the file 61 corresponding to the second hierarchy and the files 611, 612, and 613 corresponding to the third hierarchy in FIG. 7 are stored in the reference logic circuit read file list 71 using the HDL file first search processing unit. Output.

  If an intermediate hierarchy exists, in step 704, using the HDL file second search processing unit, a file 613 corresponding to the intermediate hierarchy, a file 6131, a file 6132, a file 61131 corresponding to the lowest hierarchy below the intermediate hierarchy, The file 61312, the file 61321, and the file 61322 are output to the reference logic circuit read file list 71.

  In step 705, duplicate file names in the reference logic circuit read file list 71 are omitted. As a result, a list of file names of HDL files describing all subordinates to be verified can be obtained from the reference logic circuit read file list 71.

  Further, in the operation of the HDL file first search processing unit in step 702 in FIG. 8, the HDL file 61 describing the second hierarchy to be verified is acquired from the logic synthesis information 60 in step 801 as shown in FIG.

  In step 802, the HDL file name of the second layer to be verified is registered in the reference logic circuit read file list 71. In step 803, the file 61 is passed to the lower layer search processing unit. In step 804, the lower layer search processing unit is used. , Search the lower hierarchy.

  Further, as shown in FIG. 11, the operation of the lower hierarchy search processing unit in step 804 of FIG. 9 is to read the file 61 in step 1001, parse the syntax in step 1002, and describe the third hierarchy name described in the file 61. Is extracted and output to the lower hierarchy list 73.

  In step 1003, the file name <identifier> _ <layer name> in the HDL file list 70 is inquired using the third layer name as a key. If there is a file name that first hits the key in step 1004, it is added to the reference logic circuit read file list 71 in step 1005. The first hit file name is selected to select the file with the latest creation date. If no file name matching the key is found in step 1004, the process ends as an error.

  In step 1006, the final determination of the lower hierarchy list 73 is performed. If the final determination is not final, the process returns to step 1003, and the next third hierarchy name is used as a key to inquire about the HDL file list. As a result, the file 61, the file 611, the file 612, and the file 613 are output to the reference logic circuit read file list 71.

  In addition, as shown in FIG. 10, the operation of the HDL file second search processing unit in step 704 in FIG. 8 is as follows. If there is an intermediate hierarchy, the HDL file name file 613 in the intermediate hierarchy is obtained from the logic synthesis information in step 901. The files 6131 and 6132 are acquired and added to the reference circuit read file list 71 in step 902.

  In step 903, the intermediate hierarchy file list 72 is created. In step 904, one HDL file name is extracted from the intermediate hierarchy file list 72 and given to the lower hierarchy search processing section. In step 905, the lower hierarchy search processing section is executed.

  By executing the lower layer search processing unit shown in FIG. 11, the file 6131 and the file 6132 describing the child layers are searched from the file 613, the file 61131 and the file 61312 are searched from the file 6131, and the file from the file 6132 is searched. 61321 and the file 61322 are searched and added to the reference logic circuit read file list 71. Since the file 613, the file 6131, and the file 6132 are duplicated in the reference logic circuit read file list 71, the duplicate HDL file names are omitted in step 705 of FIG.

  In step 906, the intermediate hierarchy file list 72 is finally determined. If it is not final, the process returns to step 904, and if it is final, the process ends.

<Operation of Equivalence Verification Processing Unit 1>
Next, the operation of the equivalence verification processing unit 1 in the logical equivalence verification processing unit of the logical equivalence verification system according to the embodiment of the present invention will be described with reference to FIG. FIG. 12 is a flowchart showing the operation of the equivalence verification processing unit 1 in the logical equivalence verification processing unit of the logical equivalence verification system according to the embodiment of the present invention.

  As shown in FIG. 12, the operation of the equivalence verification processing unit 1 in Step 104 of FIG. 5 reads the technology library 74 used for logic synthesis from the logic synthesis information into the equivalence verification tool in Step 1101. The technology library 74 is a library of gate circuits constituting the netlist.

  In step 1102, the reference logic read file list 71 output in step 705 of FIG. 8 is referred to read the HDL file of the HDL file group 501 into the equivalence verification tool to generate a reference logic circuit.

  In step 1103, the netlist 502 is read into the equivalence verification tool to generate a comparison target logic circuit.

  In step 1104, setting is performed in the equivalence verification tool from the logic synthesis information 60. In step 1105, verification is performed on the verification target hierarchy of the second hierarchy.

<Operation of Equivalence Verification Processing Unit 2>
Next, the operation of the equivalence verification processing unit 2 in the logical equivalence verification processing unit of the logical equivalence verification system according to the embodiment of the present invention will be described with reference to FIG.

  FIG. 13 is a flowchart showing the operation of the equivalence verification processing unit 2 in the logical equivalence verification processing unit of the logical equivalence verification system according to the embodiment of the present invention.

  The operation of the equivalence verification processing unit 2 in step 106 of FIG. 5 reads the technology library 74 used for logic synthesis from the logic synthesis information 60 into the equivalence verification tool in step 1201.

  In step 1202, the HDL file of only the first hierarchy is read from the HDL file group 501 into the equivalence verification tool.

  In step 1203, the netlist 502 is read into the equivalence verification tool, and in step 1204, all the second and lower layers are made black boxes. In step 1205, the equivalence verification tool is set based on the logic synthesis information 60, and in step 1206, the connection relationship between the second layers is verified.

  The netlist 502 whose logical equivalence is guaranteed by the above equivalence verification processing unit 1 and equivalence verification processing unit 2 is advanced to the post-design process.

  As described above, in this embodiment, logical equivalence verification is automatically performed in conjunction with the logic synthesis apparatus, so that the number of work steps can be reduced.

  Further, by automating logical hierarchy division verification using the hierarchy search processing unit of the HDL file, it is possible to improve verification efficiency and reduce verification errors when there is a logic addition or change.

<HDL file management method>
Next, an example of a HDL file management method of the logical equivalence verification system according to the embodiment of the present invention will be described with reference to FIG. FIG. 14 is an explanatory diagram for explaining an example of the HDL file management method of the logical equivalence verification system according to the embodiment of the present invention.

  In FIG. 14, a designed / unverified HDL file group 1301 and a verified HDL file group 1302 are stored in the high-speed external storage device 80 and the low-speed large-capacity external storage device 81, respectively.

  The in-design / unverified HDL file group 1301 that is being designed or not logically verified is frequently accessed from various CAD tools (simulators, logic synthesis, equivalent verification, etc.) because it is being logically designed. For this reason, the design / unverified HDL file group 1301 under design / unverified is stored in the high-speed external storage device 80.

  In addition, since the logic described in the HDL file for which the logic equivalence verification has been completed is correctly converted into a gate circuit and enters the manufacturing process as an LSI, this is a design asset. Since the verified HDL file 1302 as such a design asset is stored for a long period of time and has a low access frequency, it is stored in the low-speed large-capacity external storage device 81 that is relatively slow.

  In other words, the logical equivalence verification system according to the present embodiment promotes an HDL file whose logical equivalence is guaranteed from the in-designed / unverified HDL file group 1301 stored in the high-speed external storage device 80 to a design asset. By moving to the low-speed large-capacity external storage device 81, design data management with high cost performance is realized.

  The verified HDL file group 1302 is a divided file group, but it is obvious that when the connection information is traced, the hierarchical structure is logically equivalent to the LSI netlist.

  As described above, according to the present embodiment, cost performance is achieved by storing the in-design / unverified HDL file group 1301 and the verified HDL file group 1302 in the high-speed external storage device 80 and the low-speed large-capacity external storage device 81. High design data management.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in this embodiment, the logic synthesis processing unit 301 and the logic equivalence verification processing unit 302 are executed in the logic synthesis server 30, but the logic synthesis processing unit 301 and the logic equivalence verification processing unit 302 are It can be executed in the input server 20 or in different servers.

It is a block diagram which shows the structure of the logical equivalence verification system which concerns on one embodiment of this invention. It is a schematic diagram of the logic hierarchy of the HDL file group (reference | standard logic circuit) of the logical equivalence verification system which concerns on one embodiment of this invention. It is a schematic diagram of the logic hierarchy of the net list (comparison target logic circuit) of the logic equivalence verification system according to the embodiment of the present invention. It is a schematic diagram which shows the verification object hierarchy of the logical equivalence verification system which concerns on one embodiment of this invention. It is a flowchart which shows the operation | movement of the logic equivalence verification of the logic equivalence verification system which concerns on one embodiment of this invention. It is a hierarchy figure of the HDL file group which has only the 3rd hierarchy used by the HDL file hierarchy search process part of the logical equivalence verification system which concerns on one embodiment of this invention. It is a hierarchy figure of the HDL file group containing the intermediate | middle hierarchy used by the HDL file hierarchy search process part of the logical equivalence verification system which concerns on one embodiment of this invention. It is a flowchart which shows operation | movement of the HDL file hierarchy search process part in the logical equivalence verification process part of the logical equivalence verification system which concerns on one embodiment of this invention. It is a flowchart which shows operation | movement of the HDL file 1st search process part in the HDL file hierarchy search process part of the logical equivalence verification system which concerns on one embodiment of this invention. It is a flowchart which shows operation | movement of the HDL file 2nd search process part in the HDL file hierarchy search process part of the logical equivalence verification system which concerns on one embodiment of this invention. It is a flowchart which shows operation | movement of the lower hierarchy search process part in the HDL file 1st search process part and HDL file 2nd search process part of the logical equivalence verification system which concerns on one embodiment of this invention. It is a flowchart which shows operation | movement of the equivalence verification process part 1 in the logic equivalence verification process part of the logic equivalence verification system which concerns on one embodiment of this invention. It is a flowchart which shows operation | movement of the equivalence verification process part 2 in the logic equivalence verification process part of the logic equivalence verification system which concerns on one embodiment of this invention. It is explanatory drawing for demonstrating an example of the management method of the HDL file of the logical equivalence verification system which concerns on one embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Logic input terminal, 20 ... Logic input server, 30 ... Logic synthesis server, 40 ... Storage area network, 50 ... External storage device for storing design data, 60 ... Logic synthesis information, 70 ... HDL file list, 71 ... reference logic circuit read file list, 72 ... intermediate hierarchy file list, 73 ... lower hierarchy list, 74 ... technology library, 80 ... high speed external storage device, 81 ... low speed large capacity external storage device, 301 ... logic synthesis processing unit, 302 ... logical equivalence verification processing unit, 501 ... HDL file group, 502 ... netlist.

Claims (5)

A logical input terminal for inputting a logically described hardware description program language file;
A storage device for storing a plurality of hardware description program language files and gate circuit information obtained by logical synthesis of the plurality of hardware description program language files;
Logic synthesis means for logically synthesizing the plurality of hardware description program language files stored in the storage device and generating the gate circuit;
Logical equivalence of comparing a reference logic circuit by the plurality of hardware description program language files with a comparison target logic circuit by a gate circuit obtained by logical synthesis of the plurality of hardware description program language files and verifying logic equivalence A verification means,
The logical equivalence verifying means receives information on the logic hierarchy that has undergone logic change or addition from the logic synthesis means, and searches the hardware description program language file necessary for the reference logic circuit to assemble the logic hierarchy. A logic equivalence verification system that divides and executes logic equivalence verification with the comparison target logic circuit. The logical equivalence verification system according to claim 1,
The logical equivalence verification means, when searching the hardware description program language file, based on the language grammar of the hardware description program language, the lower level hardware description program language file described in the lower level hardware description program language file A logical equivalence verification system that extracts a hierarchy name and searches for a program language file for hardware description having a lower hierarchy. The logical equivalence verification system according to claim 1,
The logical equivalence verification means, when searching the hardware description program language file, uses the logical hierarchy name given to the name of the hardware description program language file as a key, and the corresponding hardware description program A logical equivalence verification system that searches a language file and selects the latest file creation date when keys are duplicated. The logical equivalence verification system according to claim 1,
The logical equivalence verification means acquires information necessary for the logical equivalence verification in real time from the logic synthesis means, and reflects the acquired information when verifying logical equivalence. system. The logical equivalence verification system according to claim 1,
The storage device is composed of a high-speed storage device and a low-speed mass storage device,
The high-speed storage device stores the program language file for hardware description under design and the program language file for hardware description whose logical equivalence is not verified,
The logical equivalence verification system, wherein the low-speed mass storage device stores the program language file for hardware description that has been verified for logical equivalence.

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