JP2006091946A - Computer system for guaranteeing certain response time - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems wherein (1) delay by software has limitations, (2) it is difficult to put delay into all of a case having no source code and a case where various applications combine complexly, and (3) a system failure such as data mismatch can occur when delay is put into only a specific piece of software. <P>SOLUTION: By enabling a business server 2 to increase the memory latency of the server by a relatively free variation width, the performance of the whole server can be adjusted to an expected performance. A managing server 4 calculates the delay cycle number of appropriate memory latency based on the response time observed by a client 1, and the correlation among the operating condition, the memory latency, and the response time of the business server 2, and varies the memory latency of the business server 2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to control of computer system performance, and more particularly to a method and apparatus for making performance constant by directly controlling server hardware performance.

  The time from when a request is input to the system until the response is returned at a terminal of a service user operating on a system composed of one or more servers is called a response time. In the initial stage of system introduction, the response time is small because the load on the system is small. However, the database size and the number of users connected to the server increase as the usage time elapses. Then, the time required for the business server to search for data increases as the database size increases, and the response time increases as the throughput required for the business server increases due to the increase in the number of connected users. Even if the response time at this time falls within the time estimated at the time of system development, the user feels dissatisfied despite the introduction of a new system.

  “The Law of Database Tuning 256” by Chris Looseley & Frank Douglas, translated by Akira Mamiya, Nikkei Business Publications, Inc. 50 (Non-Patent Document 1), in the initial stage of system introduction, a timer-type delay is incorporated into the application code to increase the response time. As the system grows, the artificial delay is gradually removed to reduce the change in response time, thereby making it difficult for the user to feel dissatisfied.

In particular, in the case of applying a utility service to a business system, it is considered essential to provide a service that guarantees a constant response time.
The performance of a single CPU that constitutes a server has been significantly improved by technologies such as higher operating frequencies and multi-CPU cores, so the difference in performance improvement when increasing the number of CPUs in a multi-processor server has increased. It was.

“The Law of Database Tuning 256” by Chris Looseley & Frank Douglas, translated by Akira Mamiya, Nikkei Business Publications, Inc. 50

As described above, in the initial stage of system introduction, the technique of incorporating a timer-type delay in the application code to increase the response time is not widely used in the current development environment. The following three points can be cited as the reason.
(Reason 1) In the current system development, a system is often developed by combining a plurality of applications, and the source code is not disclosed, and the package is configured only by an executable program. Therefore, it is impossible to put a delay directly in the application code.
(Reason 2) Although application programs that disclose source codes are becoming widespread, carelessly changing the code of a large-scale and complicated application such as a database may cause a malfunction of the program.
(Reason 3) When a flow of business in which multiple applications are linked is realized, if a delay is added only to a specific application, the timing between the processing with the delay and the processing without the delay There is a risk that data consistency may be maintained and deadlock may occur.

Therefore, it can be said that there is a problem for the above reason in putting a delay in the source code of the program in order to control the response time.
Furthermore, since the performance difference due to the difference in the number of CPUs in a multiprocessor server increases as the performance of a single CPU increases, it is difficult to obtain a system configuration that provides an appropriate response time. The possibility of over-performance in the early stages of system introduction is increasing.

  On the other hand, a server developer or an operation manager needs to monitor a message displayed on the screen at the time of startup in order to set or debug the server BIOS. Since the speed of the CPU alone is improved, a key for entering the BIOS setting screen may not be hit or a message displayed on the screen may be missed. For this reason, conventionally, the server developer and operation management repeatedly turn the power on and off repeatedly until the desired operation can be performed, which may reduce the productivity of work.

In order to solve the above problems, the following points were noted.
The throughput of server transaction processing can be obtained by the following formula.
(Throughput performance) = (number of CPUs × CPU frequency × constant) ÷ (number of CPU execution steps × CPI)
Here, the constant indicates the number of throughput values converted per unit time or per second. CPI is the number of execution cycles per instruction of the CPU. In the conventional method, by inserting a delay loop in the program source code, the number of execution steps of the CPU is increased to control the performance. However, this method has a problem such as the above-mentioned problem 1. Further, there is a problem of problem 2 in changing the number of CPUs. However, this method has the problems described above. Therefore, the parameter that can be changed may be a method of controlling the number of CPUs, CPU frequency, and CPI. The number of CPUs is limited by hardware design, and there is not much freedom. For the CPU frequency, it is necessary to increase the frequency fluctuation range in order to increase the performance fluctuation range. This is thought to be difficult for LSI delay design.

The CPI can also be described as follows: However, a case where the cache memory has only level 1 and level 2 is taken as an example. A similar expression can be used when there is a cache memory of level 3 or later.
CPI = CPI0 + (L1 cache miss rate−L2 cache miss rate) × (L2 cache memory latency) × Kc + (L2 cache miss rate) × (main memory memory latency) × Km
CPI0: number of execution cycles Kc per instruction when the primary cache has an infinite capacity, Km: performance control by controlling the value of the constant value CPI when considering the case where multiple memory accesses are executed Although it is possible, controlling the cache memory miss rate may not be effective depending on the working set size of the application. Therefore, it can be said that the performance can be controlled in many cases of controlling the CPI by controlling the memory latency. In particular, it is considered to be an effective means in the case where data such as OLTP (Online Transaction Processing) and OLAP (Online Analytical Processing) using a database is large and does not fit in the cache memory.

In the present invention, it becomes possible to increase the memory latency of the server with a relatively free fluctuation range, so that the performance of the entire server can be adjusted to the expected performance.
Furthermore, a management server is provided for monitoring the response time, detecting a deviation from the response time specified in advance, calculating an appropriate memory latency increment from the correlation between the memory latency and the response time, and changing the memory latency of the business server.

As described above, according to the present invention, it is possible to change the performance for a general purpose when any system is introduced by manipulating the delay of the memory latency based on the response time or the operating state of the server.
In addition, since the performance difference due to the difference in the number of CPUs in a multiprocessor server increases due to the improvement in the single unit performance of the CPU, it is difficult to obtain a system configuration that provides an appropriate response time, and at the initial stage of system introduction The possibility of excessive performance can be suppressed.

  In addition, server developers and operations managers can slow down the server performance by reducing the server performance only during the period when the message displayed on the screen is displayed for startup and debugging of the server BIOS. It is possible to reduce the possibility of not typing a key for entering the BIOS setting screen or overlooking a message displayed on the screen, thereby improving business efficiency.

  Embodiments of the present invention will be described below with reference to the drawings. In this specification, the response time refers to the time from when the user presses the Enter key (after executing the command) until the data first returns to the client.

FIG. 1 is a system configuration diagram showing a first embodiment of the present invention. One client 1 and business server 2 are connected via a network 14. The management server 4 is connected to the client 1 and the business server 2 to collect the operation information and manage the configuration. The user receives a service such as a business system provided by the business server 2 from the client 1. Although only a single client and a single business server are shown in the figure, the entire system exists and is connected in plural.
The client 1 has a client monitoring agent 3 that measures the response time from when the service of the business server 2 is requested until the response is returned. In the business server 2, a server monitoring agent 21 that collects information related to the operating state of the server is operating.

  In the management server 4, a management program 6 for managing the client 1 and the business server 2 is running. The management server 4 can change the delay of the memory latency by hardware. The memory latency can be changed between a fixed minimum memory latency and a maximum memory latency. The delay of the memory latency can be changed by designating the number of delay cycles from the software in the configuration register arranged in the memory space. The management program 4 includes a performance monitoring unit 6 that monitors the operating state of the client 1 and the business server 2 and a configuration management unit 7 that sets a delay time of memory latency.

  The management server 4 also includes performance model data 9 in which target performance data 8 in which the target response time of the business server 2 is recorded and a relationship table of response time and memory latency for each application program running on the business server 2 are stored. And performance policy data 10 storing a criterion for determining an appropriate memory latency when the response time does not achieve the target, and monitoring target data 11 describing a server name to be monitored and an event to be monitored And performance statistics data 12 storing statistics of data indicating response time and operational status of the business server, and configuration information data 13 storing configuration information such as memory latency delay set in the business server 2 are held. Yes.

The performance monitoring unit 6 accesses the target performance data 8, the performance model data 9, the performance policy data 10, the monitoring target data 11, and the performance statistical data 12, and reads and writes data. The configuration management unit 7 accesses the configuration information data 13 and reads / writes the data. Further, the configuration management unit 7 designates a delay amount of the memory latency of the business server 2. The performance monitoring unit 6 of the management program 5 sends a response time log sending request to the client monitoring agent 3 (arrow 16). Upon receiving the response time log sending request, the client monitoring agent 3 sends the response time log to the performance management unit of the management program 5 (arrow 15). On the other hand, the performance monitoring unit 6 of the management program 5 sends a log transmission request for the operational status of the business server 2 to the server monitoring agent 21 (17). Upon receiving the response time log sending request, the server monitoring agent 21 sends the operating status log of the business server 2 to the performance management unit of the management program 5 (18).
Here, the operating state of the server refers to information related to the operating state of the server such as the CPU queue length, the disk queue length, and the CPU usage rate for each active application.

Next, a data group referred to by the management program will be described.
FIG. 2 shows an example of target performance data. The target performance data is a record of a target response time and an allowable range of response time for each application (exemplified as business A, business B, and business C in FIG. 2) used from the client. In the example of FIG. 2, it is shown that business A may have a response time of (A ± ΔA) seconds, business B may have a response time of (B ± ΔB) seconds, and business C may have a response time of (C ± ΔC) seconds. Both the target response time and the allowable range are data set by the server administrator.

  An example of performance model data is shown in FIG. The performance model data is prepared for each business in advance. Furthermore, for each business, prepare the relationship between the number of users connected to the business server for each business server operating status and configuration information and the response time for each memory latency delay amount. deep. In FIG. 3, the relationship between the number of users and the response time is shown as a graph, but the format of the data actually stored is a function or a table.

  An example of performance policy data is shown in FIG. The performance policy data includes a policy set 30. The policy set 30 further describes a determination method for achieving a certain purpose as shown in the policy 1. The policy 1 describes a method of checking whether the response time conforms to a preset target response time and changing the server performance by changing the delay of the memory latency when the purpose is not satisfied. The policy is a set because it is necessary to change the judgment method according to the required purpose.

Next, the policy 1 will be described in detail.
A policy consists of a purpose and a method. In the policy 1 of FIG. 4, the purpose is to “set the response time within the set time ± allowable range”, and the method is shown in a flowchart. This time, it is described in the flowchart for easy understanding, but it is also possible to describe in script language. A method for controlling the response time shown in the flowchart will be described below.
(Step 31) The management program on the management server collects information (performance statistical data) indicating response time and operating status from the client or business server at time intervals preset by the administrator.
(Step 32) A histogram of response time is created and a 90% value is calculated. The 90% value is a value at which the response time distribution equal to or lower than the 90% value is 90% of all data in the response time distribution (FIG. 9).
(Step 33) It is determined whether 90% of the response time is within (target response time ± allowable width). If so, step 31 is executed, and if not, step 34 is executed.
(Step 34) In the graph of performance model data shown in FIG. 5A, the graph is translated so that the point (Up, Ri) on the current memory latency delay graph Lb overlaps (Up, Rp).
(Step 35) The graph after the operation in Step 34 (FIG. 5 (b)) is searched for a graph that passes the target response time Rq with the current number of users. As a result, the decision is made to apply the memory latency delay Lc corresponding to the found graph to the business server. If no suitable graph is found, the graph closest to the target is selected.
(Step 36) The delay Lc of the memory latency determined in Step 35 is set in the business server.

  An example of observation target data is shown in FIG. The observation target data is set by the server administrator as to what data is to be observed by which client or business server. In FIG. 6, the response time is observed by the client x0, and the CPU usage rate, the number of connected users, and the disk queue length are observed by the business server y0.

  Examples of performance statistics data are shown in FIGS. The management server collects data related to the operating state from the client and the business server at time intervals preset by the administrator. As shown in FIG. 7, data such as the CPU usage rate, the number of connected users, and the disk queue are average values of data collected while a data request arrives from the management server. As shown in FIG. 8, the response time measured by the client is a set of response times (R00, R01,..., R0n) (R10, R0n) sent to the management server by collecting all response time logs at the client. R11, ..., R1n) (R20, R21, ..., R2n). The management program on the management server calculates 90% values Rth0, Rth1, and Rth2 shown in FIG. 9 from these statistical data and records them as performance statistical data. This 90% value is used to determine whether the above-described policy changes the memory latency.

  An example of the configuration information data is shown in FIG. The configuration information data includes a log indicating how the delay of the memory latency of each business server shown in FIG. 10A is changed and the server configuration information shown in FIG. FIG. 10A shows that the delay of memory latency has been changed to DLi0, DLi1, and DLi2 in the business server yi (i = 0, 1, 2). The memory latency delay recorded last is the current delay magnitude. The configuration information in FIG. 10B includes the number of CPUs, CPU frequency, memory mounting amount, number of disk drives, and the like.

Next, the process flow for making the response time constant will be described separately for initialization and operation.
(At initialization)
The flow of processing during initialization will be described with reference to FIG.
First, the system administrator requests the management server to investigate the configuration information of the current business server and the setting state of memory latency delay (40). The management server queries the business server for information (41), records the result in the configuration information data (42), and simultaneously displays the configuration information to the system administrator (43). The system administrator registers the target performance data (target response time and allowable range), performance model data, and performance policy in the management server (44, 45, 46).

  Next, the system administrator determines the delay value of the memory latency in the initial state and sends a business server configuration change request to the management server in order to register it in the business server (47). The management server calculates a delay value of the memory latency from the target performance data, performance model data, performance policy data, and configuration information (48). Then, a delay of memory latency is set for the business server (49). Thereafter, the management server checks whether the setting is correct (50), updates the configuration information data (51), and displays the change result on the screen (52). If it cannot be written correctly, it is executed again (not shown). When the number of times designated by the administrator has failed, the administrator is notified and the administrator's instruction is waited (not shown).

  Thereafter, the administrator sends a request for starting measurement of operation information to the management server (53). The management server sends a request to start the measurement agent to the client and the business server (54). The monitoring agent starts measuring response time and operating state information in the client and the business server that have received the request (55, 56).

(In operation)
The flow of controlling the memory latency to make the response time constant when the system is operating will be described with reference to FIG.
A performance monitoring agent is always running on the client and business server. The management program on the management server issues a request to send the response time measurement result and the operation status periodically to the monitoring agent of the client and the business server at the timing preset by the administrator (60). In the client, the monitoring agent sends the response time measurement result to the management server (61). In the business server, the monitoring agent sends the operating state measurement result to the management server (62). These response time and operating state data are managed by the management server as performance statistical information data.

The management program on the management server determines from the performance statistical information data and the target performance data whether the target performance condition is satisfied (64), and displays the result to the administrator (63).
If the management program determines that the target performance condition is not satisfied, the setting value of the memory latency delay is determined from the performance statistical information data, target performance data, performance policy data, performance model data, and configuration information data ( 65). Then, the delay value of the memory latency determined in (65) is set for the business server (66). The management program inquires of the business server whether the memory latency delay has been set correctly (68), updates the configuration information data if the value is correct, and displays the change information to the administrator (70). If it cannot be written correctly, it is executed again (not shown). When the number of times designated by the administrator has failed, the administrator is notified and the administrator's instruction is waited (not shown).
The processing flow for making the response time constant has been described above separately for initialization and operation.

FIG. 13 is a block diagram of the CPU representing the second embodiment of the present invention.
The CPU 50 includes a CPU core 101, a cache memory 102, address queues 104 and 106, data queues 108 and 110, queue control circuits 105, 107 and 109, and a latency variable queue control circuit 103.

The CPU core 101 is a part for processing instructions, and is connected to a cache memory 102 built in the CPU. The CPU core 101 fetches instructions and data from the cache memory 102, but when the data required by the CPU core 101 does not exist in the cache memory 102 (cache miss), the main memory is stored in the address bus 111 through the queue 104. Alternatively, a transaction for accessing data held by another cache is issued. The memory request transaction issued to the address bus is received by the other CPU (not shown) connected to the same address bus 111 and the chip set 114.
Since other CPUs have the same structure as the CPU 100, the CPU 100 will be described here. The memory request transaction issued to the address bus 111 arrives at the CPU core 101 via the queue 106. The CPU core 101 checks the cache memory 102 for data at the address requested by the transaction.
This means a general bus snooping operation. It is notified to the CPU that issued the request through the address bus 111 or another dedicated line (not shown) whether there is data requested by the memory request transaction in the cache memory. If it exists, the data is transferred to the data bus 112 through the queue 108 to the data bus.

  On the other hand, the memory request transaction transferred from the address bus 111 to the chip set 114 is transferred from the chip set 114 to an address bus connected to the main memory (not shown) or another chip set (not shown). An inquiry is made to the CPU connected to the address bus, bus snooping is performed, and the result of checking whether there is data in the cache is notified to the CPU that issued the request. Further, the data at the address requested by the memory request transaction is transferred from the main memory to the chip set 114. In the chip set 114, data from the main memory or data sent from another cache is determined from the bus snooping result, and the data is transferred to the data bus 112. The CPU 100 stores this data in the cache memory via the queue 110 and uses it for processing in the CPU core.

The configuration and operation of the queue control circuits 105, 107, and 109 will be described with reference to FIG. As shown in FIG. 14, the queue control circuit 120 includes a write pointer 121, a pointer control circuit 122, and a read pointer control circuit 123. The write pointer 121 includes a counter, indicates the position of a queue that stores a newly arrived transaction, and outputs a write pointer signal. On the other hand, the read pointer 123 indicates a position where a transaction issued from the queue is stored, and outputs a write pointer signal.
The queue control circuit 120 receives a set signal 127 indicating that a transaction to be stored in the queue has arrived from the transaction issuer, and inputs the set signal 127 to the pointer control circuit 122. The pointer control circuit counts up the value when the set signal arrives after writing the transaction and shifts the position indicated by one. Further, the release signal 125 notifies a queue connection destination block (not shown) that a transaction can be issued. When the pointer control circuit receives a release completion signal 128 indicating that this block has received a transaction, the read pointer 123 is incremented by one and the position indicated by the pointer is shifted by one.

  Next, the configuration of the latency variable queue control circuit 103 will be described with reference to FIG. As shown in FIG. 15, the latency variable queue control circuit 129 has a configuration in which a delay control circuit 120, a wait counter 131, a delay value register 132, and a comparator 133 are added to the queue control circuit 120 described above. The added part operates to delay the release timing of the queue in order to change the memory latency. The delay time is set in the delay value register 132. The delay value register 132 is a register arranged in the memory space and has a structure in which an appropriate numerical value can be set by accessing from software.

This operation of the latency variable queue control circuit 103 will be described with reference to FIG.
(Step 140) The delay control circuit 120 executes Step 31 when no transaction is stored in the queue storing the transaction, and executes Step 32 when no transaction is stored.
(Step 31) When the delay control circuit 120 releases the transaction stored in the queue, the delay control circuit 120 starts the wait counter 131 so that the transaction issuance destination does not receive the transaction. Go to 33.

(Step 32) When the delay control circuit 120 sets a transaction in the queue, the delay control circuit 120 starts the wait counter 131 so that the release signal is not activated so as not to receive the transaction at the transaction issue destination. What.
(Step 33) When the comparator 133 detects that the contents of the wait counter 131 and the delay register 132 match, the delay control circuit 120 issues a request to release the transaction from the queue to the pointer control circuit 122 to release the signal. Activate At the same time, the wait counter 131 is reset, and the process goes to step 140.
The latency variable queue control circuit 103 can delay the issue timing of the memory request transaction issued by the CPU 50 by the number of cycles set by the administrator in the delay value register 132, thereby enabling memory latency control.

FIG. 17 is a block diagram of a chip set representing the third embodiment of the present invention. The chip set 150 includes address queues 154, 155, 164, 170, data queues 156, 157, 165, 166, 171, 172, and queue control circuits 159, 160, 161, 168, 169, 173, 174, 175 and variable latency. It comprises queue control circuits 158 and 167 and multiplexers 162, 163, 183, 184, 185 and 186.
The queue control circuits 159, 160, 161, 168, 169, 173, 174, and 175 are the same circuits as those in FIG. 14 described in the second embodiment. The latency variable queue control circuits 158 and 167 are the same circuits as the circuit of FIG. 15 described in the second embodiment. The description of the configuration and operation of these queue control circuit and latency variable queue control circuit will be made with reference to the second embodiment, and description thereof will be omitted here.

Next, the interface between the chipset 150 and other modules will be described.
First, the chipset 150 is connected to the address bus 152 and the data bus 153, and through these, the CPU 150-0, 150-1, 150-2, and 150-3 perform memory request transactions and data transactions. They can be transferred to each other.
Second, the chipset 150 is interconnected with the memory controller 180, and the memory request transaction is transferred from the chipset 150 to the memory module 181 via the memory controller 180. The memory module 181 transfers the requested address data to the chip set via the memory controller 180. The write-back transaction generated by the CPU cache line replacement includes a write-back transaction for designating a write address from the chipset 150 and a data transaction for the write data from the chipset 150 via the memory controller 180 to the memory module 181. And data writing is performed.

Thirdly, the chipset 150 is also connected to the I / O bridge 183, and an inbound transaction for performing DMA transfer from the PCI device 184 such as a network card or a SCSI card to the main memory, or from the CPU to the PCI device. Inbound transactions that are accesses to the network are transferred to each other via the I / O bridge 183.
Finally, the chip set 150 is interconnected with other chip sets 182, and memory request transactions, write back transactions, data transactions, and the like are transferred to each other. This connection is used to access the CPU, memory module, and PCI device connected to the chipset 182.

In some cases, two or more chip sets are interconnected using a crossbar switch. Since it can be understood by analogy with the examples so far, the description is omitted here.
The operation of the chip set 150 in FIG. 17 will be described.
In addition, although the snooping method is used for the cache coherency control in the target chipset, the details of the cache coherency control are not changed by this patent, so in this embodiment, only the flow of transactions will be described. . The memory request transaction issued by the CPU 150-i (i = 0, 1, 2, 3) is stored in the address queue 154 of the chipset 150 via the address bus 152. The address queue 154 is controlled by the latency variable queue control circuit 158, and the administrator determines a delay time for releasing the transaction from the address queue 154. The memory request transaction issued from the address queue 154 is transferred to the memory controller 180, the I / O bridge 183, and the chipset 182, and cache coherency control is performed. When there is the latest data in the cache memory of the CPU, the data is transferred from the chipset 182 to the data bus 153 with the requesting CPU via the data queue 172, the multiplexer 163, and the data queue 157, and the request source The CPU receives data. Data from the main memory (memory module 181) is transferred via the multiplexer 163 and data queue 157 to the data bus 153 where the requesting CPU is located, and the requesting CPU receives the data.

On the other hand, the inbound transaction from the PCI device 184 is stored in the address queue 164 of the chipset 150 via the I / O bridge 183. The timing of releasing the address queue 164 by the latency variable queue control circuit 167 is changed. The inbound transaction issued in the address queue 164 is issued to the address bus 152 via the multiplexer 162 and the address queue 155, and processing for cache coherency is performed. The data is transferred to the memory controller 180 via the multiplexer 184 to the memory. For cache coherency processing to other hipsets 182 and memory access. The data is transferred to the chip set 182 via the multiplexer 183. When data in the memory is read by DMA transfer, the data is transferred from the memory module 181 to the I / O bridge via the memory controller 180, the multiplexer 185, and the data queue 166. When data is written from the I / O to the memory by DMA transfer, the memory request transaction is transferred from the I / O bridge 183 to the memory controller 180 via the queue 164 and the multiplexer 184. On the other hand, the data is transferred to the memory controller 180 via the data queue 165 and the multiplexer 186, and the data is written to the memory module 181.
With the above operation, the server performance can be controlled by manipulating the release timing of the address queue in the chipset.

  FIG. 18 shows the hierarchical structure of the firmware representing the fourth embodiment of the present invention. The computer has a hierarchical structure of hardware 200, firmware 201, OS 202, and application 203. The firmware 201 initializes the hardware 200 after power-on, and sets an environment for operating the OS 202 in the hardware 200.

The hardware 200 includes a mechanism for changing the memory latency delay described in the second or third embodiment. This memory latency delay cycle number is provided as a configuration register allocated in the memory space. When the firmware 201 is starting up after power-on or system reset, the hardware performance is changed by accessing this configuration register.
When it is necessary to frequently switch to the firmware setup screen, such as when developing a computer, or when the message displayed by the firmware must be read, switching to the setting screen or other messages by reducing the hardware performance Do not miss any error messages that appear on the screen.

FIG. 19 shows a flow of processing in which the firmware 201 sets the memory latency delay of the hardware 200.
The computer administrator 220 turns on the hardware 200 (210). Then, the hardware 200 executes BIST (Built In Self Test) (211). The CPU, chipset, and memory each execute BIST. When these are completed, the hardware 200 starts the firmware 201 stored in the ROM (212). The firmware 201 sets a memory latency delay for the hardware 200 after being activated. The magnitude of this delay is set in advance by the administrator 220. The delay of the memory latency of the hardware 200 is increased only during the period when the firmware 201 is displaying a message when initializing the hardware 200 (216) and when the firmware 201 is waiting for the switching key input on the setup screen (217). Keep it. Before these periods are over and before attempting to load the OS boot loader onto the memory, the firmware 201 sets the memory latency delay to 0 and restores the original performance (213). Thereafter, the firmware 201 loads the OS boot loader onto the memory (214), and starts the OS (215).

  With the above operation, when the message displayed by the firmware has to be read, the performance of the hardware may be reduced so that the switching message to the setting screen and other error messages displayed on the screen are not overlooked. it can.

  The present invention provides means for stably controlling the response performance of an information processing system based on the operating state, and the performance can be set universally without affecting the type of CPU being used. Adoption is expected.

1 is a block diagram of a system representing a first embodiment of the present invention. An example of target performance data. An example of performance model data. An example of performance policy data. Conversion process of performance model data. An example of monitoring target data. An example of performance statistics data (excluding response time). An example of performance statistics data (response time). 90% value in response time distribution. An example of configuration information data. Flow of operation of system of first embodiment (at initialization). The flow of operation | movement of the system of a 1st Example (at the time of operation). The block diagram of CPU showing the 2nd Example of this invention. The block diagram of a queue control circuit. The block diagram of a latency variable queue control circuit. Logic of the delay control circuit of the latency variable queue control circuit. The block diagram of the chipset showing the 3rd example of the present invention. The block diagram of the firmware showing the 4th Example of this invention. Firmware processing flow.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Client 2 Business server 3 Client monitoring agent 4 Management server 5 Management program 8 Target performance data 9 Performance model data 10 Performance policy data 11 Monitoring object data 12 Performance statistics data 13 Configuration information data 21 Server monitoring agents 100, 151-0, 151 -1,151-2, 151-3 CPU
101 CPU core 102 Cache memory 103, 129, 158, 167 Latency variable queue control circuit 105, 107, 109, 120, 159, 160, 161, 167, 168, 169, 173, 174, 175 Queue control circuit 104, 106, 154, 155, 164, 170 Address queue 108, 110, 156, 157, 165, 166, 171, 172 Data queue 111, 152 Address bus 112, 153 Data bus 114, 150, 182 Chipset 121 Write pointer 122 Pointer control circuit 123 Read pointer 124 Write pointer signal 125 Release signal 126 Read pointer signal 127 Set signal 128 Release completion signal 130 Delay control circuit 131 Wait counter 132 Delay value register 33 comparator 180 the memory controller 181 memory module 183 I / O bridge 184 PCI devices 162,163,183,184,185,186 multiplexer 200 hardware 201 firmware 202 OS
203 Application.

Claims (6)

A business server composed of one or more computers having an interface capable of changing the memory latency during operation, one or more clients on which an agent program for measuring a response time from the business server operates, and the agent Appropriate memory latency is obtained from performance monitoring processing for comparing the target performance values by creating statistical data of the response time measured by the program and data representing the correlation between the memory latency and the response time, and the memory latency of the business server. And a management server that controls the memory latency of the business server so as to maintain the target performance value by feeding back the response time of the business server after changing the memory latency. Computer system. CPU core,
Cache memory,
A first queue for storing memory access transactions issued by the CPU core to the address bus;
A wait cycle specifying register for setting an interval for sending a memory access transaction in which the first queue is stored, and a wait cycle for counting a waiting time for sending a transaction in the first queue. A counter, a comparison circuit for comparing the value stored in the wait cycle designation register with the value stored in the wait cycle counter, and the comparison circuit matches the values stored in the wait cycle designation register and the wait counter A latency control circuit for controlling the memory latency, comprising a first queue control circuit for sending the first memory access transaction in the first queue to the address bus when it is determined that
A second queue for storing memory access transactions from the address bus to the CPU core;
A second queue control circuit for controlling the second queue, a third queue for storing a data transaction to be written from the CPU core to the memory,
A third queue control circuit for controlling the third queue;
A fourth queue for storing data transactions sent from memory;
A CPU having a fourth queue control circuit for controlling the fourth queue. An address bus and a data bus connected to the CPU;
I / O bridge and memory controller connected to PCI devices,
Interface with other chipsets,
A queue for storing memory access transactions issued by the CPU to the address bus;
A wait cycle designation register for setting an interval for sending a memory access transaction in which the queue is stored, a wait cycle counter for counting a waiting time for sending a transaction in the queue, and the wait cycle A comparison circuit for comparing a value stored in the designated register with a value stored in the wait cycle counter; and when the comparison circuit determines that the values stored in the wait cycle designation register and the wait counter match. A chip set comprising a queue control circuit for sending the first memory access transaction in the queue to the address bus, and a latency control circuit for controlling memory latency. An address bus and a data bus connected to the CPU;
An I / O bridge that connects to PCI devices,
A memory controller;
Interface with other chipsets,
A first queue for storing memory access transactions issued by the CPU to the address bus;
A first wait cycle specification register for setting an interval for issuing a transaction in which the first queue is stored, and a waiting time for sending a memory access transaction in the first queue is counted. A waiting first cycle counter, a first comparison circuit for comparing a value stored in the first waiting cycle designation register with a value stored in the first waiting cycle counter, and the first comparison circuit A first latency control circuit for controlling the memory latency by providing a first queue control circuit for sending the first memory access transaction in the first queue to the address bus when it determines that the values match.
A second queue for storing DMA transactions issued by the PCI device via the I / O bridge;
A second wait cycle designating register for setting an interval for issuing a transaction in which the second queue is stored, and a second wait cycle transmission time count for counting DMA transactions in the second queue; 2 wait cycle counters, a second comparison circuit that compares the value stored in the second wait cycle designation register with the value stored in the wait cycle counter, and the comparison circuit determines whether the values match. A chip set comprising a second queue control circuit for sending the first DMA transaction in the second queue to the address bus, and a second latency control circuit for controlling memory latency. Response time and target response time of transactions issued from the client to the business server, a relationship table of memory latency and response time collected in advance for each service provided by the business server, and the delay of the memory latency of the business server From the configuration information indicating the response time, the statistical value of the response time, the operating state of the business server, and the target performance, an appropriate memory latency delay magnitude that brings the statistical value of the response time close to the target response time is selected. When a performance policy, which is a procedure manual for making a decision, is input, and the statistical value of the response time deviates from a predetermined range of the target response time, a large memory latency delay is caused for the business server. A server management program that outputs instructions to set the file size. A computer system equipped with firmware that initializes a platform at the time of startup of the computer, the step of setting the delay of the memory latency of the computer to increase before the key input for moving to the setting screen of the firmware, and the key After the input display, the step of reducing the delay of the memory latency of the computer at a preset timing, the step of increasing the delay of the memory latency of the computer when the firmware displays a message, and after displaying the message, A computer system comprising the firmware having a step of reducing a delay in memory latency of the computer at a set timing.

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