JP2006091475A - Image processing apparatus and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing apparatus in which high-speed arithmetic processing is achieved by causing a smaller circuit to perform non-linear conversion processing in modulation element control of a display device. <P>SOLUTION: In the image processing apparatus for a display device that forms a display image by modulating light from a predetermined light source using a modulation element, an offset bit and a shift amount S are determined in accordance with the state of predetermined high-order bits (T bits) of a luminance value X1 that is an integral input control value, and by coupling K bits resulting from shifting the luminance value X1 for the shift amount S and the offset bit, a conversion luminance level Yb is determined. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for improving image quality of a display device, and more particularly to an image processing device and method suitable for realizing an increase in dynamic range of display luminance, an increase in gradation, and an increase in contrast.

In recent years, electronic display devices such as LCD (Liquid Crystal Display), EL (Electro-Luminescence), plasma display, CRT (Cathode Ray Tube), and projection display devices have improved dramatically. Devices with performance that is roughly comparable to the characteristics are being realized. However, regarding the luminance dynamic range, the reproduction range is limited to about 1 to 10 ² [nit], and the number of gradations is generally 8 bits. On the other hand, the human visual perception has a range of luminance dynamic range that can be perceived at a time of about 10 ⁻² to 10 ⁴ [nit], and the luminance discrimination ability is 0.2 [nit]. It is said to be considerable. When viewing the display image of the current electronic display device via such visual characteristics, the narrowness of the luminance dynamic range is conspicuous, and in addition, the gradation of the shadow part and highlight part is insufficient, so the display image You will feel unsatisfied with reality and power.

  In CG (Computer Graphics) used in movies, games, etc., the movement for pursuing the reality of depiction by giving the data a luminance dynamic range and gradation characteristics close to human vision is becoming mainstream. However, since the performance of the electronic display device that displays it is insufficient, there is a problem that the expressive power inherent in CG content cannot be fully exhibited.

  In addition, the next Windows (registered trademark) is scheduled to adopt a 16-bit color space, and the dynamic range and the number of gradations are dramatically increased as compared with the current 8-bit color space. For this reason, it is expected that there will be an increasing demand for realizing a high dynamic range and high gradation electronic display device that can make use of the 16-bit color space.

  Among electronic display devices, projection display devices such as liquid crystal projectors and DLP (Digital Light Processing) (registered trademark) projectors are capable of displaying large screens and are effective in reproducing the reality and power of displayed images. Device. In this field, the following proposals have been made to solve the above problems.

  The basic configuration for expanding the luminance dynamic range in a projection display device is to form a desired illumination light quantity distribution by modulating a luminous flux emitted from a light source with a first transmission type modulation element, and It is transmitted on the two transmissive modulation elements to illuminate it. As the transmissive modulation element, an element having a pixel structure or a segment structure whose transmittance can be individually controlled and capable of controlling a two-dimensional transmittance distribution is used. A typical example is a liquid crystal light valve. A reflective modulation element may be used instead of the transmission modulation element, and a typical example is a DMD (Digital Micromirror Device) element.

  Consider a case where a transmission type modulation element having a transmittance of 0.2% for dark display and a transmittance of 60% for bright display is used. In a configuration in which a modulation element is used alone in a conventional projection display apparatus, the luminance dynamic range is 60 / 0.2 = 300. On the other hand, the above configuration using two modulation elements corresponds to (optically) serial arrangement of 300 transmissive modulation elements with a dynamic range, so theoretically a dynamic range of 300 x 300 = 90000 is realized. It becomes possible to do. Further, the same idea holds for the gradation characteristics, and the gradation characteristics exceeding 8 bits can be obtained by arranging (optically) the transmission modulation elements of 8 bits gradation in series.

  The first and second transmission (reflection) modulation elements are driven separately by the first and second modulation signals generated from the video signal.

  An example of a display device using two modulation elements is described in Patent Document 1. In this conventional example, LCD is used as the first light modulation element, and light source illumination that can be modulated for each region such as LED (Light Emitting Diode) and fluorescent lamp is used as the second light modulation element, and pixel value data of each pixel is obtained. Based on this, backlight luminance control + LCD gradation control is performed. As a method of determining the luminance level of the backlight, an average luminance level of pixels existing in an area illuminated by the backlight is obtained, and the obtained average luminance level is positioned closest to the median value (reference value) of the displayable signal level range. A method for selecting such a backlight brightness level is shown. This method is a processing flow for comparing a plurality of reference values many times and determining a backlight luminance level indicating the closest value. This processing flow has a problem that the processing time increases as the number of luminance levels increases.

  As a simple calculation method for suppressing an increase in calculation processing time for obtaining the backlight luminance level, there is a linear calculation method in which lower bits are discarded. The backlight luminance level is obtained by this linear calculation, and the control value of the other modulation element is obtained based on the luminance level. It has been found that a display image obtained by simply linearly converting the luminance value of a pixel is an image with poor gradation in the dark part. This is because the visual sensitivity characteristic with respect to human brightness is ignored. Considering the visibility characteristics with respect to human brightness, the dark portion is fine, and conversion with a small number of gradations is effective when the luminance is high. Such conversion includes non-linear conversion.

Patent Document 2 describes an example of an image processing apparatus using nonlinear transformation. In this conventional example, a method for high-speed processing of nonlinear conversion is used. Divide the value to be converted into several intervals. The input value is compressed and output in each section, but the compression ratio is doubled (1/2) in the adjacent section, thereby realizing a process of compressing only by bit manipulation. The comparison is performed from the most significant bit, and the section is divided according to the position where 1 appears for the first time. The maximum number of bits used for segmentation is specified as J. Further, the section in the section is performed using the fixed length bit (K bit) following the upper bit (j bit) used as the section. Since the number of classifications in each interval is a fixed number (defined by K), it can be seen that this non-linear transformation is a non-linear transformation for a power-of-two curve. In this conventional example, in order to obtain a compressed value, 2K−1 · (J−j + 2) is defined as an offset value, and the target numerical value is obtained only after performing multiplication and addition operations. Is possible.
JP 2002-99250 A JP 2001-143063 A

  However, in moving image data processing, it is desired to perform data processing with a minimum of multiplication operation, and when determining a control value on the luminance side, the circuit scale increases if multiplication + addition processing is performed for each pixel. There is a problem that the processing speed also decreases.

  The present invention has been made in view of such circumstances, and can perform non-linear conversion processing used in controlling a modulation element in a display device with a smaller circuit (simple configuration) than that in the past, and can perform at higher speed. An object of the present invention is to provide an image processing apparatus and method capable of realizing various arithmetic processes.

  In order to solve the above problems, the present invention is an image processing apparatus for a display device that forms a display image by modulating light from a predetermined light source by a modulation element, and for obtaining a control value of the modulation element The processing means obtains an offset value and a shift amount according to a state of a predetermined high-order bit of the integer type input control value, and a plurality of bits obtained by shifting the input control value by the shift amount, and The output control value is obtained by combining the offset bit representing the offset value. According to the present invention, non-linear conversion processing can be performed only by bit processing, and conversion processing can be executed at a very high speed.

  The present invention is also an image processing apparatus for a display device that forms a display image by modulating light from a predetermined light source with a modulation element, and includes processing means for obtaining a control value of the modulation element. The processing means obtains a predetermined set value and a shift amount corresponding to the offset value according to a state of a predetermined high-order bit of the integer type input control value, and a plurality of input control values shifted by the shift amount The output control value is obtained by a logical operation of the bit and the set value in bit units. According to the present invention, non-linear conversion processing can be performed only by bit operation, and conversion processing can be executed at a very high speed.

    The present invention also drives a plurality of light modulation elements from a pixel value in a display device that forms a display image by modulating a plurality of light modulation elements optically arranged in series with light from a predetermined light source. An image processing apparatus that generates a signal, an integerization processing unit that converts a pixel value to an integer, a luminance value calculation unit that calculates a luminance value from the pixel value that has been converted to an integer, a non-linear conversion of the luminance value, and a luminance panel A non-linear luminance level calculation unit which calculates a control value of a light modulation element forming a color panel from a pixel value and a luminance panel control value However, according to the remaining bits (J bits) excluding the higher-order several bits (A bits) among the predetermined upper bits (T bits) of the input luminance value, “1” is started for the first time from the upper bits of the J bits. Or “0” appears. A bit detection means for obtaining a position to be shifted, a shift means for shifting the input luminance value by a predetermined shift amount based on the detection result of the bit detection means, and an offset generated based on the shifted bit string and the detection result of the bit detection means Bit combining means for determining a control value by combining bits. According to the present invention, non-linear conversion processing can be performed only by bit processing, and conversion processing can be executed at a very high speed.

  The present invention is also characterized in that when the number of offset bits is n bits, the number of bits of the J bits is 2n-1. According to the present invention, the conversion luminance level can be calculated only by bit combination, and the conversion process can be executed at a very high speed.

  The present invention is also characterized in that the number of bits of the J bits is 7 bits and the number of bits of the output control value is 8 bits. According to the present invention, it is possible to execute nonlinear conversion closer to a desired characteristic at high speed when obtaining a control value of 8-bit output.

  The present invention is also characterized in that the shift means is a barrel shift circuit. According to the present invention, since the shift processing is fast, the processing speed can be increased.

  The present invention also drives a plurality of light modulation elements from a pixel value in a display device that forms a display image by modulating a plurality of light modulation elements optically arranged in series with light from a predetermined light source. An image processing apparatus that generates a signal, an integerization processing unit that converts a pixel value to an integer, a luminance value calculation unit that calculates a luminance value from the pixel value that has been converted to an integer, a non-linear conversion of the luminance value, and a luminance panel A non-linear luminance level calculation unit which calculates a control value of a light modulation element forming a color panel from a pixel value and a luminance panel control value However, according to the remaining bits (J bits) excluding the higher-order several bits (A bits) among the predetermined upper bits (T bits) of the input luminance value, “1” is started for the first time from the upper bits of the J bits. Or “0” appears. A bit detecting means for obtaining a position to be detected, a shifting means for shifting the input luminance value by a predetermined shift amount based on a detection result of the bit detecting means, a predetermined bit obtained based on the shifted bit string and the detection result of the bit detecting means And a bit operation means for obtaining a control value by performing a logical operation in bit units with the set value. According to the present invention, non-linear conversion processing can be performed only by bit operation, and conversion processing can be executed at a very high speed.

  The present invention is also characterized in that the set value includes a value corresponding to an offset value based on the J bits with two or more different bit lengths, and the logical operation is exclusive OR. According to the present invention, it is possible to execute a nonlinear transformation that is closer to a desired characteristic at high speed.

  The present invention is also an image processing method for a display device that forms a display image by modulating light from a predetermined light source by a modulation element, and in the process for obtaining a control value of the modulation element The offset value and the shift amount are obtained according to the state of a predetermined higher-order bit of the integer type input control value, and a plurality of bits obtained by shifting the input control value by the shift amount and the offset bit representing the offset value are combined. Thus, the output control value is obtained.

  The present invention is also an image processing method for a display device that forms a display image by modulating light from a predetermined light source by a modulation element, and in the process for obtaining a control value of the modulation element A predetermined set value and a shift amount corresponding to the offset value according to a state of a predetermined higher-order bit of the integer type input control value, and a plurality of bits and the set value obtained by shifting the input control value by the shift amount The output control value is obtained by a logical operation in bit units.

  Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, in a display device that forms a display image by modulating a plurality of light modulation elements optically arranged in series with light from a predetermined light source, the plurality of light modulation elements are driven from pixel values. The image processing apparatus which produces | generates the signal to perform is comprised. However, the configuration of the display device is not limited to that described here, but can be applied to other non-linear characteristics that are used for controlling the light modulation element. In each figure, the same reference numerals are used for corresponding components.

  FIG. 1 is an example of a configuration diagram of a projection display device according to the present embodiment, in which optical modulation elements are optically arranged in series. As shown in FIG. 1, the projection display device 1 includes a light source 10, a uniform illumination unit 20 that uniformizes a luminance distribution of light incident from the light source 10, and an incident light incident from the uniform illumination unit 20. Color modulator 30 that modulates the brightness of each of the three primary colors (R, G, B), relay lens 40 that relays light incident from color modulator 30, and the luminance of all wavelengths in the light incident from relay lens 40 A luminance modulation light valve (luminance panel) 50 for modulating the light and a projection lens 60 for projecting light incident from the luminance modulation light valve 50 onto a screen (not shown).

  The light source 10 includes a lamp 11 such as a high-pressure mercury lamp, and a reflector 12 that reflects light emitted from the lamp 11. The light beam emitted from the light source 10 is made uniform by the uniform illumination means 20 in which the first fly-eye lens 21, the second fly-eye lens 22, the polarization conversion element 23, and the condenser lens 24 are sequentially installed. Further, the light is converted into polarized light having a uniform polarization direction by the polarization conversion element 23.

  Liquid crystal light valve (color panel) 31 that modulates the respective color components after the light with uniform polarization emitted from the uniform illumination means 20 enters the color modulation unit 30 and is separated into three primary colors (R, G, B), It is modulated by 32, 33 (first modulation). The modulated three primary color lights (R, G, B) are combined by the cross dichroic prism 34 and output to the relay lens 40. Here, the liquid crystal light valve 31 forms a light modulation element for the R component, the liquid crystal light valve 32 for the G component, the liquid crystal light valve 33 forms a light modulation element for the B component, and the dichroic mirror 35 transmits the light for the R component. The dichroic mirror 36 transmits the B component light. A reflection mirror 37 is provided for the liquid crystal light valve 31, and a relay lens 38 and two reflection mirrors 39a and 39b are provided for the liquid crystal light valve 33.

  The modulated light emitted from the relay lens 40 enters the luminance modulation light valve 50 (second modulation) that forms the other light modulation element (liquid crystal modulation element), and undergoes second modulation. The luminance modulation light valve 50 modulates the luminance of all wavelengths of incident light, and the modulated light is emitted to the projection lens 60 and projected onto a screen (not shown) by the projection lens 60. In this way, the projected image is formed by modulating each light modulation element (luminance modulation light valve 50 and liquid crystal light valves 31, 32, 33) optically arranged in series on a pixel basis.

  FIG. 2 shows an example of the circuit configuration of the image processing apparatus 102 and its peripheral circuits according to the present embodiment. An HDR (High Dynamic Range) video signal is input to the image processing apparatus 102 via the interface 101. The image processing apparatus 102 performs processing for obtaining the control value Yb for the luminance panel and the control value Yc for the color panel based on the input pixel value X0. The luminance panel control value Yb obtained by the image processing apparatus 102 is stored in the luminance frame memory 103, and the color panel control value Yc is stored in the color frame memory 104. The drive control circuit 105 gives the control values stored in the respective frame memories 103 and 104 to the corresponding light modulation elements (luminance modulation light valve 50 and liquid crystal light valves 31, 32 and 33) as drive signals. It displays images with a wide luminance dynamic range.

  FIG. 3 is a block diagram of the image processing apparatus 102 of FIG. In the case of HDR data, the pixel value X0 is often expressed as a floating point. In the case of a floating point, the integer processing unit 201 performs integerization (binary integer conversion). Here, it is assumed that 32-bit integer processing is performed by multiplying system coefficients such as the maximum luminance level. The 32-bit integerized pixel value X0 ′ is input to the luminance calculation unit 202. The luminance value calculation unit 202 obtains the luminance value X1 based on the pixel value data X0 ′. The normal luminance value Y is obtained as Y = 0.30 * R + 0.59 * G + 0.11 * B (R, G, and B are RGB signal systems). It may be obtained as Y = 30 * R + 59 * G + 11 * B by unit conversion. Although the image quality is slightly lowered, by setting Y = 32 * R + 64 * G + 8 * B, it is possible to realize coefficient multiplication only by shift processing. The luminance value X1 obtained by the luminance value calculation unit 202 in this way is sent to the non-linear luminance level calculation unit 203, where the control value calculation of the luminance panel is performed and the Yb conversion luminance level is calculated. The color panel control value Yc is obtained by the color value calculation unit 204 from the obtained Yb conversion luminance level (luminance panel control value) and the pixel value X0. In these processes, calculation processing is performed using the characteristic tables of the brightness panel (brightness modulation light valve 50) and the color panel (liquid crystal light valves 31, 32, 33), but details of the process are omitted here. .

  FIG. 4 is a block diagram of the nonlinear luminance level calculation unit 203 in FIG. The total number of bits of the luminance value X1 converted to an integer by the luminance value calculation unit 202 is M bits (see FIG. 8A). A predetermined number of bits from the most significant bit of the luminance value X1 is referred to as T bits. The T bit is a determination bit string, and the upper several bits are referred to as an A bit string and the remaining bit strings are referred to as a J bit string. The T bit string is sent to the bit detection unit 301. The bit detection unit 301 calculates the select signal (SEL), the offset (offset) bit string, and the shift amount (S) when shifting the luminance value X1 according to the state of the T bit string. The bit concatenation unit 302 concatenates (combines) the Offset bit string and the K bit string having a predetermined bit length out of the luminance value X1 shifted by the shift circuit 303 configured by the barrel shifter, and the Ya bit string (conversion luminance value) ) Is generated. The generated Ya bit string is sent to the selector circuit 304. To the selector circuit 304, a bit string having all bits “1” and a Ya bit string, and a selector signal (SEL) for determining which input bit string to select are input.

  FIG. 5 is a block diagram of the bit detection unit 301 in FIG. The A bit string that is the upper bit string of the input T bit string is sent to the select signal generation unit 401, and the J bit string that is the remaining bit string is sent to the R bit generation unit 402. The select signal generation unit 401 generates a select signal (SEL) based on the input A bit string. The R bit generation unit 402 generates an R bit indicating a position where “1” is first detected from the most significant bit of the J bits. The decoding circuit 403 generates an Offset bit and a shift amount (S) based on the R bit.

  FIG. 6 is a block diagram of the SEL signal generation unit 401 in FIG. An i-bit A bit string is input to this circuit, and it is detected that “1” is present in at least one bit in the A bit string. In this example, a basic OR circuit 4011 is used.

  FIG. 7 is a block diagram of the R bit generation unit 402 of FIG. If the length of the input J bit string is m bits, the most significant bit is expressed as J [m−1]. In this circuit, the R bit indicating the position where “1” is detected for the first time from the most significant bit is obtained. This is realized by a combination of exclusive OR 501 to 504 and logical products 505 to 507.

  FIG. 8 is a diagram for explaining an example of bit detection for the luminance value X1. The high-order bits of the input luminance value X1 are T bits, and are used for the purpose of classifying the luminance value X1 (weight division into a plurality of areas). The T bit string is composed of an A bit string and a J bit string, and is classified into a total number of states J + 2 of one state value (valid or invalid) based on the A bit string and J + 1 state value in the J bit string. Used for. The state value is determined by whether or not at least one “1” appears for the A bit string.

  In the example shown in FIG. 8A, the T bit is 5 bits, the A bit string is 2 bits, and the J bit string is 3 bits. In this case, as shown in FIG. 8 (b), both or one of the two bits of the A bit string is “1” (in the case of positive logic) (or “0” (in the case of negative logic); The same applies to the bit string), and it is determined that the A bit string is valid. At this time, the non-linear luminance level calculation unit 203 outputs a conversion result in which all bits of the converted luminance level Yb are “1”. . On the other hand, when each bit of the A bit string is “0”, it is determined that the A bit string is in an invalid state, and processing is performed using other bit strings excluding the A bit (FIGS. 8C to 8F). .

  For the J bit string, the position where “1” appears for the first time is counted from the most significant bit of the J bit string. When the appearance of “1” can be detected for the first time with the J bit, the shift amount for shifting the bit string of the luminance value X1 to the right (lower bit direction) by a predetermined bit according to the appearance position ( S) is required. Also, as shown in Fig. 8 (c), when the most significant bit of the J bit string is "1", the bit string of K bit length (6 bits in the example of Fig. 8) is the K bit string for the first time from the next bit. Detected. The K bit string is a fixed-length bit string. From the number of bits of luminance value X1 (M bits) to the number of bits in the A bit string, the number of bits from the most significant bit of the J bit string to the position where “1” was first detected (1 bit in this case), and K bits The remainder excluding the number is the shift amount (S). For example, when the number of bits (M bits) of the luminance value X1 is 32 bits, the shift amount (S) is 23 bits (= 32−2 (A bit) −1 (J bits) in the example of FIG. 8C. The number of bits up to the first “1” bit position) −6 (K bits)).

  8 (d), (e), and (f) show that the number of bits from the most significant bit up to the position where “1” is first detected in the J bit string is 2 bits, 3 bits, and Each state when “1” is not detected is shown. In these cases, the K bits are a bit string having a length of 6 bits, starting from the fourth, fifth, and fifth bits from the top. The shift amount (S) is M-2-2-6 bits (22 bits), M-2-3-6 bits (21 bits), and M-2-3-6 bits (21 bits), respectively. (If M = 32 in parentheses)

  When the luminance value X1 is shifted based on the shift amount (S) determined here, the Kth bit from the least significant bit of the obtained bit string is the bit for which “1” is detected for the first time in the J bit string. It is a bit located one level lower. These K bit strings (K bit strings) are used for calculating the converted luminance level Yb.

  The R bit generation unit 402 shown in FIGS. 5 and 7 obtains the R bit from the J bit, and the decoding circuit 403 in FIG. 5 obtains the offset bit from the R bit, and concatenates the offset bit string and the K bit string. Thus, the converted luminance level Yb is obtained. Note that the shift amount (S) is also determined by the decoding circuit 403 based on the R bit.

  FIG. 9 presents an example of the conversion process. In this example, M = 32-bit luminance value X1 is nonlinearly converted to an 8-bit converted luminance level Yb. Here, the T bit string is 5 bits, the A bit string is 2 bits, and the J bit string is 3 bits. The number of states classified by the 3-bit J bit is 4 (the most significant bit is “1”, the second bit is “1” for the first time, the third bit is “1” for the first time, and there is no “1”. Therefore, the offset bit length is 2 bits (the number of bits necessary to correspond to different offset bit values for each of the 4 states), and the K bit is 6 bits (excluding the offset bit number from the output bit number) The number of bits (8 bits-2 bits)). When the offset bit length is n bits, a converted luminance level having a continuous value can be obtained only by bit combination processing when the bit length of the J bit string is 2n-1. The R bit has a 4-bit length because any bit is expressed as “1” in the four states. In FIG. 9, “x” indicates a value of “0” or “1”, and two * marks indicate that at least one of them is “1”.

  If “1” exists in any of the A bits (symbol 9a in FIG. 9), the SEL select signal in FIG. 4 becomes valid, and the converted luminance level Yb is “11111111” (all “1”) through the selector circuit 304. ) When all the A bit strings are “0”, the A bit is not detected, so the SEL selector signal becomes invalid, and the selector circuit 304 selects the Ya bit string output from the bit concatenation unit 302 as the conversion luminance level Yb.

The R bit generation circuit 402 sets the R bit string to “1000” when X1 [29] = “1”. The decoding circuit 403 decodes “11” as the offset and “23” as the shift amount from the input value of “1000” (see FIG. 8C). The luminance value X1 is shifted rightward by the obtained shift amount, and the lower 6 bits of the shifted luminance value and the 2 bits of the offset bit are concatenated at the bit concatenation unit to generate the converted luminance level Ya (however, The offset bit is the upper bit). When the A bit string is invalid, the converted luminance level Ya is output from the selector circuit 304 as the converted luminance level Yb that is an output control value. Since the other J bit states are processed in the same manner, the details are omitted.
Here, in the J bit string, detection is performed from the most significant bit, and an offset value having a larger value is assigned as the position where “1” is detected first is located in the upper bit of the bit string.
This offset value indicates the position of the bit where “1” appears in the R bit string.
For example, when the offset bits are 3 bits, offset values from 0 to 7 can be expressed.
In the input bit string (8-bit bit string from 0 bit to 7 bits (most significant bit)), if the third bit is “1”, 3 (“011” in binary number) is the offset bit.

  FIG. 10 is a characteristic graph of the nonlinear conversion characteristic (FIG. 10 (a)) and γ characteristic (γ = 5) (FIG. 10 (b)) in the above conversion processing example, and shows a case where the A bit is not detected. ing. As shown in FIG. 10, in the conversion characteristics between the input luminance value X1 and the converted luminance level Yb, the ratio of the change amount of the converted luminance level Yb to the change amount of the input luminance value X1 is larger in the region where the input luminance value X1 is smaller. It has a non-linear characteristic. As described above, according to the present embodiment, when the control value of the luminance panel is directly obtained, the non-linear conversion process can be performed only by the bit operation, and a high-speed calculation process can be realized with a small circuit. I can do it.

  As can be seen from FIG. 10, in the conversion processing example in which the J bit is 3 bits, the γ characteristic (γ = 5) and the output characteristic are greatly different. As in this embodiment, for example, when determining the control value of the brightness value panel directly from the brightness value, when the control value of the brightness value panel is determined by performing a conversion process using a γ characteristic having a γ value of 4 or more, It has been found that it is possible to display an image with a good balance of gradation between the dark side and the bright side. Therefore, when the nonlinear conversion characteristic is brought close to the γ characteristic, the modulation element can be controlled with high accuracy without performing additional correction or the like by the conversion luminance level Yb obtained by the present embodiment. become able to.

  FIG. 11 shows an example of non-linear conversion when the length of the J bit string is increased to 7 bits. The processing is an example in which a 32-bit luminance value is nonlinearly converted to an 8-bit converted luminance level as before. Since the J bit string is 7 bits, the R bit length is 8 bits and the offset value is 3 bits. The length of the K bit string is 5 bits. The flow of processing is the same as before. If the A bit is detected, “11111111” becomes the converted luminance level. If the A bit is not detected, the R bit is uniquely determined from the J bit and the R bit is “1”. The offset is uniquely determined according to the position of. Also, the shift amount is uniquely determined from the R bit, and the Ya bit string is obtained by concatenating the lower 5 bits obtained by shifting the luminance value X1 by this obtained offset value and the obtained offset bit as the upper bits, and the converted luminance level Yb Will be required.

  FIG. 12 shows non-linear conversion characteristics when the length of the J bit string described with reference to FIG. 11 is 7 bits. In this conversion process, all values above a certain luminance value are converted to the maximum value of the converted luminance level Yb. When the input luminance value X1 is equal to or higher than the highest luminance value that can be displayed by the display body, the highest luminance value of the display body is assigned.

  FIG. 13 is a characteristic graph of a nonlinear conversion characteristic and a γ characteristic (γ = 5) when the A bit related to the conversion characteristic of FIG. 12 is not detected. Compared with FIG. 10, it can be seen that if the J bit is 7 bits, the non-linear transformation characteristic approaches the γ characteristic.

  However, it is considered that there is still room for improvement in the dark side gradation characteristics. However, simply trying to increase J bits increases the number of offset bits from 3 bits to 4 bits. In this case, the number of J bit strings increases from 7 bits to 15 bits, and the number of K bits decreases from 5 bits to 4 bits. That is, there is a possibility that the range of each segmented area by the J bit string is slightly too wide.

  Therefore, in the next embodiment, a non-linear transformation method is adopted in which the number of state divisions between the dark part and the bright part in the characteristic diagram of FIG. 13 that has a relatively large deviation from the characteristic of γ = 5 is increased. did. This conversion method is shown in FIG. In this method, the number of A bit strings is 2 bits and the number of J bit strings is 9 bits. However, the number of offset bits is not fixed to 4 bits. Based on the 3-bit length, we decided to use a variable length with a 4-bit length. In the example of FIG. 14, the number of offset bits included in the converted luminance value Ya is 4 bits long for the luminance value X1 in which J [26] or J [27] in the J bit string is “1” for the first time ( Reference numeral 14a) is set such that the number of offset bits is 3 bits long for other values.

  A bit determination and J bit determination are the same as in the above embodiment. The R bit string obtained from the J bit is also obtained by the same process. Up to now, offset bits have been obtained based on R bits, but in this conversion process, offset bits are not obtained as independent bit strings from R bit strings, but a new P bit string and shift amount (S) are first calculated from R bit strings. Asking for. The P bit string is a bit string having the same number of bits (8 bits) as the number of bits of the converted luminance level Ya to be output, and the upper 8 bits of the luminance value X1 shifted according to the shift amount (S) obtained according to the R bits and P The converted luminance level Ya is set to a value that can be directly obtained by taking an exclusive OR with the bit string of 8 bits. In this process, only the offset bit string in the state (partition area) in which the gradation is to be increased is increased, and the number of K bit strings is decreased by the increase of the offset bits. That is, since the number of bits of the K bit string changes depending on the state, if the converted luminance level Ya is obtained by the bit concatenation (combination) process, the bit concatenation process becomes complicated. Therefore, the converted luminance value Ya can be obtained not by bit concatenation processing but by exclusive OR operation of the higher 8 bits of the shifted luminance value X1 and the P bit string. In this case, in the P bit string, the bit corresponding to the K bit string in the converted luminance value Ya is zero (the part in the broken line 14b). Further, the value of the upper 4 bits or 3 bits of the P bit string is obtained by calculating the exclusive OR of the upper 4 bits or 3 bits of the shifted luminance value X1 and the P bit string, and the converted luminance value Ya of FIG. It is set in advance to be a constant that matches the value of the upper 4 bits or 3 bits.

  When this conversion process is performed, the conversion characteristics are as shown in FIG. 15, and it can be seen that the dark side characteristics are closer to the γ characteristics.

  FIG. 16 is a block diagram of a non-linear luminance level calculation unit 203A (corresponding to the non-linear luminance level calculation unit 203 in FIG. 3) for realizing the conversion method described with reference to FIG. The bit detection unit 601 sends a P bit string to the bit calculation unit 602. The bit operation unit 602 is a circuit composed of an exclusive OR circuit. An exclusive OR operation is performed for each bit on the P bit string and the bit string of the upper predetermined bits (the same number of bits as the P bit string) of the shifted luminance value X1, and the converted luminance value Ya is obtained. The obtained Ya bit string is sent to the selector circuit 304. Based on the select signal (SEL) output from the bit detector 601, all “1” 8 bits or the converted luminance value Ya are selected and output from the selector circuit 304 as the converted luminance value Yb. The shift circuit 303 and the selector circuit 304 have the same configurations as those given the same reference numerals described with reference to FIG.

  FIG. 17 is a block diagram of the bit detection unit 601 in FIG. The SEL signal generation unit 401, the R bit generation unit 402, and the decode circuit 701 are included. In the decoding circuit 701, the P bit string and the shift amount (S) are generated in the same manner as in the above embodiment.

  As described above, according to each embodiment of the present invention, for example, when the control value of the luminance panel is directly obtained, the nonlinear conversion process can be performed only by bit operation, and a high-speed calculation can be performed with a small circuit. Processing can be realized.

  The embodiment of the present invention is not limited to the above, for example, integrating each block, dividing the configuration in each block into a plurality of blocks, changing the number of bits of each bit string, It is possible to replace the circuit configuration of each logic with another equivalent logic circuit. In addition, a part of the configuration of the present invention can be replaced by a computer and software, and in that case, the software can be distributed via a predetermined recording medium or a communication line.

The block diagram of the projection type display apparatus which concerns on this Embodiment. 1 is a circuit configuration diagram of an image processing apparatus 102 and its peripheral circuits according to the present embodiment. FIG. 3 is a block diagram of the image processing apparatus 102 in FIG. FIG. 4 is a block diagram of the non-linear luminance level calculation unit 203 in FIG. FIG. 5 is a block diagram of the bit detection unit 301 in FIG. FIG. 6 is a block diagram of a select signal generation unit 401 in FIG. FIG. 6 is a block diagram of an R bit generation unit 402 in FIG. FIG. 3 is a diagram for explaining an example of bit detection for a luminance value X1 in the image processing apparatus 102 of FIG. FIG. 3 is an explanatory diagram illustrating an example of conversion processing by the image processing apparatus 102 in FIG. 10 is a graph of nonlinear conversion characteristics according to the conversion processing example of FIG. FIG. 10 is a diagram for explaining an example of non-linear conversion when the length of a J bit string is increased to 7 bits with respect to the conversion process of FIG. FIG. 12 is a graph of nonlinear conversion characteristics by the conversion process of FIG. 13 is a characteristic graph showing a comparison between the conversion characteristic of FIG. 12 and the γ characteristic (γ = 5). The figure explaining the system of the nonlinear transformation which is other embodiment of this invention and increased the number of state divisions of the middle part of a dark part and a bright part. FIG. 15 is a graph of nonlinear conversion characteristics according to the conversion processing example of FIG. FIG. 15 is a block diagram of a non-linear luminance level calculation unit 203A for realizing the conversion method of FIG. FIG. 17 is a block diagram of the bit detection unit 601 in FIG.

Explanation of symbols

1 Projection display device, 10 light sources, 31, 32, 33 Liquid crystal light valve (color panel; liquid crystal modulation element), 50 Luminance modulation light valve (luminance panel; liquid crystal modulation element), 102 Image processing device, 201 Integer processing unit , 202 Luminance value calculation unit, 203, 203A Non-linear luminance level calculation unit, 204 Color value calculation unit, 301, 601 bit detection unit, 302 bit concatenation unit, 303 Shift circuit, 602 bit calculation unit

Claims (10)

An image processing device for a display device that forms a display image by modulating light from a predetermined light source by a modulation element,
A processing means for obtaining a control value of the modulation element;
The processing means obtains an offset value and a shift amount according to the state of a predetermined upper bit of the integer type input control value, and a plurality of bits obtained by shifting the input control value by the shift amount and an offset bit representing the offset value An image processing apparatus characterized in that an output control value is obtained by combining. An image processing device for a display device that forms a display image by modulating light from a predetermined light source by a modulation element,
A processing means for obtaining a control value of the modulation element;
The processing means obtains a predetermined set value and a shift amount corresponding to the offset value according to a state of a predetermined upper bit of the integer type input control value, and a plurality of bits obtained by shifting the input control value by the shift amount An image processing apparatus characterized in that an output control value is obtained by a logical operation in units of bits between a set value and a set value. Image processing for generating signals for driving a plurality of light modulation elements from pixel values in a display device that forms a display image by modulating a plurality of light modulation elements optically arranged in series with light from a predetermined light source A device,
An integer processing unit for converting pixel values into integers;
A luminance value calculation unit for calculating a luminance value from an integer pixel value;
A non-linear luminance level calculation unit that non-linearly converts the luminance value and obtains a control value of the light modulation element forming the luminance panel;
A color value calculation unit that calculates a control value of a light modulation element forming a color panel from a pixel value and a luminance panel control value;
The non-linear luminance level calculation unit
Depending on the remaining bits (J bits) of the input luminance value excluding several upper bits (A bits) of the predetermined upper bits (T bits), the first bit from the upper bits of J bits is “1” or “ Bit detection means for determining the position where 0 ″ appears;
Shift means for shifting the input luminance value by a predetermined shift amount based on the detection result of the bit detection means;
An image processing apparatus comprising: a bit combination means for obtaining a control value by combining a shifted bit string and an offset bit generated based on a detection result of the bit detection means.   4. The image processing apparatus according to claim 3, wherein when the number of offset bits is n, the number of J bits is 2n-1.   The image processing apparatus according to claim 4, wherein the number of bits of the J bits is 7 bits, and the number of bits of the output control value is 8 bits.   The image processing apparatus according to claim 3, wherein the shift unit is a barrel shift circuit. Image processing for generating signals for driving a plurality of light modulation elements from pixel values in a display device that forms a display image by modulating a plurality of light modulation elements optically arranged in series with light from a predetermined light source A device,
An integer processing unit for converting pixel values into integers;
A luminance value calculation unit for calculating a luminance value from an integer pixel value;
A non-linear luminance level calculation unit that non-linearly converts the luminance value and obtains a control value of the light modulation element forming the luminance panel;
A color value calculation unit that calculates a control value of a light modulation element forming a color panel from a pixel value and a luminance panel control value;
The non-linear luminance level calculation unit
Depending on the remaining bits (J bits) of the input luminance value excluding several upper bits (A bits) of the predetermined upper bits (T bits), the first bit from the upper bits of J bits is “1” or “ Bit detection means for determining the position where 0 ″ appears;
Shift means for shifting the input luminance value by a predetermined shift amount based on the detection result of the bit detection means;
Bit operation means for obtaining a control value by performing a logical operation in bit units between the shifted bit string and a predetermined set value obtained based on the detection result of the bit detection means. Image processing device.   The image processing apparatus according to claim 7, wherein the set value includes a value corresponding to an offset value based on the J bits with two or more different bit lengths, and the logical operation is an exclusive OR. An image processing method for a display device for forming a display image by modulating light from a predetermined light source by a modulation element,
During the process for obtaining the control value of the modulation element,
Find the offset value and shift amount according to the state of the predetermined high-order bit of the integer type input control value,
An image processing method comprising: obtaining an output control value by combining a plurality of bits obtained by shifting an input control value by a shift amount and an offset bit representing an offset value. An image processing method for a display device for forming a display image by modulating light from a predetermined light source by a modulation element,
During the process for obtaining the control value of the modulation element,
According to the state of a predetermined high-order bit of the integer type input control value, a predetermined setting value and a shift amount corresponding to the offset value are obtained,
An image processing method characterized in that an output control value is obtained by a logical operation in bit units of a plurality of bits obtained by shifting an input control value by a shift amount and a set value.

Images