JP2006086334A - Pin diode element and transmission/reception changeover switch - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PIN diode element having low capacity and low high-frequency resistance characteristic. <P>SOLUTION: The PIN diode element has a first conductive type semiconductor substrate, a first conductive type intrinsic semiconductor layer formed on the first surface of the semiconductor substrate, a first conductive type second intrinsic semiconductor layer formed on the first conductive type intrinsic semiconductor layer, a second conductive type semiconductor layer selectively formed on the surface layer portion of the second intrinsic semiconductor layer, a first electrode formed on the second conductive type semiconductor layer, and a second electrode formed on the second surface of the semiconductor substrate. The second intrinsic semiconductor layer has a higher impurity concentration than the impurity concentration of the first intrinsic semiconductor layer. The semiconductor substrate is made of silicon, and has a resistivity of about 0.02 Ω-cm. The first intrinsic semiconductor layer has a resistivity of about 4,100 Ω-cm. The second intrinsic semiconductor layer has a resistivity of about 43-420 Ω-cm. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a PIN diode element and a transmission / reception changeover switch incorporating the PIN diode element.

PIN diodes (elements) are frequently used in high-frequency switches (transmission / reception switching switches) in wireless communication systems such as cellular phones (for example, Patent Documents 1 and 2).
Patent Document 1 discloses a two-frequency switch capable of switching between an ON state and an OFF state in two bands as a high-frequency switch used for mobile communication such as a mobile phone.

  Patent Literature 2 discloses a high frequency switch with low insertion loss and high isolation used for switching between transmission and reception systems in a radio communication system such as satellite communication using a microwave or a car phone or a mobile phone. In the switches of Patent Document 1 and Patent Document 2, PIN diodes are used.

JP-A-9-139601 Japanese Patent Laid-Open No. 11-55002

  A PIN diode (element) used as a transmission / reception selector switch of a cellular phone is required to have a low capacitance and a low frequency resistance characteristic. In particular, in recent years, there has been a demand for low resistance with low driving as the mobile phone has low driving. For this reason, PIN diodes are required to improve the high-frequency resistance characteristics in the low drive region without affecting other characteristics.

FIG. 12 is a schematic diagram showing the structure and impurity concentration distribution of a conventional PIN diode element. FIG. 12A is a cross-sectional view of the PIN diode element 80. As shown in FIG. 12A, the PIN diode element 80 is formed on a semiconductor chip 82 based on a semiconductor substrate 81 made of silicon. An n layer (n ⁻ layer) 83 having an impurity concentration of about 1E + 12 cm ⁻³ is formed on the main surface (upper surface) of the semiconductor substrate 81. The n layer 83 is formed by epitaxial growth and is an intrinsic semiconductor layer (I layer). A p layer (p ⁺⁺ layer) 84 is selectively formed on the surface layer portion of the n layer 83. In addition, a guard ring (gettering layer) 85 including an n layer (n ⁺⁺ layer) is formed so as to surround the p layer 84 along the edge of the main surface of the semiconductor chip 82. Although not shown, an insulating film is formed on the main surface of the semiconductor chip 82. Of the insulating film, the insulating film on the p layer 84 is removed, and a p-electrode is formed in the removed portion. An n electrode is formed on the back surface (lower surface) of the semiconductor chip 82. In FIG. 12A, a dotted area indicates a depletion layer 86 generated when a predetermined voltage is applied. FIG. 12B is a graph showing the impurity concentration distribution in each semiconductor layer in the PIN diode element. As can be seen from this graph, the n layer (n ⁻ layer) 83 has a low impurity concentration because it forms an intrinsic semiconductor layer.

  Here, as an example of the dimensions of the semiconductor chip 82, the semiconductor chip has a square shape with a side of 0.24 mm and a thickness of 120 μm. The epitaxial layer is 20 μm thick. The p layer 84 has a depth of 3 μm and a diameter of 140 μm. The depth of the n-layer guard ring 85 is 2 μm.

  In such a PIN diode element, in order to reduce the high-frequency resistance (high-frequency forward resistance: rf), it is conceivable to increase the pn junction area or increase the impurity concentration of the epitaxial layer (n layer 83). However, an increase in pn junction area results in an increase in capacitance. In addition, an increase in the impurity concentration of the epitaxial layer causes a decrease in the width of the depletion layer and an increase in capacity. On the other hand, the capacitance and the high-frequency forward resistance rf are in a trade-off relationship, and it is difficult to improve both in a good state.

  Therefore, the inventor of the present invention has two epitaxial layers, one layer is a high-concentration epitaxial layer that reduces high-frequency resistance, and the other layer is a low-concentration epitaxial layer that reduces high-frequency capacitance characteristics. Accordingly, the present invention has been made possible by providing a PIN diode element having low capacitance and low frequency resistance characteristics.

An object of the present invention is to provide a PIN diode element having a low capacity and a low frequency resistance characteristic.
Another object of the present invention is to provide a transmission / reception selector switch with good characteristics.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

The following is a brief description of an outline of typical inventions disclosed in the present application.
(1) A PIN diode element includes a first conductivity type semiconductor substrate, a first conductivity type first intrinsic semiconductor layer formed on a first surface of the semiconductor substrate, and the first intrinsic semiconductor layer. A first conductive type second intrinsic semiconductor layer formed on the second intrinsic semiconductor layer, a second conductive type semiconductor layer selectively formed on a surface layer of the second intrinsic semiconductor layer, and the second conductive type semiconductor A first electrode formed on the layer and a second electrode formed on a second surface of the semiconductor substrate, wherein the impurity concentration of the second intrinsic semiconductor layer is the first intrinsic semiconductor. The impurity concentration is higher than the impurity concentration of the layer, the second intrinsic semiconductor layer is a zero bias state and the depletion layer is spread over a predetermined region, and the first intrinsic semiconductor layer is a layer without the depletion layer being spread in the zero bias state It is characterized by.

  The semiconductor substrate is made of silicon, the resistivity is about 0.02 Ω-cm, the resistivity of the first intrinsic semiconductor layer is about 4100 Ω-cm, and the resistivity of the second intrinsic semiconductor layer is It is about 43 to 420 Ω-cm.

  Such a PIN diode element is used for a transmission / reception selector switch. The transmission / reception selector switch is connected in series between an antenna connected in parallel to a signal transmission line between a transmission terminal and a reception terminal, and a connection part between the transmission terminal and the signal transmission line of the antenna. Are connected to the first PIN diode in parallel and in a reverse-biased state, at a position that is a quarter of the transmission wavelength away from the connecting portion toward the receiving terminal. A transmission / reception changeover switch having a second PIN diode, wherein the first and second PIN diodes are constituted by the PIN diode element.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the means (1), the intrinsic semiconductor layer of the PIN diode element is formed of the first intrinsic semiconductor layer and the second intrinsic semiconductor layer. Since the impurity concentration of the second intrinsic semiconductor layer is higher than the impurity concentration of the first intrinsic semiconductor layer and becomes a high-concentration epitaxial layer that lowers the high-frequency resistance, it has low-frequency resistance characteristics. In addition, since the first intrinsic semiconductor layer is a low-concentration epitaxial layer having a low impurity concentration, it is possible to reduce the high-frequency capacitance characteristics. Thereby, it is possible to provide a PIN diode element having low capacitance and low high frequency resistance characteristics.

  A transmission / reception changeover switch incorporating such a low-capacitance / low-frequency resistance PIN diode element has improved characteristics (isolation / insertion loss).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.

  1 to 10 are diagrams relating to a PIN diode (element) which is Embodiment 1 of the present invention. The PIN diode (PIN diode element) 1 of the first embodiment is formed on a semiconductor chip 3 formed on the basis of a semiconductor substrate 2 made of silicon, as shown in FIG. The semiconductor chip 3 is, for example, a square having a side of 0.24 mm and a thickness of 120 μm.

The semiconductor substrate 2 is made of an n-type silicon (Si) substrate. The semiconductor substrate 2 contains a large amount of As as an impurity and becomes an n ⁺⁺ type, and has a resistivity of about 0.02 Ω-cm, for example. A first intrinsic semiconductor layer 4 is formed on the first surface (main surface: upper surface in FIG. 1) of the semiconductor substrate 2 by epitaxial growth. The first intrinsic semiconductor layer 4 is, for example, an I layer (n ⁻⁻ type) having a thickness of a (= 20 μm) with phosphorus as an impurity, an impurity concentration of about 1E + 12 cm ⁻³ (FIG. 3 ( a)).

A second intrinsic semiconductor layer 5 is formed on the upper surface of the first intrinsic semiconductor layer 4 by epitaxial growth. The second intrinsic semiconductor layer 5 is, for example, an I layer (n ⁻ type) having phosphorus as an impurity, an impurity concentration of about 1E + 13 to 14 cm ⁻³ and a thickness of ³ to 10 μm. The total thickness of the first intrinsic semiconductor layer 4 and the second intrinsic semiconductor layer 5 is the same as the thickness of the n layer 83 made of the intrinsic semiconductor layer (I layer) shown in FIG. That is, in Example 1, the n layer 83 made of the intrinsic semiconductor layer (I layer) in FIG. 12 is made into two layers, the lower layer is made the first intrinsic semiconductor layer 4, and the upper layer is made the second intrinsic semiconductor layer 5. This is one of the characteristics.

A p layer (p ⁺⁺ layer) 6 is selectively formed on the surface layer portion of the second intrinsic semiconductor layer 5. Further, a guard ring (gettering layer) 7 composed of an n layer (n ⁺⁺ layer) is formed so as to surround the p layer 6 along the edge of the main surface of the semiconductor chip 3. An insulating film 8 is formed on the main surface of the semiconductor chip 3. Of the insulating film 8, the insulating film on the p layer 6 is removed, and a p-electrode 9 is formed in the removed portion. An n electrode 10 is formed on the back surface (lower surface) of the semiconductor chip 3. For example, the p-electrode 9 is made of aluminum (Al) containing Si and has a thickness of 1.5 μm. The n-electrode 10 is formed of an Au layer having a thickness of 1.2 μm.

  In the PIN diode element 1 according to the first embodiment, the depletion layer 11 is generated in the second intrinsic semiconductor layer 5 due to the internal potential (zero bias state), but the depletion layer is widened in the first intrinsic semiconductor layer 4. Absent.

The p layer (p ⁺⁺ layer) 6 has a depth of 3 μm and a diameter of 140 μm. The depth of the n-layer guard ring 7 is 2 μm. FIG. 3B is a graph showing the impurity concentration distribution of each semiconductor layer.

Such a PIN diode element 1 is manufactured as shown in FIGS. As shown in FIG. 2A, for example, a semiconductor substrate 2 made of n-type (n ⁺⁺ type) silicon (Si) having a resistivity of about 0.02 Ω-cm is prepared. The impurity of the semiconductor substrate 2 is, for example, As. At this stage, the semiconductor substrate 2 has a thickness of, for example, 550 μm.

Next, as shown in FIG. 2A, the first intrinsic semiconductor layer 4 and the second intrinsic semiconductor layer 5 are formed on the first surface (main surface: the upper surface in FIG. 1) of the semiconductor substrate 2 by ordinary epitaxial growth. Are sequentially formed. The first intrinsic semiconductor layer 4 has a thickness of 20 μm, for example. Further, phosphorus is added as an impurity to the first intrinsic semiconductor layer 4 to be n-type, but the impurity concentration is about 1E + 12 cm ⁻³ in order to form the intrinsic semiconductor layer (I layer). Therefore, the first intrinsic semiconductor layer 4 is n ⁻⁻ type.

The second intrinsic semiconductor layer 5 formed on the upper surface of the first intrinsic semiconductor layer 4 has a thickness of 3 to 10 μm, for example. Further, phosphorus is added as an impurity to the second intrinsic semiconductor layer 5 to be n-type, but the impurity concentration is about 1E + 13 to 14 cm ⁻³ in order to form the intrinsic semiconductor layer (I layer). Therefore, the first intrinsic semiconductor layer 4 is n ⁻ type. The total thickness of the first intrinsic semiconductor layer 4 and the second intrinsic semiconductor layer 5 is the same as the thickness of the n layer 83 made of the intrinsic semiconductor layer (I layer) shown in FIG.

  In the formation of the second intrinsic semiconductor layer 5, the second intrinsic semiconductor layer 5 may be formed by depositing an n-type dopant on the upper surface of the first intrinsic semiconductor layer 4 by implantation. In this case, the impurity concentration and depth (thickness) can be freely set as compared with the epitaxial growth. At this time, the second intrinsic semiconductor layer 5 has a thickness that is approximately the same as the depletion layer width that is spread by the internal potential.

Next, as shown in FIG. 2B, a p layer (p ⁺⁺ layer) 6 is partially formed on the surface layer portion of the second intrinsic semiconductor layer 5 by conventional photolithography technology, etching technology, and impurity diffusion technology. To do. That is, the thermal oxide film 16 is formed over the entire upper surface of the second intrinsic semiconductor layer 5. Thereafter, a photoresist film is selectively formed on the thermal oxide film 16 (not shown). Next, the thermal oxide film 16 is etched using the photoresist film as an etching mask to selectively expose the surface of the second intrinsic semiconductor layer 5. Next, after removing the photoresist film, impurities are deposited (or implanted) on the surface of the second intrinsic semiconductor layer 5 using the thermal oxide film 16 as a mask, and thermally diffused to form a p layer (p ⁺⁺ layer) 6. To do. For example, boron (B) is implanted as an impurity. The p layer (p ⁺⁺ layer) 6 is formed with a diameter of about 140 μm and a depth of about 3 μm.

Next, the thermal oxide film 16 is removed. Thereafter, as shown in FIG. 2C, a thermal oxide film 17 is selectively formed on the upper surface of the second intrinsic semiconductor layer 5 by the same method as described above. The thermal oxide film 17 is formed on a predetermined rectangular region centered on the p layer (p ⁺⁺ layer) 6. Then, using this thermal oxide film 17 as a mask, an impurity is implanted into the exposed surface layer portion of the second intrinsic semiconductor layer 5 to form an n-type (n ⁺⁺ type) guard ring (gettering layer) 7. . Arsenic (As) or antimony (Sb) is used as the impurity. The guard ring 7 is formed to a depth of 2 μm, for example.

  Next, the thermal oxide film 17 is removed. Next, as shown in FIG. 2D, a thermal oxide film 18 having a predetermined pattern is formed on the upper surface of the second intrinsic semiconductor layer 5 by a conventional method. The center of the thermal oxide film 18 is opened, and a p-electrode 9 is formed in this opening. The p electrode 9 is made of, for example, aluminum (Al) containing Si and has a thickness of 1.5 μm.

Next, the back surface (lower surface) of the semiconductor substrate 2 is removed by a predetermined thickness so that the total thickness becomes about 120 μm. Thereafter, an Au layer serving as the n electrode 10 is formed on the lower surface of the semiconductor substrate 2 to a thickness of 1.2 μm. Next, the semiconductor substrate 2 is cut vertically and horizontally to manufacture a plurality of PIN diode elements 1 as shown in FIG. In the PIN diode element 1 of the first embodiment, in the manufacturing stage, the second layer is formed by the internal potential (zero bias state) when the p layer (p ⁺⁺ layer) 6 is formed on the surface of the second intrinsic semiconductor layer 5. A depletion layer 11 is formed in the intrinsic semiconductor layer 5. The depletion layer 11 does not extend to the first intrinsic semiconductor layer 4 having a low impurity concentration. The depletion layer 11 is shown in FIGS. 2 (c) and 2 (d).

  In the PIN diode element 1 according to the first embodiment, the intrinsic semiconductor layer is a two-layer epitaxial layer in which the high concentration epitaxial layer (second intrinsic semiconductor layer 5) and the low concentration epitaxial layer (first intrinsic semiconductor layer 4) are formed. It has a structure. Therefore, the high-concentration epitaxial layer (second intrinsic semiconductor layer 5) can reduce the high-frequency resistance, and the low-concentration epitaxial layer (first intrinsic semiconductor layer 4) can reduce the high-frequency capacitance characteristics.

  The high-frequency resistance can be lowered by the high concentration layer (second intrinsic semiconductor layer 5) of the epitaxial layer. 5A to 5C are graphs showing the correlation between the resistivity and the high-frequency resistance due to the difference in the forward current (IF). In the graph of FIG. 5A, IF is 0.3 mA, in the graph of FIG. 5B, IF is 0.8 mA, and in the graph of FIG. 5C, IF is 6.0 mA. As can be seen from these graphs, it can be seen that the higher the resistance, the lower the high frequency resistance.

  However, simply increasing the impurity concentration of the epitaxial layer reduces the width of the depletion layer and increases the capacitance.

  Therefore, in the first embodiment, the concentration of the epitaxial layer that is not depleted is set to a low concentration, thereby suppressing an increase in capacitance (when using a high frequency). FIGS. 7A to 7D are schematic views for explaining the reason for improving the characteristics of the PIN diode element of the first embodiment. FIG. 7A is a schematic diagram showing the spread state of each layer between the p-electrode 9 and the n-electrode 10 and the depletion layer 11. The capacity of the first intrinsic semiconductor layer 4 that is not depleted is high frequency, and the capacity of the second intrinsic semiconductor layer 5 that is depleted is Cj. That is, the non-depleted epitaxial layer (first intrinsic semiconductor layer 4) has the property of changing to dielectric at low frequencies and capacitive at high frequencies. This point will be described with reference to FIG.

FIG. 7B is a schematic diagram showing an equivalent circuit model of the PIN diode. Between the p-electrode 9 and the n-electrode 10, the resistor Rus and the capacitor Cus are connected in parallel in the first intrinsic semiconductor layer 4 portion, and the capacitor Cj in the second intrinsic semiconductor layer 5 portion. The current flowing between the p-electrode 9 and the n-electrode 10 flows through the resistor Rus at low frequencies and flows through the capacitor Cus at high frequencies. FIG. 7C shows the capacitance at low frequency, and the equivalent circuit at this time has a configuration in which a capacitor Cj and a resistor Rus are connected in series between the p electrode 9 and the n electrode 10. FIG. 7D shows the capacitance at high frequency, and the equivalent circuit at this time has a configuration in which a capacitor Cj and a capacitor Cus are connected in series between the p electrode 9 and the n electrode 10.
The total capacity C at high frequency is given by the following equation.

  As can be seen from Equation 1, for this reason, since the high frequency component is connected in series with the capacitive component of the depletion layer, the overall capacitance C is low. Therefore, in the PIN diode element 1 of the first embodiment, the range where the depletion layer spreads with the internal potential is high concentration (low resistance), and the region where the depletion layer does not spread is low concentration (high resistance). In addition, low capacity characteristics can be obtained. In other words, according to the first embodiment, the high-frequency resistance in the low bias region can be improved without deteriorating the capacitance characteristics.

  FIG. 4 is a graph showing high-frequency forward characteristics of the PIN diode element 1 of the first embodiment. From this graph, the PIN diode element 1 is effective as a variable resistor. FIG. 6 is a graph showing the correlation between the capacitance and the frequency due to the difference in resistivity of the PIN diode element 1. That is, it shows the frequency dependence of the capacitance characteristics when the resistivity is 150 Ω · cm, 470 Ω · cm, and 1600 Ω · cm. It can be seen that the total capacitance C decreases as the resistivity decreases.

  FIG. 8 is a schematic diagram for explaining another effect of the PIN diode 1 according to the first embodiment. In the PIN diode element 1, an intrinsic semiconductor layer is formed by a first intrinsic semiconductor layer 4 having a low impurity concentration and a second intrinsic semiconductor layer 5 having an impurity concentration higher than that of the first intrinsic semiconductor layer 4. Therefore, since the impurity concentration on the surface of the PIN diode element 1 is high, it is difficult to reverse. The dotted line frame portion shown in FIG. 8 is a region that is difficult to reverse because the impurity concentration is high.

  The PIN diode element 1 according to the first embodiment is used by being incorporated in various semiconductor devices in a chip state, or provided as a discrete product. FIG. 10 is a cross-sectional view of a PIN diode device incorporating the PIN diode element of the first embodiment.

  As shown in FIG. 10, the PIN diode device 30 has an external appearance of a sealing body 31 made of a flat rectangular insulating resin, and leads 32 and 33 protruding from a pair of side surfaces facing the sealing body 31. It is made up of. The leads 32 and 33 extend over the inside and outside of the sealing body 31, the inner end portion is covered with the sealing body 31, the outer end protrudes from the sealing body 31, and the lower surface is the lower surface of the sealing body 31. It is supposed to match.

  The PIN diode element 1 is connected to the upper surface of the inner end portion of one lead 32 via a conductive adhesive 34. That is, the n-electrode 10 (not shown in FIG. 10) of the PIN diode element 1 is electrically connected to the lead 32 via the adhesive 34. The upper surface of the inner end portion of the other lead 33 and the upper surface of the PIN diode element 1 are electrically connected by a conductive wire 35. Although not shown in FIG. 10, a p-electrode 9 is formed on the upper surface of the PIN diode element 1. The p electrode 9 is electrically connected to the lead 33 by the wire 35. The PIN diode device 30 may have another sealing structure. For example, the PIN diode element 1 is sandwiched between a pair of leads called DHD (Double Heat Sink Diode), and the PIN diode element 1 and the lead portion connected to the PIN diode element 1 are sealed with insulating glass. It may be a structure.

  The PIN diode element 1 according to the first embodiment is used as a part constituting an antenna switch as shown in FIG. 9, for example. This antenna switch is, for example, an antenna switch used for a mobile phone having a frequency of 900 MHz or 1.8 GHz. FIG. 9 is an equivalent circuit diagram of the antenna switch.

  As shown in FIG. 9, the antenna switch (transmission / reception selector switch) 40 includes an antenna 42 connected in parallel to a signal transmission line 41 between the transmission terminal TX and the reception terminal RX, and the transmission terminal TX and the antenna 42 described above. A first PIN diode 1a connected in series between a connection part (node) 43 to the signal transmission line 41, and a position 44 separated from the connection part 43 by a length of 1/4 of the transmission wavelength toward the reception terminal RX. And a second PIN diode 1b connected in parallel and in reverse bias to the PIN diode 1a. A signal transmission line 41a having a length of ¼ of the transmission wavelength is provided between the connection portion 43 and a position 44 that is a length of ¼ of the transmission wavelength. A power supply 45 is disposed between the second PIN diode 1b and the transmission terminal TX. C1 and C2 are capacities.

  A transmission / reception changeover switch incorporating such a low-capacitance / low-frequency resistance PIN diode element has improved characteristics (isolation / insertion loss).

The first embodiment has the following effects.
(1) The intrinsic semiconductor layer of the PIN diode element 1 is formed by the first first intrinsic semiconductor layer 4 and the second intrinsic semiconductor layer 5. Since the impurity concentration of the second intrinsic semiconductor layer 5 is higher than the impurity concentration of the first intrinsic semiconductor layer 4 and becomes a high-concentration epitaxial layer that lowers the high-frequency resistance, it has low-frequency resistance characteristics. . Further, since the first intrinsic semiconductor layer 4 is a low-concentration epitaxial layer having a low impurity concentration, it is possible to reduce the high-frequency capacitance characteristics. Thereby, it is possible to provide a PIN diode element having low capacitance and low high frequency resistance characteristics.

  (2) The characteristics (isolation / insertion loss) of the transmission / reception changeover switch incorporating the PIN diode element having the low capacitance and low high frequency resistance characteristics according to the first embodiment is improved.

11A to 11D are cross-sectional views of each manufacturing process showing the method for manufacturing the PIN diode of the second embodiment. In the PIN diode element 1 of the first embodiment, the semiconductor substrate 2 and the first intrinsic semiconductor layer 4 and the second intrinsic semiconductor layer 5 formed on the main surface of the semiconductor substrate 2 have the same size. The PIN diode element 1 c of the embodiment has a mesa structure in which the first intrinsic semiconductor layer 4 and the second intrinsic semiconductor layer 5 are narrower than the semiconductor substrate 2. A second conductivity type semiconductor layer (p layer (p ⁺⁺ layer) 6) is provided on the entire top surface of the second intrinsic semiconductor layer.

In the manufacture of the PIN diode element 1c, as shown in FIG. 11A, as in the case of the first embodiment, the first intrinsic semiconductor layer 4 and the second intrinsic semiconductor layer 2 are formed on the main surface of the semiconductor substrate 2 by ordinary epitaxial growth. The semiconductor layer 5 is formed sequentially. During this epitaxial growth, as shown in FIG. 11B, a p layer (p ⁺⁺ layer) 6 is formed. By forming the p layer (p ⁺⁺ layer) 6, a depletion layer 11 is generated in the second intrinsic semiconductor layer 5. The depletion layer 11 is a dotted area. When the p layer (p ⁺⁺ layer) 6 is formed, a depletion layer 11 is formed in the second intrinsic semiconductor layer 5 by an internal potential (zero bias state). The depletion layer 11 does not extend to the first intrinsic semiconductor layer 4 having a low impurity concentration.

Next, as shown in FIG. 11C, an insulating film 50 is selectively formed on the upper surface of the p layer (p ⁺⁺ layer) 6. Thereafter, using this insulating film 50 as an etching mask, the p layer (p ⁺⁺ layer) 6, the second intrinsic semiconductor layer 5, and the first intrinsic semiconductor layer 4 are selectively etched to form a mesa 51. Etching is performed up to the surface layer portion of the semiconductor substrate 2.

Next, the insulating film 50 is removed. Next, the main surface side of the semiconductor substrate 2 is covered with an insulating film 52, the insulating film 52 on the mesa 51 is selectively opened, and the p-electrode 9 is formed in the opening. The p electrode 9 overlaps the p layer (p ⁺⁺ layer) 6 and is electrically connected.

  Next, the back surface (lower surface) of the semiconductor substrate 2 is removed to a predetermined thickness. Thereafter, an n-electrode 10 is formed on the lower surface of the semiconductor substrate 2, and the semiconductor substrate 2 is further cut vertically and horizontally to produce a plurality of PIN diode elements 1c as shown in FIG.

Since the PIN diode element 1c of the second embodiment has a mesa structure, the capacitance can be further reduced.
Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.

It is sectional drawing of the PIN diode element which is Example 1 of this invention. It is sectional drawing of each manufacturing process which shows the manufacturing method of the PIN diode element of the present Example 1. 2 is a schematic diagram showing a structure and impurity concentration distribution of a PIN diode element of Example 1. FIG. It is a graph which shows the high frequency forward characteristic of a PIN diode. It is a graph which shows the correlation of the resistivity and high frequency resistance by the difference in a forward current. It is a graph which shows the correlation of the capacity | capacitance by the difference in resistivity, and a frequency. It is a schematic diagram explaining the characteristic improvement reason of the PIN diode element of the present Example 1. It is a schematic diagram which shows the effect in the PIN diode of the present Example 1. It is an equivalent circuit diagram of an antenna switch. It is sectional drawing of the PIN diode apparatus incorporating the PIN diode element of the present Example 1. It is sectional drawing of each manufacturing process which shows the manufacturing method of the PIN diode of the present Example 2. It is a schematic diagram which shows the structure and impurity concentration distribution of the conventional PIN diode element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1a, 1b ... PIN diode (PIN diode element), 2 ... Semiconductor substrate, 3 ... Semiconductor chip, 4 ... 1st intrinsic semiconductor layer, 5 ... 2nd intrinsic semiconductor layer, 6 ... p layer (p ⁺⁺ layer) ), 7 ... Guard ring (gettering layer), 8 ... Insulating film, 9 ... p electrode, 10 ... n electrode, 11 ... depletion layer, 16-18 ... thermal oxide film, 30 ... PIN diode device, 31 ... sealing Body, 32, 33 ... lead, 34 ... adhesive, 35 ... wire, 40 ... antenna switch, 41 ... signal transmission line, 41a ... signal transmission line of 1/4 length of transmission wavelength, 42 ... antenna, 43 ... Connection part 44 ... position separated by a quarter of the transmission wavelength, 45 ... power source, 50 ... insulating film, 51 ... mesa part, 52 ... insulating film, 80 ... PIN diode element, 81 ... semiconductor substrate, 82 ... semiconductor chip, 83 ... n layer (n ^- layer), 4 ... p layer ^{(p ++} layer), 85 ... guard ring (gettering layer), 86 ... the depletion layer.

Claims (5)

A first conductivity type semiconductor substrate;
A first intrinsic semiconductor layer of a first conductivity type formed on a first surface of the semiconductor substrate;
A second intrinsic semiconductor layer of a first conductivity type formed on the first intrinsic semiconductor layer;
A second conductivity type semiconductor layer selectively formed on a surface layer portion of the second intrinsic semiconductor layer;
A first electrode formed on the second conductivity type semiconductor layer;
A second electrode formed on the second surface of the semiconductor substrate;
The impurity concentration of the second intrinsic semiconductor layer is higher than the impurity concentration of the first intrinsic semiconductor layer,
The second intrinsic semiconductor layer has a depletion layer spread over a predetermined region in a zero bias state;
The PIN diode element, wherein the first intrinsic semiconductor layer is a layer in which a depletion layer does not expand in a zero bias state.   The first and second intrinsic semiconductor layers formed on the first surface side of the semiconductor substrate have a mesa structure that is narrower than the semiconductor substrate, and the second intrinsic semiconductor layer has the second surface over the entire upper surface of the second intrinsic semiconductor layer. The PIN diode element according to claim 1, wherein a conductive semiconductor layer is provided. The first intrinsic semiconductor layer is n-type, and the impurity concentration is about 1E + 12 cm ⁻³ ,
2. The PIN diode element according to claim 1, wherein the second intrinsic semiconductor layer is n-type and has an impurity concentration of about 1E + 13 to 14 cm ⁻³ . The semiconductor substrate is made of silicon, and its resistivity is about 0.02 Ω-cm,
The resistivity of the first intrinsic semiconductor layer is about 4100 Ω-cm,
2. The PIN diode element according to claim 1, wherein the resistivity of the second intrinsic semiconductor layer is about 43 to 420 [Omega] -cm. An antenna connected in parallel to the signal transmission line between the transmission terminal and the reception terminal;
A first PIN diode connected in series between the connection between the transmission terminal and the signal transmission line of the antenna;
A second PIN diode connected at a position that is a quarter of the transmission wavelength away from the connection portion toward the receiving terminal, and connected in parallel and in a reverse bias state to the first PIN diode. A transmission / reception selector switch having
The transmission / reception change-over switch, wherein the first and second PIN diodes are constituted by the PIN diode element according to claim 1.

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