JP2006080964A - Communication method and apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the number of levels which can be stored in one chip without decreasing a hopping speed. <P>SOLUTION: A transmission unit 10 converts the level assigned to each of chips forming a communication frame conforming to FH-MMFSK into waveform data having an in-chip position, a time width and frequency which correspond to this level, and transmits the data. On the contrary, a receiver unit 20 receives the communication frame, and specifies the level assigned to this chip on the basis of the in-chip position, the time width, and the frequency which are stored in each of the chips forming the received communication frame. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention, FH-MMFSK about - - (M-ary Multilevel Multitone FSK Frequency Hopping) communication technology using (Frequency Hopping M-ary Multilevel FSK ) or ^FH-M 3 FSK.

FH-MMFSK and FH-M ³ FSK have been proposed as radio communication technologies using frequency hopping (FH: Frequency Hopping) (Patent Document 1, Non-Patent Document 1).

JP 2000-91957 A Akihiko OSHINOMI, Gen MARUBAYASHI, Shinich TACHIKAWA, and Masanori HAMAMURA, "Trial Model of The M-ray Multilavel FSK Power-line Transmission Modem", ISPL2003, Proceedings of the 7th International Symposium on Power-Line Communications and ITc Applications, March 26- 28, 2003, Kyoto, Japan

By the way, in FH-MMFSK and FH-M ³ FSK, the number of tones (frequency spectrum representing a level) stored in each chip constituting a communication frame and the time width of the chip are in a trade-off relationship.

FIG. 7A is a diagram schematically showing communication frames of conventional FH-MMFSK and FH-M ³ FSK. FIG. 7B is a diagram schematically showing tones that can be stored in each chip constituting the communication frame of the conventional FH-MMFSK and FH-M ³ FSK. As illustrated, the communication frame includes an AGC preamble 1091, a synchronization signal 1092, and chips 1093 for at least one hopping. Each chip 1093 stores a tone 1094.

  When the chip width of the chip 1093 (time width of one chip) is Tc, the tone 1094 is cut out by a rectangular pulse having the width Tc, so the main lobe width (frequency band) of the frequency spectrum is 2 / Tc. Further, in order to avoid interference between adjacent tones 1094, adjacent tones 1094 need to be orthogonal to each other. Therefore, the frequency interval (center frequency interval) between adjacent tones 1094 is 1 / Tc. For this reason, if the number of tones, that is, the number of levels that can be stored in the chip 1093 in the determined frequency band is increased, the chip width Tc is increased and the hopping speed (the number of hops that can be transmitted per unit time) is decreased. On the other hand, when the hopping speed is increased, the chip width Tc is shortened, and the number of tones, that is, the number of levels that can be stored in the chip 1093 in the determined frequency band is decreased.

The present invention has been made in view of the above circumstances, and the object of the present invention is the number of levels that can be stored in one chip without reducing the hopping speed in communication using FH-MMFSK and FH-M ³ FSK. It is to provide a technology that can increase

  In order to solve the above problems, in the present invention, the waveform data stored in the chip has a frequency spectrum and time information (the position and time width of the waveform data in the chip), thereby expressing the level assigned to the chip. is doing.

For example, the present invention is, FH-MMFSK a - - (M-ary Multilevel Multitone FSK Frequency Hopping) communication method using, (Frequency Hopping M-ary Multilevel FSK) or ^FH-M 3 FSK
The transmission side device converts the level assigned to each chip constituting the communication frame according to FH-MMFSK or FH-M ³ FSK into waveform data having a position in the chip, a time width and a frequency according to the level. Then send
The receiving side device receives the communication frame, and determines the level assigned to the chip based on the position, time width and frequency of the waveform data stored in each chip constituting the received communication frame. Identify.

  According to the present invention, the above configuration can increase the number of levels that can be stored in one chip without reducing the hopping speed.

  Hereinafter, embodiments of the present invention will be described.

  FIG. 1 is a schematic diagram of an FH-MMFSK modem apparatus to which an embodiment of the present invention is applied. As shown in the figure, the FH-MMFSK modem apparatus of this embodiment includes a transmission unit 10 that converts transmission data into an FH-MMFSK signal and transmits it, and a reception unit that receives an FH-MMFSK signal and converts it into reception data. 20 and.

The transmission unit 10 includes an S / P (Serial / Parallel) conversion unit 101, a level conversion unit 102, a pattern selection unit 103, a hopping pattern storage unit 104, an addition unit 105, a remainder calculation unit 106, a level- Frequency / time calculation unit 107, a plurality of IFFT (Inverse Fast Fourier Transform) units 108 _{1 to} 108 _m having different analysis time lengths, synchronization signal addition unit 109, DA (Digital Analog) conversion unit 110, and AFE ( Analog Front End) part 111.

Serial data K bits inputted to the transmitting unit 10 (transmitting data) is converted into parallel data by the S / P conversion unit 101, the upper (or lower) K ₁ bit is input to the level conversion unit 102, the remaining K ₂ bits are input to the pattern selection unit 103.

The level conversion unit 102 converts the K _1- bit parallel data input from the S / P conversion unit 101 into a level corresponding to the value indicated by the parallel data. Then, a level pattern in which the converted level is continuously configured for the number of chips constituting one hopping (chip width is Tc) is output to the adding unit 105.

FIG. 2A is a diagram schematically showing the level pattern 1021 output from the level conversion unit 102. In this example, the number of chips for one hopping = 5, the number of bits of K ₁ bit = 5, and the parallel data of K ₁ bit is “01100”. When the number of levels is 32, the number of possible bits is 5.

The pattern selection unit 103 reads the hopping pattern associated with the value indicated by the K _2- bit parallel data input from the S / P conversion unit 101 from the hopping pattern storage unit 104 and outputs the hopping pattern to the addition unit 105. Here, the hopping pattern storing unit 104, the hopping pattern is stored for each possible value is K ₂ bits of para data. Note that the number of chips and the number of levels of the hopping pattern are the same as the number of chips and the level of the level pattern output from the level converter 102.

FIG. 2B is a diagram schematically showing a hopping pattern 1041 stored in the hopping pattern storage unit 104. The hopping pattern associated with each value that can be taken by the K _2- bit parameter is a combination that can be used as a hopping pattern among the patterns that can be taken as a matrix of the number of chips × the number of levels (there is a variation that can be distinguished from other hopping patterns A combination).

  Adder 105 adds the level of the level pattern input from level converter 102 and the level of the hopping pattern output from pattern selector 103 for each chip. Then, the addition result is output to the remainder calculation unit 106. The remainder calculation unit 106 calculates a remainder of the level number of the level pattern and the hopping pattern with respect to the addition result of each chip input from the addition unit 105. That is, when the addition result is x and the number of levels of the level pattern and the hopping pattern is n, x (mod n) is calculated. Then, the calculation result is output to the level-frequency / time conversion unit 107. However, when the calculation result is 0, the level number n is output as the calculation result.

  The level-frequency / time conversion unit 107 uses the pre-registered level-frequency / time conversion table to convert the calculation result of each chip input from the remainder calculation unit 106 into a frequency spectrum and time information (in-chip position and Time width) and output to the IFFT unit 108 having the same analysis time length as the time width included in the time information.

  FIG. 3 is a diagram schematically showing a level-frequency / time conversion table registered in the level-frequency / time conversion unit 107, where the number of levels as a calculation result of the remainder calculation unit 106 is 32. Is assumed. In the present embodiment, a level-frequency / time conversion table is prepared for each IFFT unit 108, that is, for each analysis time length.

  FIG. 3A shows a level-frequency / time conversion table 1071A provided for the IFFT unit 108 having an analysis time length equal to the chip width Tc. The calculation result of the remainder calculation unit 106 is shown in FIG. Of the possible levels 1 to 32, levels 1 to 8 are assigned. For example, the level 3 output from the remainder calculation unit 106 includes the frequency spectrum corresponding to the number “3” and the waveform data corresponding to the frequency spectrum between the top of the chip (in-chip position) and Tc (time width). It is converted into a combination with time information indicating that it is output, and this combination of frequency spectrum and time information is output to IFFT section 108 corresponding to level-frequency / time conversion table 1071A.

  FIG. 3B shows a level-frequency / time conversion table 1071B provided for the IFFT unit 108 having a time width Tc / 2 whose analysis time length is half of the chip width Tc. Of the levels 1 to 32 that can be taken by the calculation results, levels 9 to 16 are assigned. For example, the level 14 output from the remainder calculation unit 106 is the frequency spectrum corresponding to the numbers “3” to “4” and the Tc / 2 (time) from the position after Tc / 2 from the top of the chip (in-chip position). IFFT section corresponding to the level-frequency / time conversion table 1071B, which is converted into a combination with time information indicating that waveform data corresponding to the frequency spectrum is output. It is output to 108.

  FIG. 3C shows a level-frequency / time conversion table 1071C provided for the IFFT unit 108 whose analysis time length is a time width Tc / 4 that is a quarter of the chip width Tc. Of the levels 1 to 32 that can be taken by the calculation result of the arithmetic unit 106, levels 17 to 24 are assigned. For example, the level 24 output from the remainder calculation unit 106 is the frequency spectrum corresponding to the numbers “5” to “8” and the Tc / 4 (time) from the position after 3 Tc / 4 from the top of the chip (in-chip position). IFFT section corresponding to the level-frequency / time conversion table 1071C. The combination of the frequency spectrum and the time information is converted into a combination with time information indicating that waveform data corresponding to the frequency spectrum is output. It is output to 108.

  FIG. 3D shows a level-frequency / time conversion table 1071D provided for the IFFT unit 108 having an analysis time length having a time width Tc / 8 that is one-eighth of the chip width Tc. Of levels 1 to 32 that can be taken by the calculation result of the arithmetic unit 106, levels 25 to 32 are assigned. For example, the level 30 output from the remainder calculation unit 106 is the frequency spectrum corresponding to the numbers “1” to “8” and the Tc / 8 (time) from the position after 5 Tc / 8 from the top of the chip (in-chip position). IFFT section corresponding to the level-frequency / time conversion table 1071D. The combination of the frequency spectrum and the time information is converted into a combination with time information indicating that waveform data corresponding to the frequency spectrum is output. It is output to 108.

  FIG. 4 is a diagram schematically showing a transmission spectrum 1072 with time information for one hopping (for the number of chips in the level pattern and the hopping pattern) output from the level-frequency / time conversion unit 107. In this example, the level pattern and hopping pattern input to the adding unit 105 are the patterns shown in FIGS. 2A and 2B, and the level-frequency When the time conversion table is the table shown in FIG. 3, the transmission spectrum with time information output from the level-frequency / time conversion unit 107 is shown. As shown in the figure, each chip stores a combination of a frequency spectrum and time information having an in-chip position and a time width.

Each of the IFFT units 108 _{1 to} 108 _m is a chip included in the time information stored in the chip with respect to the frequency spectrum stored in the chip input from the level-frequency / time conversion unit 107. The IFFT process is started from the inner position. As a result, the waveform data starts from the position in the chip specified by the time information stored in the chip, and the time width specified by the time information (that is, the analysis time length set in the own IFFT unit). And waveform data having a frequency spectrum stored in the chip is generated. This waveform data is output to the synchronization signal adding unit 109.

Next, the synchronization signal adding unit 109 adds the AGC preamble and the synchronization signal to the head of the communication frame composed of waveform data of at least one hopping chip output from the IFFT units 108 _{1 to} 108 _m. Append. As described above, the synchronization signal adding unit 109 outputs the communication frame of the FH-MMFSK signal to which the AGC preamble and the synchronization signal are added to the DA conversion unit 110.

  Finally, the DA conversion unit 110 converts the communication frame of the FH-MMFSK signal output from the synchronization signal adding unit 109 into an analog signal. This analog signal is transmitted from the antenna via the AFE unit 111.

On the other hand, the reception unit 20 selects an AFE unit 201, an AD (Analog Digital) conversion unit 202, a synchronization unit 203, and a plurality of FFT (Fast Fourier Transform) units 204 _{1 to} 204 _m each having a different analysis time length. Unit 205, frequency / time-level conversion unit 206, hopping pattern storage unit 207, a plurality of subtraction units 208 _{1 to} 208 _n , a plurality of remainder calculation units 209 _{1 to} 209 _n , a majority decision determination unit 210, A P / S (Parallel / Serial) conversion unit 211.

The FH-MMFSK signal received from the antenna via the AFE unit 201 is converted into a digital signal by the AD conversion unit 202 and input to the synchronization signal detection unit 203. The synchronization unit 203 detects a synchronization signal from the input FH-MMFSK signal, and recognizes a communication frame of the FH-MMFSK signal based on the detected synchronization signal. Then, the waveform data of each chip stored in the recognized communication frame is output to the FFT units 204 _{1 to} 204 _m .

As shown in FIG. 5, each of the FFT units 204 _{1 to} 204 _m repeatedly performs FFT processing with different analysis time lengths in synchronization with the chip output from the synchronization unit 203. Here, the analysis time length of the IFFT unit 204 _i (1 ≦ i ≦ m) matches the analysis time length of the IFFT unit 108 _i of the communication partner. FIG. 5 shows an example in which four FFT units 204 having analysis time lengths of Tc, Tc / 2, Tc / 4, and Tc / 8 (where Tc is the chip width) are provided. 4 parallel processing). The FFT unit 204 with the analysis time length Tc performs one FFT process for one chip (2041), and the FFT unit 204 with the analysis time length Tc / 2 performs two FFT processes for one chip. (2042), the FFT unit 204 with the analysis time length Tc / 4 performs four FFT processes on one chip (2043), and the FFT unit 204 with the analysis time length Tc / 8 has 1 The FFT process is performed 8 times on the chip (2044).

The selection unit 205 compares the calculation results output from each of the FFT units 204 _{1 to} 204 _{m for} each chip, and selects the frequency spectrum corresponding to the waveform data included in the chip and the time information (chip). The calculation result that correctly represents the combination with the internal position and time width is selected and output to the frequency / time-level conversion unit 206.

  FIG. 6 is a flowchart for explaining the operation of the selection unit 205. In this figure, calculation results are input from four FFT units 204 having analysis time lengths of Tc, Tc / 2, Tc / 4, and Tc / 8 (where Tc is the chip width) to the selection unit 205, respectively. Assumed.

  When the calculation result (one calculation result) for one chip is input from the FFT unit 204 having the analysis time length Tc (S601), the selection unit 205 sets the calculation result to the calculated value V1 (S602). . Further, when the calculation result (two calculation results) for one chip is input from the FFT unit 204 having the analysis time length Tc / 2 (S603), the selection unit 205 determines from the absolute value of the first calculation result. The absolute value of the value obtained by subtracting the absolute value of the second calculation result (= || first calculation result |-| second calculation result ||) is obtained, and this is set to the calculated value V2 (S604). In addition, when the calculation result (four calculation results) for one chip is input from the FFT unit 204 having the analysis time length Tc / 4 (S605), the selection unit 205 determines from the absolute value of the first calculation result. The absolute value (|| first calculation result | -Σ | second and subsequent calculation results ||) of the value obtained by subtracting the absolute value of each calculation result after the second time is obtained and set to the calculated value V3 ( S606). When the calculation result for one chip (eight calculation results) is input from the FFT unit 204 having the analysis time length Tc / 8 (S607), the selection unit 205 calculates the absolute value of the first calculation result. The absolute value (|| first calculation result | -Σ | second and subsequent calculation results ||) of the value obtained by subtracting the absolute value of each calculation result after the second time is obtained and set to the calculated value V4 ( S608).

  As described above, when the calculation values V1 to V4 of all the FFT units 204 are calculated for the same chip, the FFT unit 204 corresponding to the calculation value having the largest value is selected and selected. The calculation result of the chip (calculation result of (chip width Tc / analysis time length)) input from the FFT unit 204 is used as the frequency spectrum and time information (in-chip position) corresponding to the waveform data included in the chip. And the time width) are output to the frequency / time-level conversion unit 206.

  For example, when waveform data having 8 cycles within the chip width Tc is continuous in the chip, the results of the FFT processing for the waveform data are the analysis times of Tc, Tc / 2, Tc / 4, and Tc / 8, respectively. The four FFT units 204 having a length coincide with each other. For this reason, it cannot be identified which FFT unit 204 outputs the combination of the frequency spectrum and time information corresponding to the waveform data. However, according to the flow shown in FIG. 6, the calculated value V1 corresponding to the FFT unit 204 having the analysis time length Tc is the largest, and therefore, the combination of the frequency spectrum and time information corresponding to the waveform data can be correctly selected. .

The frequency / time-level conversion unit 206 registers the same table as the level-frequency / time conversion table registered in the level-frequency / time conversion unit 107 of the communication partner. Then, using this table, the combination of the frequency spectrum of each chip and the time information input from the selection unit 205 is converted into a level and output to the subtraction units 209 _{1 to} 209 _n . It is assumed that the table shown in FIG. 3 is registered in the frequency / time-level conversion unit 206. For example, if the FFT calculation result for one chip input from the selection unit 205 includes the calculation result for two times, the analysis time length of the calculation result is Tc / 2, so the table shown in FIG. 1071B is selected. If the first calculation result is zero and the second calculation result is a frequency spectrum corresponding to the numbers “5” to “6”, the level “15” is obtained from the table 1071B shown in FIG. Is converted to

The hopping pattern storage unit 207 stores the same pattern as the hopping pattern stored in the hopping pattern storage unit 104 of the communication partner in association with each value that can be taken by K _2- bit parallel data. Yes. The subtraction units 208 _{1 to} 208 _n and the remainder calculation units 209 _{1 to} 209 _n are provided for each hopping pattern stored in the hopping pattern storage unit 207. The subtracting units 208 _{1 to} 208 _n subtract the level of the corresponding hopping pattern and the level of one hopping chip output from the frequency / time-level converting unit 206 for each chip, and the subtraction result corresponds to the corresponding remainder. It outputs to the arithmetic units 209 _{1 to} 209 _n . The remainder calculation units 209 _{1 to} 209 _n calculate the remainder of the level number of the level pattern and the hopping pattern used by the communication partner with respect to the subtraction results input from the corresponding subtraction units 208 _{1 to} 208 _n . That is, y (mod n) is calculated, where y is the subtraction result and n is the number of levels of the level pattern and hopping pattern used by the communication partner. Then, the calculation result is output to majority decision section 210.

The majority determination section 210, in association with the residue calculating unit ₂₀₉ 1 _{~209 n} each, parallel data of _{K 2} bits corresponding to the hopping pattern to which the remainder calculation unit ₂₀₉ 1 _{~209 n} is associated with data A value is registered. Now, the majority decision determination unit 210 performs majority decision on the calculation result of one hopping chip input from each of the remainder calculation units 209 _{1 to} 209 _n , and one hopping portion including the most chips having the same calculation result. The remainder calculation units 209 _{1 to} 209 _n that output the calculation results of the chips are identified. The specified remainder calculation units 209 _{1 to} 209 _n output K ₁ -bit parallel data having a value corresponding to the calculation result (level) of the chip that is output most, and the specified remainder calculation units 209 _{1 to} 209 _n. The parallel data of K ₂ bits registered in association with is output.

Finally, the P / S conversion unit 211 uses the K ₁ bit and K ₂ bit parallel data output from the majority decision determination unit 210 as K ₁ bits as upper (or lower) bit data, and K ₂ bits as the remaining bits. It is converted into K-bit serial data (received data) as bit data and output.

  Each configuration of the above-described FH-MMFSK modem device may be executed by hardware by an integrated logic IC such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), or may be a DSP. (Digital Signal Processor) etc. may be executed by software by a computer.

  The embodiment of the present invention has been described above.

  In this embodiment, the waveform data stored in one chip has a frequency spectrum and time information (in-chip position and time width). By doing so, the number of levels that can be stored in one chip can be increased without changing the chip width, that is, without decreasing the hopping speed.

  In addition, this invention is not limited to said embodiment, Many deformation | transformation are possible within the range of the summary.

For example, in the above embodiment, the case where the present invention is applied to the FH-MMFSK modem has been described as an example. However, the present invention can also be applied to FH-M ³ FSK modems. However, in this case, the time widths of waveform data representing a plurality of levels stored in one chip are all the same, that is, waveform data representing a plurality of levels stored in one chip is processed by the same IFFT unit and FFT unit. Shall be.

In the above-described embodiment, a plurality of FFT processes having different analysis time lengths are executed in parallel, so that waveform data stored in the chip has a frequency spectrum and time information (in-chip position and time width). I am doing so. However, the present invention is not limited to this. For example, instead of FFT, a wavelet transform that can simultaneously analyze both time information and frequency information may be used. In this way, a plurality of waveform data having different time information can be stored in one chip, so that the present invention can be applied to an FH-M ³ FSK modem.

  In the above-described embodiment, the case where the present invention is applied to a modem device including both a transmission unit and a reception unit has been described as an example. However, a modem device including only a transmission unit or a reception unit may be used.

FIG. 1 is a schematic diagram of an FH-MMFSK modem apparatus to which an embodiment of the present invention is applied. 2A schematically shows a level pattern 1021 output from the level conversion unit 102, and FIG. 2B schematically shows a hopping pattern 1041 stored in the hopping pattern storage unit 104. FIG. 3A to 3D are diagrams schematically showing a level-frequency / time conversion table 1071 registered in the level-frequency / time conversion unit 107. FIG. FIG. 4 is a diagram schematically showing a transmission spectrum 1072 for one hopping output from the level-frequency / time conversion unit 107. FIG. 5 is a diagram for explaining parallel processing of FFT by a plurality of FFT processing units 204. FIG. 6 is a diagram for explaining the operation flow of the selection unit 205. FIG. 7A schematically shows communication frames of conventional FH-MMFSK and FH-M ³ FSK, and FIG. 7B shows communication frames of conventional FH-MMFSK and FH-M ³ FSK. It is the figure which represented typically the tone which can be stored in the chip | tip which comprises.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Transmission part, 20 ... Reception part, 101 ... S / P conversion part, 102 ... Level conversion part, 103 ... Pattern selection part, 104 ... Hopping pattern storage part, 105 ... Addition part, 106 ... Remainder calculation part, 107 ... Level-frequency / time conversion unit, 108 ... IFFT unit, 109 ... synchronization signal addition unit, 110 ... DA conversion unit, 111 ... AFE unit, 201 ... AFE unit, 202 ... AD conversion unit, 203 ... synchronization unit, 204 ... FFT , 205 ... selection unit, 206 ... frequency / time-level conversion unit, 207 ... hopping pattern storage unit, 208 ... subtraction unit, 209 ... residue calculation unit, 210 ... majority determination unit, 211 ... P / S conversion unit

Claims (6)

FH-MMFSK a - - (M-ary Multilevel Multitone FSK Frequency Hopping) communication method using, (Frequency Hopping M-ary Multilevel FSK) or ^FH-M 3 FSK
The transmission side device converts the level assigned to each chip constituting the communication frame according to FH-MMFSK or FH-M ³ FSK into waveform data having a position in the chip, a time width and a frequency according to the level. Then send
The receiving side device receives the communication frame, and determines the level assigned to the chip based on the position, time width and frequency of the waveform data stored in each chip constituting the received communication frame. A communication method characterized by specifying. The communication method according to claim 1,
The transmission side device has a plurality of IFFT (Inverse Fast Fourier Transform) means having different analysis time lengths, and the level assigned to each chip is set to the same analysis time as the time width corresponding to the level. It is processed by IFFT means having a length, and converted into waveform data having an on-chip position, a time width and a frequency according to the level,
The receiving apparatus has a plurality of FFT (Fast Fourier Transform) means each having a different analysis time length, and the waveform data stored in each chip is processed by each of the plurality of FFT means. A communication method characterized by specifying an on-chip position, a time width, and a frequency of the waveform data. The communication method according to claim 2,
The plurality of IFFT means and the plurality of FFT means have an analysis time length of 1 / n of a chip time width (where n is 1 or an even number),
The receiving side apparatus analyzes the waveform data stored in each of the chips based on an arithmetic value of a processing result of n times in each of the plurality of FFT means and has the same analysis time as the time width of the waveform data. A communication method characterized by specifying an FFT unit having a length and specifying an in-chip position, a time width, and a frequency of the waveform data from a result of n times of processing by the specified FFT unit. The communication method according to claim 3, wherein
The calculated value is the absolute value of the first processing result when n is 1, and the sum of the absolute values of the second and subsequent processing results from the absolute value of the first processing result when n is an even number. The absolute value of the subtracted value,
The receiving apparatus specifies the FFT means having the largest calculation value for waveform data as the FFT means having the same analysis time length as the time width of the waveform data. A - (M-ary Multilevel Multitone FSK Frequency Hopping) communication device using, - FH-MMFSK (Frequency Hopping M-ary Multilevel FSK) or ^FH-M 3 FSK
Means for converting a level assigned to each chip constituting a communication frame according to FH-MMFSK or FH-M ³ FSK into waveform data having an in-chip position, a time width and a frequency according to the level;
Means for transmitting a communication frame in which a level assigned to each chip is converted into waveform data. A - (M-ary Multilevel Multitone FSK Frequency Hopping) communication device using, - FH-MMFSK (Frequency Hopping M-ary Multilevel FSK) or ^FH-M 3 FSK
Means for receiving a communication frame transmitted by the communication device according to claim 5;
And means for specifying the level assigned to the chip based on the in-chip position, time width, and frequency of the waveform data stored in each chip constituting the received communication frame. apparatus.

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