JP2006080675A - Semiconductor integrated circuit and layout design method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce leakage current of a semiconductor integrated circuit independently of a threshold voltage of its MOS transistors. <P>SOLUTION: The semiconductor integrated circuit 1 is provided with a NAND gate unit 10 comprising a high speed operation 2-input NAND gate 2 and a control Nch MOS transistor NS1. The NAND gate 2 comprises Pch MOS transistors P1, P2, and Nch MOS transistors N1, N2. A control signal SG1 is given to the gate of the control Nch MOS transistor NS1, the control signal SG1 having a voltage of +V1 the same as a voltage of a high level power supply Vdd in the case of a "High level" and having a voltage of -V2 greater than the absolute voltage of the threshold voltage of the transistor in the case of a "Low level". In the case of the "High level", the control Nch MOS transistor NS1 is turned on and the NAND gate 2 is activated. Whereas, in the case of the "Low level", the control Nch MOS transistor NS1 is turned off and the NAND gate 2 is deactivated. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a logic circuit and an amplifier circuit including control transistors, and more particularly to a semiconductor integrated circuit capable of reducing leakage current and a layout design method thereof.

  In recent years, the threshold voltage (Vth) of MOS transistors has been steadily decreasing along with the progress of miniaturization, lower voltage, and higher integration of LSI. This low Vth increases the sub-threshold leakage current of the transistor, shortens the battery life in devices such as mobile phones and portable terminals, and in the MPU, the leakage current at the time of off is equal to or equal to the current level during operation. This leads to an increase in power consumption.

  As a technique for reducing this leakage current, for example, the Vth of a control MOS transistor for controlling the operation of a logic circuit such as a NAND gate or a latch circuit is made larger than the Vth of a MOS transistor constituting the logic circuit (for example, (See Patent Document 1).

However, when Vth of the control MOS transistor is increased, the on-resistance of the transistor increases, and there is a problem that the amount of current flowing from the logic circuit to the low-potential side power source decreases and high-speed operation of the logic circuit becomes difficult. Further, there is a problem that if the gate width (Wg) is increased while the gate length (Lg) of the control MOS MOS transistor is kept constant in order to reduce the on-resistance, the chip area of the logic circuit increases.
JP-A-10-261946 (page 9, FIG. 7 and FIG. 8)

  The present invention provides a semiconductor integrated circuit capable of reducing leakage current regardless of the threshold voltage of a MOS transistor and a layout design method thereof.

  In order to achieve the above object, a semiconductor integrated circuit of one embodiment of the present invention includes a logic circuit connected to a high-potential-side power supply and a threshold voltage provided between the logic circuit and the low-potential-side power supply. A control transistor that stops the operation of the logic circuit by a control signal voltage that is larger than the absolute value of the threshold voltage that is input when turned off, and that operates the logic circuit by the control signal voltage that is input when turned on It is characterized by doing.

  Furthermore, in order to achieve the above object, a layout design method for a semiconductor integrated circuit according to one embodiment of the present invention includes a step of performing layout according to a floor plan with reference to element information, circuit connection information, process information, and layout information. , Arranging a normal operation cell in accordance with the layout information, and performing a first operation speed determination as to whether or not the arranged normal operation cell satisfies a high-speed operation specification. A control transistor for stopping the operation of the logic circuit with a control signal voltage larger than the absolute value of the threshold voltage input when turned off, and for operating the logic circuit with the control signal voltage input when turned on And replacing the high-speed cell with a transistor having the same occupation area and the same shape as the normal operation cell; If the signal / power supply wiring is arranged according to the out information, and the second operation speed determination is made as to whether the normal operation cell arranged in the wiring satisfies the high-speed operation specification. The operation of the logic circuit is stopped by a control signal voltage that has the threshold voltage and is larger than the absolute value of the threshold voltage that is input when turned off, and operates the logic circuit by the control signal voltage that is input when turned on A step of replacing the high-speed cell with the transistor for control, having the same occupied area as the normal operation cell, and having the same shape, and arranging a signal line in the high-speed cell. .

  According to the present invention, it is possible to provide a semiconductor integrated circuit capable of reducing a leakage current regardless of the threshold voltage of a MOS transistor and a layout design method thereof.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a semiconductor integrated circuit according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a semiconductor integrated circuit, and FIG. 2 is a diagram showing a control signal level input to the gate of a control Nch MOS transistor. In this embodiment, a NAND gate is used as the logic circuit.

  As shown in FIG. 1, the semiconductor integrated circuit 1 is provided with a NAND gate portion 10 composed of a high-speed operation 2-input NAND gate 2 and a control Nch MOS transistor NS1. The NAND gate 2 includes Pch MOS transistors P1, P2 and Nch MOS transistors N1, N2.

  The source of the Pch MOS transistor P1 is connected to the high potential side power supply Vdd, and the input signal A1 is input to the gate. The Nch MOS transistor N1 has a drain connected to the drain of the Pch MOS transistor P1, and an input signal A1 is input to the gate. The source of the Pch MOS transistor P2 is connected to the high potential side power supply Vdd, and the input signal B1 is input to the gate. The Nch MOS transistor N2 has a drain connected to the source of the Nch MOS transistor N1, and an input signal B1 input to the gate. A connection node between the drain of the Pch MOS transistor P1 and the drain of the Nch MOS transistor N1 is connected to the drain of the Pch MOS transistor P2, and the output signal Out1 is output from the drain of the Pch MOS transistor P2.

  In the control Nch MOS transistor NS1, the drain is connected to the source of the Nch MOS transistor N2, the source is connected to the low potential side power supply Vss, the gate is supplied with the control signal GS1, and the on / off operation of the NAND gate 2 is controlled. To do. Here, the absolute value (| Vth |) of the threshold voltage of the Pch MOS transistors P1 and P2, the Nch MOS transistors N1 and N2, and the control Nch MOS transistor NS1 is, for example, 0 to operate the NAND gate 2 at high speed. .15V (normal operation transistor 0.3V) is set to a small value.

  As shown in FIG. 2, a control signal having a voltage of + V1 which is the same voltage as the high-potential-side power supply Vdd at the “High” level and −V2 at the “Low” level is applied to the gate of the control Nch MOS transistor NS1. SG1 is input. The control Nch MOS transistor NS1 is turned on when it is at “High” level, and the NAND gate 2 operates. On the other hand, it is turned off at the “Low” level, and the NAND gate 2 stops its operation.

Here, the relationship between the absolute value | V2 | of -V2 and the absolute value | Vth1 | of the threshold voltage Vth1 of the control Nch MOS transistor NS1 is
| -V2 |> | Vth1 | ... Formula (1)
Is set to satisfy.

  As described above, in the semiconductor integrated circuit according to the present embodiment, the voltage (−V2) at the time of the “Low” level of the control signal SG1 input to the gate of the control Nch MOS transistor NS1 that controls the on / off operation of the NAND gate 2. ) Is set to | −V2 |> | Vth1 |. Therefore, the voltage applied to the gate of the control Nch MOS transistor NS1 when the control signal SG1 is at the “Low” level is shifted from the threshold voltage Vth1 to | Vth1 | × 2 or more (−) side. Therefore, the channel layer of the control Nch MOS transistor NS1 can be brought into a sufficiently accumulated state (accumulation mode) while operating the NAND gate 2 at high speed, and the leakage current at the off time can be greatly reduced.

Although this embodiment is applied to a high-speed NAND gate using a MOS transistor having a small Vth, it can also be applied to a normal operation or low power consumption NAND gate having a relatively large Vth. Although the NAND gate is described as an example of the logic circuit, the present invention can be applied to a gate circuit such as an inverter, an AND gate, an OR gate, and a NOR gate, a sequential circuit such as a flip-flop, a register, and a counter. Furthermore, although a Pch MOS transistor and an Nch MOS transistor using a silicon oxide film as a gate insulating film are used, a SiNxOy film obtained by nitriding a silicon oxide film, a laminated film of a silicon nitride film (Si ₃ N ₄ ) / silicon oxide film Alternatively, a Pch MIS transistor and an Nch MIS transistor using a high dielectric film (High-K gate insulating film) may be used. As the high dielectric film, an oxide of Hf (hafnium), Zr (zirconium), La (lanthanum), or a silicate thereof (for example, HfSiON) is used.

  Next, a semiconductor integrated circuit according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 3 is a circuit diagram showing a semiconductor integrated circuit, and FIG. 4 is a diagram showing a control signal level input to the gate of the control Nch MOS transistor. In this embodiment, a NAND gate for high speed operation and a NAND gate for low power consumption are provided as logic circuits.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 3, the semiconductor integrated circuit 1a includes a two-input NAND gate 2a and a control Nch MOS transistor NS11, a high-speed operation NAND gate unit 11, and a two-input NAND gate 2b and a control Nch MOS transistor NS21. A low power consumption NAND gate section 12 is provided. The NAND gate 2a is composed of Pch MOS transistors P11 and P12 and Nch MOS transistors N11 and N12, and the NAND gate 2b is composed of Pch MOS transistors P21 and P22 and Nch MOS transistors N21 and N22.

  The source of the Pch MOS transistor P11 is connected to the high potential side power supply Vdd, and the input signal A2 is input to the gate. The Nch MOS transistor N11 has a drain connected to the drain of the Pch MOS transistor P11 and an input signal A2 input to the gate. The source of the Pch MOS transistor P12 is connected to the high potential side power supply Vdd, and the input signal B2 is input to the gate. The Nch MOS transistor N12 has a drain connected to the source of the Nch MOS transistor N11 and an input signal B2 input to the gate. A connection node between the drain of the Pch MOS transistor P11 and the drain of the Nch MOS transistor N11 is connected to the drain of the Pch MOS transistor P12, and the output signal Out2 is output from the drain of the Pch MOS transistor P12.

  In the control Nch MOS transistor NS11, the drain is connected to the source of the Nch MOS transistor N12, the source is connected to the low potential side power supply Vss, the control signal GS1 is input to the gate, and the on / off operation of the NAND gate 2a is controlled. To do.

  In the Pch MOS transistor P21, the source is connected to the high potential side power supply Vdd, and the input signal A3 is input to the gate. The Nch MOS transistor N21 has a drain connected to the drain of the Pch MOS transistor P21 and an input signal A3 input to the gate. In the Pch MOS transistor P22, the source is connected to the high potential side power supply Vdd, and the input signal B3 is input to the gate. The Nch MOS transistor N22 has a drain connected to the source of the Nch MOS transistor N21, and an input signal B3 input to the gate. A connection node between the drain of the Pch MOS transistor P21 and the drain of the Nch MOS transistor N21 is connected to the drain of the Pch MOS transistor P22, and the output signal Out3 is output from the drain of the Pch MOS transistor P22.

  In the control Nch MOS transistor NS21, the drain is connected to the source of the Nch MOS transistor N22, the source is connected to the low potential side power supply Vss, the control signal GS2 is input to the gate, and the on / off operation of the NAND gate 2b is controlled. To do.

  Here, the absolute value (| Vth |) of the threshold voltage of the Pch MOS transistors P11 and P12, the Nch MOS transistors N11 and N12, and the control Nch MOS transistor NS11 is, for example, 0 to operate the NAND gate 2a at high speed. It is set to a small value of .15V. On the other hand, the absolute value (| Vth |) of the threshold voltage of the Pch MOS transistors P21 and P22, the Nch MOS transistors N21 and N22, and the control Nch MOS transistor NS21 is, for example, It is set to 0.5V.

  As shown in FIG. 4, the control signal SG2 having the same voltage + V1 as that of the high potential side power supply Vdd at the “High” level and the voltage of 0V at the “Low” level is applied to the gate of the control Nch MOS transistor NS21. Entered. The control Nch MOS transistor NS21 is turned on at the “High” level, and the NAND gate 2b operates. On the other hand, it is turned off at the “Low” level, and the NAND gate 2b stops operating. The control signal SG1 is input to the gate of the control Nch MOS transistor NS11 as in FIG.

  As described above, in the semiconductor integrated circuit of this embodiment, the voltage (−V2) at the time of the “Low” level of the control signal SG1 input to the gate of the control Nch MOS transistor NS11 that controls the on / off operation of the NAND gate 2a. ) Is set to | −V2 |> | Vth1 |, and the voltage at the time of “Low” level of the control signal SG2 input to the gate of the control Nch MOS transistor NS21 for controlling the on / off operation of the NAND gate 2b is set to 0V. It is set. Therefore, the voltage applied to the gate of the control Nch MOS transistor NS11 when the control signal SG1 is at the “Low” level is shifted from the threshold voltage Vth1 to | Vth1 | × 2 or more (−) side, and the control signal SG2 The voltage applied to the gate of the control Nch MOS transistor NS21 at the “Low” level is 0V, shifted from the threshold voltage 0.5 of the control Nch MOS transistor NS21 to | Vth1 | × 2 or more (−) side. Yes. Therefore, the channel layers of the control Nch MOS transistors NS11 and NS21 can be sufficiently accumulated (accumulation mode) while the NAND gate 2a is operated at high speed and the NAND gate 2b is operated at low power consumption. Leakage current can be greatly reduced.

  Next, a semiconductor integrated circuit according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 5 is a circuit diagram showing a semiconductor integrated circuit, and FIG. 6 is a diagram showing a control signal level inputted to the gate of the control Pch MOS transistor. In this embodiment, a negative power source is used.

  As shown in FIG. 5, the semiconductor integrated circuit 1b is provided with a NAND gate portion 10a composed of a high-speed operation 2-input NAND gate 2c and a control Pch MOS transistor PS31. The NAND gate 2c is composed of Nch MOS transistors N31 and N32 and Pch MOS transistors P31 and P32.

  The Nch MOS transistor N31 has a drain connected to the low potential side power supply Vss and an input signal A4 input to the gate. The source of the Pch MOS transistor P31 is connected to the source of the Nch MOS transistor N31, and the input signal A4 is input to the gate. The Nch MOS transistor N32 has a drain connected to the low potential side power supply Vss and an input signal B4 input to the gate. The source of the Pch MOS transistor P32 is connected to the drain of the Pch MOS transistor P31, and the input signal B4 is input to the gate. In the control Pch MOS transistor PS31, the source is connected to the drain of the Pch MOS transistor P32, the drain is connected to the negative high potential side power source -Vdd, the control signal SG3 is input to the gate, and the NAND gate 2c is turned on / off Control the behavior.

  Here, the absolute value (| Vth |) of the threshold voltage of the Nch MOS transistors N31 and N32, the Pch MOS transistors P31 and P32, and the control Pch MOS transistor PS31 is, for example, 0 to operate the NAND gate 2c at high speed. .15V (threshold voltage for normal operation 0.3V) is set to a small value.

  As shown in FIG. 6, the gate of the control Pch MOS transistor PS31 has a voltage of + V3 at the “High” level and the same voltage (−V4) as the negative high potential power supply −Vdd at the “Low” level. The control signal SG3 having is input. The control Pch MOS transistor PS31 is turned on at the “Low” level, and the NAND gate 2c operates. On the other hand, it is turned off at the “High” level, and the NAND gate 2c stops operating.

Here, the relationship between the absolute value | + V3 | of + V3 and the absolute value | -Vth2 | of the threshold voltage −Vth2 of the control Pch MOS transistor PS31 is
| + V3 |> | −Vth2 | ・ ・ ・ ・ ・ Formula (2)
Is set to satisfy.

  As described above, in the semiconductor integrated circuit of this embodiment, the voltage (+ V3) at the time of “High” level of the control signal GS3 input to the gate of the control Pch MOS transistor PS31 that controls the on / off operation of the NAND gate 2c. Is set to | + V3 |> | −Vth2 |. Therefore, the voltage applied to the gate of the control Pch MOS transistor PS31 when the control signal SG3 is at “High” level is shifted from the threshold voltage −Vth3 to | −Vth2 | × 2 or more (+) side. Therefore, the channel layer of the control Pch MOS transistor PS31 can be sufficiently accumulated (accumulation mode) while operating the NAND gate 2c at high speed, and the leakage current at the off time can be greatly reduced.

  Next, a semiconductor integrated circuit according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 7 is a circuit diagram showing the comparator.

  As shown in FIG. 7, the high-speed comparator 4 includes an amplifying unit 13 and a control Nch MOS transistor NS3. The amplifying unit 13 includes Pch MOS transistors P41 and P42 and Nch MOS transistors N41 and N42. The comparator is also referred to as a comparison amplifier circuit.

  The Pch MOS transistor P41 has a source connected to the high potential side power supply Vdd and a gate connected to the drain. The Pch MOS transistor P42 has a source connected to the high potential side power supply Vdd and a gate connected to the gate of the Pch MOS transistor P41. Pch MOS transistors P41 and P42 constitute a current mirror circuit. The Nch MOS transistor N41 has a drain connected to the drain of the Pch MOS transistor P41 and an input potential Vin input to the gate. The Nch MOS transistor N42 has a drain connected to the drain of the Pch MOS transistor P42 and a reference potential Vref input to the gate. In the control Nch MOS transistor NS3, the drain is connected to the sources of the Nch MOS transistors N41 and N42, the source is connected to the low potential side power supply Vss, the control signal SG1 is input to the gate, and the comparator 4 is turned on / off. Control. Then, a comparatively amplified output signal Out4 is output from a connection node between the drain of the Pch MOS transistor P42 and the drain of the Nch MOS transistor N42.

  Here, the absolute values (| Vth |) of the threshold voltages of the Pch MOS transistors P41 and P42, the Nch MOS transistors N41 and N42, and the control Nch MOS transistor NS3 are, for example, 0. It is set to a small value of 2V.

  A control signal SG1 having a voltage of + V1 which is the same voltage as that of the high-potential power supply Vdd at the “High” level and a voltage of −V2 at the “Low” level is input to the gate of the control Nch MOS transistor NS3. The control Nch MOS transistor NS3 is turned on when it is at “High” level, and the comparator 4 operates. On the other hand, it is turned off at the “Low” level, and the comparator 4 stops its operation.

Here, the relationship between the absolute value | V2 | of -V2 and the absolute value | Vth3 | of the threshold voltage Vth3 of the control Nch MOS transistor NS3 is
| −V2 | >> | Vth3 | ・ ・ ・ ・ ・ Formula (3)
Is set to satisfy.

  As described above, in the semiconductor integrated circuit of this embodiment, the voltage (−V2) at the time of “Low” level of the control signal SG1 input to the gate of the control Nch MOS transistor NS3 that controls the on / off operation of the comparator 4 Is set to | −V2 |> | Vth3 |. Therefore, the voltage applied to the gate of the control Nch MOS transistor NS3 when the control signal SG1 is at the “Low” level is shifted from the threshold voltage Vth1 to | Vth3 | × 2 or more (−) side. Therefore, the channel layer of the control Nch MOS transistor NS3 can be brought into a sufficiently accumulated state (accumulation mode) while operating the comparator 4 at high speed, and the leakage current at the time of off can be greatly reduced.

  In this embodiment, the high-speed comparator has been described. However, the present invention can be applied to an amplifier circuit including a control transistor, for example, a high-speed amplifier having a differential amplifier stage.

  Next, a semiconductor integrated circuit and a layout design method thereof according to Embodiment 5 of the present invention will be described with reference to the drawings. 8 is an operation flowchart showing a layout design method of a semiconductor integrated circuit, FIG. 9 is a circuit diagram showing a normal operation NAND gate cell, FIG. 10 is a circuit diagram showing a high-speed NAND gate cell, and FIG. 11 is a circuit diagram showing a semiconductor integrated circuit. .

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 8, in the operation flowchart of the layout design method, first, layout by a floor plan is performed with reference to element characteristic information, circuit connection information, process information, layout information, and the like (step S1).

  Next, normal operation cells are arranged according to the layout information. As the cell to be arranged, for example, as shown in FIG. 9, a normal operation NAND gate cell NANDC1 in which the absolute value of the threshold voltage (Vth) of the MOS transistor is 0.3V is used. In the control Nch MOS transistor NS21, the drain and source are short-circuited, and no control signal is input to the gate. Although not shown here, the drain and source of the control Nch MOS transistor are also short-circuited in other normal operation cells, and no control signal is input to the gate. (Step S2).

  Subsequently, a first operation speed determination is performed as to whether the arranged normal operation cell satisfies the high-speed operation specification (step S3). If it is acceptable, go to the next step. If it is not acceptable, replace it with a fast cell. As a cell to be replaced, for example, as shown in FIG. 10, it has the same occupied area as the normal operation NAND gate cell NANDC1, and has the same shape as the transistor constituting the normal operation NAND gate cell NANDC1, and has a threshold voltage (Vth) of the transistor. A high-speed NAND gate cell NANDC2 having an absolute value of 0.15V is used (step S4).

  Next, as shown in FIG. 11, the cells in the replacement region (first time) 7a of the semiconductor integrated circuit 1c for the high-speed gate cell are, for example, from the normal operation inverter cell INVC1 to the high-speed inverter cell INVC2 and from the normal operation NOR gate cell NORC1. The high-speed NOR gate cell NORC2 and the normal operation NAND gate cell NANDC1 are replaced with the high-speed NAND gate cell NANDC2. Here, the control signal GS1 output from the control circuit 6 is input to the replaced cell. Note that the normal operation inverter cell INVC1 and the high-speed inverter cell INVC2, the normal operation NOR gate cell NORC1 and the high-speed NOR gate cell NORC2 have the same occupied area, and the transistors constituting the same also have the same shape. Then, the signal / power wiring of the layout designed part is arranged (step S5).

  Subsequently, a second operation speed determination is performed as to whether or not the normal operation cell in which the signal / power supply lines are arranged satisfies the high-speed operation specification (step S6). If acceptable, end the step. If it is not acceptable, replace it with a fast cell. As the replacement cell, for example, as shown in FIG. 11, the cell in the replacement region (second time) 7b for the high-speed gate cell of the semiconductor integrated circuit 1c is replaced by, for example, the normal operation inverter cell INVC1 to the high-speed inverter cell INVC2. . (Step S7).

  Next, the cell replaced with the high-speed gate cell performs the wiring arrangement of the signal wiring and connects the replaced cell with the control signal GS1 output from the control circuit 6 (step S8).

  As described above, in the semiconductor integrated circuit and the layout design method thereof according to the present embodiment, the layout is first performed according to the floor plan, and then the normal operation cells are arranged. Subsequently, the cells in the region requiring high-speed operation are replaced with high-speed cells having the same occupied area and having the same shape transistor after the normal operation cell arrangement and after the signal / power supply wiring arrangement. For this reason, it is possible to optimally arrange cells without changing the layout design area, and to suppress the current consumption of the entire circuit while satisfying the required performance of the semiconductor integrated circuit.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, the transistors constituting the logic circuit and the comparator are composed of MOS transistors, but the transistors constituting the logic circuit, the comparator, and the amplifier circuit may be composed of a bipolar transistor and BiCMOS.

The present invention can be configured as described in the following supplementary notes.
(Supplementary note 1) A logic circuit connected to a high potential side power supply and having a plurality of Nch MOS transistors and Pch MOS transistors each having an absolute value of a threshold voltage; provided between the logic circuit and the low potential side power supply; For controlling the logic circuit to stop the operation of the logic circuit by a control signal voltage that is larger than the absolute value of the threshold voltage inputted at the time of turning off and to operate the logic circuit by the control signal voltage inputted at the time of turning on A semiconductor integrated circuit comprising an Nch MOS transistor.

(Supplementary Note 2) A logic circuit that is connected to a low-potential side power supply and has a plurality of Nch MOS transistors and Pch MOS transistors each having an absolute value of a threshold voltage, and is provided between the logic circuit and the negative high-potential side power supply, The control signal voltage that has a threshold voltage different in polarity from the threshold voltage, stops the operation of the logic circuit by a control signal voltage that is larger than the absolute value of the threshold voltage that is input when turned off, and that is input when turned on And a control Pch MOS transistor for operating the logic circuit.

(Supplementary Note 3) An amplifying unit that is connected to a high-potential-side power supply and includes a plurality of Nch MOS transistors and Pch MOS transistors each having an absolute value of a threshold voltage, and provided between the amplifying unit and the low-potential-side power source, Control for stopping the operation of the amplifying unit by a control signal voltage having a voltage and larger than the absolute value of the threshold voltage inputted at the time of off, and operating the amplifying unit by the control signal voltage inputted at the time of on A semiconductor integrated circuit comprising an Nch MOS transistor.

(Additional remark 4) The step which performs layout by a floor plan with reference to element information, circuit connection information, process information, layout information, the step which arrange | positions a normal operation cell according to the said layout information, The said normal arranged A first operation speed determination is made as to whether the operation cell satisfies the high-speed operation specification. If the operation cell is unacceptable, the control cell voltage has a threshold voltage and is greater than the absolute value of the threshold voltage input when the operation cell is off. A control Nch MOS transistor for stopping the operation of the logic circuit and operating the logic circuit by the control signal voltage input when turned on, and having the same occupied area and the same shape as the normal operation cell A step of replacing with a high-speed cell, a step of laying out signal / power supply wiring in accordance with the layout information, and a placement If the wired normal operation cell satisfies the high-speed operation specification, a second operation speed determination is performed. If the normal operation cell is not allowable, the normal operation cell has the threshold voltage and the absolute value of the threshold voltage input when turned off. The control Nch MOS transistor for stopping the operation of the logic circuit by a control signal voltage larger than the value and operating the logic circuit by the control signal voltage inputted at the time of ON, and having the same occupied area as the normal operation cell And a layout design method for a semiconductor integrated circuit, comprising: replacing the high-speed cell having a transistor with the same shape, and arranging a signal wiring in the high-speed cell.

1 is a circuit diagram showing a semiconductor integrated circuit according to Embodiment 1 of the present invention. The figure which shows the control signal level input into the gate of the control Nch MOS transistor which concerns on Example 1 of this invention. FIG. 6 is a circuit diagram showing a semiconductor integrated circuit according to Embodiment 2 of the present invention. The figure which shows the control signal level input into the gate of the control Nch MOS transistor which concerns on Example 2 of this invention. FIG. 6 is a circuit diagram showing a semiconductor integrated circuit according to Embodiment 3 of the present invention. The figure which shows the control signal level input into the gate of the control Pch MOS transistor which concerns on Example 3 of this invention. Circuit diagram showing a comparator according to Embodiment 4 of the present invention. 10 is an operation flowchart showing a layout design method for a semiconductor integrated circuit according to a fifth embodiment of the present invention. FIG. 10 is a circuit diagram showing a normal operation NAND gate cell according to Embodiment 5 of the present invention; FIG. 9 is a circuit diagram showing a high-speed NAND gate cell according to a fifth embodiment of the present invention. FIG. 9 is a circuit diagram showing a semiconductor integrated circuit according to a fifth embodiment of the present invention.

Explanation of symbols

1, 1a, 1b, 1c Semiconductor integrated circuit 2, 2a, 2b, 2c NAND gate 4 Comparator 5 Flip-flop 7a Replacement region for high-speed gate cell (first time)
7b Replacement area for high-speed gate cells (second time)
DESCRIPTION OF SYMBOLS 11, 11a First stage part 10, 10a NAND gate part 11 High speed NAND gate part 12 Low power consumption NAND gate part 13 Amplification part A1, A2, A3, A4, B1, B2, B3, B4 Input signal GS1, GS2, GS3, GS4 Control signal INVC1 Normal operation inverter cell INVC2 High speed inverter cells N1, N2, N11, N12, N21, N22, N31, N32, N41, N42 Nch MOS transistor NANDC1 Normal operation NAND gate cell NANDC2 Normal operation NOR gate cell NORC2 High speed NOR gate cells NS1, NS3, NS11, NS21 Nch MOS transistors for control Out1, Out1a, Out2, Out3, Out4 Output signals P1, P2, P11, P12, P21 P22, P31, P32, P41, P42 Pch MOS transistor PS31 control Pch MOS transistor Vdd high-potential-side power supply Vin input voltage Vref reference potential Vss low potential side power supply

Claims (5)

A logic circuit connected to the high potential side power supply;
Provided between the logic circuit and the low-potential side power supply, has a threshold voltage, stops the operation of the logic circuit by a control signal voltage larger than the absolute value of the threshold voltage input when turned off, and inputs when turned on And a control transistor for operating the logic circuit by the control signal voltage. A first logic circuit connected to a high-potential-side power supply and including a plurality of Nch MOS transistors and Pch MOS transistors each having an absolute value of a first threshold voltage;
A first control signal voltage that is provided between the first logic circuit and the low-potential-side power supply, has the first threshold voltage, and is larger than the absolute value of the first threshold voltage that is input when turned off. To stop the operation of the first logic circuit, and to operate the first logic circuit by the first control signal voltage input when turned on,
A second logic circuit connected to a high-potential side power supply and including a plurality of Nch MOS transistors and Pch MOS transistors each having an absolute value of a second threshold voltage larger than the absolute value of the first threshold voltage;
A second control signal that is provided between the second logic circuit and the low-potential-side power supply, has the second threshold voltage, and is different from the first control signal, and is input when turned off. The second control Nch MOS transistor which stops the operation of the second logic circuit by the second control signal voltage and operates the second logic circuit by the second control signal voltage inputted at the time of ON. A semiconductor integrated circuit comprising: A logic circuit connected to the low potential side power supply;
Provided between the logic circuit and the negative high-potential side power supply, has a threshold voltage, and stops the operation of the logic circuit by a control signal voltage larger than the absolute value of the threshold voltage input when turned off. A semiconductor integrated circuit, comprising: a control transistor that operates the logic circuit by the control signal voltage that is sometimes input. An amplifier connected to the high-potential side power supply;
Provided between the amplifying unit and the low-potential side power supply, has a threshold voltage, stops the operation of the amplifying unit by a control signal voltage larger than the absolute value of the threshold voltage input when turned off, and inputs when turned on And a control transistor for operating the amplifier by the control signal voltage. A step of performing layout according to a floor plan with reference to element information, circuit connection information, process information, layout information,
Arranging normal operation cells in accordance with the layout information;
A first operation speed determination is made as to whether or not the arranged normal operation cell satisfies the high-speed operation specification. If the normal operation cell is not acceptable, the normal operation cell has a threshold voltage, and is based on an absolute value of the threshold voltage input when turned off. And a control transistor for stopping the operation of the logic circuit by a large control signal voltage and operating the logic circuit by the control signal voltage inputted at the time of ON, having the same occupied area as the normal operation cell and having the same shape Replacing a fast cell with a transistor;
Wiring the signal / power wiring along the layout information; and
The normal operation cell arranged in wiring performs a second operation speed determination as to whether or not the high-speed operation specification is satisfied. If the normal operation cell is not allowable, the normal operation cell has the threshold voltage and is input when the threshold voltage is off. The control transistor for stopping the operation of the logic circuit by a control signal voltage larger than an absolute value and for operating the logic circuit by the control signal voltage inputted at the time of ON is provided with the same occupied area as the normal operation cell. And a layout design method for a semiconductor integrated circuit, comprising: replacing the high-speed cell having a transistor with the same shape, and arranging a signal wiring in the high-speed cell.

Images