JP2006080610A - Parity time difference transmitting system, transmitter and receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten an accumulating time required for realizing a correct reception rate of desired accumulation data. <P>SOLUTION: The transmitter has a coding means for coding packet data, a parity extracting means for extracting a parity from coded data to be acquired by the coding means, and a first time adjusting means for transmitting the parity to be acquired by the parity extracting means and main data corresponding to the party section so that the sections may have a time difference. The receiver has a separating means for separating the main data and the party from the received transmission packet, a second time adjusting means for eliminating the time difference adjusted by the first time adjusting means for the main data and the parity which are acquired by the separating means, and a re-multiplexing means for re-multiplexing the packet data of the main data and the parity which are acquired by the second time adjusting means. With this configuration, the above problem is solved. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a parity time difference transmission system, a transmission device, and a reception device, and in particular, a parity time difference transmission system, a transmission device, and a transmission time for shortening an accumulation time necessary to achieve a desired positive data reception rate. The present invention relates to a receiving device.

  Conventionally, as a rain attenuation compensation technique in satellite broadcasting, a non-real-time transmission method using stored reception has been studied (for example, see Non-Patent Document 1).

  In Non-Patent Document 1, since heavy rainfall tends to occur intensively in a short time, a partial continuous error caused by concentration of the rain occurring in a short time is sufficiently more than the occurrence time of the rain. It describes a long-period interleave transmission system that spreads over a long time and restores the original signal by error correction processing. Here, a system configuration example of the above-described long-period interleave transmission scheme will be described with reference to the drawings.

  FIG. 1 is an example of a schematic configuration of a conventional long-period interleave transmission system. A long-period interleave transmission system 10 shown in FIG. 1 is configured to include a transmission device 11 and a reception device 12, and radio waves output from the transmission device 11 are received by a satellite propagation path via a broadcasting satellite 13. Transmitted to the device 12.

  The transmission apparatus 11 is configured to include a long-period interleaver 21, a first RS encoding unit 22, a second RS encoding unit 23, a modulation unit 24, and a transmission antenna 25. In addition, the reception device 12 is configured to include a reception antenna 26, a demodulation unit 27, a first RS decoding unit 28, a long period deinterleaver 29, and a second RS decoding unit 30.

  Note that the long-cycle interleaver 21 and the long-cycle deinterleaver 29 shown in FIG. 1 have a memory, a hard disk, and the like as data storage means for writing and reading data.

  First, in the transmission apparatus 11, when packet data is input to the long cycle interleaver 21, the long cycle interleaver 21 writes data for a preset time. Further, the long cycle interleaver 21 reads the accumulated data in a direction different from the writing direction, and outputs the data to the first RS encoding unit 22. The first RS encoder 22 performs RS (Reed Solomon) encoding by adding a parity for correcting a missing data portion caused by rain attenuation during transmission on the reception side.

  Next, the first RS encoding unit 22 outputs the RS-encoded transmission packet to the long-period interleaver 21. The long-period interleaver 21 performs writing for a preset interleaving time with respect to the transmission packet input from the first RS encoding unit 22. Further, the long cycle interleaver 21 reads the accumulated data in a direction different from the writing direction, and outputs the data to the second RS encoding unit 23.

  The 2nd RS encoding part 23 performs RS encoding for making the missing part generated by rain attenuation etc. during transmission disappear on the receiving side. In addition, the second RS encoding unit 23 outputs the encoded transmission packet to the modulation unit 24. The modulation unit 24 modulates the input transmission packet by a method suitable for an application that modulates the transmission packet, a satellite transmission path, or the like, and causes the transmission antenna 25 to transmit, for example, as a radio wave having a predetermined carrier frequency.

  Here, the data relayed by the broadcasting satellite 13 is transmitted to the receiving device 12 under the influence of radio wave attenuation when there is heavy rainfall or the like in the middle of the transmission path. In the receiving device 12, the radio wave affected by the rain attenuation is received by the receiving antenna 26, and the received data is output to the demodulator 27. The demodulator 27 performs demodulation using a method corresponding to the modulation method of the input transmission packet. Also, frequency conversion is performed up to the input frequency of the demodulator. Further, the demodulation unit 27 outputs the demodulated data to the first RS decoding unit 28.

  The first RS decoding unit 28 performs error detection on the input data, and performs RS decoding or disappearance based on the detected result. Specifically, error detection is performed on the input data, and if the number of errors exceeds the number that can be corrected, RS decoding is not performed and erasure is performed on a packet basis.

  In addition, data that is not lost in the first RS decoding unit 28 is decoded and output to the long-period deinterleaver 29. The long-period deinterleaver 29 writes the input data for a preset interleave time, and rearranges it with the same frame configuration as that on the transmission side. Further, the long cycle deinterleaver 29 reads the accumulated data in a direction different from the writing direction, and outputs it to the second RS decoding unit 30.

  The second RS decoding unit 30 performs error correction (erasure correction) on the input data. In addition, the second RS decoding unit 30 outputs the decoded data to the long-period deinterleaver 29.

  The long cycle deinterleaver 29 writes the data input from the second RS decoding unit 30 for a predetermined time. The long cycle deinterleaver 29 outputs (reproduces) the accumulated data as read packet data in a direction different from the writing direction.

  Next, an accumulation frame generated by the transmission apparatus 11 shown in FIG. 1 will be described with reference to the drawings. FIG. 2 is a diagram illustrating an example of an accumulation frame configured by the transmission apparatus in FIG. FIG. 2 shows an accumulated frame after being encoded by the second RS encoder 23.

  As shown in FIG. 2, the transmission packet of RS code length k bytes × Fn in the X-axis direction and the transmission packet of RS code length K bytes in the Y-axis direction are arranged. It can also be said that the accumulated frames are obtained by multiplexing Fn small accumulated frames of k × K bytes, and the RS code length k bytes and the RS code length K are in a product code relationship. On the receiving device side, data loss can be performed with n bytes and erasure correction can be performed with N bytes based on the frame data. M and m indicate the information block length in the RS code.

With the system configuration shown in FIG. 1, the first RS encoding unit 22 and the second RS encoding unit 23 are used to transmit a product code that is a combination of a plurality of codes, and the first RS decoding unit 28 and the second RS The error correction capability can be improved by using the decoding unit 30, and the error data distributed by the long-period interleaver 21 and the long-period deinterleaver 29 can be restored to the original signal.
Yamazaki Saki, Ryota Hashimoto, Masaru Kamei, Takao Murata, Toshihiro Nomoto “Transmission method for rain attenuation compensation, long-period interleaved transmission method”, NHK STRL R & D, no. 85 (May 2004), pp42-49.

  By the way, in the conventional long-period interleave transmission system, the main data portion (M × L region in FIG. 2) and the parity portion (N × L in FIG. 2) corresponding to the main data portion shown in FIG. Area) is transmitted in the same frame.

  However, when heavy rain occurs in a concentrated manner, both the main data portion and the parity portion may be affected by rain attenuation and the like, and may not fully perform error correction capability.

  In such a case, it is necessary to increase the parity length corresponding to the number of missing bytes of data or to further increase the data storage time so that the reception rate does not deteriorate.

  The present invention has been made in view of the above-described problems, and achieves a desired data positive reception rate without increasing the amount of parity and increasing the storage time required in the long-period interleave transmission system. It is an object of the present invention to provide a parity time difference transmission system, a transmission apparatus, and a reception apparatus for shortening the accumulation time required for the transmission.

  In order to solve the above problems, the present invention employs means for solving the problems having the following characteristics.

  According to the first aspect of the present invention, a parity time-difference transmission comprising: a transmitting device that transmits a time difference between a main data portion and a parity portion of encoded packet data; and a receiving device that receives a transmission packet from the transmitting device. In the transmission system, the transmission device includes: an encoding unit that encodes packet data; a parity extraction unit that extracts a parity part from encoded data obtained by the encoding unit; and a parity unit obtained by the parity extraction unit And a first time adjusting means for time-sequentially transmitting the main data portion corresponding to the parity portion, and the receiving device separates the main data portion and the parity portion from the received transmission packet. And the main data part and the parity part obtained by the separating means are adjusted by the first time adjusting means. A second time adjusting means for eliminating the time difference, and having a re-multiplexing means for re-multiplexing the packet data of the main data portion and a parity portion obtained by the second time adjusting means.

  According to the first aspect of the present invention, the storage required to achieve the correct reception rate of desired data without increasing the amount of parity and increasing the storage time required in the long-period interleave transmission system. Time can be shortened.

  The invention described in claim 2 is obtained by encoding means for encoding packet data, and the encoding means, in a transmission apparatus for transmitting a time difference between a main data portion and a parity portion of encoded packet data. Parity extraction means for extracting a parity part from encoded data, and first time adjustment means for time-sequentially transmitting the parity part obtained by the parity extraction means and the main data part corresponding to the parity part It is characterized by.

  According to the second aspect of the present invention, the accumulation required to achieve the desired normal data reception rate without increasing the parity amount and increasing the accumulation time required in the long-period interleave transmission system. Time can be shortened.

  The invention described in claim 3 is characterized in that the first time adjustment means adds adjustment time information adjusted for time difference transmission to a header portion of a transmission packet.

  According to invention of Claim 3, adjustment time information can be efficiently transmitted to the receiving side. On the receiving side, the time difference between the main data portion and the parity portion can be accurately adjusted by acquiring the adjustment time information.

  According to a fourth aspect of the present invention, there is provided a receiving apparatus for receiving a transmission packet in which a main data part and a parity part are time-transmitted and outputting the packet as packet data, wherein the main data part and the parity part are received from the received transmission packet. Second time for adjusting time based on adjustment time information obtained from the transmission packet or preset time information, with respect to separation means for separating data, and the main data part and the parity part obtained by the separation means It has time adjustment means and remultiplexing means for remultiplexing packet data of the main data part and parity part obtained by the second time adjustment means.

  According to the fourth aspect of the present invention, the storage required to achieve the correct reception rate of desired data without increasing the amount of parity and increasing the storage time required in the long-period interleave transmission system. Time can be shortened.

  According to a fifth aspect of the present invention, there is provided first decoding means for detecting an error in packet data of the main data portion and performing decoding or erasure in units of packets based on the detection result, and packet data of the parity portion A second decoding means for decoding or erasing in units of packets based on the detection result, and a third error correcting for lost packets from the packet data obtained by the remultiplexing means And decryption means.

  According to the fifth aspect of the present invention, the first decoding means and the second decoding means perform error position detection, and the third decoding is performed by deleting the corresponding packet unit based on the detection result. Since the conversion means can easily specify the error detection position and only need to perform erasure correction, the error correction capability can be improved.

  According to a sixth aspect of the present invention, when the first decoding unit and the second decoding unit detect an error in the input transmission packet and the number of errors exceeds a correctable number In this case, the packet is erased in units of packets without being decoded.

  According to the sixth aspect of the invention, the decoding time can be shortened by omitting the time for the detection process.

  According to the present invention, it is possible to shorten the accumulation time required to achieve a desired normal data reception rate.

<Outline of the present invention>
In the present invention, parity transmission time difference transmission (PTD: Parity-Symbols Time Differential) is performed by providing a parity transmission interval control buffer means for time difference transmission of a main data part and a parity part corresponding to the main data part on the transmission side Do. In addition, the time adjustment buffer means for adjusting the time difference generated on the transmission side is provided on the reception side, and the main data part and the parity part corresponding to the main data part are re-multiplexed, so that the existing configuration is obtained. Accumulation time can be reduced without significant changes.

<Embodiment>
Hereinafter, preferred embodiments of a parity time difference transmission system, a transmission apparatus, and a reception apparatus according to the present invention having the above-described features will be described in detail with reference to the drawings. In addition, although the example which transmits MPEG (Moving Picture Experts Group) packet data as an example of the data transmitted in embodiment shown below is shown, the packet data applicable in this invention are not this limitation.

<System configuration>
FIG. 3 is an example of a schematic configuration of a parity time difference transmission system according to the present invention. The parity time difference transmission system 40 shown in FIG. 3 is configured to include a transmission device 41 and a reception device 42, and radio waves output from the transmission device 41 are received by a satellite propagation path via a broadcasting satellite 43. 42.

  The transmission device 41 is configured to include a main data processing unit 51, a parity processing unit 52, a multiplexing unit 53, a modulation unit 54, and a transmission antenna 55. In addition, the reception device 42 includes a reception antenna 56, a demodulation unit 57, a demultiplexing unit 58, a main data processing unit 59, a parity processing unit 60, a remultiplexing unit 61, a storage unit 62, and a third RS. A decoding unit 63.

  Further, the main data processing unit 51 in the transmission device 41 is configured to include first RS encoding means 71 and time adjustment buffer means 72. In addition, the parity processing unit 52 in the transmission device 41 includes a data storage unit 73, a second RS encoding unit 74, a parity extraction unit 75, a parity storage unit 76, a third RS encoding unit 77, and a parity transmission interval control. Buffer means (first time adjusting means) 78.

  The main data processing unit 59 in the receiving device 42 is configured to include a time adjustment buffer means (second time adjustment means) 79 and a first RS decoding means 80. Further, the parity processing unit 60 in the receiving device 42 is configured to include second RS decoding means 81.

  First, the MPEG packet is input to the main data processing unit 51 and the parity processing unit 52. In the main data processing unit 51, the first RS encoding means 71 performs RS encoding of the input MPEG packet in order to correct or eliminate the missing portion of data caused by rain attenuation or the like during transmission on the receiving side. Further, the first RS encoding means 71 outputs the RS encoded data to the time adjustment buffer means 72.

  The time adjustment buffer means 72 adjusts the time difference in processing that occurs between the main data processing unit 51 and the parity processing unit 52. Specifically, since the processing in the parity processing unit 52 requires more processing time, the output is delayed by a buffer unit composed of a FIFO (First In First Out). The time adjustment buffer means 72 outputs the delayed data to the multiplexing unit 53.

  On the other hand, in the parity processing unit 52, the data storage unit 73 temporarily writes the input MPEG packet data, then reads it in a direction different from the writing direction, and outputs it to the second RS encoding means 74. The second RS encoding means 74 performs RS encoding of the data read from the data storage unit 73 in order to correct or eliminate the missing portion of data caused by rain attenuation or the like during transmission on the reception side. The second RS encoding means 74 outputs the RS encoded data to the parity extraction means 75.

  The parity extraction means 75 extracts only the parity code part of the RS code. In addition, the parity extraction means 75 inputs the extracted parity data to the parity accumulation means 76 and writes only the parity portion in the accumulation frame.

  The parity accumulating unit 76 reads the accumulated data in a direction different from the writing direction and outputs it to the third RS encoding unit 77. The third RS encoding means 77 performs RS encoding in order to correct or eliminate the missing portion of data caused by rain attenuation or the like during transmission on the receiving side. The third RS encoding means 77 outputs the RS-encoded data to the parity transmission interval control buffer means 78.

  Since the parity transmission interval control buffer means 78 performs time difference transmission between the main data portion and the parity portion, the parity portion data is sent for a predetermined time (for example, 30 minutes or 1 hour) than the data of the corresponding main data portion. Etc.) Delay. The parity transmission interval control buffer means 78 outputs the encoded parity part data to the multiplexing part 53 after being delayed by a predetermined time. The parity transmission interval control buffer means 78 adds the delayed time information (adjusted time information) to the header portion of the transmission packet. Here, the transmission packet to which the delayed time information is added may be transmitted separately from the transmission packet of the main data portion and the parity portion. For example, the delayed time information is transmitted by TMCC (Transmission & Multiplexing Configuration Control). Or the like can be transmitted.

  Thereby, adjustment time information can be efficiently transmitted to the receiving side. On the receiving side, the time difference between the main data portion and the parity portion can be accurately adjusted by acquiring the adjustment time information.

  The multiplexing unit 53 performs TS (Transport Stream) multiplexing of the transmission packet input from the main data processing unit 51 and the transmission packet input from the parity processing unit 52. Further, the multiplexing unit 53 outputs the TS multiplexed data to the modulation unit 54.

  The modulator 54 modulates the input data by a method suitable for the application and the satellite transmission path. The modulation method in the modulation unit 54 includes, for example, phase modulation, but is not limited to this. Further, the modulation unit 54 outputs the modulated data to the transmission antenna 55. The transmission antenna unit 55 transmits data as a radio wave having a predetermined carrier frequency.

  Here, the data relayed by the broadcasting satellite 43 is transmitted to the receiving device 42 under the influence of radio wave attenuation when there is heavy rainfall or the like in the middle of the transmission path.

  In the reception device 42, the reception antenna 56 receives the radio wave affected by the rain attenuation, and outputs the received data to the demodulation unit 57. The demodulator 57 performs demodulation by a method corresponding to the modulation method of the input transmission packet, and performs frequency conversion up to the input frequency. The demodulator 57 outputs the demodulated data to the demultiplexer 58. The demultiplexer 58 separates the packet data of the main data portion and the packet data of the parity portion, outputs the packet data of the main data portion to the main data processing portion 59, and sends the packet data of the parity portion to the packet processing portion 60. Output.

  The time adjustment buffer means 79 in the main data processing unit 59 adjusts the time when the transmission device 41 transmits the time difference. That is, the output of the main data portion is delayed by the same time as the parity transmission interval control buffer means 78. The time to be adjusted is adjusted based on adjustment time information obtained from the transmission packet or preset time information. The time adjustment buffer means 79 outputs the delayed main data to the first RS decoding means 80.

  The first RS decoding means 80 performs error detection on the input main data, and performs RS decoding or data loss on a packet basis based on the detected result. Specifically, error detection is performed on the input main data, and when the number of errors exceeds a predetermined number, data is lost in units of packets without performing RS decoding. The lost packet portion is set to an initial value such as NULL. Also, the first RS decoding means 80 performs RS decoding when the number of errors is equal to or less than a predetermined number, and outputs the decoded data to the remultiplexing unit 61.

  On the other hand, the 2nd RS decoding means 81 in the parity process part 60 performs error detection about the data of a parity part, and performs the RS decoding or the loss | disappearance of the data per packet based on the detected result. Specifically, error detection is performed on the input parity data in the same manner as the first RS encoding unit 80 described above, and data is lost in packet units without performing RS decoding when the number of errors exceeds a predetermined number. Turn into. The lost packet portion is set to an initial value such as NULL. Further, the second RS decoding means 81 performs RS decoding for data having a predetermined number of errors or less, and outputs the decoded data to the remultiplexing unit 61.

  The remultiplexing unit 61 multiplexes the main data unit from the main data processing unit 59 and the parity unit from the parity processing unit 60. That is, in the remultiplex unit 61, the multiplexed data is configured as an accumulation frame in which the main data unit and the parity unit correspond.

  The remultiplexing unit 61 outputs the remultiplexed data to the storage unit 62. The storage unit 62 writes all data portions in the input storage frame. In addition, the storage unit 62 reads the written data in a direction different from the writing direction, and outputs the data to the third RS decoding unit 63.

  The third RS decoding unit 63 performs error correction of the input data (in the case of a lost packet, erasure correction). In addition, the third RS decoding unit 63 outputs the decoded data to the storage unit 62. The accumulating unit 62 writes the data input from the third RS decoding unit 63, reads in the direction opposite to the writing direction, and outputs packet data.

  As described above, by transmitting the main data portion and the parity portion in a time difference manner, it is possible to avoid the loss of both the main data portion and the parity portion corresponding to the main data due to rain attenuation or the like. As a result, it is possible to shorten the storage time required to achieve the desired correct data reception rate without increasing the amount of parity and increasing the storage time required in the long-period interleave transmission method. .

<Transmission device functional configuration>
Next, a specific functional configuration example of the transmission device 41 in the present embodiment will be described with reference to the drawings. FIG. 4 is a diagram illustrating an example of a functional configuration of the transmission apparatus according to the present embodiment. FIG. 4 shows a functional configuration of the main data processing unit and the parity processing unit according to the present invention.

  The transmission apparatus 41 shown in FIG. 4 is configured to include a first m-FIFO means 101, a first RS encoding means 102, and a time adjustment FIFO means 103 as the main data processing unit 51. Further, as the parity processing unit 52, a first main data switching unit 104, a first main data storage unit 105, a second main data storage unit 106, a main data control unit 107, and a second main data switching unit 108 are provided. , M-FIFO means 109, second RS encoding means 110, parity extraction means 111, byte clock counter 112, first parity switching means 113, first parity accumulation means 114, and second parity accumulation means 115. A parity control unit 116, a second parity switching unit 117, a second m-FIFO unit 118, a third RS encoding unit 119, and a parity transmission interval control FIFO unit 120. Further, the transmission device 41 is configured to include multiplexing means 121.

  In FIG. 4, first, an MPEG packet is input to the main data processing unit 51 and the parity processing unit 52. In the main data processing unit 51, the first m-FIFO means 101 inputs and outputs data in units of m bytes. Note that m is an information block length of data to be transmitted. Also, the first RS encoding means 102 performs RS encoding in units of m bytes, and outputs it to the time adjustment FIFO means 103 as a transmission packet. The time adjustment FIFO unit 103 delays a predetermined time in order to adjust the processing time in the parity processing unit 52.

  The time adjustment FIFO unit 103 can accurately adjust the time interval between the main data portion and the parity portion by receiving the voltage High which is a control signal from the parity transmission interval control FIFO unit 120. Further, the time adjustment FIFO unit 103 outputs the transmission packet after the time adjustment to the multiplexing unit 121.

  Next, the parity processing unit 52 will be described. In FIG. 4, the first main data switching means 104, the first main data storage means 105, the second main data storage means 106, the main data control means 107, and the second main data switching means 108 are the same as those shown in FIG. The data storage means 73 shown in FIG. Further, the first parity switching unit 113, the first parity storage unit 114, the second parity storage unit 115, the parity control unit 116, and the second parity switching unit 117 are added to the parity storage unit 76 shown in FIG. This is a function provided.

  The first main data storage means 105 and the second main data storage means 106 have the same data writing speed, reading speed, and storage capacity, and the first parity storage means 114 and the second parity storage means 115 indicates that the writing speed, the reading speed, and the storage capacity are all the same.

  The first main data storage unit 105 and the second main data storage unit 106 output the voltage High, which is a control signal, to the main data control unit 107 when the writing for a predetermined time is completed. Further, the first parity storage unit 114 and the second parity storage unit 115 output the voltage High, which is a control signal, to the parity control unit 116 at the time when the writing of the parity data is completed.

  As described above, the reason why the first main data storage means 105 and the second main data storage means 106 and the first parity storage means 114 and the second parity storage means 115 are paired is that the double buffer configuration is used. This is to prevent data stagnation by alternately repeating the writing and reading timings. Note that the number of main data storage means and parity storage means is not limited to two, but may be plural.

  When the first main data switching unit 104 and the first parity switching unit 113 receive the voltage High of the control signal from the main data control unit 107, the first main data switching unit 104 and the first parity switching unit 113 output the input data to the Side 1 shown in FIG. When the voltage Low of the control signal is received, it plays a role of a switch that outputs input data to Side 2 shown in FIG.

  On the other hand, when the second main data switching means 108 and the second parity switching means 117 receive the voltage High of the control signal from the main data control means 107 and the parity control means 116, respectively, the data from the Side 2 shown in FIG. When the voltage Low of the control signal is received by switching, it plays the role of a switch that switches and outputs the data from Side 1 shown in FIG.

  Further, the main data control means 107 controls operations in the first main data storage means 105, the second main data storage means 106, the first main data switching means 104, and the second main data switching means 108. Specifically, every time the control signal voltage High from the first main data storage unit 105 or the second main data storage unit 106 is received, the voltage High or Low of the same control signal is switched and output to each unit.

  Similarly, the parity control unit 116 controls operations in the first parity storage unit 114, the second parity storage unit 115, the first parity switching unit 113, and the second parity switching unit 117. Specifically, every time the control signal voltage High from the first parity storage unit 114 or the second parity storage unit 115 is received, the voltage High or Low of the same control signal is switched and output to each unit.

  The M-FIFO unit 109 inputs and outputs data in units of M bytes. The parity extraction unit 111 extracts a predetermined byte portion based on a control signal from the byte clock counter unit 112.

  The second m-FIFO unit 118 inputs and outputs data in units of m bytes. Further, the parity transmission interval control FIFO unit 120 outputs a control signal for adjusting a processing time difference between the main data processing unit 51 and the parity processing unit 52 to the time adjustment FIFO unit 103. As described above, the multiplexing unit 53 performs TS multiplexing of the main data and the parity having a time difference, and outputs the result to the modulation unit.

  The first m-FIFO unit 101, the M-FIFO unit 109, and the second m-FIFO unit 118 described above are assumed to have a FIFO unit of about several hundred bytes, and each corresponds to an information block length.

<Details of data processing on the sending side>
Next, specific data processing contents on the transmission side in FIG. 4 will be described. In the main data processing unit 51, the MPEG packet is input to the first m-FIFO unit 101, data is input and output in units of m bytes, and the MPEG packet is output to the first RS encoding unit 102 in units of m bytes. The first RS encoding means 102 generates an RS code having an information block length m, a check block length n, and a code block length k. Thereafter, the first RS encoding unit 102 outputs the encoded transmission packet data to the time adjustment FIFO unit 103.

  The time adjustment FIFO unit 103 accumulates data until the voltage High which is a control signal from the parity transmission interval control FIFO unit 120 is received. In FIG. 4, the voltage High is used for the sake of convenience. However, the present invention is not limited to this. For example, the voltage Low may be used, or another control signal may be set.

  After receiving the control signal voltage High from the parity transmission interval control FIFO unit 120, the time adjustment FIFO unit 103 outputs the accumulated data to the multiplexing unit 121 in order from the top.

  On the other hand, in the parity processing unit 52, the first main data switching unit 104 that has received the control signal from the main data control unit 107 selects Side1 as the data transmission destination of the input MPEG data, and the first main data storage unit 105 Output an MPEG packet.

  Here, the data writing order and reading order in the first main data storage means 105 and the second main data storage means 106 will be described with reference to the drawings. FIG. 5 is a diagram illustrating an example of the MPEG packet writing order and reading order.

  In the MPEG packet input to the first main data storage unit 105 and the second main data storage unit 106, the main data portion (M × L (byte)) in the storage frame is written in the order of the arrow 131 shown in FIG. . Note that L indicates a packet string. In FIG. 5, the packet length (information block length) is m bytes × Fn (= L) transmission packets in the X-axis direction.

  The first main data accumulating unit 105 and the second main data accumulating unit 106 output the voltage High of the control signal to the main data control unit 107 after the completion of the writing of M × L bytes. It waits until the voltage Low which is the control signal is received. Next, the first main data storage unit 105 and the second main data storage unit 106 read the MPEG packet in the order of the arrow 132 after receiving the voltage Low which is a control signal from the main data control unit 107.

  The first main data storage unit 105 outputs the MPEG packet to the second main data switching unit 108 after receiving the voltage Low which is a control signal from the main data control unit 107. The second main data switching unit 108 outputs the input MPEG packet to the M-FIFO unit 109. The M-FIFO unit 109 inputs and outputs the input data in units of M bytes, and outputs an M-byte MPEG packet to the second RS encoding unit 110.

  The second RS encoding means 110 calculates the check block length N from the information block length M, obtains the code block length K, and performs encoding. The second RS encoding means 110 outputs the transmission packet after RS encoding to the parity extraction means 111.

  The parity extraction unit 111 outputs data only during a period in which the voltage High that is a control signal from the byte clock counter 112 is received. Specifically, the byte clock counter 112 outputs the voltage High of the control signal during the byte count period from M + 1 byte to K bytes, and the counter is reset to 1 when it is counted up to K bytes. Thereby, only the parity part excluding the main data part can be extracted from the input transmission packet.

  The parity extraction unit 111 outputs the output data to the first parity switching unit 113. The first parity switching unit 113 receives the control signal voltage High from the parity control unit 116 and then outputs the transmission packet to the first parity storage unit 114 of Side1. Here, the data writing order and reading order in the first parity storage means 114 and the second parity storage means 115 will be described with reference to the drawings.

  FIG. 6 is a diagram illustrating an example of a data write order and a read order in the first parity storage unit and the second parity storage unit. FIG. 6 shows a frame configuration example of transmission packets stored in the first parity storage unit 114 and the second parity storage unit 115. As shown in FIG. 6, in the first parity storage unit 114 and the second parity storage unit 115, the parity portion (N × L bytes) of the storage frame in FIG. 6 is written in the order of the arrow 133.

  The first parity storage unit 114 and the second parity storage unit 115 output the control signal voltage High to the parity control unit 116 after the writing of N × L bytes shown in FIG. The first parity storage unit 114 and the second parity storage unit 115 receive the control signal voltage Low from the parity control unit 116, and then read the data in the order of the arrow 134 shown in FIG. It outputs to 117. The second parity switching unit 117 outputs the input transmission packet of the parity part to the second m-FIFO unit 118.

  The second m-FIFO means 118 inputs and outputs the transmission packet data in units of m bytes and outputs it to the third RS encoding means 119. The third RS encoding means 119 generates an RS code having an information block length m, a check block n, and a code block length k. Thereafter, the third RS encoding means 119 outputs the RS encoded data to the parity transmission interval control FIFO means 120.

  The parity transmission interval control FIFO means 120 performs time adjustment for time-sequential transmission of the main data portion and the parity portion. Specifically, the transmission packet of the parity part is accumulated for a predetermined time.

  The parity transmission interval control FIFO unit 120 outputs the voltage High as a control signal to the time adjustment FIFO unit 103 in the main data processing unit 51 as long as there is an input from the third RS encoding unit 119. Thereby, a time difference in data processing between the main data processing unit 51 and the parity processing unit 52 can be eliminated.

  Further, the parity transmission interval control FIFO means 120 adds adjustment time information (accumulation time (T)) accumulated for a predetermined time to the header portion of the transmission packet. For example, when the BS digital transmission method is used, it is described in a header part such as TMCC and added and transmitted as additional information. The parity transmission interval control FIFO means 120 outputs to the multiplexing means 121 the transmission packet of the parity part that has been time adjusted for time difference transmission.

  The multiplexing means 121 multiplexes the transmission packet of the main data part and the transmission packet of the parity part generated by the function described above. As described above, since there is a time difference between the transmission packet data of the main data portion and the parity portion at the time of input to the multiplexing means 121, conventional multiplexing, modulation, and transmission functions can be used.

  Thereby, it is possible to avoid the loss of both the main data part and the parity part corresponding to the main data due to rain attenuation or the like by transmitting the main data part and the parity part in a time difference manner. Therefore, it is possible to reduce the storage time required to achieve the desired normal data reception rate without increasing the amount of parity and increasing the storage time required in the long-period interleave transmission method.

  Note that the transmission apparatus 41 described above has described the case where the parity part is transmitted later than the main data part. However, the present invention is not limited to this, and the time difference is set so that the parity part is transmitted earlier than the main data part. May be.

<Receiver functional configuration>
Next, a specific functional configuration example of the receiving device 42 in the present embodiment will be described with reference to the drawings. FIG. 7 is a diagram illustrating an example of a functional configuration of the receiving device according to the present embodiment. Since the functions up to the demodulator in the receiving device 42 are the same as those used in the prior art represented by BS digital broadcasting and the like, FIG. 7 mainly shows the components after demodulation according to the present invention. The function of will be described.

  The receiving apparatus 42 shown in FIG. 7 includes a time adjustment FIFO unit 142, a first k-FIFO unit 143, and a first data erasure unit 144 as the main data processing unit 59. Further, the parity processing unit 60 is configured to include second k-FIFO means 145 and second data erasure means 146. The receiving device 42 also includes a demultiplexing unit 141, a remultiplexing unit 147, a first switching unit 148, a first control unit 149, a first accumulation unit 150, a second accumulation unit 151, and a second Switching means 152, K-FIFO means 153, data loss correction means 154, third switching means 155, second control means 156, third storage means 157, fourth storage means 158, and fourth switching Means 159.

  Here, in FIG. 7, the first switching means 148, the first control means 149, the first storage means 150, the second storage means 151, the second switching means 152, the third switching means 155, The 2 control unit 156, the third storage unit 157, the fourth storage unit 158, and the fourth switching unit 159 are functions provided in the storage unit 62.

  Furthermore, the first storage unit 150, the second storage unit 151, the third storage unit 157, and the fourth storage unit 158 are all assumed to have the same data writing speed, reading speed, and storage capacity. In addition, the first storage unit 150 and the second storage unit 151 output a voltage High that is a control signal to the first control unit 149 when the writing of all the data portions in the frame to be stored is completed. Further, the third storage unit 157 and the fourth storage unit 158 output the voltage High which is a control signal to the second control unit 156 when the writing of the MPEG packet data in the storage frame is completed.

  Further, as shown in FIG. 7, the reason why the first storage unit 150 and the second storage unit 151 are paired with the third storage unit 157 and the fourth storage unit 158 is the same as that of the transmission apparatus described above. This is because a double buffer configuration is used to prevent data stagnation. Note that the data storage means is not limited to two but may be a plurality.

  Further, when the first switching unit 148 and the third switching unit 155 receive the voltage High which is the control signal from the first control unit 149 and the second control unit 156, respectively, the input data is Side1 shown in FIG. When the control signal voltage Low is received, it serves as a switch for outputting the input data to Side 2 shown in FIG.

  On the other hand, the second switching unit 152 and the fourth switching unit 159 switch to the data from Side 2 shown in FIG. 7 when receiving the voltage High which is the control signal from the first control unit 149 and the second control unit 156, respectively. When the voltage Low of the control signal is received, it plays the role of a switch that switches to and outputs the data from Side 1 shown in FIG.

  Further, the first control unit 149 controls operations in the first switching unit 148, the first storage unit 150, the second storage unit 151, and the second switching unit 152. Specifically, every time the control signal voltage High from the first storage unit 150 or the second storage unit 151 is received, the voltage High or Low of the same control signal is switched and output to each unit.

  Similarly, the second control unit 156 controls operations in the third switching unit 155, the third storage unit 157, the fourth storage unit 158, and the fourth switching unit 159. Specifically, every time the control signal voltage High from the third accumulation unit 157 or the fourth accumulation unit 158 is received, the voltage High or Low of the same control signal is switched and output to each unit.

  Further, the first k-FIFO unit 143, the second k-FIFO unit 145, and the K-FIFO unit 153 are assumed to have a FIFO unit of about several hundred bytes, and each correspond to the code length of the RS code. Further, the time adjustment FIFO unit 142 adjusts the parity transmission difference delayed on the transmission side.

<Specific data processing on the receiving side>
Next, specific data processing contents on the receiving side will be described. The demodulated data is input to the demultiplexing means 141 and separated into a transmission packet of the main data part and a transmission packet of the parity part. The demultiplexing unit 141 outputs the separated transmission packet of the main data part to the main data processing unit 59 and outputs the transmission packet of the parity part to the parity processing unit 60.

  In the main data processing unit 59, the time adjustment FIFO unit 142 delays the transmission packet of the main data unit in order to restore the parity transmission time difference generated on the transmission side. That is, the time adjustment FIFO unit 142 delays the output of the input transmission packet of the main data portion by a time difference. Note that the FIFO capacity for absorbing this time difference is calculated from the accumulation time (T) added to the above-described TMCC, the preset accumulation time, the transmission packet rate (R), etc. can do.

  The time adjustment FIFO unit 142 outputs the delayed output data to the first k-FIFO unit 143. The first k-FIFO unit 143 inputs and outputs data in units of k bytes, and outputs the data in units of k bytes to the first data erasure unit 144. The first data erasure means 144 detects an error position for the input transmission packet (RS (k, m) code, n = k−m) of the main data portion.

  For example, when the number of errors exceeds n / 2 bytes, RS decoding is not performed, data for the code length is lost, and data of the packet is not output. However, the writing position to the storage means at this time is counted, and an initial value such as NULL is set in the lost packet portion. When the number of errors is n / 2 bytes or less, error detection and correction are performed.

  Normally, in the RS code, an error is detected after the error is detected, so that an error is detected with n / 2 bytes for the check block n and an error is corrected with the remaining n / 2 bytes. However, if the erasure position is known, erasure correction that restores all n-byte data is possible. If erasure correction can be performed, the number of data can be corrected twice as compared with a normal RS decoding system that simply detects and corrects error positions. The first data erasure unit 144 outputs the decoded transmission packet to the remultiplexing unit 147.

  On the other hand, in the parity processing unit 60, the second k-FIFO unit 145 inputs and outputs data in units of k bytes similarly to the first k-FIFO unit 143, and transmits the transmission packet data of the parity unit in units of k bytes to the second data. Output to the erasure means 146. The second data erasure means 146 detects an error position for the input transmission packet of the parity part.

  Here, as in the first data erasure means 144, when the number of errors exceeds n / 2 bytes, RS decoding is not performed and the data corresponding to the code length is lost so that the data of the packet is not output. To do. However, the writing position to the storage means at this time is counted, and an initial value such as NULL is set in the lost packet portion. When the number of errors is n / 2 bytes or less, error detection and correction are performed. The second data erasure unit 146 outputs the decoded parity data to the remultiplexing unit 147.

  The remultiplexing unit 147 multiplexes the transmission packets obtained from the main data processing unit 59 and the parity processing unit 60. Further, the remultiplexing means 147 outputs the remultiplexed data to the first switching means 148. The first switching unit 148 receives the voltage High which is a control signal from the first control unit 149, for example, and outputs the transmission packet to the first storage unit 150 of Side1.

  Here, the data writing order and reading order in the first storage means 150 and the second storage means 151 will be described with reference to the drawings. FIG. 8 is a diagram illustrating an example of the data writing order and reading order in the first storage means and the second storage means. FIG. 8 shows a frame configuration example of transmission packets stored in the first storage unit 150 and the second storage unit 151. The first accumulation means 150 writes K × L bytes of data for the input transmission packet in the order of the arrow 135 shown in FIG.

  Note that data loss caused by rain attenuation or the like during transmission occurs as lost packets (lost packet) continuously in the X-axis direction as shown in FIG. However, by reading this in the Y-axis direction, that is, in the order of the arrow 136, the data loss for the packet loss is only 1 / L byte, and the data is lost in units of packets, so the error position can be easily identified. Thus, error correction can be performed more effectively than in the conventional method.

  Next, after the writing for the transmission frame is completed, the first accumulation unit 150 transmits the voltage High that is a control signal to the first control unit 149 and the voltage Low that is the control signal from the first control unit 149. Wait for reception.

  Further, after receiving the control voltage Low from the first control unit 149, the first storage unit 150 reads out the transmission packet for K × L bytes according to the order of the arrow 136 shown in FIG. 8 and outputs it to the second switching unit 152. To do.

  Thereafter, the second switching unit 152 outputs the data output from the first storage unit 150 to the K-FIFO unit 153. The K-FIFO unit 153 inputs and outputs data in units of K bytes. The K bytes correspond to the Y-axis direction in FIG. 8, that is, the code length in the RS code.

  The K-FIFO unit 153 outputs K bytes of data to the data loss correction unit 154. The data loss correction unit 154 corrects the loss of input data. That is, only correction processing is performed on data whose erasure position in the code is known. Note that packets that are not stored in the first storage unit 150 are lost. That is, since this erasure position becomes an error position, the error position can be easily specified, and error correction can be performed efficiently.

  The data loss correction unit 154 outputs the MPEG packet after the loss correction to the third switching unit 155. The third switching unit 155 receives the voltage High, which is a control signal from the second control unit 156, and outputs the MPEG packet to the third storage unit 157 of Side1.

  Here, a writing order and a reading order of data stored in the third storage unit 157 and the fourth storage unit 158 will be described with reference to the drawings. FIG. 9 is a diagram illustrating an example of the data writing order and reading order in the third storage means and the fourth storage means. In the third accumulation means 157 and the fourth accumulation means 158, writing for the frame (M × L bytes) shown in FIG.

  The third storage unit 157 outputs a voltage High as a control signal to the second control unit 156 after the writing for M × L bytes is completed. Further, after receiving the voltage Low which is the control signal from the second control unit 156, the third storage unit 157 reads the data in the order of the arrow 138 shown in FIG. 9 and sends the MPEG data to the fourth switching unit 159. Output. The fourth switching unit 159 outputs (reproduces) the MPEG data under the control of the second control unit 156.

  By using this configuration as described above, for example, when a parity time difference transmission (PTD) method is performed using a stored frame generated by a long-period interleave transmission method, and compared with a transmission efficiency equivalent to that of the prior art Therefore, it is possible to shorten the storage time necessary for obtaining the correct reception rate of the desired stored data.

  The above-described receiving apparatus 42 has been described in the case where the transmission time difference of the parity part is slower than that of the main data part. However, the present invention is not limited to this, and the transmission packet of the parity part is transmitted earlier than the main data part. 7, for example, the time adjustment FIFO unit 142 in the main data processing unit 59 in FIG. 7 is provided in the parity processing unit 60 to adjust the time difference, or both the main data processing unit 59 and the parity processing unit have time adjustment FIFOs. Means are provided to adjust the time difference.

<Comparison between conventional and present invention>
Here, the comparison between the conventional method and the transmission method to which the present invention is applied will be described based on the measurement result indicating the relationship between the accumulation time with the transmission efficiency being the same condition (50%) and the normal reception rate of the accumulated data. .

  Here, the period from May 2000 to December 2002 was used as the rain attenuation data, and the long-period interleave transmission system and the parity time difference transmission system were applied to the current 12 GHz band BS digital broadcasting transmission system.

  Further, the transmission parameters for BS digital broadcasting are as follows: satellite EIRP (Equivalent Isotropy Radiated Power) is 59 dBW, modulation method is TC8PSK (Tellis Coded 8 Phase Shift Keying), rainfall margin is 4.8 dB, and modulation rate is 86 dB. The receiving antenna diameter was 45 cm (efficiency: 70%), and the code length in RS encoding was also the same.

  FIG. 10 shows the relationship between the storage time measured based on the above-described conditions and the normal reception rate of stored data. As shown in FIG. 10, when the conventional long-period interleave transmission scheme is compared with the parity time difference transmission scheme of the present invention, the long-period interleave transmission scheme achieves about 4 hours to achieve a positive reception rate of 100%. Whereas time is required, the parity time difference transmission system of the present invention requires only about 3 hours of accumulation time, and the accumulation time can be shortened by about 1 hour.

  As described above, according to the present invention, the accumulation required to achieve the correct reception rate of desired data without increasing the amount of parity and increasing the accumulation time required in the long-period interleave transmission system. Time can be shortened.

  Although the preferred embodiment of the present invention has been described in detail above, the present invention is not limited to the specific embodiment, and various modifications, within the scope of the gist of the present invention described in the claims, It can be changed.

It is a figure of an example which shows schematic structure of the conventional long-period interleave transmission system. It is a figure which shows an example of the accumulation | storage frame comprised with the transmitter in FIG. It is a figure of an example which shows schematic structure of the parity time difference transmission system in this invention. It is a figure which shows an example of a function structure of the transmitter in this embodiment. It is an example for demonstrating the order of writing of MPEG packets, and the order of reading. It is a figure of an example for demonstrating the writing order and reading order of the data in a 1st parity storage means and a 2nd parity storage means. It is a figure which shows an example of a function structure of the receiver in this embodiment. It is a figure of an example for demonstrating the writing order and reading order of the data in a 1st storage means and a 2nd storage means. It is a figure of an example for demonstrating the writing order of data in the 3rd storage means and the 4th storage means, and the reading order. It is a figure which shows the relationship between accumulation | storage time and the normal reception rate of accumulation | storage data.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Long period interleave transmission system 11, 41 Transmitter 12, 42 Receiver 13, 43 Broadcasting satellite 21 Long period interleaver 22 1st RS encoding part 23 2nd RS encoding part 24, 54 Modulation part 25, 55 Transmitting antenna 26, 56 receiving antenna 27, 57 demodulator 28 first RS decoding unit 29 long period deinterleaver 30 second RS decoding unit 40 parity time difference transmission system 51, 59 main data processing unit 52, 60 parity processing unit 53 multiplexing unit 58 multiplexing Separation unit 59 Main data processing unit 61 Remultiplexing unit 62 Storage unit 63 Third RS decoding unit 71, 102 First RS encoding unit 72 Time adjustment buffer unit 73 Data storage unit 74, 110 Second RS encoding unit 75, 111 Parity extraction means 76 Parity storage means 77 Third RS code 78 Parity transmission interval control buffer means 101 1 m-FIFO means 103 Time adjustment FIFO means 104 First main data switching means 105 First main data storage means 106 Second main data storage means 107 Main data control means 108 Second Main data switching means 109 M-FIFO means 112 Byte clock counter 113 First parity switching means 114 First parity storage means 115 Second parity storage means 116 Parity control means 117 Second parity switching means 118 Second m-FIFO means 119 Third RS Encoding means 120 Parity transmission interval control FIFO means 131 to 138 Arrow 141 Demultiplexing means 142 Time adjustment FIFO means 143 First k-FIFO means 144 First data erasure means 145 Second k-FIFO means 146 2 Data loss means 147 Remultiplexing means 148 First switching means 149 First control means 150 First accumulation means 151 Second accumulation means 152 Second switching means 153 K-FIFO means 154 Data loss correction means 155 Third switching means 156 Second control means 157 Third storage means 158 Fourth storage means 159 Fourth switching means

Claims (6)

In a parity time difference transmission transmission system comprising a transmission device that transmits a time difference between a main data portion and a parity portion of encoded packet data, and a reception device that receives a transmission packet from the transmission device,
The transmission apparatus includes: encoding means for encoding packet data; parity extraction means for extracting a parity part from encoded data obtained by the encoding means; a parity part obtained by the parity extraction means; and the parity part A first time adjustment means for transmitting a time difference with a main data portion corresponding to
The receiving device separates a main data part and a parity part from the received transmission packet, and the main data part and the parity part obtained by the separating means by the first time adjusting means. A second time adjusting means for eliminating the adjusted time difference; and a remultiplexing means for remultiplexing packet data of the main data portion and the parity portion obtained by the second time adjusting means. Parity time difference transmission transmission system. In a transmission device that performs time difference transmission of the main data portion and the parity portion of the encoded packet data,
Encoding means for encoding packet data;
Parity extraction means for extracting a parity part from the encoded data obtained by the encoding means;
A transmission apparatus comprising: a first time adjustment unit for transmitting a time difference between a parity part obtained by the parity extraction unit and a main data part corresponding to the parity part. The first time adjusting means includes
The transmission device according to claim 2, wherein adjustment time information adjusted for time difference transmission is added to a header portion of a transmission packet. In the receiving device that receives the transmission packet in which the main data portion and the parity portion are transmitted in a time difference and outputs the packet as packet data,
Separating means for separating a main data portion and a parity portion from the received transmission packet;
Second time adjustment means for adjusting time based on adjustment time information obtained from the transmission packet or preset time information for the main data part and the parity part obtained by the separation means;
Receiving apparatus, comprising: remultiplexing means for remultiplexing packet data of the main data part and the parity part obtained by the second time adjusting means. First decoding means for detecting an error in the packet data of the main data portion and performing decoding or erasure in units of packets based on the detection result;
Second decoding means for detecting an error in the packet data of the parity part and performing decoding or erasure in units of packets based on the detection result;
5. The receiving apparatus according to claim 4, further comprising third decoding means for correcting an error of a packet lost from the packet data obtained by the remultiplexing means. The first decoding means and the second decoding means are:
6. The receiving apparatus according to claim 5, wherein error detection is performed on the input transmission packet, and if the number of errors exceeds a correctable number, the packet is erased in units of packets without being decoded.

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