JP2006074497A - Solid-state image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the occurrence of fixed pattern noise in a dark part with little light irradiation. <P>SOLUTION: A signal output circuit 43 outputs a video signal corresponding to difference between potential VS1 to be generated in a source area and stored in a first line memory 50 when pixels are subjected to light irradiation and potential VS2 to be generated in the source area and stored in a second line memory 52 when the pixels are initialized. The potential VS1 and VS2 is transferred to first and second horizontal signal lines 52 and 53 and inputted to a differential amplifier 54. An arithmetic amplifying means constituted of the differential amplifier 54 outputs the video signal to the horizontal output lines 57 and 58, subsequently makes both the potential of the first and second horizontal signal lines 52 and 53 equal and sets the potential to be a potential to be determined in accordance with potential VS1 and VS2 transferred to the first and second horizontal signal lines 52 and 53 by the time the potential is outputted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device used for a digital camera, a mobile phone with a camera, and the like.

  CCD (Charge Coupled Device) type and MOS (Metal Oxide Silicon) type solid-state imaging devices (image sensors) are excellent in mass production, so they are mass-produced with the advancement of pattern miniaturization technology. Applied to input device devices. In particular, in recent years, MOS-type solid-state imaging devices have been reconsidered that have lower power consumption than CCD-type solid-state imaging devices and have the advantage that an imaging device and peripheral circuits can be created by the same CMOS (Complementary MOS) technology. .

  In view of these trends, various improvements have been made to MOS type solid-state imaging devices, and carrier pockets (holes) for accumulating charge carriers (holes) transferred from the light-receiving diodes under the channel region of the photodetection MOS transistor. A solid-state imaging device having a pocket) is disclosed (for example, see Patent Document 1). This solid-state imaging device includes a light receiving region in which pixels (pixels) each including a light receiving diode and a light signal detection MOS transistor are arranged in a row direction and a column direction, and a peripheral circuit that drives the light receiving region. Video signals are sequentially output while repeating the period → reading period → initialization period. In the accumulation period, charge carriers generated in the light receiving diode by light irradiation are transferred to the carrier pocket. In the readout period, the source potential of the photodetection MOS transistor proportional to the amount of charge of the charge carriers accumulated in the carrier pocket is output to the outside as a video signal. In the initialization period, charge carriers accumulated in the carrier pocket are discharged to the substrate.

  The video signal obtained in this way includes a reference potential (noise potential) unique to the photodetection MOS transistor before charge carrier accumulation. Therefore, a solid-state imaging device capable of removing the noise potential from the video signal is known, and the video signal is sequentially output while repeating the accumulation period → the first readout period → the initialization period → the second readout period. (See Patent Document 2). From the accumulation period to the first reading period to the initialization period, the signal potential VS1 including the noise potential is read in the first reading period. In the second read period after the subsequent initialization period, the noise potential VS2 is read. The potentials VS1 and VS2 are temporarily stored in the first line memory and the second line memory in the signal output circuit, respectively, and the potentials according to the potential difference (VS1-VS2) calculated by the operational amplifier in the signal output circuit are It is output to the outside as a video signal.

  The operation of the signal output circuit of this conventional solid-state imaging device will be briefly described with reference to FIG. The vertical output line 100 is connected to the source region of each pixel arranged in the column direction, and one vertical output line 100 is provided for each column. Immediately after the start of the first readout period after the accumulation period, when the switches S1, S2, and S3 are closed in a state where all the pixels are not selected, the vertical output line 100 and the first line memory 101 are set to a predetermined preset voltage Vmpr. The Subsequently, when pixels arranged in the first row (first horizontal run) are selected and the switch S2 is opened, the first line memory 101 is charged with the potential VS1 via the vertical output line 100. In the subsequent initialization period, the accumulated charge of each pixel in the selected first row is discharged to the substrate with the switches S1, S2, S3, particularly S1, being opened, and initialization is performed. Immediately after the start of the second readout period after the initialization period, the switches S1, S2 and S5 are closed with all the pixels not selected, and the vertical output line 100 and the second line memory 102 are set to a predetermined preset voltage Vmpr. The When the pixels arranged in the first row are selected and the switch S2 is opened, the second line memory 102 is charged with the noise potential VS2 through the vertical output line 100.

  The operations of the first readout period, the initialization period, and the second readout period are performed within one horizontal blanking period, and the signal potential VS1 and the noise potential VS2 of the pixels connected to one horizontal line are The data is accumulated in the first line memory 101 and the second line memory 102 in the column, and is scanned in the horizontal direction and read out in the subsequent accumulation period.

  In this accumulation period, the switches S3 and S5 are opened, and the switches S4 and S6 are driven by the horizontal scanning signal supply line 103 drawn from the horizontal scanning circuit. When the switches S4 and S6 are closed, the potentials VS1 and VS2 stored in the first and second line memories 101 and 102 are transmitted to the first and second horizontal signal lines 104 and 105, respectively. The first and second horizontal signal lines 104 and 105 are connected to the negative input terminal and the positive input terminal of the differential amplifier 106, respectively, and charges corresponding to the potentials VS1 and VS2 are supplied to the first and second feedback capacitors 107, 105, respectively. 108, respectively. At this time, the switches RSTs and RSTn are opened.

  The differential amplifier 106 includes a common mode feedback (CMF) circuit, and the output potentials VoutP and VoutM are level-shifted by the input CMF potential Vcm. That is, the output potentials VoutP and VoutM always satisfy the relationship Vcm = (VoutP + VoutM) / 2. The potentials VoutP and VoutM are input to the negative input terminal and the positive input terminal of the differential amplifier 109, respectively, and an image corresponding to the potential difference (VoutP−VoutM) is applied to the horizontal output line 110 connected to the output terminal of the differential amplifier 109. A signal is output. After the video signal is output, the switches RSTs and RSTn and the switch S7 are closed, the feedback capacitors 107 and 108 of the differential amplifier 106 are reset, and the first and second horizontal signal lines 104 and 105 are short-circuited. . As a result, the CMF potential Vcm is fed back to the input terminal, and the first and second horizontal signal lines 104 and 105 are both set to the potential Vcm.

Thereafter, each time the horizontal scanning signal supply lines 103 in each column are selected in sequence by the horizontal scanning circuit, the line memory reading operation similar to the above is performed, and video signals are sequentially output from the horizontal output lines 110. The above operations are sequentially performed for each row.
Japanese Patent No. 3315962 JP 2001-230973 A

  However, in the solid-state imaging device configured in this way, there is a problem that a fixed pattern noise is generated in an area (dark part) where light irradiation of the light receiving area is small. This fixed pattern noise is particularly generated in the form of vertical stripes along the columns.

  SUMMARY An advantage of some aspects of the invention is that it provides a solid-state imaging device capable of suppressing generation of fixed pattern noise in a dark portion where light irradiation is small.

  In order to achieve the above object, a solid-state imaging device according to the present invention includes a plurality of photoelectric conversion elements that are arranged in rows and columns and generate a potential signal corresponding to the amount of light irradiation, and a plurality of vertical devices provided for each column. An output line; a plurality of first storage means connected to the respective vertical output lines so as to be openable to a short circuit; and storing a first potential signal generated when the photoelectric conversion element is irradiated with light; and the respective vertical output lines A plurality of second storage means for storing a second potential signal generated when the photoelectric conversion element is initialized, and a plurality of second storage means connected to each of the first storage means. A first horizontal signal line, a second horizontal signal line connected to each of the second storage means so as to be openable to a short circuit, and the first and second horizontal signal lines are connected to an input terminal, and the first and second Operational amplification means for outputting a difference signal corresponding to the difference in potential signal; and Horizontal scanning for controlling the connection state between the first and second storage means and the first and second horizontal signal lines and transmitting the first and second potential signals to the first and second horizontal signal lines for each column. The operational amplification means equalizes the potentials of the first and second horizontal signal lines after the output of the difference signal, and sets the potential to the first by the time of the output. And a potential determined according to the first and second potential signals transmitted to the second horizontal signal line.

  In the operational amplifier, the first and second horizontal signal lines are connected to the negative and positive input terminals, one end of the first feedback capacitor is connected to the negative input terminal, and the other end is connected to the positive output terminal so that the short circuit can be freely opened. A reference signal that is connected, has one end of the second feedback capacitor connected to the positive input terminal and the other end connected to the negative output terminal so as to be freely open-circuited, and determines an average potential of two output signals output from the positive and negative output terminals The other ends of the first and second feedback capacitors are short-circuited to the positive and negative output terminals to output the difference signal, and then the positive and negative outputs It is preferable that the reference signal is provided by being released from the terminal.

  In the operational amplifier, the first and second horizontal signal lines are connected to the negative and positive input terminals, one end of the first feedback capacitor and the first switch is connected to the negative input terminal, and the other end is connected to the positive output terminal. A reference signal that is connected, one end of the second feedback capacitor and the second switch is connected to the positive input terminal, the other end is connected to the negative output terminal, and determines the average potential of the two output signals output from the positive and negative output terminals And a potential determined in accordance with the first and second potential signals transmitted to the first and second horizontal signal lines by the horizontal scanning means by the time of the output. And potential holding means for inputting this potential as the reference signal to the differential amplifier, and after the signal is output, both ends of the first and second feedback capacitors are connected to the first and second Shorted by switch It is also preferable to so that.

  According to the present invention, the potentials of the first and second horizontal signal lines are equalized when the difference signal is output, and the first and second horizontal signal lines transmitted to the first and second horizontal signal lines by the time of the output are output. By setting the potential to be determined according to the second potential signal, it is possible to suppress the occurrence of fixed pattern noise in a dark part where light irradiation is small.

  As shown in FIGS. 1 and 2, the pixel 10 is provided with a light receiving diode 10 a and an optical signal detection MOS transistor (hereinafter simply referred to as a MOS transistor) 10 b so as to be adjacent to each other in the p-type well layer 15. ing. The light receiving diode 10a excites an electron-hole pair (photogenerated charge) according to the amount of light irradiation. The MOS transistor 10b receives the potential imparted by the hole transferred to the hole pocket 25 formed below the channel region among the electron-hole pairs generated in the light-receiving diode 10a, and the threshold voltage is modulated. Fluctuates. The pixel 10 is a photoelectric conversion element that generates a potential signal (source potential) corresponding to the amount of light irradiation.

  As shown in FIG. 1, the pixels 10 are arranged in a two-dimensional matrix along the column direction and the row direction. The number of pixels 10 arranged in each direction is arbitrary. In the pixel 10, the peripheral edge portion of the gate electrode 19 of the MOS transistor 10 b is formed in an octagonal ring shape and is connected to the plug 21. The n-type source region 16 a is formed in a region surrounded by the inner periphery of the ring-shaped gate electrode 19 and connected to the plug 20. Further, an n-type low concentration drain region 17 a is formed so as to surround the outer periphery of the gate electrode 19.

In the light receiving diode 10a, an n-type impurity layer 17b having substantially the same n-type impurity concentration as the drain region 17a is formed integrally with the drain region 17a. Further, a high-concentration, low-resistance n ⁺ -type impurity region 17c that forms a contact layer of the plug 22 is formed around the drain region 17a and the n-type impurity layer 17b. The n ⁺ -type impurity region 17c extends to the adjacent pixel 10, and the n ⁺ -type impurity region 17c of each pixel 10 is connected to each other and integrated.

FIG. 2 shows a cross-sectional structure of the pixel 10 along the line AA in FIG. On the substrate 11 made of p ⁺ type silicon, p ⁻ type silicon having an impurity concentration lower than that of the substrate 11 is epitaxially grown to form an epitaxial layer 31.

  The light-receiving diode 10a has an n-type buried layer 32 having a relatively high impurity concentration embedded in the epitaxial layer 31, and a low-concentration formed on the n-type buried layer 32 so as to be connected to the n-type buried layer 32. The n-type well layer 12, a p-type well layer 15 formed on the surface of the n-type well layer 12, and an n-type impurity layer 17 b formed on the surface of the p-type well layer 15. Further, the surface layer of the n-type impurity layer 17 b is covered with a thin insulating film 18.

  The n-type impurity layer 17b, the p-type well layer 15, the n-type well layer 12, and the n-type buried layer 32 together constitute an embedded photodiode having an npn structure. By adopting such a buried structure for the light receiving diode 10a, the influence of the semiconductor surface having a large number of trap levels is eliminated, and noise is reduced. The n-type buried layer 32 provided deep from the surface layer forms a thick n-type layer integrally with the n-type well layer 12 and forms a deep depletion layer, and reacts to light having a long wavelength. As a result, the charge is excited, and the sensitivity to red light is increased.

The drain region 17a of the MOS transistor 10b is formed on the surface layer of the p-type well layer 15 so as to surround the outer periphery of the ring-shaped gate electrode 19, and is integrated with the n-type impurity layer 17b. The source region 16a is formed in the surface layer of the p-type well layer 15 so as to be surrounded by the inner periphery of the ring-shaped gate electrode 19, and the source region 16a has a plug 20 made of tungsten and a low thickness on the surface layer of the source region 16a. An n ⁺ -type contact layer 16b for connection by a resistor is formed.

  The gate electrode 19 is formed on the p-type well layer 15 via an insulating film 18. A surface layer of the p-type well layer 15 sandwiched between the drain region 17a and the source region 16a under the gate electrode 19 serves as a channel region. Further, in order to keep the channel region in a depletion state at the normal operating voltage of the MOS transistor 10b, an n-type impurity having an appropriate concentration is implanted into the channel region to form the channel dope layer 15c. The MOS transistor 10b is a depletion type n-channel MOS transistor.

The hole pocket 25 is formed in the p-type well layer 15 below the channel dope layer 15c, is formed in a region covered with the gate electrode 19, and has a ring shape. The hole pocket 25 is a p ⁺ type high concentration region in which the impurity concentration is locally increased in the p type well layer 15.

  A p-type buried layer 33 having a relatively high impurity concentration is buried via the n-type well layer 12 below the p-type well layer 15 in the region of the MOS transistor 10b, and n in the region of the light receiving diode 10a. Adjacent to the mold buried layer 32. As a result, in the region of the MOS transistor 10b, the n-type well layer 12 is sandwiched between the upper and lower p-type layers and kept thin. The impurity distribution of the p-type buried layer 33 and the n-type well layer 12 is such that when the holes accumulated in the hole pockets 25 are swept out to the substrate 11 via the p-type buried layer 33, the depletion layer becomes p-type buried. It is set so that the electric field concentrates in the p-type well layer 15 instead of the buried layer 33, and the depletion layer extending in the p-type buried layer 33 is thin. That is, a rapid potential change occurs in the p-type well layer 15 at a low reset voltage, and the holes accumulated in the hole pocket 25 can be reliably swept out to the substrate 11 and reset.

The n ⁺ -type impurity region 17c is formed to extend to the adjacent pixel 10 outside the light-receiving diode 10a and the MOS transistor 10b so as to surround the p-type well layer 15, and the plug 22 formed of tungsten is low. This is a region connected by a resistor. The drain region 17a and the n-type impurity layer 17b are connected to the n-type well layer 12 having the same conductivity through the n ⁺ -type impurity region 17c. As a result, the p-type well layer 15 is isolated by being surrounded by the n-type conductor in the pixel 10.

  The region other than the light receiving window 24 formed above the light receiving diode 10a is covered and shielded by a metal layer (light shielding film) 23.

As shown in FIG. 3, the plugs 20 connected to the source region 16 a of each pixel 10 are connected by a vertical output line 34, and the plugs 20 arranged in one column are connected to the same vertical output line 34. Has been. The plugs 21 connected to the gate electrode 19 of each pixel 10 are connected by a vertical scanning signal supply line 35, and the plugs 21 arranged in one row (horizontal line) are the same one vertical scanning signal supply line 35. It is connected to. The vertical output line 34 and the vertical scanning signal supply line 35 are formed by different metal layers, and intersect each other without being in contact with each other. The plugs 22 connected to the n ⁺ -type impurity regions 17c of the respective pixels 10 are connected by drain voltage supply lines 36 wired along the row direction or the column direction. Note that the vertical output line 34, the vertical scanning signal supply line 35, and the drain voltage supply line 36 are not shown in FIGS. 1 and 2 in order to prevent complication. In FIG. 3, the pixels 10 are arranged in 2 rows and 2 columns for simplification.

  The solid-state imaging device is configured by connecting a peripheral circuit to a light receiving region in which a plurality of pixels 10 are arranged. The peripheral circuit includes a booster circuit 40 for applying a high voltage to the vertical output line 34, a vertical scanning circuit (V scanning) 41 for applying a voltage by scanning the vertical scanning signal supply line 35, and a drain voltage for applying a voltage to the drain voltage supply line 36. The drive circuit 42, the signal output circuit 43 that outputs the light detection signal, the horizontal scanning (H scanning) circuit 44 that horizontally scans the signal output circuit 43, and the drain voltage supply line 36 and the boosted voltage output line 37 are electrically connected (short-circuited). ) / Non-conductive (open) switch circuit 45 and the like.

  One boosted voltage output line 37 is output from the booster circuit 40 for each column. The boosted voltage output lines 37 are connected to corresponding vertical output lines 34 for each column, and these vertical output lines 34 are connected to a signal output circuit 43. The vertical scanning signal supply line 35 is connected to the V scanning circuit 41 and supplies a gate voltage to the gate electrode 19 of each pixel 10. A drain voltage supply line 36 is connected to the drain voltage drive circuit 42 and supplies a common drain voltage to the drain region 17 a of each pixel 10. The H scanning circuit 44 is disposed along the signal output circuit 43, and one horizontal scanning signal supply line 38 is provided for each column. The horizontal scanning signal supply line 38 is connected to the signal output circuit 43.

  The switch circuit 45 is connected to the drain voltage supply line 36 and the boosted voltage output line 37 corresponding to each of the pixels 10, and switches these to conduction / non-conduction. That is, the switch circuit 45 connects and disconnects the source region 16a and the drain region 17a from the outside of the pixel 10.

  FIG. 4 shows details of the signal output circuit 43. The aforementioned vertical output line 34 is connected to the switch S1 for high voltage block. The switch S1 includes a switch S2 connected to a circuit (not shown) that generates a preset voltage Vmpr, a switch S3 connected to one terminal of a first line memory (first storage means) 50, and a second line memory (first 2 storage means) 51 and a switch S5 connected to one terminal.

  The other terminal of the first line memory 50 is grounded, and one terminal thereof is further connected to the first horizontal signal line 52 via the switch S4 whose on / off is controlled by the horizontal scanning signal supply line 38 described above. ing. Similarly, the other terminal of the second line memory 51 is grounded, and one terminal of the second line memory 51 is further connected to the second horizontal signal line 53 via a switch S6 whose ON / OFF is controlled by the horizontal scanning signal supply line 38. Has been.

  The first horizontal signal line 52 is connected to a first line memory 50 provided in each column via a switch 54, and one end thereof is connected to a negative input terminal of the differential amplifier 54. Similarly, the second horizontal signal line 53 is connected to the second line memory 51 provided in each column via a switch 56, and one end thereof is connected to the positive input terminal of the differential amplifier 54. Further, a switch S7 for short-circuiting / opening them is provided between the first horizontal signal line 52 and the second horizontal signal line 53.

  A first feedback capacitor 55 and a switch S8 are provided between the negative input terminal and the positive output terminal of the differential amplifier 54. One end of the first feedback capacitor 55 is connected to the negative input terminal. The switch S8 switches whether the other end of the first feedback capacitor 55 is connected to the positive output terminal or to a potential generation circuit (not shown) that generates the potential Vcm. Similarly, a second feedback capacitor 56 and a switch S9 are provided between the positive input terminal and the negative output terminal of the differential amplifier 54. One end of the second feedback capacitor 56 is connected to the positive input terminal. The switch S9 switches whether the other end of the second feedback capacitor 56 is connected to the negative output terminal or to a potential generation circuit (not shown) that generates the potential Vcm.

  The differential amplifier 54 incorporates a common mode feedback (CMF) circuit, and this CMF circuit determines the average potential of the output potentials VoutP and VoutM by the potential Vcm input to the CMF terminal. That is, the output potential VoutP at the positive output terminal and the output potential VoutM at the negative output terminal always satisfy the relational expression Vcm = (VoutP + VoutM) / 2. The output potential VoutP of the differential amplifier 54 is output from the horizontal output line 57, and the output potential VoutM is output from the horizontal output line 58. Since these VoutP and VoutM have a relationship of VoutM−VoutP = VS1−VS2 or VoutP−VoutM = VS2−VS1 and can output a difference between the source potentials VS1 and VS2, the output potentials VoutP and VoutM are By inputting to a signal circuit having an AD converter (not shown), the difference between the source potentials VS1 and VS2 can be obtained.

  A plurality of switches similar to those described above and first and second line memories are provided for the vertical output lines 34 in adjacent columns, and the first line memories in each column are connected via the switches. The second line memory of each column is connected to the second horizontal signal line 53 through a switch. Each switch in the signal output circuit 43 is composed of an n-channel MOS transistor or a p-channel MOS transistor alone or in combination.

  The imaging operation of the MOS type solid-state imaging device will be described with reference to FIGS. When the imaging operation is started, each row of the light receiving region in which the pixels 10 are arranged in a matrix is sequentially selected by the V scanning circuit 41, and a series of four steps ST1 to ST4 (accumulation period → first reading shown in FIG. 6). (Period → initialization period → second reading period) is repeated in order line by line. After the series of four steps ST1 to ST4 in the last row is completed, a so-called rolling operation is performed in which the same operation is repeated after returning to the first row.

  In the accumulation period (ST1), holes are generated and accumulated by light irradiation in all rows of the light receiving region, and the (N-1) th (N-1) one before the Nth row selected from the signal output circuit 43. The row video signal Vout is output. First, in the period A within the accumulation period, a voltage of about 2.5 V is applied to the gate electrodes 19 of all the pixels. The voltage applied to the gate electrode 19 is called a gate voltage and is indicated as Vg1 and Vg2 in the figure. The gate voltage Vg1 is a gate voltage in a selected row selected by the V scanning circuit 41, and the gate voltage Vg2 is a gate voltage in other non-selected rows. However, there is no distinction between the selected row and the non-selected row in this accumulation period.

  In addition, the pn junction formed by the drain region 17a and the source region 16a and the p-type well layer 15 is reverse-biased, and the channel region is not depleted with respect to a gate voltage of 2.5 V, which is sufficient for the channel region. A voltage of about 1.6 V is applied to the drain regions 17a of all pixels so that electrons are accumulated with a high density. The voltage applied to the drain region 17a is called a drain voltage, and is indicated as Vd in the figure. Further, the switch S1 is opened to disconnect the source region 16a of each pixel from the signal output circuit 43 so that no current flows through the channel region. As a result, electrons having a sufficient density are accumulated in the channel region (a so-called electron pinning state is formed), and the source region 16a is connected to the drain region 17a through the channel region and has substantially the same potential as the drain region 17a. .

At this time, the p-type well layer 15 and the n-type well layer 12 are depleted, and holes are accumulated in the p-type well layer 15 among the electron-hole pairs generated by light irradiation of the light receiving diode 10a. At this time, since the p ⁺ -type hole pocket 25 has the lowest potential with respect to the hole in the p-type well layer 15, the hole moves to the hole pocket 25.

  In a period A, by storing a sufficient amount of electrons in the channel region, the level hole generation center at the interface between the insulating film 18 and the channel region is held in an inactivated state, Hole emission is prevented. That is, since leakage current due to the emission of holes is suppressed, accumulation of holes other than holes generated by light irradiation in the hole pocket 25 is suppressed.

  In the period B before the end of the accumulation period, the gate voltages Vg1 and Vg2 are set to the ground potential 0.0 V, and the pn junction formed by the drain region 17a and the source region 16a and the p-type well layer 15 is from the period A. The drain voltage Vd is set to about 3.3V so that the reverse bias is deeper. As a result, the channel region maintains a depletion state, and a stronger electric field is generated in the p-type well layer 15 toward the hole pocket 25, so that all the holes remaining in the p-type well layer 15 of the light receiving diode 10a are all hole pockets. 25. In the hole pocket 25, since the negative charge amount of the acceptor corresponding to the accumulated charge amount of the hole is neutralized, the potential near the source region 16a is modulated, and the threshold voltage of the MOS transistor 10b changes.

  In this accumulation period, the video signal Vout corresponding to the potential difference between the source potentials stored in the first line memory and the second line memory in each column in the horizontal blanking period of the previous (N−1) th row is a signal. Although it is output from the output circuit 43, this signal output operation will be described after the second readout period.

  Next, the process proceeds to the first reading period (ST2). In the period C immediately after the start of the first reading period, the switches S1 and S3 of the signal output circuit 43 are closed and the other switches are opened, and the first line memory 50 and the vertical output line 34 are electrically connected. The 2-line memory 51 and the vertical output line 34 are made non-conductive. At this time, the gate voltages Vg1 and Vg2 are set to the ground potential 0.0V, the switch S2 is closed, and a preset voltage Vmpr of about 1.6V is applied to the first line memory 50. At this time, the drain voltage Vd of all the pixels 10 is maintained at about 3.3V. The preset voltage Vmpr is set to a voltage higher than the ground potential and lower than the source potentials VS1 and VS2 read to the first and second line memories 50 and 51 in the first and second read periods.

  In the second half period D of the first read period, the switch S2 is opened, and the first line memory 50 and the vertical output line 34 are kept conductive. At this time, the V scanning circuit 41 applies the gate voltage Vg1 of about 2.2 V to the vertical scanning signal supply line 35 of the Nth row to be selected, and the gate voltage Vg2 of the other non-selected vertical scanning signal supply lines 35. Is set to ground potential 0.0V. At this time, the drain voltage Vd of all the pixels 10 is maintained at about 3.3V. By such voltage application, the MOS transistor 10b in the selected row operates in a saturated state.

  In this period D, the first line memory 50 in each column is charged by the potential (first potential signal) VS1 generated in the source region 16a of each pixel 10 in the Nth row. The potential VS <b> 1 is a potential including a unique reference potential (noise potential) VS <b> 2 before hole accumulation and a potential raised by holes accumulated in the hole pocket 25. Note that the transfer of the source potential to the line memory is expressed as “reading”. In each column, the potential VS1 is simultaneously read from the first line memory.

  When the first read period ends, the closed voltage block switch S1 and switch S3 are opened, the potential VS1 is held in the first line memory 50, and the process proceeds to the initialization period (ST3). First, the selected gate electrode 19 in the Nth row is electrically disconnected from the outside to enter a floating state (high impedance state). At this time, the gate electrodes 19 of other non-selected rows are grounded, and the gate voltage Vg2 is set to 0.0V.

  Subsequently, a high voltage is supplied from the booster circuit 40 to the source region 16a of each pixel 10 via the boosted voltage output line 37. At this time, the switch circuit 45 connects the drain voltage supply line 36 and the boosted voltage output line 37. By short-circuiting and electrically connecting the source region 16a and the drain region 17a from the outside of the pixel 10, a high voltage of about 6.6 V is simultaneously applied to the source region 16a and the drain region 17a. The gate electrode 19 in the Nth row is already charged to about 2.2 V, and a voltage of about 6.6 V is applied through the capacitance between the source and gate and between the source and drain, and the gate voltage Vg1 is about 8.V. 6V.

  The voltage Vg1 of the gate electrode 19 of about 8.6 V is applied to the p-type well layer 15 and the n-type well layer 12 therebelow. Due to the high electric field generated at this time, holes can be swept out to the substrate 11 from the p-type well layer 15 and the hole pocket 25 in the pixels 10 in the Nth row. In this way, initialization can be performed by reliably sweeping out holes with a low voltage. The holes accumulated in the hole pockets 25 of other non-selected rows are not discharged but are held in the hole pockets 25.

  Next, the process proceeds to the second reading period (ST4). The switches S1 and S2 are controlled in the same manner as in the first readout period. The control of the switch S3 in the first readout period is changed to the switch S5, and the control of the switch S4 in the first readout period is changed to the switch S6. A reading operation similar to that in the first reading period is performed for. That is, the period E is the same as the period C, and the period F is the same as the period D. As a result, the second line memory 51 is charged with the inherent reference potential (second potential signal) VS2 generated in the source region 16a of the pixel 10 in the Nth row in a state where holes are discharged from the hole pocket 25. . In each column, the potential VS2 is simultaneously read from the second line memory. Note that steps ST2 to ST4 are performed during the horizontal blanking period, and are performed for initialization of one row and the source potential is read before and after the initialization.

  After the end of the second read period, the switches S1 and S5 are opened to hold the potential VS2 in the second line memory 51, and the process returns to the accumulation period of step ST1. In the accumulation period, the above-described accumulation operation is performed, and the potential difference between the source potentials VS1 and VS2 read to the first and second line memories 50 and 51 in each column in the first and second readout periods is calculated by the operational amplification means. A signal output operation for sequentially performing operational amplification and outputting as a video signal Vout is performed.

  During this signal output operation, the horizontal scanning signal (HSCAN) is sequentially supplied to the horizontal scanning signal supply line 38 provided for each column by the H scanning circuit 44. The switches S4 and S6 are closed simultaneously when the horizontal scanning signal HSCAN is supplied to the horizontal scanning signal supply line 38. The switch S8 is switched to connect the other end of the first feedback capacitor 55 to the positive output terminal side of the differential amplifier 54, and the switch S9 is switched to connect the other end of the second feedback capacitor 56 to the negative output terminal side of the differential amplifier 54. When the switches S4 and S6 are closed, the potentials VS1 and VS2 held in the first and second line memories 50 and 51 are transmitted to the first and second horizontal signal lines 52 and 53, and the potential VS1, Charges corresponding to VS2 are stored in feedback capacitors 55 and 56, respectively. Thus, the H scanning circuit 44 functions as a horizontal scanning unit.

  The output potentials VoutP and VoutM of the differential amplifier 54 have values based on the accumulated charges of the first and second feedback capacitors 55 and 56. An output potential VoutP corresponding to the potential difference (VS1-VS2) is output to the horizontal output line 57, and an output potential VoutM corresponding to the potential difference (VS2-VS1) is output to the horizontal output line 58. The output potentials VoutP and VoutM are input to an AD converter (not shown), for example, and are subjected to video signal processing.

  As described above, when the output of the video signal Vout is completed for one column in which the horizontal scanning signal HSCAN is supplied to the horizontal scanning signal supply line 38, the switches S4 and S6 are opened, and the switches S8 and S9 are switched to the first. The potential Vcm is applied to the other ends of the second feedback capacitors 55 and 56. At this time, the switch S7 is closed to bring the first horizontal signal line 52 and the second horizontal signal line 53 to the same potential. Thereafter, the switch S7 is opened, the horizontal scanning signal supply line 38 of the adjacent column is selected by the H scanning circuit 44, and the same signal output operation is repeated until the final column.

  When this accumulation period ends, the next (N + 1) th row is selected, and the operations in steps ST2 to ST4 described above are performed. In this way, the operations in steps ST1 to ST4 are performed for each row of the light receiving region, and when reaching the last row, the operation returns to the first row and the same operation is repeated (rolling operation). The exposure time (hole accumulation time) of each row is required for the time from the end of the horizontal blanking period of steps ST2 to ST4 to the start of the next horizontal blanking period after the rolling operation is performed, that is, one frame. It corresponds to the time.

  Next, the potential state of each part in the signal output circuit 43 during the signal output operation is verified. First, the capacitance of the first line memory 50 is C1, the capacitance of the second line memory 51 is C2, the potential of the first horizontal signal line 52 is V1, the potential of the second horizontal signal line 53 is V2, the first The capacitance of the feedback capacitor 55 is C3, the capacitance of the second feedback capacitor 56 is C4, the potential of the other end of the first feedback capacitor 55 is V3, and the potential of the other end of the second feedback capacitor 56 is V4. In an initial state where no output operation is performed, the potentials V1 and V2 are set to 0V.

  In a state before the switches S4 and S6 are closed, that is, in a state where the potentials VS1 and VS2 are held in the first and second line memories 50 and 51, V1 = V2 = 0V, V3 = V4 = Vcm, VoutP = VoutM = Vcm. From this state, even if the switches S8 and S9 are switched to connect the other ends of the first and second feedback capacitors 55 and 56 to the output terminal side of the differential amplifier 54, the potential state does not change.

Here, the potentials of the respective parts before and after the switches S4 and S6 are closed and the switches S8 and S9 are switched to the output terminal side are as follows:
C1 * VS1-C3 * Vcm = C1 * V1 + C3 * (V1-VoutP)
C2 / VS2-C4 / Vcm = C2 / V2 + C4 / (V2-VoutM)
Is satisfied. Here, for simplification of explanation, assuming that C1 = C2 = C3 = C4, the above relational expressions are respectively
Relational expression 1: VS1-Vcm = 2 · V1-VoutP
Relational expression 2: VS2-Vcm = 2 · V2-VoutM
And simplified.

  Assuming that the amplification factor (gain) of the differential amplifier 54 is A, the relationship of A · (−V1 + V2) = (VoutP−VoutM) is obtained, and the amplification factor A is almost infinite, so that V1 = V2. (So-called imaginary short). By subtracting relational expressions 1 and 2 with V1 = V2, a relational expression of VoutM−VoutP = VS1−VS2 is obtained. Further, when relational expressions 1 and 2 are added with V1 = V2 = Vx, a relational expression of Vx = (VS1 + VS2) / 4 + (VoutP−Vcm) / 4 + (VoutM−Vcm) / 4 is obtained.

  Since the output potentials VoutP and VoutM of the differential amplifier 54 satisfy the relationship Vcm = (VoutP + VoutM) / 2, the relationship Vx = (VS1 + VS2) / 4 is obtained. Therefore, the potential V1 of the first horizontal signal line 52 and the potential V2 of the second horizontal signal line 53 at the time of signal output are substantially equal, and the potential VS1 held in the first line memory 50 and the second line memory 51 The potential is averaged with the held potential VS2.

  After the horizontal output lines 57 and 58 output the potentials VoutP and VoutM, the switches S4 and S6 are opened, the switches S8 and S9 are switched, and the potentials VoutP and VoutM at the other ends of the first and second feedback capacitors 55 and 56 are switched. Are reset to the potential Vcm. At this time, the switch S7 is closed to ensure that the first horizontal signal line 52 and the second horizontal signal line 53 have the same potential Vx. Note that the switch S7 is not always necessary and may not be provided.

Thereafter, the switch S7 is opened, and the horizontal scanning signal supply line 38 in the adjacent column is selected by the H scanning circuit 44, and a similar signal output operation is performed. At this time, the potentials V1 and V2 of the first and second horizontal signal lines 52 and 53 have (VS1 + VS2) / 4 as an initial value, and at the time of signal output, the potentials Vx ⁽²⁾ = (VS1 ⁽²⁾ + VS ^{( 2)} ) / 4+ (VS1 + VS2) / 8. Note that VS1 ⁽²⁾ and VS ⁽²⁾ represent potentials held in the first and second line memories in the second column in the first and second readout periods, respectively.

  The potentials V1 and V2 of the first and second horizontal signal lines 52 and 53 when the horizontal scanning signal supply line 38 of the nth column is selected and signal output is performed are equal, and the following relational expression 3 Represented by

なお、ＶＳ１^(k) ，ＶＳ２^(k) は、第１及び第２読出期間において第ｋ列目の第１及び第２ラインメモリにそれぞれ保持された電位を表し、ＶＳ１⁽⁰⁾ ＝ＶＳ１、ＶＳ２⁽⁰⁾ ＝ＶＳ２である。このように、Ｈ走査回路４４による水平走査中の第１及び第２水平信号線５２，５３の電位は、それまでに走査された各列の第１及び第２ラインメモリに保持されていた電位に応じて決定される平均化された電位となる。

Note that VS1 ^(k) and VS2 ^(k) represent potentials held in the first and second line memories in the k-th column in the first and second readout periods, respectively, and VS1 ⁽⁰⁾ = VS1, VS2 ⁽⁰⁾ = VS2. As described above, the potentials of the first and second horizontal signal lines 52 and 53 during the horizontal scanning by the H scanning circuit 44 are the potentials held in the first and second line memories of each column scanned so far. Is an averaged potential determined according to.

  When the horizontal scanning is completed up to the last column and the signal output of the first row is completed, the switches S2 and S1 in all the vertical output lines 34 are closed and the vertical output lines 34 are reset with the preset voltage Vmpr, and then the switch S2 , S1 are opened. Thereafter, the second row is selected and the process proceeds to the next step.

  In the first embodiment of the present invention described above, the potentials V1 and V2 of the first and second horizontal signal lines 52 and 53 are equal to the potential represented by the relational expression 3 after the horizontal scanning is completed for one row. However, the present invention is not limited to this, and the potentials V1 and V2 may be reset to a predetermined potential every time one horizontal scan or one frame signal output is completed. Good.

  FIG. 7 shows a signal output circuit 60 used in the solid-state imaging device according to the second embodiment of the present invention. In the signal output circuit 60, the switches S8 and S9 used in the signal output circuit 43 in FIG. 4 are eliminated, and the first feedback capacitor 55 and the switch are provided between the negative input terminal and the positive output terminal of the differential amplifier 54. S10 is connected in parallel, and the second feedback capacitor 56 and the switch S11 are connected in parallel between the positive input terminal and the negative output terminal of the differential amplifier 54. Further, the signal output circuit 60 is provided with a potential holding circuit 61 for holding a predetermined potential. The input side of the potential holding circuit 61 is connected to the second horizontal signal line 53 via the switch S12, and the potential holding circuit. The output side of 61 is connected to a CMF terminal provided in the differential amplifier 54. The potential holding circuit 61 is configured by an integrating circuit using a differential amplifier, for example.

  During the signal output operation during the accumulation period, when the signals S are output by closing the switches S4 and S6 in the first column, the potential Vx is generated in the first and second horizontal signal lines 52 and 53. After the switch S12 is closed and the potential holding circuit 61 holds the potential Vx, the potential Vx is input to the differential amplifier 54 as the potential Vcm, and the switches S10 and S11 are closed to input and output terminals of the differential amplifier 54. And short circuit. By repeatedly performing this operation together with the horizontal scanning of each column, the potentials of the first and second horizontal signal lines 52 and 53 become the same as in the relational expression 3. That is, the averaged potential is determined according to the potential held in the first and second line memories of each column scanned so far.

  FIG. 8 shows a signal output circuit 70 used in the solid-state imaging device according to the third embodiment of the present invention. In the signal output circuit 70, differential amplifiers 71 and 72 are provided instead of the differential amplifier 54 used in the signal output circuit 43 of FIG. The signal output circuit 60 is provided with the same potential holding circuit 73 as in the second embodiment, and the output side of the potential holding circuit 73 is commonly connected to the positive input terminals of the differential amplifiers 71 and 72. Further, for example, one of the plurality of rows of the light receiving region in which the pixels 10 are arranged is shielded to form a region (optical black region) where no light is irradiated.

  During the signal output operation, the source potential of the pixel in the optical black area is held in the potential holding circuit 73 as needed, and is input to the positive input terminals of the differential amplifiers 71 and 72 as a reference potential. Even in this case, the potentials of the first and second horizontal signal lines 52 and 53 are determined according to the potentials held in the first and second line memories of each column scanned so far. This is the same as in the first and second embodiments.

  As described in the first to third embodiments, the first and second lines of each column that have been scanned with the potentials of the first and second horizontal signal lines 52 and 53 so far during the signal output operation. By setting the potential to be determined according to the potential held in the memory, generation of fixed pattern noise in the dark portion is suppressed. The generation of fixed pattern noise in the dark area is caused by the potential difference between the potential determined by each line memory and a fixed potential different from this when each horizontal signal line is fixed at a fixed potential as in the prior art. This is considered to be caused by a slight difference in output particularly in a dark part due to the nonlinear output characteristics of

  In the first to third embodiments, the light receiving region is configured by the threshold modulation type pixel 10 illustrated in FIGS. 1 and 2, but the present invention is not limited to this, and the configuration of the pixel in the light receiving region and The arrangement and the like can be changed as appropriate. Any pixel may be used as long as it can charge each line memory in the signal output circuit with a potential based on the amount of accumulated charge.

It is a top view which shows the structure of a pixel. It is sectional drawing of the pixel which follows the AA line of FIG. It is a figure which shows the circuit structure of a solid-state imaging device. It is a circuit diagram which shows the structure of a signal output circuit. It is a flowchart explaining the imaging operation of a solid-state imaging device. It is a timing chart which shows the applied voltage at the time of imaging operation. It is a circuit diagram which shows the structure of the signal output circuit in 2nd Embodiment. It is a circuit diagram which shows the structure of the signal output circuit in 3rd Embodiment. It is a circuit diagram which shows the structure of the signal output circuit in the conventional solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Pixel 10a Photodiode 10b Optical signal detection MOS transistor 16a Source region 17a Drain region 19 Gate electrode 34 Vertical output line 35 Vertical scanning signal supply line 36 Drain voltage supply line 38 Horizontal scanning signal supply line 43 Signal output circuit 44 Horizontal scanning circuit 45 switch circuit 50 first line memory 51 second line memory 52 first horizontal signal line 53 second horizontal signal line 54 differential amplifier 55 first feedback capacitor 56 second feedback capacitor 57, 58 horizontal output line 60, 70 signal output Circuit 61, 73 Potential holding circuit 71, 72 Differential amplifier

Claims (3)

A plurality of photoelectric conversion elements arranged in rows and columns and generating a potential signal according to the amount of light irradiation;
A plurality of vertical output lines provided for each column;
A plurality of first storage means which are connected to the respective vertical output lines so as to be freely open-circuited and store a first potential signal generated when the photoelectric conversion element is irradiated with light;
A plurality of second storage means connected to each of the vertical output lines so as to be openable to a short circuit and storing a second potential signal generated when the photoelectric conversion element is initialized;
A first horizontal signal line connected to each of the first storage means so as to be openable to a short circuit;
A second horizontal signal line connected to each of the second storage means so as to be openable to a short circuit;
Operational amplification means for connecting the first and second horizontal signal lines to an input terminal and outputting a difference signal corresponding to a difference between the first and second potential signals;
The connection state between the first and second storage means and the first and second horizontal signal lines is controlled, and the first and second potential signals are transmitted to the first and second horizontal signal lines for each column. Horizontal scanning means,
The operational amplifying means equalizes the potentials of the first and second horizontal signal lines after the output of the difference signal and sets the potentials to the first and second horizontal signals before the output. A solid-state imaging device having a potential determined according to the first and second potential signals transmitted to the line. In the operational amplifier, the first and second horizontal signal lines are connected to the negative and positive input terminals, one end of the first feedback capacitor is connected to the negative input terminal, and the other end is connected to the positive output terminal so as to be freely open-circuited. , One end of the second feedback capacitor is connected to the positive input terminal, the other end is connected to the negative output terminal so as to be short-circuited freely, and a reference signal for determining an average potential of two output signals output from the positive and negative output terminals is input. A differential amplifier,
The other ends of the first and second feedback capacitors are short-circuited to the positive and negative output terminals to output the difference signal, and then released from the positive and negative output terminals to provide the reference signal. The solid-state imaging device according to claim 1, wherein: In the operational amplifier, the first and second horizontal signal lines are connected to the negative and positive input terminals, one end of the first feedback capacitor and the first switch are connected to the negative input terminal, and the other end is connected to the positive output terminal. The second feedback capacitor and the second switch have one end connected to the positive input terminal and the other end connected to the negative output terminal. A reference signal for determining the average potential of the two output signals output from the positive and negative output terminals is input. A differential amplifier,
By the time of the output, the potential determined according to the first and second potential signals transmitted to the first and second horizontal signal lines by the horizontal scanning means is held, and this potential is used as the reference signal. A potential holding means for inputting to the differential amplifier,
The solid-state imaging device according to claim 1, wherein both ends of the first and second feedback capacitors are short-circuited by the first and second switches after the signal is output.

Images