JP2006073604A - Semiconductor evaluation method and semiconductor evaluation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor evaluation method capable of evaluating a sample at a high resolution and precision with no damage to the sample, and a semiconductor evaluation device. <P>SOLUTION: The semiconductor evaluation method evaluates a sample 12 of a semiconductor device comprising a semiconductor substrate, a semiconductor element formed on the first surface side of the semiconductor substrate, and an insulating layer so formed as to cover the semiconductor element using a scanning probe microscope. In a first step, a sample is so fixed on a sample stage 36 that the side of sample where the insulating layer is formed contacts the sample stage. In a second step, the second surface side of the semiconductor substrate is polished to reduce the thickness of the semiconductor substrate to a prescribed thickness. In a third step, a probe 22 of the scanning probe microscope is applied with a voltage, and the probe is made to contact the second surface side of the semiconductor substrate for measuring a current flowing in the probe. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor evaluation method and a semiconductor evaluation apparatus, and more particularly to a semiconductor evaluation method and a semiconductor evaluation apparatus that can evaluate a sample with high resolution and high accuracy.

  Conventionally, evaluation of electrical characteristics of a semiconductor device has been performed as follows.

  FIG. 16 is a cross-sectional view showing a conventional method for evaluating a semiconductor device.

  First, a semiconductor device to be evaluated is prepared.

  For example, a gate electrode 158 is formed on a semiconductor substrate 154 made of silicon via a gate insulating film 156. The gate electrode 158 is constituted by, for example, a laminated film formed by sequentially laminating a polysilicon film 158a and a metal film 158b.

  A sidewall insulating film 160 is formed on the side wall portion of the gate electrode 158. A source / drain diffusion layer 162 is formed in the semiconductor substrate 154 on both sides of the gate electrode 158 on which the sidewall insulating film 160 is formed. Thus, a transistor 164 having the gate electrode 158 and the source / drain diffusion layer 162 is formed.

  An interlayer insulating film 166 is formed over the semiconductor substrate 154 so as to cover the transistor 164. A conductor plug 168 and a wiring 170 are embedded in the interlayer insulating film 166. An electrode pad 172 is formed on the interlayer insulating film 166. The electrode pad 172 is electrically connected to the gate electrode 158 or the source / drain diffusion layer 162 of the transistor 164 via the conductor plug 168 and the wiring 170. A protective film 167 is formed on the interlayer insulating film 166. The electrode pad 172 is exposed from the protective film 167.

  When evaluating the semiconductor device, the probe 122 of the semiconductor inspection device is brought into contact with the electrode pad 172, and a voltage is applied to the transistor 164 and the like through the conductor plug 168 and the wiring 170. And the characteristic of the electric circuit which consists of several transistors 164 grade | etc., Is measured with a semiconductor test | inspection apparatus.

  However, in the method for evaluating a semiconductor device as shown in FIG. 16, since the characteristics as an electric circuit are measured, the characteristics of the transistor 164 cannot be evaluated alone.

  Here, it can be considered that the transistor 164 is evaluated in a state where only the transistor 164 is formed over the semiconductor substrate 154. However, in an actual semiconductor device, various film formation processes, heat treatment, and the like are performed after the transistor 164 is formed. Therefore, the characteristics of the transistor 164 at the stage where only the transistor 164 is formed over the semiconductor substrate 154 and the characteristics of the transistor 164 in the actually manufactured semiconductor device often differ greatly. Therefore, it is extremely important to evaluate the completed semiconductor device.

  As an evaluation method for a completed semiconductor device, the following evaluation method has been proposed. FIG. 17 is a process diagram showing a proposed semiconductor evaluation method.

  First, a sample 112 made of a completed semiconductor device is prepared (see FIG. 16).

  Next, the electrode pad 172, the wiring 170, and the like are removed by mechanical polishing or the like (see FIG. 17A).

  Next, the interlayer insulating film 166 is removed by etching (see FIG. 17B).

  Next, the conductor plug 168 and the gate electrode 158 are selectively removed by etching (see FIG. 17C).

In this way, a sample to be measured is created.
JP 2002-323431 A JP 2000-211941 A

  However, in the proposed evaluation method, the gate insulating film 156 is damaged when the gate electrode 158 is selectively etched. Further, in the proposed evaluation method, when the wiring 170 or the like is polished, the surface of the sample 112 must be frequently checked with an optical microscope or the like in order to prevent even the transistor 164 from being polished. There wasn't. Further, when etching is performed, the etching solution, etching gas, etching conditions, and the like have to be optimized. For this reason, in the proposed evaluation method, the preparation of the sample itself is not easy, and it takes a long time to prepare the sample. In addition, the sample prepared as described above has large irregularities formed on the surface, and thus is not suitable for evaluation using an SPM (Scanning Probe Microscope) or the like.

  An object of the present invention is to provide a semiconductor evaluation method and a semiconductor evaluation apparatus capable of evaluating a sample with high resolution and high accuracy without damaging the sample.

  According to one aspect of the present invention, a sample comprising a semiconductor device having a semiconductor substrate, a semiconductor element formed on the first surface side of the semiconductor substrate, and an insulating layer formed to cover the semiconductor element. Is a semiconductor evaluation method using a scanning probe microscope to fix the sample on the sample stage so that the side of the sample on which the insulating layer is formed contacts the sample stage Applying a voltage to the probe of the scanning probe microscope, and a second step of reducing the thickness of the semiconductor substrate to a predetermined thickness by polishing the second surface side of the semiconductor substrate. And a third step of measuring the current flowing through the probe by bringing the probe into contact with the second surface side of the semiconductor substrate.

  According to another aspect of the present invention, the semiconductor device includes a semiconductor substrate, a semiconductor element formed on the first surface side of the semiconductor substrate, and an insulating layer formed to cover the semiconductor element. A semiconductor evaluation apparatus for evaluating a sample using a scanning probe microscope, the voltage applying means for applying a voltage to a probe of the scanning probe microscope, and the second of the semiconductor substrate thinned to a predetermined thickness There is provided a semiconductor evaluation apparatus having current measuring means for measuring the current flowing through the probe by bringing the probe into contact with the surface of the surface.

  According to the present invention, the thickness of the semiconductor substrate is made extremely thin by polishing the back side of the semiconductor substrate, and the probe is brought into contact with the back side of the semiconductor substrate and the probe is scanned in a state where a voltage is applied to the probe. Thus, measurement is performed on the sample. Since the thickness of the semiconductor substrate is extremely thin, electrons flowing from the probe into the semiconductor substrate flow into the transistor side in a state of being concentrated in an extremely narrow region. Therefore, according to the present invention, measurement can be performed with high resolution and high accuracy. In addition, since the polishing is performed on the back surface side of the semiconductor substrate, the transistor formed on the front surface side of the semiconductor substrate is not damaged. Therefore, according to the present invention, the sample can be evaluated with high resolution and high accuracy without damaging the sample.

  Moreover, according to the present invention, since the AFM image is acquired together with the current image, it is possible to display the AFM image and the current image so as to correspond to each other. Therefore, according to the present invention, the measurement result can be easily used as a powerful guideline for device development.

[First Embodiment]
A semiconductor evaluation apparatus and a semiconductor evaluation method according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic view showing the semiconductor evaluation apparatus according to the present embodiment.

  First, the semiconductor evaluation apparatus according to the present embodiment will be explained with reference to FIG.

  The semiconductor evaluation apparatus according to the present embodiment is a semiconductor evaluation apparatus using a scanning electron microscope (SPM), a voltage applying means 21 for applying a voltage to the probe 22, and a semiconductor thinned to a predetermined thickness. The probe 22 is brought into contact with the back side of the substrate 54 (see FIGS. 7 and 8), and current measuring means 24 and 26 for measuring the current flowing through the probe 22 are provided.

As shown in FIG. 1, the semiconductor evaluation apparatus according to the present embodiment mainly includes a processing unit 10 that controls the entire semiconductor evaluation apparatus and performs predetermined processing, and an XY stage that scans a sample 12 in the XY direction. 14, a scanner 18 that moves the conductive cantilever 16 in the Z direction using a piezoelectric element (not shown), and an AFM (Atomic Force Microscope, atomic force) based on the voltage applied to the piezoelectric element of the scanner 18. Microscope) based on the AFM image generation unit 20 that generates an image, a power source 21 for applying a bias voltage V _bias to the sample 12, an amplifier 24 that amplifies the current flowing through the probe 22, and a signal amplified by the amplifier 24. A current image generation unit 26 that generates a current image, and a display unit 28 that displays the AFM image and the current image in association with each other.

  The processing unit 10 is configured by a computer, for example.

  A storage unit 30 is connected to the processing unit 10. The storage unit 30 stores various data such as measurement results temporarily or continuously. The storage unit 30 can be configured by, for example, a hard disk or a RAM. A program for causing the processing unit 10 to perform predetermined processing and control is installed in the storage unit 30.

  An input unit 32 for an operator to input a command is connected to the processing unit 10. The input unit 32 can be configured by a keyboard, a mouse, or the like, for example.

  An XY scanning circuit 34 is connected to the processing unit 10. The XY scanning circuit 34 outputs a signal for controlling the XY stage 14 based on a signal regarding the XY coordinates output from the processing unit 10.

  A sample stage 36 that supports the sample 12 is placed on the XY stage 14. The XY stage 14 appropriately moves the sample stage 36 in the XY direction based on the signal output from the XY scanning circuit 34.

  As a material for the sample stage 36, a transparent material that transmits natural light or laser light is used. The reason why a transparent material is used as the material for the sample stage 36 is that, as will be described later, it is necessary to make light incident on the sample 12 through the sample stage 36 when observing equal thickness interference fringes using an optical microscope. Because.

An electrode 38 is embedded in the sample table 36. The electrode 38 is for applying a bias voltage V _bias to the sample 12. The sample 12 is fixed to the sample table 36 using, for example, a conductive adhesive 76 (see FIG. 8). An electrode pad 72 (see FIG. 8) connected to the transistor 64 (see FIG. 8) or the like is formed on the surface of the sample 12 facing the sample table 36. The electrode pad 72 is electrically connected to the positive side of the power source 21 through the conductive adhesive 76 and the electrode 38. Thus, the bias voltage V _bias is applied to the sample 12.

  The scanner 18 includes a piezoelectric element (not shown) and an actuator 40 driven by the piezoelectric element. A conductive cantilever 16 is attached to the actuator 40. The actuator 40 is moved in the Z direction according to the voltage applied to the piezoelectric element, and the cantilever 16 is moved in the Z direction as the actuator 40 moves.

  A conductive probe (probe) 22 is provided on the lower surface side of the distal end portion of the conductive cantilever 16. When measuring the sample 12, the measurement is performed while the tip of the conductive probe 22 is in contact with the sample 12.

  A mirror 42 is provided on the upper surface side of the tip of the cantilever 16. A laser light source 44 is provided above the mirror 42. The laser light emitted from the laser light source 44 is reflected by the mirror 42 and enters the detector 46.

  The detector 46 detects the position where the laser beam is incident on the detection surface. When the probe 22 is scanned in the XY direction, the degree of warpage of the cantilever 16 changes and the tilt angle of the mirror 42 changes according to the unevenness of the surface of the sample 12 with which the probe 22 is in contact. When the tilt angle of the mirror 42 changes with respect to the reference angle, the position of the laser light incident on the detection surface of the detector 46 also changes according to the tilt angle of the mirror 42. The detector 46 outputs a signal based on the incident position of the laser beam on the detection surface.

  A signal output from the detector 46 is input to a servo circuit (feedback loop circuit) 48. The servo circuit 48 changes the voltage applied to the piezoelectric element of the scanner 18 based on the signal output from the detector 46 so that the position of the laser light incident on the detection surface of the detector 46 becomes the reference position. Let

  The piezoelectric element drives the actuator 40 in the Z direction according to the voltage applied by the servo circuit. Specifically, the piezoelectric element drives the actuator 40 in the Z direction so that the inclination angle of the mirror 42 returns to the reference inclination angle. When the height of the surface of the sample 12 in contact with the tip of the probe 22 is higher than the reference height, a voltage corresponding to the height of the surface of the sample 12 in contact with the tip of the probe 22 is applied to the piezoelectric element. The actuator 40 moves to a position corresponding to the height of the surface of the sample 12 that is applied and the tip of the probe 22 is in contact. Further, when the height of the surface of the sample 12 in contact with the tip of the probe 22 is lower than the reference height, a voltage corresponding to the height of the surface of the sample 12 in contact with the tip of the probe 22 is piezoelectric. The actuator 40 moves downward to a position corresponding to the height of the surface of the sample 12 that is applied to the element and the tip of the probe 22 is in contact with. Thus, the voltage applied to the piezoelectric element is a voltage corresponding to the height of the surface of the sample 12 with which the tip of the probe 22 is in contact.

  The voltage signal input from the servo circuit 48 to the piezoelectric element of the scanner 18 is also input to the AFM image generation unit 20 for generating an AFM image. Since the voltage applied to the piezoelectric element of the scanner 18 is a voltage corresponding to the height of the surface of the sample 12 with which the tip of the probe 22 is in contact, the AFM image generation unit 20 applies the voltage to the piezoelectric element of the scanner 18. Based on the applied voltage signal, the height of the surface of the sample 12 with which the tip of the probe 22 is in contact can be obtained. Information regarding the XY coordinates where the tip of the probe 22 is located is input from the processing unit 10 to the AFM image generation unit 20. The AFM image generation unit 20 generates an AFM image based on the data regarding the height of the surface of the sample 12 with which the tip of the probe 22 is in contact and the information regarding the XY coordinates where the tip of the probe 22 is located. .

The power source 21 is for applying a bias voltage V _bias to the sample 12. The positive side of the power source 21 is electrically connected to an electrode pad 72 provided on the sample 12 via the wiring 50, the electrode 38 and the conductive adhesive 76. The negative side of the power source 21 is connected to the ground potential GND.

  The conductive cantilever 16 is connected to the positive side of the input terminal of the amplifier 24 via the wiring 52. The negative side of the input terminal of the amplifier 24 is connected to the ground potential GND.

  The probe 22 and the conductive cantilever 16 are supplied with a current corresponding to the electrical characteristics of the portion in contact with the probe 22. The current flowing through the probe 22 and the conductive cantilever 16 is amplified by the amplifier 24.

  The signal amplified by the amplifier 24 is input to the current image generation unit 26. The signal input to the current image generation unit 26 is a signal corresponding to the current flowing through the probe 22 and the cantilever 16. The current image generation unit 26 can obtain the current flowing through the probe 22 and the cantilever 16 based on the signal input to the current image generation unit 26. Information regarding the XY coordinates where the tip of the probe 22 is located is input from the processing unit 10 to the current image generation unit 26. The current image generation unit 26 generates a current image based on data relating to the current flowing through the probe 22 and the like and information relating to XY coordinates where the probe 22 is located. The current image is an image representing the distribution of current measured at each location of the sample.

  Data relating to the AFM image generated by the AFM image generation unit 20 is input to the processing unit 10. Data relating to the current image generated by the current image generation unit 26 is also input to the processing unit 10.

  The processing unit 10 displays the AFM image and the current image on the display screen of the display unit 28. Since the AFM image and the current image are associated with the same XY coordinate system, the current image can be displayed so as to correspond to the AFM image. The display unit 28 is configured by, for example, a CRT or a liquid crystal display. In addition, the AFM image and the current image can be printed and displayed by a printer (not shown).

  Thus, the semiconductor evaluation apparatus according to the present embodiment is configured.

  Next, the semiconductor evaluation method according to the present embodiment will be explained with reference to FIGS. FIG. 2 is a cross-sectional view showing a state in which transistors and the like are formed on a semiconductor substrate. FIG. 3 is a process diagram showing a method of polishing the back side of the semiconductor substrate. FIG. 4 is a cross-sectional view showing a state in which the sample is fixed to the sample stage. FIG. 5 is a cross-sectional view showing a state where the thickness of the semiconductor substrate is reduced. 6A and 6B are a plan view and a cross-sectional view illustrating a state where the thickness of the semiconductor substrate is reduced. 6A is a plan view, and FIG. 6B is a cross-sectional view taken along line AA ′ of FIG. 6A. FIG. 7 is a perspective view showing a state in which a sample is set. FIG. 8 is a cross-sectional view showing a state where a sample is set.

  First, as shown in FIG. 2, a semiconductor substrate 54 on which a transistor or the like is formed on the front surface side (first surface side) is prepared.

  For example, a silicon substrate is used as the semiconductor substrate 54. The thickness of the semiconductor substrate 54 is, for example, 0.3 mm or more. A gate electrode 58 is formed on the surface side of the semiconductor substrate 54 via a gate insulating film 56. The gate electrode 58 is constituted by, for example, a laminated film in which a polysilicon film 58a and a metal film 58b are sequentially laminated. The gate length is, for example, about 40 nm. A sidewall insulating film 60 is formed on the side wall portion of the gate electrode 58. A source / drain diffusion layer 62 is formed in the semiconductor substrate 54 on both sides of the gate electrode 58 on which the sidewall insulating film 60 is formed. Thus, the transistor 64 having the gate electrode 58 and the source / drain diffusion layer 62 is formed. An interlayer insulating film 66 is formed on the semiconductor substrate 54 so as to cover the transistor 64. Conductor plugs 68 and wirings 70 are embedded in the interlayer insulating film 66. An electrode pad 72 is formed on the interlayer insulating film 66. The electrode pad 72 is electrically connected to the gate electrode 58 or the source / drain diffusion layer 62 of the transistor 64 through the conductor plug 68 and the wiring 70. A protective film 67 is formed on the interlayer insulating film 66. The electrode pad 72 is exposed from the protective film 67.

  Next, as shown in FIG. 3A, a sample stage 36 made of a transparent material is prepared. The reason why the transparent material is used as the material for the sample stage 36 is that, as will be described later, when observing the equal thickness interference fringes with an optical microscope, it is necessary to make light incident on the sample 12 through the sample stage 36. is there. Examples of the sample stage 36 made of a transparent material include a glass plate and a quartz plate.

  Next, a through hole 74 is formed in the sample stage 36.

Next, the electrode 38 is embedded in the through hole 74. The electrode 38 is for applying a bias voltage V _bias to the sample 12.

  Note that a transparent plate having conductivity may be used as the sample stage 36. Examples of the conductive transparent plate include a glass plate having an ITO film formed on the surface thereof. When a conductive transparent plate is used as the sample stage 36, it is possible to apply a voltage to the sample 12 through the sample stage 36 without embedding the electrode 38 in the sample stage 36.

  Next, as shown in FIGS. 3B and 4, the sample 12 is fixed on the sample stage 36 using a conductive adhesive 76. As the conductive adhesive 76, a transparent conductive adhesive is used. When the sample 12 is bonded to the sample table 36, the surface side (first surface side) of the semiconductor substrate 54, that is, the side on which the transistor 64 and the like are formed faces the sample table 36. In order to fix the sample 12 to the sample stage 36 using the conductive adhesive 76, the electrode 38 is connected to the gate electrode 58 and the source / drain diffusion layer of the transistor 64 via the conductive adhesive 76 and the electrode pad 72. 62 is electrically connected.

  Next, as shown in FIG. 3C, the back surface side (second surface side) of the semiconductor substrate 54 is polished (back surface polishing) using a polishing cloth 78 or the like, and the thickness of the semiconductor substrate 54 is reduced. . When polishing the back surface side of the semiconductor substrate 54, first, the thickness of the semiconductor substrate 54 is reduced to a certain degree by rough polishing (rough polishing), and then mirror polishing is performed by a CMP method or the like (finish polishing). By performing the final polishing, the back surface side of the semiconductor substrate 54 becomes sufficiently flat.

  In this way, the thickness of the semiconductor substrate 54 is reduced as shown in FIGS. In order to evaluate the sample 12 with high resolution and high accuracy, it is necessary to make the thickness t of the semiconductor substrate 54 extremely thin. Specifically, it is desirable that the thickness t of the semiconductor substrate 54 be 1 μm or less.

  The thickness t of the semiconductor substrate 54 thinned by polishing can be obtained by observing equal thickness interference fringes using an optical microscope. The equal thickness interference fringes are interference fringes caused by light reflected on the front and back surfaces of a thin layer whose thickness varies depending on the location. In the equal-thickness interference fringes, portions having the same thickness have the same brightness. When the equal thickness fringes are observed with an optical microscope, the sample stage 36 needs to be transparent in order to allow light to enter the sample 12 through the sample stage 36.

As shown in FIG. 6 (b), the edge of the semiconductor substrate 54, the thickness t ₀ of the semiconductor substrate 54 has a 0 .mu.m. The thickness t of the semiconductor substrate 54 gradually increases from the edge of the semiconductor substrate 54 toward the center. When such a sample 12 is observed with an optical microscope, uniform thickness fringes as shown in FIG. 6A are observed. Therefore, the thickness t of the semiconductor substrate 54 at each location of the sample 12 is obtained based on the number of equal thickness interference fringes with the thickness t ₀ at the edge of the semiconductor substrate 54 having a thickness of 0 μm as a reference. Is possible.

  Thus, the thickness t of the semiconductor substrate 54 thinned by polishing is confirmed.

  Next, as shown in FIG. 1, the sample stage 36 is placed on the XY stage 14. When placing the sample stage 36 on the XY stage 14, the sample stage 36 is placed so that the back surface side (second surface side) of the semiconductor substrate 54 is positioned on the upper side.

  Next, the wiring 50 drawn from the electrode 38 embedded in the sample stage 36 is connected to the positive side of the power source 21.

  Next, as shown in FIGS. 1, 7, and 8, the probe 22 is aligned.

  In this way, the preparation for measuring the sample 12 is completed.

  Next, measurement for the sample 12 is started.

  When starting measurement on the sample 12, an operator (not shown) inputs a command to start measurement of the sample from the input unit 32.

  The processing unit 10 performs predetermined processing based on an instruction from the operator. Specifically, the XY stage 14 is scanned with a voltage applied to the probe 22. The current image generation unit 26 acquires a signal corresponding to the current flowing through the probe 22 in association with the XY coordinates. The AFM image generation unit 20 acquires a voltage signal applied to the piezoelectric element of the scanner 18 in association with the XY coordinates.

  In the claims and specification of the present application, applying a voltage to the probe (probe) includes all cases in which a bias voltage is applied between the probe 22 and the sample 12. That is, the sample 12 may be connected to the positive side of the power source 21 and the probe 22 may be connected (grounded) to the negative side of the power source 21, or the sample 12 may be connected (grounded) to the negative side of the power source 21. May be connected to the positive side of the power source 21.

  FIG. 9 is a conceptual diagram showing the relationship between the thickness of the semiconductor substrate and the resolution in measurement. FIG. 9A shows a case where the thickness of the semiconductor substrate is relatively thick, and FIG. 9B shows a case where the thickness of the semiconductor substrate is relatively thin.

  Electrons flowing from the probe 22 into the semiconductor substrate 54 diverge within the semiconductor substrate 54. As shown in FIG. 9A, when the thickness t of the semiconductor substrate 54 is relatively thick, the electrons diverge into a relatively wide area and flow into the gate electrode 58 side, so that measurement is performed with a very high resolution. In other words, variations in measurement values and noise are relatively large.

  On the other hand, as shown in FIG. 9B, when the thickness t of the semiconductor substrate 54 is extremely thin, electrons flow into the gate electrode 58 in a state where the electrons are concentrated in a very narrow region. Therefore, it is possible to measure with a very high resolution, and it is possible to reduce variations in measurement values and noise. Therefore, by making the thickness t of the semiconductor substrate 54 extremely thin as in the present embodiment, it becomes possible to perform measurement with high resolution and high accuracy.

  Next, the processing unit 10 uses the data related to the current image generated by the current image generation unit 26 and the data related to the AFM image generated by the AFM image generation unit 20 to display the current image and the AFM image on the display 28. Is displayed on the display screen.

  FIG. 10 is a conceptual diagram showing a current image obtained by the semiconductor evaluation method according to the present embodiment. The current image shown in FIG. 10 is obtained by causing the probe 22 to scan the region 81 including the region where the gate electrode 58 is formed, as shown in FIG. In FIG. 10, the magnitude of the current is expressed by changing the brightness of the display color. The darker the display color, the smaller the current, and the lighter the display color, the larger the current.

  As can be seen from FIG. 10, the current flowing through the region where the sidewall insulating film 60 is formed is very small. In addition, a uniform current flows in the region where the sidewall insulating film 60 is formed. Since the current flows uniformly, it can be seen that there is no portion where an abnormal current flows in the region where the sidewall insulating film 60 is formed.

  Also, as can be seen from FIG. 10, the current flowing through the region where the source / drain diffusion layer 62 is formed is larger than the current flowing through the region where the sidewall insulating film 60 is formed. In addition, a uniform current flows through the source / drain diffusion layer 62. Since the current flows uniformly, it can be seen that there is no portion where an abnormal current flows in the region where the source / drain diffusion layer 62 is formed.

  Further, as can be seen from FIG. 10, the current flowing through the region where the gate electrode 58 and the gate insulating film 56 are formed is larger than the current flowing through the region where the source / drain diffusion layer 62 is formed. In addition, a relatively large current flows in a part of the region 80 where the gate insulating film 56 is formed. From this, it can be seen that a region 80 where a relatively large leakage current flows exists in a part of the gate insulating film 56.

  As described above, according to the present embodiment, it is possible to specify a portion where an abnormal leakage current flows with high resolution and high accuracy. Further, according to the present embodiment, the leakage current value can be measured with high resolution and high accuracy.

  As described above, in this embodiment, the thickness of the semiconductor substrate 54 is extremely thin by polishing the back surface side of the semiconductor substrate 54, and the probe 22 is applied to the back surface side of the semiconductor substrate 54 in a state where a voltage is applied to the probe 22. And the probe 22 is scanned to measure the sample 12. Since the semiconductor substrate 54 is extremely thin, electrons flowing from the probe 22 into the semiconductor substrate 54 flow into the transistor 64 while being concentrated in a very narrow region. For this reason, according to this embodiment, it is possible to measure with high resolution and high accuracy. In addition, since the polishing is performed on the back surface side of the semiconductor substrate 54, the transistor or the like formed on the front surface side of the semiconductor substrate 54 is not damaged. Therefore, according to the present embodiment, the sample can be evaluated with high resolution and high accuracy without damaging the sample.

  Moreover, according to the present embodiment, since the AFM image is acquired together with the current image, the AFM image and the current image can be displayed so as to correspond to each other. Therefore, according to the present embodiment, the measurement result can be easily used as an effective guideline for device development.

(Modification)
Next, modified examples of the semiconductor evaluation method according to the present embodiment will be described with reference to FIGS. 11 and 12 are process diagrams showing a semiconductor evaluation method according to this modification.

  In the semiconductor evaluation method according to this modification, after the rough polishing is performed on the semiconductor substrate 54, the semiconductor substrate 54 is partially thinned to partially form a region where the semiconductor substrate 54 is extremely thin. There is a main feature.

  First, since the process until the sample 12 is fixed on the sample stage 36 is the same as the semiconductor evaluation method described above with reference to FIGS. 3A and 3B, the description thereof is omitted (FIG. 11A). ) And FIG. 11 (b)).

  Next, as shown in FIG. 11C, the back surface side of the semiconductor substrate 54 is polished using a polishing cloth 78 or the like (rough polishing). Thereby, the thickness of the semiconductor substrate 54 is reduced to some extent.

  Next, as shown in FIG. 12A, the back side of the semiconductor substrate 54 is partially thinned using a dimple grinder 82. The dimple grinder 82 is a polishing apparatus capable of partially thinning a sample by pressing a cylindrical wheel 86 having a polishing cloth 84 around it against the sample while rotating.

  FIG. 13 is a schematic view showing a state in which the semiconductor substrate is partially thinned. FIG. 13A is a plan view, and FIG. 13B is a cross-sectional view taken along the line AA ′ of FIG.

As shown in FIG. 13B, the thickness t of the semiconductor substrate 54 is partially reduced. When such a sample 12 is observed with an optical microscope, an equal thickness interference fringe as shown in FIG. 13B is observed. The thickness t ₀ at the edge of the semiconductor substrate 54 can be measured using a film thickness inspection apparatus or the like. The thickness t of the semiconductor substrate 54 at each location of the sample 12 can be obtained based on the number of equal thickness interference fringes with the thickness t ₀ at the end of the semiconductor substrate 54 as a reference.

  In this way, the thickness t of the polished semiconductor substrate 54 is confirmed.

  The subsequent semiconductor evaluation method is the same as the above-described semiconductor evaluation method according to the present embodiment, and thus the description thereof is omitted.

  Thus, the semiconductor substrate 54 may be partially thinned using the dimple grinder 82 or the like.

[Second Embodiment]
A semiconductor evaluation apparatus and a semiconductor evaluation method according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 14 is a schematic diagram showing the semiconductor evaluation apparatus according to the present embodiment. FIG. 15 is a perspective view showing a state in which the sample is set. The same components as those in the semiconductor evaluation method according to the first embodiment shown in FIG. 1 to FIG.

  The semiconductor evaluation apparatus and the semiconductor evaluation method according to the present embodiment are mainly characterized in that measurement is performed while appropriately applying a bias voltage to each of the plurality of electrode pads 72.

  As shown in FIG. 15, the thickness t of the semiconductor substrate 54 is reduced by polishing. Since the method for reducing the thickness t of the semiconductor substrate 54 is the same as the semiconductor evaluation method according to the first embodiment, the description thereof is omitted.

  In the present embodiment, since the voltage is applied to the sample via the conductor plugs 88a to 88d embedded in the semiconductor substrate 54 or the like, it is not necessary to embed the electrode 38 in the sample stage 36.

  A conductor plug 88 a is embedded in the semiconductor substrate 54 and the interlayer insulating film 66. One end of the conductor plug 88 a is connected to an electrode pad 72 a electrically connected to the source diffusion layer 62 a of the transistor 64. The other end of the conductor plug 88 a is exposed on the back surface side (second surface side) of the semiconductor substrate 54. In FIG. 15, the back surface side (second surface side) of the semiconductor substrate 54 is located on the upper side of the paper surface, and the front surface side (first surface side) of the semiconductor substrate 54 is located on the lower side of the paper surface. .

  In addition, a conductor plug 88 b is embedded in the semiconductor substrate 54 and the interlayer insulating film 66. One end of the conductor plug 88 b is connected to an electrode pad 72 b that is electrically connected to the gate electrode 58 of the transistor 64. The other end of the conductor plug 88 b is exposed on the back side of the semiconductor substrate 54.

  A conductor plug 88 c is embedded in the semiconductor substrate 54 and the interlayer insulating film 66. One end of the conductor plug 88 c is connected to an electrode pad 72 c that is electrically connected to the drain diffusion layer 62 b of the transistor 64. The other end of the conductor plug 88 c is exposed on the back side of the semiconductor substrate 54.

  A conductor plug 88d is embedded in the semiconductor substrate 54 and the interlayer insulating film 66. One end of the conductor plug 88 d is connected to an electrode pad 72 d that is electrically connected to the semiconductor substrate 54. The other end of the conductor plug 88d is exposed on the back side of the semiconductor substrate 54.

  For the conductor plugs 88a to 88d, after the semiconductor substrate 54 is thinned by polishing, contact holes are formed in the semiconductor substrate 54 and the interlayer insulating film 66 using, for example, FIB (Focused Ion Beam), and the conductor plugs are formed in the contact holes. It can be formed by embedding 88a to 88d.

  The sample 12a is fixed to the sample table 36 (see FIG. 14) with a non-conductive adhesive 76a. The reason why the sample 12a is fixed to the sample table 36 by using a non-conductive adhesive is to prevent the electrode pads 72a to 72d from being electrically connected to each other via the adhesive.

As shown in FIG. 14, the positive side of the power source 21a is connected to the conductor plug 88a. A bias voltage V _bias1 is applied to the conductor plug 88a by the power source 21a.

The positive side of the power source 21b is connected to the conductor plug 88b. A bias voltage V _bias2 is applied to the conductor plug 88b by the power source 21b.

The positive side of the power source 21c is connected to the conductor plug 88c. A bias voltage V _bias3 is applied to the conductor plug 88c by the power source 21c.

The positive side of the power source 21d is connected to the conductor plug 88d. A bias voltage V _bias4 is applied to the conductor plug 88d by the power source 21d.

  The minus side of the power supplies 21a to 21d is connected to the ground voltage GND.

The bias voltages V _{bias1 to} V bias ₄ are appropriately set so that, for example, the transistor 62 operates.

In this way, the bias voltages V _{bias1 to} V bias ₄ are independently applied to each of the plurality of electrode pads 72a to 72d.

The semiconductor evaluation method according to the present embodiment is the same as the semiconductor evaluation method according to the first embodiment described above, _except that measurement is performed while appropriately applying the bias voltages V _{bias1 to} V bias 4 to each of the plurality of electrode pads 72a to 72d. Therefore, the description is omitted.

As described above, according to the present embodiment, the conductor plugs 88a to 88d are embedded in the semiconductor substrate 54 and the like, and the bias voltages V _{bias1 to} V bias ₄ are appropriately applied to the electrode pads 72a to 72d via the conductor plugs 88a to _88d. Therefore, the measurement can be performed in a state where the specific transistor 62 is operated. Therefore, according to this embodiment, a very useful measurement result can be acquired and it can become a useful guideline for device development.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications can be made.

  For example, in the embodiment described above, the sample 12 is connected to the positive side of the power source 21 and the probe 22 is connected to the negative side of the power source 21. However, the probe 22 is connected to the positive side of the power source 21. The sample 12 may be connected to the negative side of the power source 21.

  In the above embodiment, the case where the current flowing through the probe 22 is measured has been described as an example. However, the potential of the probe 22 may be measured. In this case, a potential image of the sample is obtained. Note that the potential image is an image representing the distribution of potential measured at each location of the sample.

  As described above in detail, the features of the present invention are summarized as follows.

(Appendix 1)
Using a scanning probe microscope, a sample comprising a semiconductor device having a semiconductor substrate, a semiconductor element formed on the first surface side of the semiconductor substrate, and an insulating layer formed to cover the semiconductor element is obtained. A semiconductor evaluation method for evaluating,
A first step of fixing the sample on the sample stage such that the side of the sample on which the insulating layer is formed contacts the sample stage;
A second step of reducing the thickness of the semiconductor substrate to a predetermined thickness by polishing the second surface side of the semiconductor substrate;
And applying a voltage to the probe of the scanning probe microscope, bringing the probe into contact with the second surface side of the semiconductor substrate, and measuring a current flowing through the probe. A semiconductor evaluation method.

(Appendix 2)
In the semiconductor evaluation method according to attachment 1,
In the second step, the thickness of the semiconductor substrate in a region where the semiconductor element to be measured is formed is partially reduced.

(Appendix 3)
In the semiconductor evaluation method according to attachment 1 or 2,
In the second step, the thickness of the semiconductor substrate is reduced until the thickness of the semiconductor substrate in the region where the semiconductor element to be measured is formed becomes 1 μm or less. Method.

(Appendix 4)
In the semiconductor evaluation method according to any one of appendices 1 to 3,
The sample stage is made of a material that transmits light,
In the second step, the thickness of the semiconductor substrate is measured based on the equal thickness interference fringe observed when light is introduced into the sample.

(Appendix 5)
In the semiconductor evaluation method according to any one of appendices 1 to 4,
The sample further includes an electrode pad that is electrically connected to the semiconductor element and exposed on the insulating layer;
The sample stage is a conductive sample stage,
The sample is fixed to the sample stage via a conductive adhesive,
A voltage is applied to the electrode pad through the sample stage and the conductive adhesive. A semiconductor evaluation method, wherein:

(Appendix 6)
In the semiconductor evaluation method according to any one of appendices 1 to 4,
The sample further includes an electrode pad electrically connected to the semiconductor element and exposed on the insulating layer,
An electrode is embedded in the sample stage,
The sample is fixed to the sample stage via a conductive adhesive,
A voltage is applied to the electrode pad through the electrode and the conductive adhesive. A semiconductor evaluation method, wherein:

(Appendix 7)
In the semiconductor evaluation method according to any one of appendices 1 to 4,
The sample further includes a plurality of conductor plugs electrically connected to each part of the semiconductor element and exposed on the second surface side of the semiconductor substrate,
A voltage is applied to each part of the semiconductor element through the plurality of conductor plugs. A semiconductor evaluation method, comprising:

(Appendix 8)
In the semiconductor evaluation method according to any one of appendices 1 to 7,
The semiconductor evaluation method further comprising a fourth step of displaying a current image based on the current measured at each location of the sample.

(Appendix 9)
In the semiconductor evaluation method according to attachment 8,
In the fourth step, the current image is displayed in correspondence with an atomic force microscope image.

(Appendix 10)
Using a scanning probe microscope, a sample comprising a semiconductor device having a semiconductor substrate, a semiconductor element formed on the first surface side of the semiconductor substrate, and an insulating layer formed to cover the semiconductor element is obtained. A semiconductor evaluation device for evaluation,
Voltage applying means for applying a voltage to the probe of the scanning probe microscope;
A semiconductor evaluation apparatus comprising: a current measuring unit configured to measure the current flowing through the probe by bringing the probe into contact with the second surface side of the semiconductor substrate thinned to a predetermined thickness.

It is the schematic which shows the semiconductor evaluation apparatus by 1st Embodiment of this invention. It is sectional drawing which shows the state which formed the transistor etc. on the semiconductor substrate. It is process drawing which shows the method of grind | polishing the back surface side of a semiconductor substrate. It is sectional drawing which shows the state which fixed the sample to the sample stand. It is sectional drawing which shows the state which made thickness of a semiconductor substrate thin. It is the top view and sectional drawing which show the state which made the thickness of the semiconductor substrate thin. It is a perspective view which shows the state in which the sample is set. It is sectional drawing which shows the state in which the sample is set. It is a conceptual diagram which shows the relationship between the thickness of a semiconductor substrate, and the resolution | decomposability in a measurement. It is a conceptual diagram which shows the electric current image obtained by the semiconductor evaluation method by one Embodiment of this invention. It is process drawing (the 1) which shows the semiconductor evaluation method by the modification of 1st Embodiment of this invention. It is process drawing (the 2) which shows the semiconductor evaluation method by the modification of 1st Embodiment of this invention. It is the schematic which shows the state which made the semiconductor substrate partially thin. It is the schematic which shows the semiconductor evaluation apparatus by 2nd Embodiment of this invention. It is a perspective view which shows the state in which the sample is set. It is sectional drawing which shows the evaluation method of the conventional semiconductor device. It is process drawing which shows the semiconductor evaluation method proposed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Processing part 12, 12a ... Sample 14 ... XY stage 16 ... Cantilever 18 ... Scanner 20 ... AFM image generation part 21, 21a-21d ... Power source 22 ... Probe 24 ... Amplifier 26 ... Current image generation part 28 ... Display DESCRIPTION OF SYMBOLS 30 ... Memory | storage part 32 ... Input part 34 ... XY scanning circuit 36 ... Sample stage 38 ... Electrode 40 ... Actuator 42 ... Mirror 44 ... Laser light source 46 ... Detector 48 ... Servo circuit 50 ... Wiring 52 ... Wiring 54 ... Semiconductor substrate 56 ... Gate insulating film 58 ... Gate electrode 58a ... Polysilicon film 58b ... Metal film 60 ... Side wall insulating film 62 ... Source / drain diffusion layer 62a ... Source diffusion layer 62b ... Drain diffusion layer 64 ... Transistor 66 ... Interlayer insulating film 67 Protective film 68 Conductor plug 70 Wiring 72, 72a to 72d Electrode pad 74 Through hole 76 Conductive adhesive 76 ... Non-conductive adhesive 78 ... Polishing cloth 80 ... Region 82 where leakage current is large ... Dimple grinder 84 ... Polishing cloth 86 ... Wheels 88a to 88d ... Conductor plug 122 ... Probe 154 ... Semiconductor substrate 156 ... Gate insulating film 158 ... Gate electrode 158a ... polysilicon film 158b ... metal film 160 ... sidewall insulating film 162 ... source / drain diffusion layer 164 ... transistor 166 ... interlayer insulating film 167 ... protective film 168 ... conductor plug 170 ... wiring 172 ... electrode pad

Claims (5)

Using a scanning probe microscope, a sample comprising a semiconductor device having a semiconductor substrate, a semiconductor element formed on the first surface side of the semiconductor substrate, and an insulating layer formed to cover the semiconductor element is obtained. A semiconductor evaluation method for evaluating,
A first step of fixing the sample on the sample stage such that the side of the sample on which the insulating layer is formed contacts the sample stage;
A second step of reducing the thickness of the semiconductor substrate to a predetermined thickness by polishing the second surface side of the semiconductor substrate;
And applying a voltage to the probe of the scanning probe microscope, bringing the probe into contact with the second surface side of the semiconductor substrate, and measuring a current flowing through the probe. A semiconductor evaluation method. The semiconductor evaluation method according to claim 1,
In the second step, the thickness of the semiconductor substrate in a region where the semiconductor element to be measured is formed is partially reduced. In the semiconductor evaluation method according to claim 1 or 2,
In the second step, the thickness of the semiconductor substrate is reduced until the thickness of the semiconductor substrate in the region where the semiconductor element to be measured is formed becomes 1 μm or less. Method. In the semiconductor evaluation method according to any one of claims 1 to 3,
The sample further includes a plurality of conductor plugs electrically connected to each part of the semiconductor element and exposed on the second surface side of the semiconductor substrate,
A voltage is applied to each part of the semiconductor element through the plurality of conductor plugs. A semiconductor evaluation method, comprising: Using a scanning probe microscope, a sample comprising a semiconductor device having a semiconductor substrate, a semiconductor element formed on the first surface side of the semiconductor substrate, and an insulating layer formed to cover the semiconductor element is obtained. A semiconductor evaluation device for evaluation,
Voltage applying means for applying a voltage to the probe of the scanning probe microscope;
A semiconductor evaluation apparatus comprising: a current measuring unit configured to measure the current flowing through the probe by bringing the probe into contact with the second surface side of the semiconductor substrate thinned to a predetermined thickness.

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