JP2006065850A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer capable of minimizing a bottleneck caused by data linkage at memory access generated when a CPU and an accelerator are operated in cooperation with each other to enhance multimedia processing performance. <P>SOLUTION: This multimedia microcomputer 1 has the CPU 11 and the accelerator 12 and is adapted to execute multimedia processing by cooperating the CPU 11 with the accelerator 12. In order to eliminate a bottleneck by memory access generated for implementing data linkage between the CPU 11 and the accelerator 12 via a memory 2, an I/O-specific cache 14 accessible by the CPU 11 and the accelerator 12 in common is formed in front of the memory 2, and data required for data linkage are kept in the I/O-specific cache 14, whereby the speed of the data linkage between the CPU 11 and the accelerator 12 is increased and the speed-up of multimedia processing is obtained. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a microcomputer (hereinafter, simply referred to as a microcomputer), and more particularly to a technique that is effective when applied to a microcomputer that performs communication and multimedia processing including an auxiliary circuit such as an accelerator in addition to processing by a CPU.

  According to a study by the present inventor, the following techniques can be considered for a microcomputer that performs multimedia processing.

  For example, a microcomputer that performs multimedia processing incorporates an accelerator that assists the CPU in addition to the CPU in order to improve the performance of the multimedia processing. This accelerator performs high-speed multimedia processing by performing high-speed processing using hardware that is particularly difficult for the CPU, and performing collaborative work (hereinafter referred to as data linkage) between the CPU and the accelerator. It has become.

  The CPU and accelerator have a built-in cache in order to prevent processing degradation due to waiting for memory access, that is, a bottleneck. Therefore, when the contents of the memory are changed by another accelerator, the data in the cache is discarded and the CPU again sets the address to eliminate the mismatch between the data in the CPU cache and the data in the memory. When accessed, the data is read from the memory into the cache, thereby maintaining data coincidence between the cache and the memory, that is, cache coherency.

  Therefore, even if the cache is built in the CPU or accelerator, data linkage between the CPU and the accelerator is not benefited from the cache, and is performed by directly accessing the memory.

For example, Patent Document 1 and Patent Document 2 are examples of techniques for accessing a memory from a CPU or an accelerator. Patent Document 1 discloses a technique that enables an accelerator to quickly access a memory. Patent Document 2 discloses a technique that enables a CPU to quickly access a memory.
Japanese Patent Laid-Open No. 11-161598 JP 2001-216194 A

  By the way, as a result of examination by the present inventor regarding the microcomputer for performing the multimedia processing as described above, the following has been clarified.

  For example, in recent years, due to advances in semiconductor manufacturing technology, multimedia processing systems have been made into system LSIs, and a plurality of accelerators are mounted on one chip, and the accelerator itself has been accelerated at the same speed as a CPU.

  For this reason, the load on the memory has increased and it has become important to increase the access speed. What is important here is the speed at which the data written in the memory is read, that is, the latency. However, in SDRAM and DDR-SDRAM, although the memory access throughput has been improved, the overhead associated with the command input is large and the latency is lowered.

  Therefore, when data is linked between the CPU and the accelerator, the CPU waits for the accelerator to process and after the data processed by the accelerator is written to the memory, the CPU reads the data from the memory until the CPU reads the data. Wait for memory access. In other words, a phenomenon has occurred in which multimedia processing is rate-limited to a memory that is slower than a CPU or an accelerator. In addition, due to advances in semiconductor manufacturing technology, multiple accelerators are built in one chip, and when data linkage occurs between the CPU and multiple accelerators, the CPU is increasingly waiting for memory. The effect of a decrease in processing speed is increased.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a microcomputer capable of improving multimedia processing performance by minimizing a bottleneck caused by data cooperation in memory access that occurs when a CPU and an accelerator operate in cooperation. There is.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention is applied to a microcomputer that has a CPU that operates as a master and an accelerator that operates as a slave and can access a memory from the CPU and the accelerator, and has the following characteristics.

  In other words, in the microcomputer of the present invention, the data that the CPU and the accelerator access to the memory is composed of linked data that the CPU and the accelerator exchange with each other and the data body other than the linked data. Having an I / O dedicated cache.

  In the microcomputer of the present invention, the I / O dedicated cache has a function of determining whether or not to hold write access request data when a write access request from the CPU and accelerator to the memory is made. Further, the accelerator has a function of issuing a holding request to the I / O dedicated cache when performing write access to the memory. Further, the I / O dedicated cache has a function of determining whether to hold data output from the accelerator in response to a holding request output at the time of write access to the memory from the accelerator. The I / O dedicated cache has a function of determining whether to hold data based on addresses output from the CPU and the accelerator when the CPU and the accelerator perform a write access to the memory.

  In the microcomputer of the present invention, the I / O-dedicated cache is an I / O when the I / O-dedicated cache holds read access request data at the time of a read access request from the accelerator to the memory. The dedicated cache has a function of outputting data to the accelerator.

  Further, the microcomputer of the present invention includes a memory controller that controls access to the memory from the CPU and the accelerator, and has a priority order for access requests from the CPU and the accelerator. It has a function of processing an access request from an accelerator. Further, the memory is SDRAM or DDR-SDRAM, and the memory controller has a function of continuously accessing the same bank and the same row address of the memory in response to an access request from the CPU and the accelerator. Further, the memory controller has a function of managing the dependency relationship for the access to the same address among the access requests from the CPU and the accelerator to keep the access to the memory consistent.

  In the microcomputer of the present invention, the memory is provided outside the microcomputer. Alternatively, the memory is provided inside the microcomputer.

  Specifically, the microcomputer of the present invention has a CPU and an accelerator, and occurs in the multimedia microcomputer in which the CPU and the accelerator cooperate to perform multimedia processing, because the data cooperation between the CPU and the accelerator is performed through the memory. In order to eliminate the bottleneck caused by memory access, an I / O dedicated cache that can be accessed in common by the CPU and accelerator is provided in front of the memory, and linked data required for data linkage is held in the I / O dedicated cache. As a result, the data linkage between the CPU and the accelerator is speeded up, and the speed of multimedia processing is realized.

  In the microcomputer of the present invention, the CPU has a cache inside.

  In the microcomputer of the present invention, the microcomputer is connected to an external memory, and a program or work area is formed in the external memory. In addition, an accelerator data area is formed in the external memory.

  In the microcomputer of the present invention, the internal cache of the CPU has a snoop function.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, it is possible to minimize a bottleneck caused by data cooperation in memory access that occurs when a CPU and an accelerator operate in cooperation with each other. Therefore, it is possible to improve multimedia processing performance.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  An example of the configuration and operation of a multimedia microcomputer according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a multimedia microcomputer. FIG. 2 is a diagram illustrating the configuration of the memory. FIG. 3 is a block diagram showing another multimedia microcomputer.

  As shown in FIG. 1, the multimedia microcomputer 1 of the present embodiment is characterized by a CPU 11 that operates as a master, a plurality of accelerators 12 (12-1 to 12-n) that operate as slaves, and the present invention. It is composed of an I / O dedicated cache 14, a bus 13 for connecting them, and a memory controller 15. A memory 2 is connected to the outside of the multimedia microcomputer 1.

  The accelerator 12 has a function of assisting the CPU 11 and has a function of executing a time-consuming process that the CPU 11 is not good at using hardware. The memory controller 15 is connected to the I / O dedicated cache 14 and the memory 2, and in response to a memory access request coming via the bus 13 and the I / O dedicated cache 14, the memory controller 15 sends SDRAM or DDR to the memory 2. -It has a function of issuing an SDRAM command to access.

  As shown in FIG. 2, the memory 2 stores a program 21 describing a series of procedure processes related to multimedia processing executed by the CPU 11, a work area 22, and data to be processed for each accelerator 12. There is a data area 23 (23-1 to 23-n). In addition, a common data area 23 may be accessed among a plurality of accelerators 12.

  As shown in FIG. 3, in the multimedia microcomputer of the present embodiment, in addition to the configuration in which the memory 2 is connected to the outside as shown in FIG. 1, the memory 2 is provided inside, and the memory 2 and the CPU 11 The multimedia microcomputer 10 in which the plurality of accelerators 12 (12-1 to 12-n), the I / O dedicated cache 14, the bus 13, and the memory controller 15 are integrated is also possible.

  Next, an operation when the I / O dedicated cache 14 is OFF in the multimedia microcomputer 1 shown in FIG. 1 will be described. The same applies to the multimedia microcomputer 10 shown in FIG.

  The CPU 11 performs processing by accessing the program 21, the work area 22, and the data in the data area 23 from the memory 2 via the bus 13, the I / O dedicated cache 14, and the memory controller 15. At this time, the CPU 11 sets data to be processed by the accelerator 12 in the data area 23 according to the program 21, requests processing to the accelerator 12, and reads the processing result in the accelerator 12 from the data area 23, so that MPEG or Multimedia processing including MP3 is realized.

  In this way, in the multimedia microcomputer 1, data processing is performed between the CPU 11 and the accelerator 12 via the data area 23 in the memory 2, and multimedia processing is executed. Therefore, the memory 2 having a slower access speed than the processing speed of the CPU 11 and the accelerator 12 has become a bottleneck in multimedia processing, and it has become difficult to improve multimedia processing performance. Therefore, in the present embodiment, as will be described later, it is possible to realize high-speed multimedia processing by smoothly exchanging data between the CPU 11 and the accelerator 12.

  That is, as shown in FIG. 1, the I / O dedicated cache 14 is placed on the memory controller 15 side so that it can be accessed from both the CPU 11 and the accelerator 12, and the cooperation data between the CPU 11 and the accelerator 12 is held. As a result, data linkage between the CPU 11 and the accelerator 12 is performed by the I / O dedicated cache 14 that can be accessed at a higher speed, and the overhead caused by waiting for memory access is greatly reduced, so that smooth multimedia processing can be executed. .

  Note that the data necessary for data linkage between the CPU 11 and the accelerator 12 is not all data to be processed by the accelerator 12, but only a part of the header, commands to the accelerator 12, and the like. The cache 14 holds only linkage data that is data necessary for linkage, and the data body that is data processed only by the CPU 11 and only the accelerator 12 is placed on the memory 2 instead of the I / O dedicated cache 14. The amount of data held in the I / O dedicated cache 14 is suppressed, and effective use of the I / O dedicated cache 14 and improvement of the hit rate are realized.

  It should be noted here that the cooperation data to be held by the I / O dedicated cache 14 is data that is always written into the memory 2 by the CPU 11 or the accelerator 12. Therefore, the I / O dedicated cache 14 only needs to determine whether or not to cache only for write access to the memory 2. For this determination, there is a method of using the address of the write access and the I / O. There are two methods using a cache request signal to the dedicated cache 14. Note that the cache determination in the write access from the CPU 11 can use the determination using the address, and the cache determination in the write access from the accelerator 12 can use both the determination using the address and the determination based on the cache request signal. .

  On the other hand, regarding the read to the memory 2, if a hit occurs, the data is output from the I / O dedicated cache 14, but in the case of a cache miss, the I / O dedicated cache 14 only passes the access to the memory 2, and the memory The read data from 2 is not cached. This is because the CPU 11 and the accelerator 12 have a dedicated cache or buffer, and read data from the memory 2 is held in the dedicated cache or buffer. Further, in order to cope with the case where the bus 13 is a split bus, the I / O dedicated cache 14 causes a cache miss, and even if the memory 2 is being read-accessed, a cache hit is detected in response to the next access request. In this case, a function for outputting the hit data to the bus 13 is required. This is where the I / O dedicated cache 14 is significantly different from conventional caches and buffers.

  Another feature is that the I / O dedicated cache 14 is a cache, and the program 21 executed by the CPU 11 is processed as an access to the memory 2 without being aware of the existence of the I / O dedicated cache 14. This is a possible point.

  Further, in order to improve the access efficiency to the memory 2, the I / O dedicated cache 14 uses the I / O dedicated cache 14 when the access size requested from the CPU 11 or the accelerator 12 is smaller than the access size of the memory 2. By using and collectively accessing the memory 2, it is possible to reduce the number of accesses to the memory 2 and to reduce bottlenecks due to memory waiting.

  Next, an example of the flow of multimedia processing executed by the multimedia microcomputer will be described with reference to FIG. FIG. 4 is a diagram showing the flow of multimedia processing.

  As shown in FIG. 4, in the multimedia microcomputer 1, the CPU 11 and the accelerator 12 cooperate to perform multimedia processing, the processing executed by the CPU 11 (1000), and the processing executed by the accelerator 12 (1100). ). The multimedia processing executed by the CPU 11 includes two processes, a pre-process (1001) and a post-process (1009), which are performed before and after the process (1005) by the accelerator 12, respectively.

  First, when the CPU 11 performs preprocessing (1001), the CPU 11 writes the data in the data area 23 in order to pass the data to the accelerator 12 (1002), and issues an activation request to the accelerator 12 (1003). In response to this, the accelerator 12 reads data from the data area 23 (1004), performs processing in the accelerator 12 (1005), writes the processing result back to the data area 23 (1006), and then processes it to the CPU 11. An end report is raised (1007). When the CPU 11 receives the processing end report from the accelerator 12, the CPU 11 reads the processing result by the accelerator 12 from the data area 23 (1008) and performs post-processing (1009). Further, depending on the processing contents, there are cases where there is no pre-processing (1001) and processing is started from the accelerator 12, or there is no post-processing (1009) and processing ends by the accelerator 12.

  As described above, the CPU 11 and the accelerator 12 perform data cooperation via the data area 23 and execute multimedia processing.

  Next, an example of the data flow of multimedia processing using the I / O dedicated cache will be described with reference to FIGS. 5 and 6 with reference to FIG. 5 and 6 are diagrams illustrating the flow of data in multimedia processing. FIG. 5 illustrates processing from pre-processing (1001) to accelerator processing (1005) in FIG. 4, and FIG. 6 illustrates processing result sets in FIG. The processes from (1006) to post-processing (1009) are respectively shown.

  First, as shown in FIG. 5, the CPU 11 performs preprocessing (1001), and writes the result data into the data area 23 for processing by the accelerator 12 (1002, 101). At this time, the I / O dedicated cache 14 caches the write data from the CPU 11 to the data area 23 and writes the write data to the data area 23 in the memory 2 (102). At this time, the I / O dedicated cache 14 determines whether the data to be cached is based on whether it is the data area 23 based on the address of the write destination output from the CPU 11 together with the write data.

  Thereafter, the CPU 11 outputs an activation request signal to the accelerator 12 (1003). In response to this, the accelerator 12 is activated and reads the data from the data area 23 (1004). At this time, the linkage data of the portion where the write data is cached on the I / O dedicated cache 14 is read from the I / O dedicated cache 14 (103), and the portion of the linkage data not cached in the I / O dedicated cache 14 is read. The data body is directly read from the data area 23 of the memory 2 (104), and the accelerator 12 performs processing (1005) on the read data.

  Subsequently, as shown in FIG. 6, when the processing by the accelerator 12 (1005) is completed, the processing result is written back to the data area 23 (1006, 111). At this time, the I / O dedicated cache 14 caches the write data from the accelerator 12 to the data area 23 and writes the processed data to the data area 23 in the memory 2 (112). At this time, the I / O dedicated cache 14 determines whether the data to be cached is based on a cache request signal output from the accelerator 12 together with the processing data or a write destination address.

  Thereafter, upon receiving a processing end report (1007) from the accelerator 12, the CPU 11 reads the processing data from the data area 23 (1008). At this time, since the data processed by the CPU 11 is the cooperative data of the portion where the processing data is cached on the I / O dedicated cache 14, the CPU 11 reads only from the I / O dedicated cache 14 (113). Post-processing (1009) can be performed. At this time, the data is read from the data area 23 of the memory 2 only when there is a portion that is not cached due to the capacity of the I / O dedicated cache 14 (114).

  As described above, the CPU 11 and the accelerator 12 perform data cooperation through the high-speed I / O dedicated cache 14 having a shorter access latency than the memory 2, thereby comparing with data cooperation through the data area 23 in the memory 2. Thus, the access waiting time, which is an overhead, can be greatly reduced, and the multimedia processing speed can be increased.

  Further, when the CPU 11 performs post-processing, the CPU 11 rarely reads out all the processing data by the accelerator 12, and when the processing data is written in the memory 2, the portion of the cooperation data that is the data read by the CPU 11 is changed. The data is cached in the I / O dedicated cache 14, and the other data body is not cached on the I / O dedicated cache 14, but is directly written in the data area 23 in the memory 2.

  When processing is performed by the accelerator 12, the accelerator 12 basically accesses the data area 23 for consecutive addresses. Therefore, paying attention to the memory 2 that is a high-speed memory such as SDRAM or DDR-SDRAM, only the first of the data area 23 is held in the I / O-dedicated cache 14, and then the continuation of the memory 2 is continued. Use the method expected for access performance.

  By adopting the above method, it is possible to reduce the portion of the cooperative data cached on the I / O dedicated cache 14 and realize effective use of the I / O dedicated cache 14.

  Next, the structure and operation of the I / O dedicated cache will be described in detail with reference to FIGS. FIG. 7 is a diagram illustrating the configuration of the bus. FIG. 8 is a diagram showing the configuration of the I / O dedicated cache. FIG. 9 is a diagram illustrating a configuration of a register. FIGS. 10A and 10B are diagrams showing register access paths in the I / O dedicated cache. FIG. 11 is a diagram showing a flow of processing in the determination circuit. FIG. 12 is a diagram illustrating a configuration of the address determination circuit. FIG. 13 is a diagram illustrating a configuration of a cache. FIG. 14 is a diagram illustrating a cache operation.

  As shown in FIG. 7, the bus 13 includes an address bus 131 and a data bus 132. The address bus 131 includes an access destination address 1311, an access signal 1312, and a cache request signal 1313 from the accelerator 12. The data bus 132 includes a read data bus 1321 and a write data bus 1322.

  As shown in FIG. 8, the I / O dedicated cache 14 is connected to the bus 13 and the memory controller 15 and includes a register 141, a determination circuit 142, and a cache 143. Further, a cache request 144 is output from the determination circuit 142 to the cache 143, and an area register data signal 145 is output from the register 141 to the determination circuit 142. Further, in the I / O dedicated cache 14, the address bus 131 is connected to the determination circuit 142 and the cache 143, and the data bus 132 is connected to the cache 143.

  As illustrated in FIG. 9, the register 141 is accessible from the CPU 11, and includes a plurality of registers that hold the state and setting values of the I / O dedicated cache 14. This register 141 is an operation mode register 1411 for setting validity / invalidity of the I / O dedicated cache 14, a cache mode register 1412 for defining the operation mode of the cache 143 such as a write back mode and a write through mode, and an I / O dedicated register. It is composed of a cooperative data area register 1413 for designating a data area (address range) to be held in the cache 14.

  In this cooperative data area register 1413, one cooperative data area uses a cooperative data area address register 1414 (1414-1 to 1414-m) and a cooperative data area mask register 1415 (1415-1 to 1415-m). By having a plurality of sets of these two registers, a plurality of linked data areas can be supported. The cooperative data area mask register 1415 represents bits to be compared when the cooperative data area address register 1414 and the address 1311 compare values. As a result, the two registers 1414 and 1415 can represent the linked data area. In addition, there is a representation of a linked data area by setting a linked data area start address register and a linked data area end address register.

  These register values in the cooperative data area register 1413 are output to the determination circuit 142 as an area register data signal 145.

  The access path from the CPU 11 to the register 141 is connected to the bus 13 via a register access bus that is different from the configuration (a) connected to the bus 13 and the bus 13 as shown in FIG. There is a configuration (b). That is, in the configuration of FIG. 10A, the register 141 is connected to the bus 13 and accessed from the CPU 11 through this bus 13. On the other hand, in the configuration of FIG. 10B, the register 141 is connected to the bus 13 via the register access bus, and is accessed from the CPU 11 via this register access bus.

  In response to a write access to the memory 2 from the CPU 11 and the accelerator 12, the determination circuit 142 caches the write data from the area register data signal 145 from the register 141, the address bus 131, and the cache request signal 1313 from the accelerator 12. It is determined whether or not the data is held in 143 and a cache request 144 is output to the cache 143. This determination method is as shown in FIG.

  As shown in FIG. 11, first, the determination circuit 142 checks the access signal 1312 in response to an access request from the bus 13 to the memory 2, checks the type of access (1421), and if it is a read access, the cache request 144 Is invalid (1426).

  In the case of a write access at 1421, it is checked from the address 1311 of the write access and the area register data signal 145 from the register 141 whether or not the address is in the linked data area (1422). If it is within the area (Yes), the cache request 144 becomes valid (1425).

  If it is outside the cooperative data area at 1422 (No), the access request source of the write access is checked (1423), and if it is a write access from the CPU 11, the cache request 144 becomes invalid (1426).

  If the access request source is the accelerator 12 at 1423, it is checked whether the cache request signal 1313 from the accelerator 12 is valid or invalid (1424). If valid, the cache request 144 is valid (1425).

  If the cache request signal 1313 from the accelerator 12 is invalid at 1424, the cache request 144 is invalidated (1426).

  Next, FIG. 12 shows determination (1422) of whether or not the above-described write access address is in the cooperative data area.

  As shown in FIG. 12, in the determination (1422), the area register data signal 145 and the address 1311 from the register 141 are input, and the linked data area address registers 1414-1 to 1414-m and the address 1311 are compared. The gates 1425-1 to 1425 -m that calculate the logical product of each bit by the cooperative data area address registers 1414-1 to 1414 -m and the cooperative data area mask register 1415, and the addresses 1311 and the cooperative data area mask register 1415. Only the bits to be compared are input to the comparators 1427-1 to 1427 -m by the gates 1426-1 to 1426 -m that calculate the logical product for each bit, and the total of the comparison results of the comparators 1427-1 to 1427 -m are input. A logical sum is calculated by the gate 1428, and it is determined whether or not the address 1311 is a cooperative data area.

  As described above, the determination circuit 142 determines whether the access to the memory 2 is an access to the cooperative data area, and outputs the cache request 144 to the cache 143. The cache 143 is connected to the bus 13 and the memory controller 15, operates as a write-back or write-through cache, receives a cache request 144 from the determination circuit 142, and caches the write data.

  The configuration of the cache 143 is shown in FIG. In FIG. 13, there are N entries in the fully associative method, and there are address information, data, and control information held in each entry. The size of data held by each entry is about 32B or 64B. In addition, the control information includes LRU information when exchanging entries, a Valid bit indicating whether data is registered in the entry, a dirty bit indicating whether the data size has been updated, etc. There is. The cache hit indicates that the address is registered in the entry of the cache 143, and the cache miss is not registered in the cache 143.

  The operation of the cache 143 is classified into the following five types (three types (a)-(1), (2), (3) for write access and two types (b), (c) for read access). .

  (A)-(1) If the cache request 144 is valid and the cache hit is a write access, the data of the entry registered in the cache 143 is overwritten with the write data of the data write bus 133, and the dirty bit Set to ON.

  (A)-(2) If the cache request 144 is valid for write access and there is a free entry in the cache 143 due to a cache miss, the free entry in the cache 143 is searched and write data is registered in the entry. To do. This validates the entry and writes the value of address 1311 to the address information. At this time, if the write data size from the data write bus 1322 is smaller than the data size of the entry, the content data at the address is read from the memory 2 and registered in the data information of the entry, and then the write data is written.

  (A)-(3) If the cache request 144 is valid for write access and there is no free entry in the cache 143 due to a cache miss, the LRU information in the control information of each entry in the cache 143 is examined, Discard the old entry and register the write data in this entry. The registration procedure is the same as (a)-(2).

  (B) When the cache 143 is hit by read access, the data information of the entry of the address registered in the cache 143 is output to the data read bus 1321.

  (C) If there is a miss in the cache 143 in read access, the address is output to the memory controller 15, data corresponding to the address is read from the memory 2, and output to the data read bus 1321. Note that the data read at this time is not registered in the cache 143.

  If all entries are in use when registered in the cache 143 in the above processing, an entry to be evicted from the cache 143 is searched using an algorithm such as LRU as in the conventional cache. At this time, if the cache 143 is in the write back mode, the data of the entry is written back to the memory 2.

  By the above procedure, the I / O dedicated cache 14 holds the write data from the CPU 11 and the accelerator 12 in the cache 143, and realizes data linkage between the CPU 11 and the accelerator 12 in the I / O dedicated cache 14. It eliminates bottlenecks caused by data linkage and can speed up multimedia processing. Further, by holding only data that is really linked to the I / O dedicated cache 14, it is possible to improve the usage efficiency of the I / O dedicated cache 14 and to minimize the overhead due to a cache miss.

  Further, in order to increase the processing speed of the I / O dedicated cache 14 and support the split bus, the processing is pipelined and a three-stage system is adopted as shown in FIG. For an entry that is being accessed to the memory 2 due to a cache miss, the access to the same entry is kept waiting until the registration process for the entry is completed, so that the memory is correctly accessed even in a memory conflict. To.

  That is, as shown in FIG. 14, in stage 1, the determination circuit 142 performs cache request determination, and the cache 143 performs hit determination when write access and read access are performed. In stage 2, in the cache operation, the cache 143 is updated in the case of a hit during a write access, the memory 2 is accessed in the case of a miss, and the data is output from the cache 143 in the case of a read access. In case of a miss, the memory 2 is accessed. In stage 3, in the cache operation, registration is made to the cache 143 if there is a miss during write access, and data is output to the bus 13 if there is a miss during read access.

  As a result, the cache request determination by the determination circuit 142 and the cache determination processing by the cache 143 can be performed even during memory access, so that the overhead by the I / O dedicated cache 14 can be reduced.

  Further, an application example of this embodiment in which the I / O dedicated cache 14 and the memory controller 15 are combined to further improve the efficiency will be described below.

  Next, as an application example of the present embodiment, a case where the efficiency is improved by combining the I / O dedicated cache 14 and the memory controller 15 will be described with reference to FIGS. FIG. 15 is a diagram illustrating a configuration of the memory controller. FIG. 16 is a diagram illustrating a configuration of a cache. FIG. 17 is a diagram illustrating a data structure of an access request.

  First, the memory controller 15 has the following functions.

  (1) In order to secure memory bandwidth, priority is introduced to memory access. That is, memory access is preferentially performed for an accelerator that requires a large bandwidth.

  (2) Adopt out-of-order access that minimizes memory access overhead. That is, the active state is managed for each bank of the SDRAM and the DDR-SDRAM, and the order of memory access is changed so that accesses to the same Row address that can be accessed only by inputting the CAS address to each bank are continuous. .

  In the write access, if the I / O dedicated cache 14 receives an access request, the CPU 11 and the accelerator 12 can move to the next processing. However, if the read access is delayed, the CPU 11 and the accelerator 12 wait for the memory. It is necessary to give priority to access. For this reason, in the present memory controller 15, only memory access is accelerated, and priority control for securing a bandwidth is performed only for read access.

  Further, it should be noted that the access order to the memory 2 is changed by performing bandwidth reservation or out-of-order access. For this reason, it is important to maintain a memory consistency so that the same result as that accessed in the access order can be obtained. The following considerations are necessary to maintain this memory consistency.

  That is, there is no problem with changing the order of two memory accesses to different addresses. The two memory accesses to the same address are not changed in order beyond the write access. Hereinafter, two memory access requests to the same address are referred to as “there is a dependency between the two memory accesses”.

  The configuration of the memory controller 15 is shown in FIG. As shown in FIG. 15, the memory controller 15 includes an access control circuit 151, a refresh control circuit 152, a priority read access request FIFO 153, a write access request FIFO 154, and a memory access control circuit 155. The read access request FIFO 153 includes a FIFO (153-1 to 153-n) for each priority.

  FIG. 16 shows the configuration of the cache 143 in the I / O dedicated cache 14. As shown in FIG. 16, in the cache 143, in addition to the address information, data, and control information held in each of the N entries shown in FIG. 13, a priority indicating priority is registered. .

  In the application example of the present embodiment having such a configuration, an access request with priority information according to the CPU 11 and the accelerator 12 comes from the I / O dedicated cache 14. In response to this, the access control circuit 151 converts the access request format shown in FIG. This format consists of access attributes related to access requests and dependency information for maintaining memory consistency, and the access attributes are composed of a tag No for managing each access, a read / write signal, an address, and data. In addition, the dependency relationship information includes a tag No of a memory access request having a dependency relationship and a final bit indicating whether or not there is an access depending on itself.

  As for the operation of this access control circuit 151, the access request coming from the I / O dedicated cache 14 is as follows.

  (1) In response to a new access request, a new tag is issued and registered in tagNo. Also, the last bit is set.

  (2) Subsequently, the preceding access requests queued in the read access request FIFO 153 and the write access request FIFO 154 are checked to determine whether there is a dependency. As a result of this check, if there is no dependency relationship, in the case of read access, the corresponding read access request FIFOs 153-1 to 153-n are queued to the corresponding FIFO, and in the case of write access, they are queued to the write access request FIFO 154. And exit.

  If there is a dependency, follow the procedure below.

  (A)-(1) When this access request is a read access request, in the case of a write access request with respect to the preceding latest access request having a dependency relationship (the last bit is set), the write access of the preceding access request Data is returned, and this read access request is terminated without queuing (FIFO hit).

  (A)-(2) When this access request is a read access request, in the case of a read access request with respect to the preceding latest access request having a dependency relationship (the last bit is set), the tag No. of the preceding read access request Is registered in the dependency tag of this access request, and the last bit of the preceding read access request is cleared.

  (B) When the access request to be queued is a write access, the tag No of the preceding access request is registered in the dependency tag of the present access request, and the last bit of the preceding write access request is cleared.

  The operation of the memory access control circuit 155 takes out access requests for each read access request FIFO 153 and write access request FIFO 154 in the order of priority of each FIFO. At this time, with respect to the access issued to the SDRAM, the read access and the write access are combined for the access related to the same bank and the same Row address, and the memory 2 is accessed. At this time, the access request for which the dependency tagNo is set is excluded, and if the last bit is set for each access request for accessing the memory 2, there is no dependency relationship. It ends as it is. If the last bit is cleared, the dependency list is updated according to the following procedure.

  (A) For each access request queued, it is checked whether or not the tag number of the access request for which the dependency tag has ended is completed.

  (B) The dependency tag is cleared for the corresponding queuing access request.

  By adopting the above method, it is possible to efficiently access the same row address to each bank of SDRAM and DDR-SDRAM while maintaining memory consistency (consistency). The access efficiency to the memory 2 can be improved. Due to the access efficiency and the effect of the I / O dedicated cache 14, the multimedia processing can minimize the bottleneck caused by the memory 2 and realize smooth processing execution.

  Next, an example of a multimedia terminal using the multimedia microcomputer of this embodiment will be described with reference to FIG. FIG. 18 is a block diagram showing a multimedia terminal using a multimedia microcomputer.

  As multimedia terminals, mobile terminals with small display functions, such as mobile phones and PDAs, have music performance functions and camera functions, and display still images (photos) and videos (movies) on the screen. It is possible to do.

  The multimedia terminal 100 has a configuration in which a multimedia microcomputer 1 is used as a core, and a memory 2, a screen 3, which is an input / output device, a camera 4, a speaker 5, and a communication device 6 are connected to the multimedia microcomputer 1. Yes.

  The multimedia microcomputer 1 has an interface for connecting to the screen 3, the camera 4, the speaker 5, and the communication device 6, and an accelerator that performs screen display control, image input control, audio output control, and communication transmission / reception control. As a result, it is possible to display video captured by the camera 4 on the screen 3 and to transmit / receive video to / from the outside via the communication device 6 at high speed.

  Next, an example of the configuration and operation of another multimedia microcomputer in this embodiment will be described with reference to FIGS. 19 and 20. FIG. 19 is a block diagram showing still another multimedia microcomputer. FIG. 20 is a diagram showing the proper use of the cache and the I / O dedicated cache.

  As shown in FIG. 19, in this embodiment, another multimedia microcomputer 1 operates as a master, and has a CPU 11 having a cache 110 therein and a plurality of accelerators 12 (12-1 to 12-12) operating as slaves. -N), an I / O dedicated cache 14 which is a feature of the present invention, a bus 13 for connecting them, and a memory controller 15. A memory 2 is connected to the outside of the multimedia microcomputer 1, and a program 21 describing a series of procedural processes executed by the CPU 11, a work area 22, and each accelerator 12 are processed in the memory 2. There is a data area 23 (23-1 to 23-n) for storing data to be processed.

  The cache 110 and the I / O dedicated cache 14 have a function as a cache that temporarily holds the contents of the memory 2, and the cache 110 improves the access efficiency when the CPU 11 accesses the memory 2, The I / O dedicated cache 14 improves the access efficiency when the CPU 11 and the accelerator 12 access the memory 2.

  The use of the cache 110 and the I / O dedicated cache 14 will be described with reference to FIG. Hereinafter, it is assumed that the cache 110 adopts a copy-back method, the access to the memory 2 from the accelerator 12 is monitored using a snoop function, and between the cache 110 and the memory 2 and the I / O dedicated cache 14. And it has a function to maintain cache coherency. The cache reads data from the memory 2 for the line size is referred to as feed, and the writing to the memory 2 for the line size is referred to as purge.

  When the CPU 11 accesses the program 21 and the work area 22, only the cache 110 is operated, and the I / O dedicated cache 14 is passed through (121). Therefore, when a cache miss occurs in the cache 110, the cache 110 feeds and purges data to the memory 2 when the CPU 11 accesses both read and write (during write back).

  On the other hand, when the CPU 11 accesses the data area 23 of the accelerator 21, both the cache 110 and the I / O dedicated cache 14 operate (122 to 124). Therefore, when a cache miss occurs in the cache 110, the cache determination is also performed in the I / O dedicated cache 14 subsequently.

  When a cache hit occurs in the I / O dedicated cache 14, the CPU 11 accesses the data in the I / O dedicated cache 14 (122). Further, when the I / O dedicated cache 14 has a cache miss, the operation differs depending on the access from the cache 110.

(1) Cache feed access from cache 110 (read)
The I / O dedicated cache 14 passes through the read data from the memory 2 and outputs the data to the cache 110 (123).

(2) Cache purge access (write) from the cache 110
(2)-(a) The I / O dedicated cache 14 registers the purge data in the I / O dedicated cache 14 when the purge data is linkage data. At this time, if the line size of the cache 110 is smaller than the line size of the I / O dedicated cache 14, the purge data is written after feeding the line including the purge data from the memory 2 (124).

  (2)-(b) If the purge data is not linkage data, the I / O dedicated cache 14 passes through and writes to the memory 2 (123).

  Next, a specific example of a multimedia microcomputer that performs encryption at the IP protocol level and speeds up communication using IPsec for ensuring security will be described with reference to FIGS. This IPsec is specified as a standard protocol of VPN (Virtual Private Network).

  FIG. 21 shows a specific configuration of the multimedia microcomputer 1. The multimedia microcomputer 1 includes a CPU 11, an accelerator 12, an I / O dedicated cache 14, a bus 13 that connects them, and a memory controller 15. The accelerator 12 includes a TCP accelerator 12-1, an IPsec accelerator 12-2, and an EtherMAC 12-3. The TCP accelerator 12-1 performs checksum calculation and memory copy, and the IPsec accelerator 12-2 performs decryption and authentication processing. The EtherMAC 12-3 is connected via the LAN 130 and has a function of transmitting and receiving frames from the LAN. Here, the LAN 130 is Ethernet (registered trademark), which is most frequently used as a LAN.

  FIG. 22 shows a frame structure when communication is performed using an IPsec transport base. In the LAN and the Internet, the TCP / IP protocol is used as a standard protocol. When the data size to be transmitted / received is larger than the size that can be transmitted in one frame, it is divided into a plurality of TCP packets and transmitted / received.

  As shown in FIG. 22, the IPsec transport mode adopts a configuration in which an IP header is added to an IPsec packet obtained by encrypting a TCP packet and encapsulated in IP. Since the multimedia microcomputer 1 uses Ethernet (registered trademark) for LAN, it has a configuration in which a MAC header is added at the end. Incidentally, FIG. 23 shows a TCP / IP frame configuration when IPsec is not used.

  Note that an IPsec packet is composed of an IPsec header and IPsec data, and the ESP header is used because the IPsec header is encrypted. The IPsec data is added with an ESP authentication value so that tampering can be detected after an ESP trailer having data necessary for encryption is added to the TCP packet and the entire packet is encrypted.

  Next, as cache operations, a reception process when the I / O dedicated cache is not used (FIG. 24), a reception process when the I / O dedicated cache is used (FIG. 25), and only the cooperative data section is I / O. The reception process (FIG. 26) in the case of holding in the dedicated cache and using the I / O dedicated cache will be described in order.

  First, when the I / O dedicated cache 14 is not used, processing when receiving an IPsec frame in the IPsec transport mode shown in FIG. 22 will be described with reference to FIG.

  (1) The multimedia microcomputer 1 receives the Ethernet frame from the LAN 130 of Ethernet (registered trademark) and writes it in the data area 23 of the accelerator 12 in the memory 2 (1001, 1011).

  (2) The CPU 11 reads the MAC header and IP header of the Ethernet frame 1011 from the data area 23 of the accelerator 12, and performs Ethernet reception and IP reception processing (1002).

  (3) Since the Ethernet frame 1011 includes an IPsec packet, the CPU 11 reads the IPsec header in the Ethernet frame 1011, performs an IPsec reception process, and activates the IPsec accelerator 12-2.

  (4) The IPsec accelerator 12-2 reads the IPsec data in the Ethernet frame 1011 from the data area 23 of the accelerator 12, performs authentication processing and decryption processing, and sends the result to the data area 23 of the accelerator 12 as a TCP packet (TCP Data) 1012 is written back (1003).

  (5) The CPU 11 reads the TCP header from the TCP packet 1012 in the data area 23 of the accelerator 12, performs reception processing, and activates the TCP accelerator 12-1 to calculate the checksum (1004).

  (6) The TCP accelerator 12-1 reads the TCP packet 1012 in the data area 23 of the accelerator 12, calculates the checksum, and sends the TCP data to an appropriate position in the received data (the third position from the left in the figure). (1005).

  Thus, when the I / O dedicated cache 14 is not used, access to the memory 2 occurs five times per Ethernet frame.

  On the other hand, the operation when the I / O dedicated cache 14 is used will be described with reference to FIG.

  (1 ') The multimedia microcomputer 1 receives the Ethernet frame from the Ethernet (registered trademark) LAN 130 and writes it in the data area 23 of the accelerator 12 in the memory 2 (1021, 1011). However, since the data is written to the data area 23 of the accelerator 12, the I / O dedicated cache 14 caches the frame (1011 '), and the memory 2 is not actually accessed.

  (2 ′) When the CPU 11 reads the MAC header and IP header in the ether frame 1011 in the data area 23 of the accelerator 12, the CPU 11 hits the I / O dedicated cache 14. Therefore, access to the memory 2 does not occur, and the MAC header and the IP header of the frame 1011 'are read from the I / O dedicated cache 14 to perform Ethernet reception and IP reception processing (1022).

  (3 ′) The CPU 11 reads the IPsec header in the Ethernet frame 1011 because the Ethernet frame 1011 ′ includes an IPsec packet, performs an IPsec reception process, and activates the IPsec accelerator 12-2. Since the access to the memory 2 also hits the I / O dedicated cache 14 as in (2), the IPsec header of the Ether frame 1011 'is read, and the access to the memory 2 does not occur (1022).

  (4 ') The IPsec accelerator 12-2 tries to read the IPsec data in the Ethernet frame 1011. However, the IPsec accelerator 12-2 hits the I / O dedicated cache 14 and is actually read from the Ethernet frame 1011' (1023). Thereafter, the IPsec accelerator 12-2 performs an authentication process and a decryption process, and writes the result back as a TCP packet 1012 in the data area 23 of the accelerator 12. However, since the data is written to the data area 23 of the accelerator 12, the I / O dedicated cache 14 caches (1012 '), and no access to the memory 2 actually occurs (1023).

  (5 ′) The CPU 11 reads the TCP header from the TCP packet 1012 in the data area 23 of the accelerator 12. However, since the CPU 11 actually hits the I / O dedicated cache 14, the TCP header of the TCP packet 1012 ′ It is read (1024). Subsequently, the CPU 11 performs TCP reception processing and activates the TCP accelerator 12-1 in order to calculate a checksum.

  (6 ') The TCP accelerator 12-1 reads the TCP packet 1012 in the data area 23 of the accelerator 12, but reads the TCP packet 1012' because it hits the I / O dedicated cache 14. The TCP accelerator 12-1 calculates the checksum and writes the TCP data at an appropriate position in the received data (1025).

  As described above, it is possible to make access to the memory 2 zero by keeping the cooperative data accessed by the accelerator 12 and the CPU 11 in the I / O dedicated cache 14. Actually, as described above, in an image, download, or the like, transmission and reception are performed by being divided into a plurality of ether frames, so the overhead of access to the memory 2 greatly affects the communication performance.

  The linkage data accessed by both the CPU 11 and the accelerator 12 are the header portions of 1031 and 1032. Since the I / O dedicated cache 14 caches this cooperative data, the CPU 11 can read the data written by the accelerator 12 from the I / O dedicated cache 14 instead of from the slow-access memory 2. Thus, it is possible to greatly reduce the access waiting time, and to perform IPsec-based TCP / IP communication at high speed.

  In FIG. 26, only the cooperative data sections 1031 (MAC header, IP header, IPsec header), 1032 (TCP header) are held in the I / O dedicated cache 14, and other data (IPsec data, TCP data) is stored. The block diagram at the time of hold | maintaining in the memory 2 is shown. This configuration is a case where a plurality of accelerators 12 operate simultaneously and the I / O dedicated cache 14 has no room.

  On the other hand, when the I / O dedicated cache 14 has a margin, as shown in FIG. 25, in addition to the linked data units 1031 and 1032, data other than the linked data unit is also cached, so that data between the accelerators 12. It can also be used for forwarding. It is noted that the accelerator 12 often accesses consecutive addresses, and the point is that the linked data 1031 and 1032 are not cached out due to data transfer between the accelerators 12. Therefore, as a method for realizing that the cooperative data is preferentially cached on the I / O dedicated cache 14, the following method can be cited.

  (A) Only the linkage data is cached.

  (B) The cache data's staying time for linked data is made longer than for other data (for example, the progress of the LRU counter is delayed compared to other data).

  (C) An in-use bit for linked data is provided for each line, and the in-use bit is cleared when a series of processing in the CPU 11 is completed. The cleared line is subject to cash out.

  Here, since the methods (a) and (b) are performed in the I / O dedicated cache 14, no application intervention is required. However, the method (c) uses the OS or driver as the bit in use.・ Middleware level management processing is essential.

  According to the above method, the linkage data can stay in the I / O dedicated cache 14 for a long time. Especially when a plurality of accelerators are operating simultaneously, the performance of the linkage data being cached out from the I / O dedicated cache 14 is achieved. It is possible to prevent the decrease.

  Further, FIG. 27 shows a process for transmitting data encrypted similarly using IPsec. The transmission process is the reverse of the reception process.

  The CPU 11 sets transmission data in the data area 23 of the accelerator 12 in the memory 2. At this time, the I / O dedicated cache 14 detects and caches transmission data being written to the data area 23 of the accelerator 12. FIG. 27 shows a process in which the transmission data is divided into four frames and the third data 1061 is transmitted.

  (1) The CPU 11 activates the TCP accelerator 12-1 to transmit the third data 1061.

  (2) The TCP accelerator 12-1 cuts out the transmission data in the data area 23 of the accelerator 12 to a size 1061 that can be transmitted in one frame, calculates a checksum, and also transmits a TCP data portion in the transmission buffer 1062 Copy to. At this time, since the TCP accelerator 12-1 accesses the data area 23 of the accelerator 12, it actually reads 1061 'in the I / O dedicated cache 14 and writes it in the TCP data portion of 1062' (1051).

  (3) The CPU 11 creates a TCP header and writes it in the TCP header in the TCP packet 1062 in the data area 23 of the accelerator 12. However, it is actually written in the TCP header portion 1071 in the TCP packet 1062 'in the I / O dedicated cache 14 (1052).

  (4) In order to encrypt the TCP packet, the CPU 11 activates the IPsec accelerator 12-2. In response to this, the IPsec accelerator 12-2 reads the TCP packet 1062, and writes the encrypted result in the IPsec data portion of the Ethernet frame 1063. At this time, actually, 1062 'in the I / O dedicated cache 14 is read, and the encrypted data is written in the IPsec data portion of 1063'.

  (5) The CPU 11 creates a header part (MAC header, IP header, IPsec header) and writes it in the header part of the ether frame 1063 in the data area 23 of the accelerator 12, but actually it is in the I / O dedicated cache 14. It is written in the header portion 1072 of 1063 ′ (1053).

  (6) Upon completion of creation of the Ethernet frame 1063, the CPU 11 sends a transmission request to the EtherMAC 12-3. In response to this, the EtherMAC 12-3 reads the Ether frame 1063 (actually 1063 'in the I / O dedicated cache 14) in the data area 23 of the accelerator 12, and outputs it to the LAN 130 of Ethernet (registered trademark).

  As described above, also in the transmission process, both the CPU 11 and the accelerator 12 can be executed without worrying about the presence / absence of the I / O dedicated cache 14.

  Even if the reception process and the transmission process occur simultaneously, the I / O dedicated cache 14 is a cache and can be used without any problem.

  Next, processing when the cache 110 in the CPU 11 has a snoop function will be described with reference to FIG.

  In the transmission process (3), when the CPU 11 creates the TCP header with the cache 110 enabled and in the write-back mode, the actual TCP header exists only in the cache 110, and the 1071 in the I / O dedicated cache 14 and , It does not exist in the data area 23 of the accelerator 12. Here, the IPsec accelerator 12-2 that has been activated by the CPU 11 reads the TCP header. When the cache 14 detects this access via the bus 13, it issues an access interruption request to the IPsec accelerator 12-2 and purges the TCP header data in the cache 110 to the TCP packet 1062 in the data area 23 of the accelerator 12. To do. However, it is actually written in the TCP header portion 1071 in the I / O dedicated cache 14.

  When the purge process ends, the cache 110 cancels the access interruption request to the IPsec accelerator 12-2. In response to this, the IPsec accelerator 12-2 resumes reading the TCP header. It is possible to read the correct TCP header 1071 data after purging from the cache 110.

  It should be noted that by using the I / O dedicated cache 14 having a short access time, cache coherency between the cache 110 and the memory 2 can be reduced without accessing the memory 2 having a large access latency. Access is made through the dedicated cache 14, and the overhead due to cache purge can be greatly reduced.

  As described above, according to the present embodiment, the following effects can be obtained.

  (1) According to the multimedia microcomputers 1 and 10 adopting the I / O dedicated cache 14, a bottleneck caused by data cooperation in memory access that occurs when the CPU 11 and the accelerator 12 operate in cooperation with the multimedia processing. It can be minimized and the multimedia processing performance can be improved.

  (2) The I / O dedicated cache 14 holds only data necessary for data linkage between the CPU 11 and the accelerator 12 and determines whether to hold the data in the I / O dedicated cache 14 by write access to the memory 2. It is possible to improve the cache hit rate in the I / O dedicated cache 14 in data linkage, and to realize the I / O dedicated cache 14 in a more compact manner.

  (3) Even when multiple accelerators for multimedia 12 are installed, data linkage can be performed efficiently, so multiple multimedia processing such as audio, still images, and videos can be processed simultaneously and at high speed. The multimedia microcomputers 1 and 10 and the multimedia terminal 100 using the multimedia microcomputer can be configured.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, a wired communication function using Ethernet (registered trademark) has been described as a specific example. However, the present invention is not limited to this, and (1) a wireless communication function, ( 2) Screen display function by graphics, MPEG, JPEG (image compression / decompression), (3) Camera processing function by image processing such as image rotation and image quality adjustment, (4) Music, MP3 (audio compression / decompression), etc. The same can be applied to the speaker processing function according to the above.

  In the above-described embodiment, the configuration example including one CPU is shown. However, the present invention can be effectively applied to a configuration including a plurality of CPUs.

  The contents of the present invention described above relate to a microcomputer, and in particular, can be applied to a microcomputer that performs auxiliary processing such as an accelerator and multimedia processing in addition to processing by a CPU.

It is a block diagram which shows the multimedia microcomputer which concerns on one embodiment of this invention. FIG. 3 is a diagram showing a configuration of a memory in an embodiment of the present invention. In one embodiment of the present invention, it is a block diagram showing another multimedia microcomputer. FIG. 5 is a diagram illustrating a flow of multimedia processing in an embodiment of the present invention. In one embodiment of the present invention, it is a diagram showing a data flow (from pre-processing to accelerator processing) of multimedia processing. FIG. 6 is a diagram illustrating a data flow (from a processing result set to post-processing) of multimedia processing in an embodiment of the present invention. In one embodiment of the present invention, it is a figure showing composition of a bus. FIG. 3 is a diagram showing a configuration of an I / O dedicated cache in an embodiment of the present invention. FIG. 3 is a diagram illustrating a configuration of a register in an embodiment of the present invention. (A), (b) is a figure which shows the register access path | route in an I / O exclusive cache in one embodiment of this invention. In one embodiment of the present invention, it is a figure showing a flow of processing in a judgment circuit. FIG. 3 is a diagram showing a configuration of an address determination circuit in an embodiment of the present invention. In one embodiment of the present invention, it is a diagram showing a configuration of a cache. FIG. 6 is a diagram illustrating a cache operation in the embodiment of the present invention. In the application example of one embodiment of this invention, it is a figure which shows the structure of a memory controller. In the application example of one embodiment of this invention, it is a figure which shows the structure of a cache. In the application example of one embodiment of this invention, it is a figure which shows the data structure of an access request. In one embodiment of the present invention, it is a block diagram showing a multimedia terminal using a multimedia microcomputer. In one embodiment of the present invention, it is a block diagram showing still another multimedia microcomputer. In one embodiment of the present invention, it is a diagram showing the proper use of a cache and an I / O dedicated cache. In one embodiment of the present invention, it is a block diagram showing a specific configuration of a multimedia microcomputer. In one embodiment of the present invention, it is a block diagram showing a frame structure when performing communication. In one embodiment of this invention, it is a block diagram which shows another frame structure at the time of performing communication. FIG. 10 is a diagram illustrating a cache operation (reception processing when an I / O dedicated cache is not used) in an embodiment of the present invention. FIG. 10 is a diagram illustrating a cache operation (reception processing when an I / O dedicated cache is used) in an embodiment of the present invention. FIG. 11 is a diagram illustrating a cache operation (reception processing when only the linkage data unit is held in the I / O dedicated cache and the I / O dedicated cache is used) in the embodiment of the present invention. FIG. 6 is a diagram illustrating a process of transmitting encrypted data according to an embodiment of the present invention. FIG. 5 is a diagram illustrating a cache operation (when a snoop function is provided) in an embodiment of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Multimedia microcomputer, 2 ... Memory, 3 ... Screen, 4 ... Camera, 5 ... Speaker, 6 ... Communication apparatus, 10 ... Multimedia microcomputer, 11 ... CPU, 12 ... Accelerator, 13 ... Bus, 14 ... I / O Dedicated cache, 15 ... Memory controller, 21 ... Program, 22 ... Work area, 23 ... Data area, 100 ... Multimedia terminal, 110 ... Cache, 130 ... LAN, 141 ... Register, 142 ... Judgment circuit, 143 ... Cache, 151 ... access control circuit, 152 ... refresh control circuit, 153 ... read access request FIFO, 154 ... write access request FIFO, 155 ... memory access control circuit.

Claims (15)

A CPU acting as a master;
An accelerator that operates as a slave,
A microcomputer capable of accessing a memory from the CPU and the accelerator,
The data that the CPU and the accelerator access to the memory is composed of first data that the CPU and the accelerator exchange with each other, and second data that excludes the first data,
A microcomputer having a cache means for holding the first data out of the first data and the second data. The microcomputer according to claim 1.
The microcomputer having a function of determining whether to hold data of the write access request when a write access request from the CPU and the accelerator to the memory is made. The microcomputer according to claim 2.
The microcomputer has a function of issuing a holding request to the cache unit when performing write access to the memory. The microcomputer according to claim 3.
The microcomputer has a function of determining whether or not to hold data output from the accelerator in response to a holding request output at the time of write access to the memory from the accelerator. . The microcomputer according to claim 2.
The cache unit has a function of determining whether to hold the data based on an address output from the CPU and the accelerator during a write access to the memory from the CPU and the accelerator. A microcomputer to do. The microcomputer according to claim 1.
The cache means outputs the data to the accelerator when the cache means holds the data of the read access request at the time of a read access request from the accelerator to the memory. A microcomputer having a function. The microcomputer according to claim 1.
A memory controller for controlling access to the memory from the CPU and the accelerator;
Has priority for access requests from the CPU and the accelerator,
The microcomputer having a function of processing an access request from the CPU and the accelerator according to the priority order. The microcomputer according to claim 7, wherein
The memory is SDRAM or DDR-SDRAM,
The microcomputer having a function of continuously accessing the same bank and the same row address of the memory in response to an access request from the CPU and the accelerator. The microcomputer according to claim 8, wherein
The memory controller has a function of managing dependency relations and maintaining consistency of access to the memory with respect to accesses to the same address among access requests from the CPU and the accelerator. Computer. The microcomputer according to claim 1.
The microcomputer having the memory outside the microcomputer. The microcomputer according to claim 1.
The microcomputer having the memory inside the microcomputer. The microcomputer according to claim 1.
The microcomputer has a cache therein. The microcomputer according to claim 12, wherein
The microcomputer is connected to an external memory;
A microcomputer having a program or work area formed in the external memory. The microcomputer according to claim 13.
The microcomputer according to claim 1, wherein a data area of the accelerator is formed in the external memory. The microcomputer according to claim 12, wherein
The microcomputer having a snoop function in the cache inside the CPU.

Images