JP2006064570A - Interferometer system, signal processing method in interferometer system, and stages using signal processing method concerned - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interferometer system and a signal processing method and the like in the interferometer system capable of measuring position information of test objects with high precision. <P>SOLUTION: Detected signals K1 are digital ones of signals acquired by irradiating the test objects with measuring beam and have no variation of their cycles and pulse width drastically. A flag generating section 22 detects the rise and decay of synchronized signals K2 synchronizing the detected signals K1. A period measuring section 23 generates delayed detection signals K3 by delaying the synchronized signals K2 by one cycle through measuring the pulse cycle and the pulse width of individual pulse included in the synchronous detected signal K2. An edge monitoring section 25 detects the rise position and the like of the delayed detection signals K3, while a complement counter section 24 generates complement signals KC on the basis of the complement on-off signal ST outputted from the edge monitoring section 25 and complements places with pulse anomaly in the delayed detection signals KC. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an interferometer system that detects reflected light obtained by irradiating a measurement object with high coherency measurement light and measures position information of the measurement object, a signal processing method in the interferometer system, and the signal processing method. The present invention relates to a stage for measuring position information of a movable body.

  The interferometer system irradiates a movable measurement target with a highly coherent measurement light such as a laser beam, detects the reflected light, and measures the position information of the measurement target. For example, the interferometer system has a high resolution of about 1 nm. Have. For this reason, the laser interferometer is also provided in an exposure apparatus that transfers a pattern formed on a mask onto a substrate such as a wafer or a glass plate in order to manufacture a semiconductor element, a liquid crystal display element, a magnetic head, or other fine devices. It is used to measure position information of a stage that moves a mask and a substrate.

  The interferometer system includes a light source that emits highly coherent light, and divides the highly coherent light emitted from the light source into a plurality of parts, and uses one of them as the measurement light. For example, an interferometer system provided in an exposure apparatus divides highly coherent light from a light source into three parts and irradiates the measurement light, a reference light that determines a reference position for the stage, and a position of the stage. In order to obtain information, it is used as a reference light for passing through a reference optical path whose optical path length is known.

The position information of the stage is obtained by detecting the interference light obtained by interfering the reflected light obtained by irradiating the movable mirror provided on the stage with the measurement light and the reference light reflected by the fixed mirror. Measurement is performed by comparing the obtained detection signal with the reference signal obtained by detecting the reference light through the reference optical path with a reference receiver. Both the detection signal of the receiver and the reference signal of the reference receiver are digitized (binarized) to measure the position information. However, if noise is superimposed on the detection signal or the reference signal, the signal cycle suddenly increases. A changing phenomenon (a so-called glitch) occurs, and the measurement accuracy of the position information decreases. In order to prevent such a problem, the following Patent Document 1 discloses a glitch reduction circuit that reduces glitches when a detection signal is digitized.
JP 2001-94401 A

  By the way, the above-described conventional glitch reduction circuit reduces glitches when digitizing the detection signal or the reference detection signal, but the glitch cannot be completely removed at the time of digitization. For this reason, the phenomenon that the pulse width of the converted digital signal fluctuates rapidly and the phenomenon that the pulse suddenly falls out over one period or a plurality of periods still occur. When such a phenomenon occurs, there is a problem that an error occurs and the measurement accuracy of the position information is lowered. Further, when the acceleration of the stage is obtained from the measurement result, an abnormal acceleration is obtained, and there is a problem that it is necessary to perform error processing such as stopping the stage.

  In recent years, in the manufacture of devices, miniaturization is required mainly for high density. In particular, in the manufacture of semiconductor elements, the process rule is becoming about 0.1 μm, and the superposition accuracy between the pattern already formed on the substrate and the pattern to be exposed is required to be extremely strict. In order to improve the overlay accuracy, first, the position information of the stage must be measured with high accuracy. For this reason, it is necessary to avoid measurement errors caused by noise as much as possible. In addition, miniaturization and improvement in throughput (the number of substrates that can be subjected to exposure processing per unit time) are required, and it is necessary to eliminate error processing that is not originally required as much as possible.

  The present invention has been made in view of the above circumstances, an interferometer system capable of measuring position information of a measurement object with high accuracy, a signal processing method in the interferometer system, and a movable body using the signal processing method. An object of the present invention is to provide a stage for measuring position information.

The present invention adopts the following configuration corresponding to each diagram shown in the embodiment. However, the reference numerals with parentheses attached to each element are merely examples of the element and do not limit each element.
In order to solve the above problems, a signal processing method in an interferometer system of the present invention is an interferometer that measures position information of a measurement object based on reflected light obtained by irradiating the measurement object (OB) with measurement light. A signal processing method in the system (10), wherein a delay step for obtaining a delay signal (K3) obtained by delaying a predetermined signal (K1, K2) by a predetermined period, and a time position other than the predetermined time position (A1, A2) A detection step for detecting a change in signal level of the delay signal in the step, a correction signal generation step for generating a correction signal (KC) for correcting the delay based on a detection result of the detection step, and the correction signal A correction step for correcting a delay signal, and a measurement step for measuring position information of the measurement object using the delay signal corrected in the correction step. It is characterized in.
According to the present invention, a change in signal level at a time position other than a predetermined time position of a delayed signal obtained by delaying a predetermined signal by a predetermined period is detected, and the delay signal is corrected by a correction signal generated based on the detection result. The position information of the measurement object is measured using the corrected delay signal.
In addition, the stage of the present invention uses the movable body (66) configured to be movable in a predetermined movement direction and the signal processing method according to any one of the above, and uses the movable body as the measurement object to determine the position information. And an interferometer system (64a, 64b, 70a, 70b) that measures the above and a drive control unit (60) that drives the movable body based on the measurement result of the interferometer system.
Further, the interferometer system of the present invention is obtained by interfering the reference light (13) that outputs the reference signal (S1), the reflected light obtained by irradiating the measurement object (OB) with the measurement light, and the reference light. Receivers (15, 17) for outputting detected signals (S2, S3), and obtaining position information of the measurement object based on a reference signal from the reference machine and a detection signal from the receiver In the interferometer system (10), the reference machine corrects the digitally processed signal and outputs the signal after the correction process as the reference signal.

According to the present invention, there is an effect that position information of a measurement target can be measured with high accuracy.
Further, according to the present invention, the position information of the movable body can be measured with high accuracy, and since the movable body is driven based on the measurement result having this high accuracy, the movable body can be precisely driven. Can do.
Furthermore, according to the present invention, since the reference machine does not use the reflected light from the measurement object that is a movable body, the reference machine generates an optimum reference signal that is more easily corrected without being affected by the Doppler phenomenon. It is possible to measure the position information of the measurement object with high accuracy.

  Hereinafter, an interferometer system, a signal processing method in the interferometer system, and a stage using the signal processing method according to an embodiment of the present invention will be described in detail with reference to the drawings.

[Interferometer system]
FIG. 1 is a block diagram showing an outline of the configuration of an interferometer system in which a signal processing method according to an embodiment of the present invention is used. In general, the interferometer system 10 shown in FIG. 1 divides the laser beam LB0 emitted from the laser light source 11 into three laser beams LB1 to LB3, and the divided laser beam LB1 has a known optical path length. Each of the detection signals S2 and S3 is obtained by receiving the interference signal obtained by irradiating the measurement target OB with the other two divided laser beams LB2 and LB3 while receiving the reference signal S1 through P1. The position information of the measurement object OB is measured from the reference signal S1 and the detection signals S2 and S3. Hereinafter, a specific configuration will be described.

  The laser light source 11 emits a laser beam LB0 including two different wavelengths λ1 and λ2. This laser beam LB0 enters the splitter 12, and is divided into three laser beams LB1 to LB3. One divided laser beam LB1 is incident on the reference receiver 13 via the reference optical path P1 while being sequentially reflected by the reflection mirrors M1 and M2. Here, since the laser beam LB1 includes two different wavelengths λ1 and λ2, these interference lights enter the reference receiver 13. The reference receiver 13 photoelectrically converts interference light of two different wavelengths λ1 and λ2 to generate a reference signal, and digitizes (binarizes) the reference signal to perform glitch reduction processing. Further, the signal subjected to these processes is subjected to a process for complementing the pulse width variation and the missing pulse, and the reference signal S1 is output.

  The laser beam LB2 split by the splitter 12 is reflected by the mirror M3 and enters the interferometer 14. The laser beam LB2 incident on the interferometer 14 includes two different wavelengths λ1 and λ2. A laser beam having one of the wavelengths (for example, a laser beam having the wavelength λ1) is attached to the measurement object OB via the optical path P2. The light is reflected by the reflected reflector MR1, travels backward along the optical path P2, and enters the interferometer 14 again. The other wavelength of laser light (for example, laser light of wavelength λ 2) is applied to a fixed mirror (not shown), and the reflected light enters the interferometer 14. Note that the measurement object OB shown in FIG. 1 is configured to be movable in two directions D1 and D2 that are orthogonal to each other in a plane parallel to the paper surface.

  The interferometer 14 causes the laser light having the wavelength λ1 that has passed through the optical path P2 to interfere with the laser light having the wavelength λ2 that has been reflected by a fixed mirror (not shown). The interference light IF1 obtained by the interferometer 14 is emitted from the interferometer 14 and enters the receiver 15. The receiver 15 photoelectrically converts the interference light IF1 to generate a detection signal, digitizes (binarizes) the detection signal, and performs glitch reduction processing. Further, the signal subjected to these processes is subjected to a process for complementing the pulse width variation and the missing pulse, and the detection signal S2 is output.

  Further, the laser beam LB3 split by the splitter 12 enters the interferometer 16. The laser beam LB3 incident on the interferometer 16 also includes two different wavelengths λ1 and λ2, and either one of the laser beams (for example, the laser beam having the wavelength λ1) is attached to the measurement target OB via the optical path P3. The light is reflected by the reflected reflector MR2, travels backward in the optical path P2, and enters the interferometer 16 again. The other wavelength of laser light (for example, laser light of wavelength λ 2) is applied to a fixed mirror (not shown), and the reflected light enters the interferometer 16.

  The interferometer 16 causes the laser light having the wavelength λ1 that has passed through the optical path P3 to interfere with the laser light having the wavelength λ2 that has been reflected by a fixed mirror (not shown). The interference light IF2 obtained by the interferometer 16 is emitted from the interferometer 16 and enters the receiver 17. The receiver 17 photoelectrically converts the interference light IF2 to generate a detection signal, digitizes (binarizes) the detection signal, and performs glitch reduction processing. Further, the signal subjected to these processes is subjected to a process for complementing the pulse width variation and the missing pulse, and the detection signal S3 is output.

  The reference signal S 1 from the reference receiver 13, the detection signal S 2 from the receiver 15, and the detection signal S 3 from the receiver 17 are input to the central measuring device 18. The central measuring device 18 measures the position information of the measurement target OB in the direction D1 by comparing the reference signal S1 and the detection signal S2, and compares the reference signal S1 and the detection signal S3 to measure the measurement target OB in the direction D2. Measure position information. By performing the processing described above, the interferometer system shown in FIG. 1 measures the position information of the measurement target OB in the paper (measurement step).

[Signal processing apparatus and signal processing method]
The overall configuration of the interferometer system 10 has been described above. Next, signal processing apparatuses and signal processing methods provided in the reference receiver 13 and the receivers 15 and 17 will be described. The configuration of the signal processing apparatus provided in the reference receiver 13 and the receivers 15 and 17 is the same as that of the reference receiver 13 and the receivers 15 and 17. The description of the configuration of the signal processing device provided in the receiver 13 and the receiver 17 is omitted.

  FIG. 2 is a block diagram showing a configuration of a signal processing apparatus in which the signal processing method according to the embodiment of the present invention is used. The signal processing device 20 shown in FIG. 2 has an abrupt change in pulse width and one period of a digitized detection signal (a digitized reference signal in the case of the reference receiver 13) inputted to the input terminal T1. It is a signal processing device that performs signal processing that complements missing pulses. Here, the detection signal input to the input terminal T1 will be described.

  FIG. 3 is a diagram illustrating an example of a detection signal input to the input terminal T1 of the signal processing device. In FIG. 3 (a), a signal indicated by reference numeral K0 is a detection signal obtained by photoelectrically converting the interference light IF1 in the receiver 15 shown in FIG. The signal shown is a detection signal (predetermined signal) obtained by performing digitization processing and glitch reduction processing of the detection signal K0. The detection signal K1 is input to the input terminal T1 of the signal processing device 20.

  In the basic process of obtaining the detection signal K1 from the detection signal K0, two different thresholds TH1 and TH2 are set for the detection signal K0, and the value of the detection signal K0 exceeds the threshold TH1 and becomes larger than the threshold TH1. In this case, the value is set to “1”, and the value is set to “0” when the value of the detection signal K0 exceeds the threshold value TH2 and becomes smaller than the threshold value TH2. Simultaneously with this process, the glitch reduction process disclosed in Patent Document 1 is performed to reduce the glitch.

  Here, for example, in a place indicated by reference sign PT1, when one pulse of the detection signal K0 exceeds the threshold value TH1, but the value is smaller as a whole than the other pulses, the detection signal to be obtained is obtained. A phenomenon occurs in which the pulse width of K1 is abruptly narrowed. Further, for example, when a value of one pulse of the detection signal K0 is extremely small and does not exceed the threshold value TH1 at a location indicated by the reference symbol PT2, a phenomenon that the pulse of the detection signal K1 is lost at that location occurs. . Such a detection signal K1 is input to the input terminal T1 of the signal processing device 20. The frequency of the detection signal K1 input to the input terminal T1 is about 3.5 MHz to 6.5 MHz, and the duty ratio (a period in which a value is “0” and a value is “1” within one period) The time ratio with respect to a certain period) is 50%.

  In FIG. 3B, the signal indicated by reference numeral K10 and the signal indicated by reference numeral K1 are both detected by performing the above-described digitization processing and glitch reduction processing of the detection signal K0. Although it is a signal, the detection signal K10 is a signal obtained when normal, and the detection signal K1 is a signal obtained when abnormal. As shown in FIG. 3 (b), the detection signal K10 has a pulse having a substantially constant width at a substantially constant period, whereas the detection signal K1 has a pulse at a location indicated by reference signs PT11, PT12, PT13. It is abnormal.

  A pulse appears much earlier in time at the location indicated by reference sign PT11, the logic is reversed at the location indicated by reference sign PT12, and a pulse is indicated at the location indicated by reference sign PT13. The width is unusually narrow. If the position information or acceleration of the measurement target OB is measured using the abnormal detection signal K1 shown in FIGS. 3 (a) and 3 (b), the measurement accuracy is lowered or abnormal acceleration is required. In the present embodiment, a normal detection signal is obtained by complementing the pulse abnormality.

  Returning to FIG. 2, the signal processing device 20 according to the present embodiment includes a synchronization unit 21, a flag generation unit 22, a period measurement unit 23, a complementary counter unit 24, an edge monitoring unit 25, and a multiplexer 26. A reference clock CLK (not shown) having a frequency of about 200 MHz is supplied to each block in the signal processing device 20, and each block operates in synchronization with the reference clock CLK.

  The synchronization unit 21 generates a synchronization detection signal K2 (predetermined signal) obtained by synchronizing the detection signal K1 (see FIG. 2) input via the input terminal T1 with the reference clock CLK. Based on the synchronization detection signal K2 output from the synchronization unit 21, the flag generation unit 22 generates flags FP, FN, and FA indicating the state change of the synchronization detection signal K2. Here, the flag FP is a flag whose value becomes “1” only when the synchronization detection signal K2 rises, and the flag FN is a flag whose value becomes “1” only when the synchronization detection signal K2 falls. Yes, the flag FA is a flag whose value changes every time the flag FP is output (the value alternately becomes “1” or “0”). The flag generation unit 22 outputs the synchronization detection signal K2 input from the synchronization unit 21 to the cycle measurement unit 23 as it is.

  The period measurement unit 23 measures the period and pulse width of each pulse included in the synchronization detection signal K2 output from the flag generation unit 22 using the flags FP, FN, and FA output from the flag generation unit 22, A delay detection signal K3 (delayed signal) is generated by delaying the synchronization detection signal K2 by a predetermined period. The period measurement unit 23 in this embodiment will be described by taking as an example the case of generating the delay detection signal K3 delayed by one period with respect to the synchronization detection signal K2, but the delay detection delayed by a plurality of periods is described. The signal K3 may be generated. Further, even if the period measurement unit 23 is set to generate the delay detection signal K3 obtained by delaying the synchronization detection signal K2 by one period, the delay detection is performed as a result according to the abnormality of the pulse of the synchronization detection signal K2. The signal K3 may be delayed by a plurality of periods with respect to the synchronization detection signal K2.

  In addition, the measurement result of the period and pulse width of each pulse measured by the period measurement unit 23 is output to the complementary counter unit 24 as a count signal E2, and an abnormal point when an abnormality occurs in the pulse of the synchronization detection signal K2 is indicated. Used to generate complementary signals to complement. Further, the period measuring unit 23 outputs an edge monitoring control signal EW for monitoring the rising time and the falling time when the synchronization detection signal K2 is predicted to be normal to the edge monitoring unit 25. The period measuring unit 23 outputs the flag FA output from the flag generating unit 22 to the correction counter unit 24 as it is.

  The complement counter unit 24 generates a complement signal KC that complements the abnormal portion of the synchronization detection signal K2 based on the count signal E2 output from the period measurement unit 23. Whether or not to generate the complementary signal KC is controlled by a complementary start / stop signal ST output from the edge monitoring unit 25. The edge monitoring unit 25 receives the flag FP from the flag generation unit 22 and the delay detection signal K3 and the edge monitoring control signal EW from the period measurement unit 23, and the flag FP and the edge monitoring control signal EW. Based on this, the rising and falling edges of the delay detection signal K3 are monitored, and the complementary start / stop signal ST is output to the complementary counter unit 24 and the selection signal SL is output to the multiplexer 26 in accordance with the monitoring result.

  FIG. 4 is a diagram for explaining an edge detection region set for the delay detection signal K3. In FIG. 4, the area denoted by reference symbol A1 is an edge detection area set at the rising edge of the delay detection signal K3, and the area denoted by reference numeral A2 is edge detection set at the falling edge of the delay detection signal K3. It is an area. As illustrated, the edge detection areas A1 and A2 have a certain width (for example, several clocks of the reference clock CLK) from the position where the delay detection signal K3 will rise or fall unless there is an influence of noise or the like. Minute width: predetermined time width).

  As described above, the edge detection areas A1 and A2 are provided to detect the rise and fall of the delay detection signal K3 even if the rise time position and the fall time position are slightly shifted due to the sampling error. This is to enable detection. Further, for example, even when an abnormality occurs in which a pulse appears significantly earlier in time as indicated by a reference numeral PT11 in FIG. 3B, the delay detection signal K3 can be complemented. Because.

  Returning to FIG. 2, the multiplexer 26 uses either the delay detection signal K3 from the period measurement unit 23 or the complementary counter unit 24 as a complementary detection signal in accordance with the selection signal SL input to the selection signal input terminal C. Output as K4. Specifically, when the selection signal SL is “0”, the delay detection signal K3 is output as the complementary detection signal K4. When the selection signal SL is “1”, the complementary signal KC is output as the complementary detection signal K4.

  The configuration of the signal processing device 20 has been described above. Next, the internal configuration of the period measurement unit 23 and the correction counter unit 24 provided in the signal processing device will be described in order. FIG. 5 is a block diagram illustrating an internal configuration of the period measurement unit 23. As shown in FIG. 5, the cycle measurement unit 23 includes a cycle measurement counter 31, a pulse width storage unit 32, complementary cycle counters 23 and 24, a complementary pulse width counter unit 35, and an edge monitoring counter unit 36. The synchronization detection signal K2 output from the flag generator 22 is input from the input terminal T11, and the flags FP, FN, and FA are input from the input terminals T12, T13, and T14, respectively.

  The period measurement counter 31 is a counter that measures the length of each period of the synchronization detection signal K2 using the flag FP input from the input terminal T12. That is, the cycle measurement counter 31 starts counting (starts incrementing) in synchronization with the reference clock CLK at the time when the flag FP is output from the flag generation unit 22, and then counts at the time when the flag FP is output next. While stopping, the value is reset (the value is set to “0”), and the operation of starting counting again is repeated. The product of the count value C1 when the period measurement counter 31 stops counting and the length of one period of the reference clock CLK (5 ns when the frequency of the reference clock CLK is 200 MHz) is one period of the synchronization detection signal K2. It becomes the length of.

  The pulse width storage unit 32 stores the pulse width of the synchronization detection signal K2 (time when the value of the synchronization detection signal K2 is “1”) using the flag FN input from the input terminal T13. The pulse width storage 32 measures the pulse width of the synchronization detection signal K2 by taking in (latching) the count value C1 of the period measurement counter 31 at the time when the flag FN is input from the input terminal T1. That is, since the period measurement counter 31 uses the flag FP to count the time since the synchronization detection signal K2 rises, the period measurement counter 31 sets the flag FN output from the flag generation unit 22 when the synchronization detection signal K2 falls. Based on the count value C1 of the period measurement counter 31, the pulse width can be obtained.

  The pulse width storage unit 32 takes in the count value C1 of the period measurement counter 31 every time the flag FN is output from the flag generation unit 22. For this reason, when one period of the synchronization detection signal K2 is defined as from the rising edge of the synchronization detection signal K2 to the next rising edge, the period during which the pulse width storage unit 32 stores the count value C1 once captured is the count value C1. This period is from the start of the second half cycle of the period in which the data has been taken in to the end of the first half cycle of the next cycle.

  The complementary period counters 33 and 34 count the period of each pulse included in the synchronization detection signal K2 using the flag FA input from the input terminal T14 and the count value C1 of the period measurement counter 32. The count values of the complementary cycle counters 33 and 34 are used to generate a delay detection signal K3 obtained by delaying each cycle of the synchronization detection signal K2 by a predetermined cycle (one cycle in the present embodiment). The flag FA input from the input terminal T14 is output as it is to the complementary counter unit 24 via the output terminal T15. Further, the count values of the complementary period counters 33 and 34 are complemented when generating the complementary signal KC necessary for complementing the abnormal part when the abnormality occurs in the synchronization detection signal K2 and making it normal. It is also used to determine the period of each pulse included in the signal KC.

  This complementary cycle counter 33 fetches the count value C1 of the cycle measurement counter 31 at the fall of the flag FA, decrements the count value fetched in synchronization with the reference clock CLK, and counts when the count value becomes “0”. To stop. Note that the count value of the complementary period counter 33 is C3. The complementary cycle counter 34 fetches the count value C1 of the cycle measurement counter 31 at the rising edge of the flag FA, decrements the count value fetched in synchronization with the reference clock CLK, and stops counting when the count value becomes “0”. To do. Note that the count value of the complementary period counter 34 is C4. Here, the reason why the complementary period counters 33 and 34 are provided in parallel is to make each period of the delay detection signal K3 continuous without interruption by operating them alternately.

  The output terminal of the complementary period counter 33 and the output terminal of the complementary period counter 34 are connected to each other. The complementary period counters 33 and 34 operate alternately at the rise and fall of the flag FA and do not operate simultaneously. Also, the count values C3 and C4 are alternately output and are not simultaneously output. For this reason, the count value C3 and the count value C4 are multiplexed so that the output terminals are connected. Hereinafter, a signal obtained by multiplexing the count value C3 and the count value C4 is referred to as a multiplexed signal E1. It should be noted that the multiplexed signal E1 can be separated into count values C3 and C4 using the flag FA.

  The multiplexed signal E1 is output to the complementary pulse width counter unit 35. The complementary pulse width counter unit 35 takes in the count value C2 stored in the pulse width storage unit 32 when the value of the multiplexed signal E1 becomes “0”, and takes in the count value taken in synchronization with the reference clock CLK. Is decremented, and the count is stopped when the count value becomes “0”. Note that the count value of the complementary pulse width counter unit 35 is C5.

  The complementary pulse width counter 35 sets the value of the delay detection signal K3 to “0” when the count value C5 is “0”, and the delay detection signal K3 when the count value C5 is other than “0”. Is set to “1”. As a result, the value of the delay detection signal K3 becomes “1” until the count value C5 becomes “0” after the count value C2 of the pulse width storage unit 32 is fetched, and after the count value C5 becomes “0”. The value of the delay detection signal K3 becomes “0” until the next count value C2 is fetched. In this way, the delay detection signal K3 is generated. Further, the count value C5 of the complementary pulse width counter unit 35 is used not only for generating the delay detection signal K3, but also for normalizing by complementing the abnormal part when the pulse is abnormal in the synchronization detection signal K2. This is also used to determine the pulse width of each pulse included in the complementary signal KC when generating the complementary signal KC necessary for this purpose.

  The count value C5 of the complementary pulse width counter unit 35 is output to the output terminal T17. The multiplexed signal E1 described above is also output to the output terminal T17. Here, for convenience, the multiplexed signal E1 and the count value C5 are combined into a count signal E2. It should be noted that the count signal E2 is divided into the multiplexed signal E1 and the count value C5 in the edge monitoring counter unit 36 and in the complementary counter unit 24 shown in FIG.

  The edge monitoring counter unit 36 generates an edge monitoring control signal EW for providing the edge detection areas A1 and A2 shown in FIG. 4 based on the multiplexed signal E1 and the count value C5 included in the counting signal E2. Specifically, after the value of the multiplexed signal E1 becomes equal to or less than a predetermined value, the value of the multiplexed signal E1 becomes “0” and a predetermined time (for example, a time corresponding to several clocks of the reference clock CLK) elapses. The value of the edge monitoring control signal EW is set to “1” only until Further, after the count value C5 becomes equal to or less than the predetermined value, the count value C5 becomes “0” until a predetermined time (for example, several clocks of the reference clock CLK) elapses. The value of the edge monitoring control signal EW is set to “1” only during the interval. The edge monitoring control signal EW is output to the output terminal T18.

  FIG. 6 is a block diagram showing the internal configuration of the complementary counter unit 24. As shown in FIG. 6, the complementary counter unit 24 includes pulse period registers 41 and 42, period generation counter units 43 and 44, an OR circuit (hereinafter referred to as an OR circuit) 45, a pulse width register 46, and a complementary execution counter unit 47. It is comprised including. The flag FA output from the period measuring unit 23 is input from the input terminal T21, and the count signal E2 is input from the input terminal T22. The complement start / stop signal ST output from the edge monitoring unit 25 is input from the input terminal T23.

  The pulse period registers 41 and 42 capture and temporarily store the multiplexed signal E1 included in the count signal E2 input from the input terminal T22 at the timing when the flag FA is input. Specifically, the pulse period register 41 captures the multiplexed signal E1 at the falling edge of the flag FA, and the pulse period register 42 captures the multiplexed signal E1 at the rising edge of the flag FA. That is, the pulse cycle registers 41 and 42 operate alternately at the rising edge or falling edge of the flag FA and take in the multiplexed signal E1. By performing this operation, when the value of the complement start / end signal ST is “1”, the count value C3 (the count value of the complement cycle counter 33) included in the multiplexed signal E1 is stored in the pulse cycle register 41. The count value C4 (count value of the complementary period counter 34) is stored in the pulse period register 42. However, the above operation is performed when the value of the complement start / end signal ST is “0”, and when the value of the complement start / end signal ST output from the edge monitoring unit 25 becomes “1”, the multiplexed signal is output. The capture of E1 is prohibited, and the multiplexed signal E1 captured before that is held.

  The cycle generation counter units 43 and 44 take in the values stored in the pulse cycle registers 41 and 42 when the value of the complement start / end signal ST input from the input terminal T23 becomes “1”, and the reference clock Each count value taken in synchronization with CLK is decremented. Specifically, the cycle generation counter unit 43 fetches the count value of the pulse cycle register 41 at the fall of the flag FA, decrements the count value fetched in synchronization with the reference clock CLK, and the count value becomes “0”. At that time, the count is stopped and a count end pulse signal is output. Further, the cycle generation counter unit 44 fetches the count value of the pulse cycle register 42 at the rising edge of the flag FA, decrements the count value fetched in synchronization with the reference clock CLK, and counts when the count value becomes “0”. Is stopped and a count end pulse signal is output. When the value of the complement start / end signal ST is “0”, the counting operation of the cycle generation counter units 43 and 44 is stopped.

  The OR circuit 45 performs a logical OR operation of the count end pulse signals output from the cycle generation counter units 43 and 44, and outputs a complementary cycle end signal D1. The complementary period end signal D1 is output to the complementary execution counter unit 47. The pulse width register 46 captures and temporarily stores the count value C5 included in the count signal E2 input from the input terminal T22 at the rising or falling edge of the flag FA. However, the above operation is performed when the value of the complement start / end signal ST is “0”, and the count value is reached when the value of the complement start / end signal ST output from the edge monitoring unit 25 becomes “1”. Taking in C5 is prohibited and the count value C5 taken in before is held.

  The complement execution counter unit 47 stores in the pulse width register 46 when the value of the complement start / end signal ST from the input terminal T23 becomes “1” and when the complement cycle end signal D1 is output from the OR circuit 45. The counted value is taken in, the count value taken in synchronization with the reference clock CLK is decremented, and the count is stopped when the count value becomes “0”. The complement execution counter unit 47 sets the value of the complement signal KC to “0” when the count value counted internally is “0”, and the complement signal KC when the count is other than “0”. Is set to “1”. Thereby, the complementary signal KC is generated. The generated complement signal KC is output from the output terminal T24.

  Next, the operation of the signal processing apparatus 20 having the above configuration, that is, a signal processing method according to an embodiment of the present invention will be described. First, the procedure for generating the delay detection signal K3 will be described. FIG. 7 is a timing chart showing a procedure for generating the delay detection signal K3 generated in the signal processing device 20. The detection signal K1 shown in FIG. 7 is a detection signal input to the input terminal T1 of the signal processing device 20 shown in FIG. 2, and the reference signal CLK is a reference clock input to each block in the signal processing device 20. . In FIG. 7, the time at which the state of the synchronization detection signal K2 changes is from time t1 to t7, and no pulse abnormality occurs in the detection signal K1 during this time.

  When the detection signal K1 is input from the input terminal T1 of the signal processing device 20 illustrated in FIG. 2, the detection signal K1 is input to the synchronization unit 21, and the synchronization unit 21 is synchronized with the reference clock CLK. A synchronization detection signal K2 is generated. The synchronization detection signal K2 is output to the flag generation unit 22. When the synchronization detection signal K2 is input to the flag generation unit 22, flags FP, FN, and FA are generated in accordance with a change in the state of the synchronization detection signal K2. For example, the flag FP is generated at the rising edge of the synchronization detection signal K2 at time t1 in FIG. The flag FP generated by the flag generation unit 22 is output to the period measurement unit 23 and the edge monitoring unit 25.

  When the flag FP is input, the period measurement counter 31 provided in the period measurement unit 23 resets the state at the time when the flag FP is input (more precisely, when the flag FP falls) and counts (increments). And the count value C1 is increased in synchronization with the reference clock CLK. While the period measurement counter 31 is measuring, the flag FN is output from the flag generation unit 22 at time t2. When the flag FN is output (exactly when the flag FN falls), the pulse width storage unit 32 takes in the count value C1 (the value “7” in the example shown in FIG. 7) of the period measurement counter 31 and counts it. Store as value C2. Here, the count value C2 captured in the pulse width storage unit 32 is a value indicating the time (the pulse width of the synchronization detection signal K2) when the value of the synchronization detection signal K2 is “1” from time t1 to time t2.

  When the period measurement counter 31 continues counting and reaches time t3, the flag FP is output again from the flag generation unit 22 and the flag FA falls. The complement cycle counter 33 fetches the count value C1 (the value “14” in the example shown in FIG. 7) of the cycle measurement counter 31 at the time when the flag FA falls, and decrements the count value C1 fetched in synchronization with the reference clock CLK. (See the count value C3 in FIG. 7). Here, the count value C3 captured by the complementary cycle counter 33 is a value indicating the length of one cycle of the synchronization detection signal K2 from time t1 to time t3.

  Further, based on the flag FP output from the flag generation unit 22 at time t3, the period measurement counter 31 resets the state and starts counting (increment). When the time t3 elapses, the cycle measurement counter 31 is incremented (see count value C1), and the complementary cycle counter 33 is decremented by the count value C1 captured at time t3 (count value C3). reference). At time t4 in this state, a flag FN is output from the flag generation unit 22, and the pulse width storage unit 32 takes in the count value C1 of the period measurement counter 31 (the value “7” in the example shown in FIG. 7). Is stored as the count value C2. Here, the value captured by the pulse width storage unit 32 is the pulse width of the synchronization detection signal K2 from time t3 to time t4.

  When the time further elapses and time t5 is reached, the flag FP is output from the flag generator 22 and the flag FA is raised. The complementary period counter 34 captures the count value C1 (the value “14” in the example shown in FIG. 7) of the period measurement counter 31 when the flag FA rises, and starts decrementing the value captured in synchronization with the reference clock CLK. (Refer to the count value C4 in FIG. 7). Here, the value captured by the complementary cycle counter 33 is a value indicating the length of one cycle of the synchronization detection signal K2 from time t3 to time t5.

  At time t5, the count value C3 of the complementary period counter 33 becomes “0”. Since the count values C3 and C4 of the complementary period counters 33 and 34 are multiplexed as the multiplexed signal E1 and output to the complementary pulse width counter unit 35, when the count value C3 of the complementary period counter 33 becomes “0”, the complementary pulse The width counter unit 35 takes in the count value C2 (value “7” in the example shown in FIG. 7) stored in the pulse width storage unit 32, and starts decrementing in synchronization with the reference clock CLK (the count in FIG. 7). See value C5). The complementary pulse width counter unit 35 sets the value of the delay detection signal K3 to “1” because the count value C5 becomes other than “0” when the count value C2 of the pulse width storage unit 32 is fetched. .

  When the time t5 elapses, the cycle measurement counter 31 performs an increment operation (see count value C1), and the complementary cycle counter 34 performs a decrement operation of the count value C1 captured at time t5 (see count value C4), and the complementary pulse width. The counter unit 35 is in a state of performing a decrementing operation of the count value C2 captured at time t5 (see the count value C5). Further, when time elapses and time t6 is reached, a flag FN is output from the flag generation unit 22, so the pulse width storage unit 32 captures the count value C1 of the period measurement counter 31. Here, when the time t6 has elapsed, the count value C5 of the complementary pulse width counter unit 35 becomes “0”, and the value of the delay detection signal K3 becomes “0”.

  When time t6 elapses and time t7 is reached, flag FP is output from flag generation unit 22 and flag FA falls. The complementary cycle counter 33 takes in the count value C1 (value “14” in the example shown in FIG. 7) of the cycle measurement counter 31 at the time when the flag FA falls, and starts decrementing the value taken in synchronization with the reference clock CLK. (Refer to the count value C3 in FIG. 7). Here, the value captured by the complementary cycle counter 33 is a value indicating the length of one cycle of the synchronization detection signal K2 from time t5 to time t7.

  At time t7, when the count value C4 of the complementary period counter 34 becomes “0”, the complementary pulse width counter unit 35 counts the count value C2 stored in the pulse width storage unit 32 (in the example shown in FIG. 7 ") and starts decrementing in synchronization with the reference clock CLK (see count value C5 in FIG. 7). The complementary pulse width counter unit 35 sets the value of the delay detection signal K3 to “1” because the count value C5 becomes other than “0” when the count value C2 of the pulse width storage unit 32 is fetched. .

  Here, paying attention to the period from time t5 to time t7, the time from when the complementary pulse K3 rises to when it falls is the count value C2 (see FIG. 5) taken by the complementary pulse width counter unit 35 from the pulse width storage unit 32 at time t5. In the example shown in FIG. 7, it is determined by the value “7”). The count value C2 is a value obtained by measuring the pulse width of the synchronization detection signal K2 at times t3 to t4. Further, the time from when the complementary pulse K3 rises to once falls and then rises again is the count value C1 (the value “14” in the example shown in FIG. 7) acquired by the complementary cycle counter 34 from the cycle measurement counter 31 at time t5. ). The count value C1 is a value obtained by measuring the length of one cycle of the synchronization detection signal K2 at times t3 to t5.

  As described above, the signal processing device 20 of the present embodiment measures the length and pulse width of each cycle of the synchronization detection signal K2, and the delay detection delayed by one cycle with respect to the synchronization detection signal K2 from these measurement results. The signal K3 is generated (delay step). The generated delay detection signal K3 is input to the edge monitoring unit 25 and the multiplexer 26 in FIG. 2, but when the pulse abnormality does not occur, the value of the selection signal SL output from the edge monitoring unit 25 is “0”. Therefore, the delay detection signal K3 is output as the complementary detection signal K4. The complementary detection signal K4 is output as a detection signal S2 (see FIG. 1) from the output terminal T2. If no pulse abnormality has occurred, the above-described operation is repeated to generate a delay detection signal K3 delayed by one cycle with respect to the synchronization detection signal K2, and this delay detection signal K3 is used as the complementary detection signal K4. Is output as

  Next, an explanation will be given by taking as an example the operation when the detection signal K1 in which a missing pulse has occurred is input to the signal processing device 20 shown in FIG. FIG. 8 is a timing chart showing an operation when the detection signal K1 in which a pulse drop has occurred is input to the signal processing device 20. In FIG. 8, for the sake of simplicity, the count value C1 of the period measurement counter 23, the count values C3 and C4 of the complementary period counter units 33 and 34, and the count value C5 of the complementary pulse width counter unit 35 are triangular waves. Is shown. When these change upward, the count value is incremented, and when they change downward, it means that the count value has been decremented.

  In the example shown in FIG. 8, the synchronization detection signal K2 obtained by synchronizing the detection signal K1 input from the input terminal T1 in FIG. 2 by the synchronization unit 21 is one cycle in the period between times t15 and t16. Minute pulse missing. For such a synchronization detection signal K2, the period measurement counter 31 resets the count value C1 for each period of the synchronization detection signal K2 and is synchronized with the reference clock CLK until time t14 when no missing pulse occurs. Then, the operation of incrementing the count value C1 is repeated.

  The complementary cycle counters 33 and 34 fetch the count value C1 measured by the cycle measurement counter 31 in the previous cycle for each cycle of the synchronization detection signal K2, and synchronize the fetched count value C1 with the reference clock CLK. The decrementing operation is repeated alternately (see the multiplexed signal E1 in FIG. 8). Further, the complementary pulse width counter 35 counts the count stored in the pulse width storage 32 every time the multiplexed signal E1 (one of the count values C3 and C4 of the complementary period counters 33 and 34) becomes “0”. The operation of taking in and decrementing the value C2 (the count value indicating the length of the previous cycle of the synchronization detection signal K2) is repeated (see the count value C5 in FIG. 8). Thereby, the delay detection signal K3 is generated for each period of the synchronization detection signal K2 (delay step).

  When the time t14 elapses, the synchronization detection signal K2 falls once between the time t14 and the time t15, and the pulse width storage unit 32 stores the count value C1 of the period measurement counter 31 at this time. However, since a missing pulse has occurred in the period from time t15 to t16, the count value C1 of the period measurement counter 31 is not reset even at time t15, until the synchronization detection signal K2 rises next (time t16 is reached). Counts up).

  Further, at time t15, the synchronization detection signal K2 does not rise, so that the count value C1 of the period measurement counter 31 is not taken into the complementary period counters 33 and 34. However, at time t15, the count value of one of the complementary period counters 33 and 34 (see the multiplexed signal E1) becomes “0”. As a result, the delay detection signal K3 whose pulse width continues for the count value C2 taken into the pulse width storage unit 32 at the time when the synchronization detection signal K2 once falls in the period between the times t14 and t15 is the time t15. It is generated in a period between t16.

  Since the synchronization detection signal K2 rises at time t16, the complementary period counters 33 and 34 capture and capture the count value C1 of the period measurement counter 31 (this count value indicates the length of two periods of the synchronization detection signal K2). The operation of decrementing the count value C1 in synchronization with the reference clock CLK is started (see the multiplexed signal E1 in FIG. 8). When the synchronization detection signal K2 rises, the period measurement counter 31 resets the count value C1 and starts counting again in synchronization with the reference clock CLK. However, since the complementary cycle counters 33 and 34 do not decrement during the period from time t15 to t16 and the count value remains “0”, the delay detection signal K3 is not transmitted during the period from time t16 to t17. Not generated.

  Further, since the synchronization detection signal K2 falls once between time t16 and time t17, the counter value C1 of the period measurement counter 31 at this time is stored in the pulse width storage unit 32. Thereafter, since the synchronization detection signal K2 rises at time t17, the count value C1 of the period measurement counter 31 at this time is taken into the complementary period counters 33 and 34. Note that the count value C1 captured here is a count value in a period from time t16 to t17. Thereafter, the complementary cycle counters 33 and 34 start an operation of decrementing the fetched count value. The period measurement counter 31 resets the count value C1, and repeats counting in synchronization with the reference clock CLK.

  Incidentally, in the period from time t16 to t17, the complementary period counters 33 and 34 are decrementing, but the initial value is a count value C1 indicating the length of two periods of the synchronization detection signal K2 captured at time t16. is there. For this reason, since the count value of the complementary synchronization counter units 33 and 34 does not become “0” even at time t17, the delay detection signal K3 is not generated even during the period from time t17 to t18.

  Since the count values of the complementary period counters 33 and 34 become “0” at time t18, the complementary detection signal K2 is taken into the pulse width storage unit 32 at the time when the complementary detection signal K2 falls once during the period between the times t17 and t18. A delay detection signal K3 whose pulse width continues for the count value C2 is generated in a period between times t18 and t19. In the period from time t11 to t19, the synchronization detection signal K2 has a missing pulse for one cycle in the period from time t15 to t16, and the generated delay detection signal K3 is in the period from time t16 to t18. A pulse missing for two periods occurs (delay step).

  While the above processing is performed and the delay detection signal K3 is generated, the count values C3 and C4 (multiplexed signal E1) of the complementary period counters 33 and 34 and the count value C5 of the complementary pulse width counter unit 35 are counted signals. E2 is output to the edge monitoring counter unit 36 and also output to the complementary counter unit 24. When the value of the complement start / end signal ST from the edge monitoring unit 25 is “0”, the count values C3 and C4 included in the count signal E2 are pulses of the complement counter unit 24 at the rise or fall of the flag FA. Captured in the period registers 41 and 42. Further, the count value C5 included in the count signal E2 is taken into the pulse width register 46 of the complementary counter unit 24 at the rise and fall of the flag FA.

  The edge monitoring counter unit 36 sets the edge detection area A1 shown in FIG. 4 every time the value of the multiplexed signal E1 included in the count signal E2 becomes “0”, and the count value C5 becomes “0”. Each time, an edge monitoring control signal EW for setting the edge detection area A2 shown in FIG. 4 is output. The edge monitoring control signal EW is output to the edge monitoring unit 25 shown in FIG. Note that the edge monitoring control signal EW is not output until the time immediately before time t16 to t18, because the values of the multiplexed signal E1 and the count value C5 do not become “0”.

  The edge monitoring unit 25 detects the flag FP output from the flag generation unit 22 in the edge detection region A1 set by the edge monitoring control signal EW (detection step). In the present embodiment, the case where the flag FP is detected in the edge detection area A1 will be described as an example. However, the flag FN may be detected in the edge detection area A2. In this case, the flag FN output from the flag generation unit 22 in FIG. 2 needs to be input to the edge monitoring unit 25.

  In the example shown in FIG. 8, the flag FP is detected in all of the edge detection areas A1 set by the edge monitoring control signal EW during the period from time t11 to t14. However, since the flag FP is not output at time t15, the flag FP is not detected in the edge detection region A1 set at time t15. In other words, the flag FP is detected at a time position other than the edge detection area A1 (detection step). As a result, the edge monitoring unit 25 sets the value of the complement start / end signal ST to “1” at time t16 when the time of one cycle of the synchronization detection signal K2 has elapsed from the time when the flag FP is not detected (time t15). At the same time, the value of the selection signal SL is set to “1”.

  When the value of the complementary start / end signal ST from the edge monitoring unit 25 becomes “1”, the pulse width register 46 provided in the complementary counter unit 24 is in a state where the count value C5 is inhibited from being taken in, and the complementary execution counter unit 47 becomes operable. When the complementary execution counter unit 47 becomes operable, the pulse width register 46 takes in the value stored in the pulse width register 46, decrements the value taken in synchronization with the reference clock CLK, and the value becomes “0”. Stop counting at the time. The complement execution counter unit 47 sets the value of the complement signal KC to “1” when the count value is other than “0”. When the count value becomes “0”, the complementary execution counter unit 47 sets the value of the complementary signal KC to “0”.

  Further, when the value of the complement start / end signal ST from the edge monitoring unit 25 becomes “1”, the pulse cycle registers 41 and 42 provided in the complement counter unit 24 are in a state in which the reception of the multiplexed signal E1 is prohibited, and the cycle The generation counter units 43 and 44 become operable. When the flag FA falls in this state, the cycle generation counter unit 43 fetches the count value of the pulse cycle register 41, decrements the count value fetched in synchronization with the reference clock CLK, and the count value becomes “0”. At the time, the count is stopped and a count end pulse signal is output. When the flag FA rises, the cycle generation counter unit 44 fetches the count value of the pulse cycle register 42, decrements the count value fetched in synchronization with the reference clock CLK, and when the count value becomes “0”. Stops counting and outputs a count end pulse signal.

  The count end pulse signals from the cycle generation counter units 43 and 44 are output to the complementary execution counter unit 47 through the OR circuit 45 as the complementary cycle end signal D1. When the complementary cycle end signal D1 is input, the complementary cycle end signal D1 takes in the value stored in the pulse width register 46 and starts counting again. In this way, every time the complementary cycle end signal D1 is input, the value stored in the pulse width register 46 is taken into the complementary execution counter unit 47 and counted. With the above operation, the complement signal KC shown in FIG. 8 is generated while the value of the complement start / end signal ST is “1” (correction signal generation step).

  The complementary signal KC generated by the complementary counter unit 24 is output to the multiplexer 26. Since the value of the selection signal SL output from the edge monitoring unit 25 to the multiplexer 26 is “1”, the complementary signal KC is output from the multiplexer 26 as the complementary detection signal K4 (correction step). Here, when the edge monitoring control signal EW is output again from the period measuring unit 23 to the edge monitoring unit 25 at time t18 in FIG. 8, the edge monitoring unit 25 detects the flag FP. As a result, the edge monitoring unit 25 sets the value of the complement start / end signal ST to “1” at the time t19 when the time of one cycle of the synchronization detection signal K2 has elapsed from the time when the flag FP is detected (time t18). Further, the value of the selection signal CL is set to “0” when the time corresponding to the half cycle of the synchronization detection signal K2 has elapsed. As a result, the operations of the cycle generation counter units 43 and 44 and the complementary momentary counter unit 47 in the complementary counter unit 24 are stopped, and the multiplexer 26 outputs the delay detection signal K3 as the complementary detection signal K4.

  As described above, in this embodiment, the delay detection signal K2 obtained by delaying the detection signal K2 by one cycle is generated, the rising position and the falling position of the delay detection signal K2 are detected, and the rising edge of the delay detection signal K2 is detected. Alternatively, when no falling edge is detected, the complementary signal KC is corrected over a plurality of periods (three periods in the example shown in FIG. 8) from the period in which the trailing edge is not detected. As a result, at least a portion where a pulse abnormality occurs due to the complementary signal KC is corrected. As a result, it is possible to obtain the complementary detection signal K4 that compensates for the rapid fluctuation of the pulse width of the detection signal K1 and the missing pulse, and as a result, the position information of the measurement target OB can be measured with high accuracy. Further, even when the acceleration or the like of the measurement object OB is obtained using this measurement result, an abnormal acceleration is not obtained.

  In the description using FIG. 8, the case where the missing pulse of the detection signal K <b> 1 (synchronization detection signal K <b> 2) has been described as an example, but the signal processing device 20 may compensate for other pulse abnormalities. it can. For example, when an abnormality occurs in which a pulse appears significantly earlier in time as indicated by the symbol PT11 in FIG. 3B, the logic is reversed as indicated by the symbol PT12. And the rise or fall of the pulse is not detected in any case where the pulse width is abnormally narrow, as indicated by the reference numeral PT13. A complementary signal for complementing the abnormal pulse is generated. In the above embodiment, the complementary signal KC is generated only after the abnormal pulse occurs until the flag FP is detected in the edge detection region A1, but the period for generating the complementary signal KC may be arbitrary. Is preferably several cycles (about 5 cycles) of the detection signal K1 (synchronization detection signal K2).

〔stage〕
Next, a stage according to an embodiment of the present invention will be described in detail. FIG. 9 is a diagram showing a schematic configuration of a stage according to an embodiment of the present invention. Note that the stage shown in FIG. 9 is a stage for moving a wafer (semiconductor wafer) W in a horizontal plane. In the description of this stage, the description proceeds with the X axis and Y axis orthogonal to each other set in the horizontal plane in which the wafer W moves.

  As shown in FIG. 9, the stage of the present embodiment drives the wafer stage 66 and a stage unit 65 including a wafer stage 66 as a movable body configured to be movable in the XY plane while holding the wafer W. And a control unit 60 as a drive control unit. The controller 60 includes a host controller 61, a controller 62, current amplifiers 63a to 63c, and position detectors 64a and 64b.

  The host controller 61 outputs a control signal indicating the position of the wafer W in the XY plane to the controller 62. The control controller 62 generates a drive signal for driving the linear motors 67 to 69 included in the stage unit 65 based on the control signal output from the host controller 61 and the detection signals output from the position detection units 64a and 64b. Generate and control the operation of the wafer stage 66 on which the wafer W is placed.

  The current amplifiers 63 a to 63 c amplify the current of the drive signal output from the controller 62 with a predetermined amplification factor, and supply the amplified current to the linear motors 67 to 69 provided in the stage unit 65. The position detectors 64a and 64b perform the above-described signal processing on the detection signals output from the laser interferometers 70a and 70b provided on the stage unit 65, and thereby the position of the wafer stage 66 in the X direction and the Y direction ( Stage position) is detected. In the stage apparatus shown in FIG. 9, the laser interferometers 70a and 70b and the position detectors 64a and 64b correspond to the interferometer system referred to in the present invention.

  Next, the stage unit 65 will be described in detail. FIG. 10 is a perspective view illustrating a configuration example of the stage unit 65. As shown in FIGS. 9 and 10, the stage unit 65 is integrated with a wafer stage 66, a wafer surface plate 71 that supports the wafer stage 66 movably in a two-dimensional direction along the XY plane, and the wafer stage 66. A sample table 72 that is provided and sucks and holds the wafer W, and an X guide bar 73 that supports the wafer stage 66 and the sample table 72 in a relatively movable manner are mainly configured. A plurality of air bearings (air pads) (not shown) which are non-contact bearings are fixed to the bottom surface of the wafer stage 66, and the wafer stage 66 is placed on the wafer surface plate 71 by, for example, about several microns by these air bearings. It is supported by levitating via clearance.

  The wafer surface plate 71 is supported substantially horizontally via a vibration isolating unit (not shown), for example, above a base plate (not shown). Here, the anti-vibration unit is arranged at each corner of the wafer surface plate 71, for example, and has a configuration in which an air mount capable of adjusting the internal pressure and a voice coil motor are arranged in parallel on the base plate. By these vibration isolation units, the micro vibration transmitted to the wafer surface plate 71 via the base plate is insulated at the micro G level.

  As shown in FIG. 10, the X guide bar 73 has a long shape along the X direction, and a movable element 67a and a movable element 68a each composed of an armature unit are provided at both ends in the longitudinal direction. Is provided. The stators 67b and 68b each having a magnet unit corresponding to each of the movers 67a and 68a are provided on a support portion protruding from a base plate (not shown).

  The mover 67a and the stator 67b constitute a linear motor 67, and the mover 68a and the stator 68b constitute a linear motor 68. The mover 67a is driven by electromagnetic interaction with the stator 67b, and the mover 68a is driven by electromagnetic interaction with the stator 68b, whereby the X guide bar 73 moves in the Y direction. Then, by adjusting the driving amounts of the linear motor 67 and the linear motor 68, the wafer stage 66 rotates around the Z axis orthogonal to the X axis and the Y axis. That is, the wafer stage 66 (and the sample stage 72) is driven about the Y direction and the Z axis almost integrally with the X guide bar 73 by the linear motors 67 and 68.

  A mover of an X trim motor 77 is attached to the X direction side of the X guide bar 73. The X trim motor 77 adjusts the position of the X guide bar 73 in the X direction by generating thrust in the X direction, and its stator is provided on a reaction frame (not shown). Therefore, the reaction force when driving the wafer stage 66 in the X direction has a function of being transmitted to the base plate via the reaction frame.

  The sample stage 72 is supported in a non-contact manner relative to the X guide bar 73 so as to be relatively movable in the X direction via a magnetic guide composed of a magnet and an actuator that maintain a predetermined amount of gap in the Z direction with the X guide bar 73. -Retained. Further, the wafer stage 66 is driven in the X direction by electromagnetic interaction by a linear motor 69 having a stator embedded in the X guide bar 73. The mover of the linear motor 69 is not shown, but is attached to the wafer stage 66. A wafer W is fixed to the upper surface of the sample table 72 by vacuum suction or the like via a wafer holder (not shown).

  The linear motor 69 is disposed closer to the wafer W placed on the wafer stage 66 than the linear motors 67 and 68, and the mover of the linear motor 69 is fixed to the sample stage 72. Yes. For this reason, it is desirable to use a moving magnet type linear motor 69 that is not fixed to the sample table 72 directly away from the wafer W, with the coil serving as a heat source serving as a stator.

  Since the linear motors 67 and 68 drive the linear motor 69, the X guide bar 73, and the sample stage 72 as one body, they require a much larger thrust than the X linear motor 69. Therefore, a large amount of electric power is required and the amount of generated heat is larger than that of the linear motor 69. Therefore, it is desirable to use moving coil type linear motors for the linear motors 67 and 68.

  A moving mirror 75 extending in the X direction and a moving mirror 76 extending in the Y direction are attached to the end of the wafer stage 66. Laser interferometers 70b and 70a (see FIG. 1) are respectively attached at positions facing the mirror surfaces of the movable mirrors 75 and 76, and the measurement results of the laser interferometers 70a and 70b are output to 64a and 64b. The above-described signal processing is performed, and the position in the X direction and the Y direction of the wafer stage 66 are measured in real time with a predetermined resolution, for example, a resolution of about 0.5 to 1 nm. Note that at least one of the laser interferometers 70a and 70b is a multi-axis interferometer having two or more measurement axes, and the X direction of the wafer stage 66 (and thus the wafer W) is measured based on the measurement values of these laser interferometers. Not only the position and the position in the Y direction, but also the rotation amount and leveling amount around the Z axis can be obtained.

[Exposure equipment]
Next, the exposure apparatus will be described in detail. FIG. 11 is a view showing a schematic configuration of the exposure apparatus. The exposure apparatus shown in FIG. 11 is a so-called step-and-scan exposure apparatus that sequentially transfers an image of a pattern formed on the reticle R onto the wafer W while moving the reticle R and the wafer W synchronously. In FIG. 11, reference numeral 80 denotes an ultrahigh pressure mercury lamp that emits g-line (wavelength 436 nm), i-line (wavelength 365 nm), or KrF excimer laser (wavelength 248 nm), ArF excimer laser (wavelength 193 nm), or F ₂ excimer laser. The illumination optical system includes a light source (wavelength 193 nm) and the like, and emits illumination light IL shaped into a predetermined shape while making the light intensity distribution of light emitted from these light sources uniform.

  81 is a reticle stage on which a reticle R as a mask is placed, which can be finely moved in the direction of the optical axis AX of the projection optical system PL, and can be two-dimensionally moved and finely rotated in a plane perpendicular to the optical axis AX. Configured. A movable mirror 82 is attached to one end of the reticle stage 81, and a laser interferometer 84 is disposed at a position facing the mirror surface of the movable mirror 82. A fixed mirror 83 is attached to the illumination optical system 80 described above. The fixed mirror 83 may be attached to the projection optical system PL.

  The laser interferometer 84 irradiates the movable mirror 82 with a laser beam having a wavelength λ1, and irradiates the fixed mirror 83 with a laser beam having a wavelength λ2 different from the wavelength of the laser beam irradiated to the movable mirror 82. A detection signal is obtained by detecting the interference light obtained by causing the reflected light to interfere. Further, an optical path similar to the reference optical path P1 shown in FIG. 1 is provided inside the laser interferometer 84, and a laser beam having wavelengths λ1 and λ2 through this optical path is caused to interfere to obtain a reference signal.

  The laser interferometer 84 performs glitch reduction processing after digitizing these reference signals and detection signals, and further performs the signal processing described above to generate the reference signals S1 and detection signals S2 and S3 shown in FIG. The signal S1 and the detection signal S2 are compared, and the reference signal S1 and the detection signal S3 are compared to measure the X coordinate, the Y coordinate, and the rotation angle of the reticle stage 81. When the reticle stage 81 is regarded as the measurement object OB shown in FIG. 1, the laser interferometer 84 corresponds to the interferometer system shown in FIG.

  Although the illustration is simplified in FIG. 11, the movable mirror 82 includes a movable mirror having a mirror surface perpendicular to the X axis and a movable mirror having a mirror surface perpendicular to the Y axis. The laser interferometer 84 includes two Y-axis laser interferometers that irradiate the moving mirror 82 with a laser beam along the Y axis, and an X-axis laser that irradiates the movable mirror 82 with a laser beam along the X axis. The X and Y coordinates of the reticle stage 81 are measured by one laser interferometer for the Y axis and one laser interferometer for the X axis. Further, the rotation angle of reticle stage 81 is measured based on the difference between the measured values of the two Y-axis laser interferometers. Information on the X coordinate, the Y coordinate, and the rotation angle of the reticle stage 81 detected by the laser interferometer 84 is supplied to the main control system 85. The main control system 85 outputs a control signal to the drive system 86 while monitoring the supplied stage position information, and controls the positioning operation of the reticle stage 81.

  The reticle R placed on the reticle stage 81 has a device pattern DP such as a semiconductor element or a liquid crystal display element formed of chromium or the like on the surface of a transparent glass substrate. When the reticle R is illuminated by the illumination light IL emitted from the illumination optical system 80, an image of the device pattern DP formed on the reticle R is transferred onto the wafer W via the projection optical system PL. The wafer W is placed on the wafer stage 87. Note that the surface (pattern surface) on which the device pattern DP of the reticle R is formed and the surface of the wafer W are optically conjugate with respect to the projection optical system PL.

  The wafer stage 87 is an XY stage that moves the wafer W in the XY plane, a Z stage that moves the wafer W in the Z-axis direction, a stage that rotates the wafer W in the XY plane, and an angle with respect to the Z-axis by changing the angle with respect to the Z-axis. The stage is configured to adjust the inclination of the wafer W with respect to the plane. A movable mirror 88 having a length longer than the movable range of the wafer stage 87 is attached to one end of the upper surface of the wafer stage 87, and a laser interferometer 90 is disposed at a position facing the mirror surface of the movable mirror 88. A fixed mirror 89 is attached to the projection optical system PL described above.

  The laser interferometer 90 irradiates the movable mirror 88 with laser light having a wavelength λ1, and irradiates the fixed mirror 89 with laser light having a wavelength λ2 different from the wavelength of the laser light irradiated on the movable mirror 88. A detection signal is obtained by detecting the interference light obtained by causing the reflected light to interfere. In addition, an optical path similar to the reference optical path P1 shown in FIG. 1 is provided inside the laser interferometer 90, and a reference signal is obtained by interfering with laser beams having wavelengths λ1 and λ2 via the optical path.

  The laser interferometer 90 performs a glitch reduction process after digitizing the reference signal and the detection signal, and further performs the signal processing described above to generate the reference signal S1 and the detection signals S2 and S3 shown in FIG. The signal S1 and the detection signal S2 are compared, and the reference signal S1 and the detection signal S3 are compared to measure the X coordinate, the Y coordinate, and the rotation angle of the wafer stage 87. When the wafer stage 87 is regarded as the measurement object OB shown in FIG. 1, the laser interferometer 90 corresponds to the interferometer system shown in FIG.

  Although the illustration is simplified in FIG. 11, the movable mirror 88 includes a movable mirror having a mirror surface perpendicular to the X axis and a movable mirror having a mirror surface perpendicular to the Y axis. The laser interferometer 90 includes two Y-axis laser interferometers that irradiate the moving mirror 88 with a laser beam along the Y-axis and an X-axis laser that irradiates the movable mirror 88 with a laser beam along the X-axis. The X and Y coordinates of the wafer stage 87 are measured by one laser interferometer for the Y axis and one laser interferometer for the X axis. Further, the rotation angle of the wafer stage 87 is measured by the difference between the measurement values of the two Y-axis laser interferometers. Information on the X coordinate, Y coordinate, and rotation angle of the wafer stage 87 measured by the laser interferometer 90 is supplied to the main control system 85. The main control system 85 outputs a control signal to the drive system 91 while monitoring the supplied stage position information, and controls the positioning operation of the wafer stage 87.

  When the image of the device pattern DP formed on the reticle R is transferred onto the wafer W, first, the main control system 85 measures accurate position information of the reticle R using a reticle alignment system (not shown) and wafer alignment. After measuring the accurate position information of the wafer W using the system, the relative positions of the reticle R and the wafer W are adjusted based on these measurement results and the measurement results of the laser interferometer 84 and the laser interferometer 90. . Next, a control signal is output to the drive system 86 and the drive system 90 to start the movement between the reticle R and the wafer W, and the reticle R is irradiated with slit-shaped illumination light IL. Thereafter, while the detection results of the laser interferometer 84 and the laser interferometer 90 are monitored, the reticle R and the wafer W are moved synchronously to sequentially transfer the device pattern DP onto the wafer W.

  As mentioned above, although embodiment of this invention was described, this invention is not restrict | limited to the said embodiment, It can change freely within the scope of the present invention. For example, in the above embodiment, the complementary signal K3 is generated by delaying the detection signal K1 input to the input terminal T1 of the signal processing device 20 by one cycle of the detection signal K1, and the detection signal K1 and the complementary signal are generated. The complementary detection signal K4 is generated by performing an OR operation with K3. However, the delay time of the complementary signal K3 with respect to the detection signal K1 may be for a plurality of cycles of the detection signal K1.

  In the above-described embodiment, the interferometer system using the signal processing of the present invention is used to measure one-dimensional or two-dimensional position information of a measurement target (stage). As disclosed in Japanese Laid-Open Patent Publication No. 2000-49066 and Japanese Translation of PCT International Publication No. 2001-513267, etc., this interferometer system is also used in order to obtain position information, rotation, inclination, etc. of a measurement target. The invention can be applied.

In the above embodiment, the step-and-scan type exposure apparatus has been described as an example. However, the present invention can also be applied to a step-and-repeat type exposure apparatus. The light source provided in the illumination optical system 80 of the exposure apparatus of the present embodiment is not only an ultrahigh pressure mercury lamp, a KrF excimer laser, an ArF excimer laser, or an F ₂ laser (157 nm), but also charged such as an X-ray or an electron beam. Particle beams can be used. For example, when an electron beam is used, thermionic emission type lanthanum hexabolite (LaB ₆ ) or tantalum (Ta) can be used as the electron gun. In the above-described embodiment, the case of manufacturing a semiconductor element or a liquid crystal display element has been described as an example. Of course, the exposure apparatus is used for manufacturing a thin film magnetic head and transfers a device pattern onto a ceramic wafer. The present invention can also be applied to an exposure apparatus used for manufacturing an image sensor such as a CCD.

  Furthermore, a single wavelength laser beam in the infrared region or visible region oscillated from a DFB semiconductor laser or fiber laser as a light source is amplified by, for example, a fiber amplifier doped with erbium (or both erbium and yttrium), and nonlinear optics You may use the harmonic which wavelength-converted into the ultraviolet light using the crystal | crystallization. For example, if the oscillation wavelength of a single wavelength laser is in the range of 1.51 to 1.59 μm, the generated wavelength is in the range of 189 to 199 nm, the eighth harmonic, or the generated wavelength is in the range of 151 to 159 nm. A 10th harmonic is output.

In particular, when the oscillation wavelength is in the range of 1.544 to 1.553 μm, the 8th harmonic in the range of 193 to 194 nm, that is, ultraviolet light having substantially the same wavelength as the ArF excimer laser light is obtained. When the oscillation wavelength is in the range of 1.57 to 1.58 μm, the 10th harmonic wave in the range of 157 to 158 nm, that is, ultraviolet light having substantially the same wavelength as the F ₂ laser light is obtained. Further, if the oscillation wavelength is in the range of 1.03 to 1.12 μm, the seventh harmonic whose output wavelength is in the range of 147 to 160 nm is output, and in particular, the oscillation wavelength is in the range of 1.099 to 1.106 μm. If it is inside, the 7th harmonic in the range of 157 to 158 μm, that is, ultraviolet light having substantially the same wavelength as the F ₂ laser light is obtained. In this case, for example, an yttrium-doped fiber laser can be used as the single wavelength oscillation laser.

  Further, the present invention is not limited to an exposure apparatus used for manufacturing a semiconductor element, but also used for manufacturing a display including a liquid crystal display element (LCD) and the like, an exposure apparatus for transferring a device pattern onto a glass plate, and a thin film magnetic head. The present invention can also be applied to an exposure apparatus that is used for manufacturing and transfers a device pattern onto a ceramic wafer, and an exposure apparatus that is used to manufacture an image sensor such as a CCD. Furthermore, in an exposure apparatus that transfers a circuit pattern onto a glass substrate or a silicon wafer in order to manufacture a reticle or mask used in an optical exposure apparatus, EUV exposure apparatus, X-ray exposure apparatus, electron beam exposure apparatus, or the like. The present invention can also be applied. Here, in an exposure apparatus using DUV (far ultraviolet) light, VUV (vacuum ultraviolet) light, or the like, a transmission type reticle is generally used. As a reticle substrate, quartz glass, fluorine-doped quartz glass, fluorite, Magnesium fluoride or quartz is used. Further, in a proximity type X-ray exposure apparatus or an electron beam exposure apparatus, a transmission mask (stencil mask, membrane mask) is used, and a silicon wafer or the like is used as a mask substrate.

  The stage of the present invention is not limited to the reticle stage and wafer stage provided in the exposure apparatus, but is also a stage apparatus that moves with the object placed thereon (not limited to one-dimensional movement or two-dimensional movement). In the case of control, it can be applied in general.

  Next, an embodiment of a microdevice manufacturing method using the above-described exposure apparatus in a lithography process will be described. FIG. 12 is a flowchart showing an example of a manufacturing process of a microdevice (a semiconductor chip such as an IC or LSI, a liquid crystal panel, a CCD, a thin film magnetic head, a micromachine, etc.). As shown in FIG. 12, first, in step S10 (design step), a function / performance design (for example, circuit design of a semiconductor device) of a micro device is performed, and a pattern design for realizing the function is performed. Subsequently, in step S11 (mask manufacturing step), a mask (reticle) on which the designed circuit pattern is formed is manufactured. On the other hand, in step S12 (wafer manufacturing step), a wafer is manufactured using a material such as silicon.

  Next, in step S13 (wafer processing step), using the mask and wafer prepared in steps S10 to S12, an actual circuit or the like is formed on the wafer by lithography or the like, as will be described later. Next, in step S14 (device assembly step), device assembly is performed using the wafer processed in step S13. This step S14 includes processes such as a dicing process, a bonding process, and a packaging process (chip encapsulation) as necessary. Finally, in step S15 (inspection step), inspections such as an operation confirmation test and a durability test of the microdevice manufactured in step S14 are performed. After these steps, the microdevice is completed and shipped.

  FIG. 13 is a diagram showing an example of a detailed flow of step S13 of FIG. 12 in the case of a semiconductor device. In FIG. 13, in step S21 (oxidation step), the surface of the wafer is oxidized. In step S22 (CVD step), an insulating film is formed on the wafer surface. In step S23 (electrode formation step), an electrode is formed on the wafer by vapor deposition. In step S24 (ion implantation step), ions are implanted into the wafer. Each of the above steps S21 to S24 constitutes a pretreatment process at each stage of the wafer processing, and is selected and executed according to a necessary process at each stage.

  At each stage of the wafer process, when the above-described pre-processing step is completed, the post-processing step is executed as follows. In this post-processing step, first, in step S25 (resist formation step), a photosensitive agent is applied to the wafer. Subsequently, in step S26 (exposure step), the circuit pattern of the mask is transferred to the wafer by the lithography system (exposure apparatus) and the exposure method described above. Next, in step S27 (development step), the exposed wafer is developed, and in step S28 (etching step), the exposed members other than the portion where the resist remains are removed by etching. In step S29 (resist removal step), the resist that has become unnecessary after the etching is removed. By repeatedly performing these pre-processing steps and post-processing steps, multiple circuit patterns are formed on the wafer.

  In the microdevice manufacturing method described above, since the positional information of the mask and the wafer is measured with high accuracy using the signal processing method described above in the exposure step (step S26), the pattern already formed on the wafer Overlay accuracy with a pattern transferred onto a wafer can be improved, and as a result, a highly integrated device having a minimum line width of about 0.1 μm can be produced with a high yield.

  Further, in order to manufacture reticles or masks used in not only microdevices such as semiconductor elements but also light exposure apparatuses, EUV exposure apparatuses, X-ray exposure apparatuses, electron beam exposure apparatuses, etc., from mother reticles to glass substrates and The present invention can also be applied to an exposure apparatus that transfers a circuit pattern to a silicon wafer or the like. Here, in an exposure apparatus using DUV (deep ultraviolet), VUV (vacuum ultraviolet) light, or the like, a transmission type reticle is generally used. As a reticle substrate, quartz glass, fluorine-doped quartz glass, fluorite, Magnesium fluoride or quartz is used. In proximity type X-ray exposure apparatuses, electron beam exposure apparatuses, and the like, a transmissive mask (stencil mask, membrane mask) is used, and a silicon wafer or the like is used as a mask substrate. Such an exposure apparatus is disclosed in WO99 / 34255, WO99 / 50712, WO99 / 66370, JP-A-11-194479, JP-A2000-12453, JP-A-2000-29202, and the like. .

It is a block diagram which shows the outline of a structure of the interferometer system in which the signal processing method by one Embodiment of this invention is used. It is a block diagram which shows the structure of the signal processing apparatus with which the signal processing method by one Embodiment of this invention is used. It is a figure which shows an example of the detection signal input into the input terminal T1 of a signal processing apparatus. It is a figure for demonstrating the edge detection area | region set with respect to the delay detection signal K3. 3 is a block diagram showing an internal configuration of a period measurement unit 23. FIG. 4 is a block diagram showing an internal configuration of a complementary counter unit 24. FIG. 3 is a timing chart showing a procedure for generating a delay detection signal K3 generated in the signal processing device 20. 7 is a timing chart showing an operation when a detection signal K1 in which a pulse drop has occurred is input to the signal processing device 20. It is a figure which shows schematic structure of the stage by one Embodiment of this invention. It is a perspective view which shows the structural example of the stage part 65. FIG. It is a figure which shows schematic structure of exposure apparatus. It is a flowchart which shows an example of the manufacturing process of a microdevice. It is a figure which shows an example of the detailed flow of FIG.12 S13 in the case of a semiconductor device.

Explanation of symbols

10 Interferometer system 13 Reference receiver (reference machine)
15, 17 Receiver 60 Control unit (drive control unit)
66 Wafer stage (movable body)
64a, 64b Position detector (interferometer system)
70a, 70b Laser interferometer (interferometer system)
A1, A2 Edge detection area (predetermined time position)
K1 detection signal (predetermined signal)
K2 Sync detection signal (predetermined signal)
K3 Delay detection signal (delay signal)
KC complementary signal (correction signal)
OB measurement object S1 reference signal S2, S3 detection signal

Claims (7)

A signal processing method in an interferometer system that measures position information of the measurement object based on reflected light obtained by irradiating the measurement object with measurement light,
A delay step of obtaining a delayed signal obtained by delaying the predetermined signal by a predetermined period;
A detection step of detecting a change in the signal level of the delayed signal at a time position other than the predetermined time position;
A correction signal generation step for generating a correction signal for correcting the delay based on a detection result of the detection step;
A signal in an interferometer system, comprising: a correction step of correcting the delay signal by the correction signal; and a measurement step of measuring position information of the measurement object using the delay signal corrected in the correction step. Processing method.   The correction signal generating step is a step of generating a correction signal for correcting the delay signal in a period extending from a time position other than the predetermined time position to a plurality of cycles of the delay signal. A signal processing method in an interferometer system.   3. The signal processing method in the interferometer system according to claim 1, wherein the detecting step is a step of detecting presence or absence of rising and falling of the signal level of the delayed signal with a predetermined time width. .   The interference signal according to any one of claims 1 to 3, wherein the predetermined signal is a detection signal obtained by detecting an interference light obtained by causing the reflected light and the reference light to interfere with each other. Signal processing method in metering system.   The predetermined signal is a reference signal for comparing with a detection signal obtained by detecting interference light obtained by causing interference between the reflected light and reference light in order to obtain position information of the measurement target. A signal processing method in the interferometer system according to any one of claims 1 to 3. A movable body configured to be movable in a predetermined movement direction;
An interferometer system that measures the position information using the movable body as the measurement object using the signal processing method according to any one of claims 1 to 5,
And a drive control unit that drives the movable body based on a measurement result of the interferometer system. A reference machine that outputs a reference signal; and a receiver that outputs a detection signal obtained by causing interference between reflected light obtained by irradiating measurement light to a measurement object and reference light; and a reference signal from the reference machine And an interferometer system for obtaining the position information of the measurement object based on the detection signal from the receiver,
The reference machine corrects the digitally processed signal using the signal processing method according to any one of claims 1 to 5, and outputs the signal after the correction process as the reference signal. Interferometer system featuring.

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