JP2006060137A - Semiconductor memory device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which the capacity of a capacitor and data retention characteristics can be enhanced furthermore, and to provide its manufacturing method. <P>SOLUTION: The semiconductor memory device comprises a semiconductor substrate, a transistor Tr formed on the semiconductor substrate, a first memory capacitor Ct formed in a trench formed in the semiconductor substrate and having a first memory node electrode connected with one node of a transistor, an interlayer dielectric formed to cover the transistor, a second memory capacitor Cs formed on the interlayer dielectric and having a second memory node electrode connected with one node, and a memory node contact plug formed while penetrating the interlayer dielectric and connecting the first and the second memory node electrodes wherein a plurality of memory cells having the first and the second memory capacitors and the transistor are arranged. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a semiconductor memory device which is a dynamic random access memory (DRAM) and a manufacturing method thereof.

In recent years, semiconductor devices such as VLSI have been reduced by 70% in three years to achieve higher integration and higher performance.
For example, a MOS type DRAM in which one memory cell is composed of one transistor for switching (metal-oxide-semiconductor stacked field effect transistor; MOSFET) and one memory capacitor is highly integrated as a process driver in a semiconductor device. It is going on.
As the device is miniaturized, the area of the memory cell is reduced, so that the area occupied by the memory capacitor is also reduced.

However, in order to secure an operating margin and to secure the soft error tolerance due to alpha rays, the storage capacity of the memory capacitor is a constant value of 20 to 30 fF per bit regardless of the generation of the DRAM. It is kept in.
Therefore, as the memory capacitor is miniaturized, it is necessary to secure the required amount of the storage capacity, although the occupied area is reduced, and various contrivances have been made for that purpose.

For example, a method of reducing the film thickness of the capacitor insulating film or a method of increasing the storage capacity using a material having a higher relative dielectric constant as the capacitor insulating film has been developed.
On the other hand, the electrode structure of the capacitor has been devised, and those having various structures have been developed. The memory capacitor has a storage node electrode (electrode connected to the capacitor transistor), a plate electrode (electrode grounded to the capacitor), and a capacitance insulating film therebetween, for example, the capacitors are configured in a stacked manner By increasing the surface area of the opposing surface of the storage node electrode and the plate electrode by using a stack type structure or a trench type structure in which the storage node electrode is formed in the depth direction with respect to the semiconductor substrate, The storage capacity can be increased.

Patent Document 1 discloses a DRAM having the above-described stack type memory capacitor.
A MOS transistor is formed on a silicon semiconductor substrate, an interlayer insulating film is formed so as to cover the MOS transistor, and a bit line is formed in connection with one source / drain region of the transistor. An interlayer insulating film is formed so as to cover this, and a storage node contact plug is formed by connecting to the other source / drain region of the transistor, and a storage node electrode, a capacitor insulating film, a plate are formed on the lower layer side. The electrodes are stacked to form a memory capacitor.
The above DRAM has a so-called COB (Capacitor Over Bitline) type structure.

Patent Document 2 discloses a DRAM having the above-described trench type memory capacitor.
FIG. 10 is a cross-sectional view of a main part of a DRAM having a trench type memory capacitor.
A gate electrode 120 is formed on a semiconductor region 112 serving as an active region provided on a silicon semiconductor substrate via a gate insulating film 119, and an impurity region 121a is included in the semiconductor region 112 on both sides of the gate electrode. Source / drain regions are formed to constitute a MOS transistor. Sidewall insulating films 122 are formed on both sides of the gate electrode.

  In addition, a trench 110a is formed in the semiconductor substrate with a predetermined gap from the MOS transistor, and a capacitor insulating film (not shown) is formed to cover the inner wall surface of the trench 110a from the bottom of the trench 110a to an intermediate depth. Has been. A plate electrode, which is an impurity diffusion region, is formed in the semiconductor substrate in the region where the capacitive insulating film is formed. On the other hand, a first conductive layer (not shown) is buried inside the capacitive insulating film. Has been.

A collar insulating film 115 is formed covering the inner wall surface of the trench 110a from the upper end of the capacitive insulating film to the vicinity of the edge of the trench 110a, and is connected to the first conductive layer on the inner side of the second insulating film. A layer 117 is formed.
Further, a thin BS (Buried-Strap) insulating film 115b is formed from the upper end of the collar insulating film 115 to the edge of the trench 110a so as to cover the inner wall surface of the trench 110a. A third conductive layer 117a made of polysilicon containing a conductive impurity such as P or As is connected to the second conductive layer 117. Further, a BS diffusion layer 117b is formed in the semiconductor region 112 so as to be connected to the impurity region 121a so as to face the third conductive layer 117a through the BS insulating film 115b.
A storage node electrode is composed of the first conductive layer, the second conductive layer 117, and the third conductive layer 117a, and the first conductive layer portion of the storage node electrode and the plate electrode are opposed to each other through the capacitive insulating film, A memory capacitor is configured.

In the BS diffusion layer 117b, conductive impurities such as P and As contained in the third conductive layer 117a are formed by the well formation, element isolation formation, and transistor formation process heat treatment processes, so that the silicon substrate trench 110a and the third conductive layer 117a are formed. This is formed by diffusing into the semiconductor region 112 through the thin BS insulating film 115b formed at the interface portion.
The above contact structure is called a buried strap (BS). In the buried portion through the BS diffusion layer 117b and the thin BS insulating film 115b, the impurity region 121a which is the source / drain region of the memory cell transistor and the memory of the trench capacitor are stored. Electrical connection with the third conductive layer 117a constituting the node electrode is realized.

By the way, with the integration of DRAMs, among the big issues of how to improve capacitor capacity and data retention characteristics, from the viewpoint of capacitor capacity, the reduction of the capacitor area due to memory cell shrink, and junction leakage from the viewpoint of data retention characteristics Subthreshold leakage is a problem.
Various technical studies have been reported for the above problem, but it is very difficult to achieve both capacitor capacity and data retention characteristics.
For example, if a high dielectric constant film is used to increase the capacitance of the capacitor, leakage between the capacitor electrodes increases. Further, if the storage node diffusion layer concentration is reduced in order to suppress junction leakage, the diffusion layer sheet resistance increases, leading to deterioration of the driving capability of the cell transistor. Due to such parasitic resistance, the random access speed of the DRAM macro becomes low, and there is a problem that the demand for high performance cannot be sufficiently satisfied.
JP 2003-332261 A JP 2004-47905 A

  The problem to be solved is that it is difficult to further improve the capacitor capacity and data retention characteristics.

  The semiconductor memory device of the present invention has a semiconductor substrate, a transistor formed in the semiconductor substrate, and a first storage node electrode formed in a trench formed in the semiconductor substrate and connected to one node of the transistor. A first memory capacitor; an interlayer insulating film formed to cover the transistor; a second memory capacitor formed on the interlayer insulating film and having a second storage node electrode connected to the one node; A storage node contact plug formed through the interlayer insulating film and connecting the first storage node electrode and the second storage node electrode; and the first memory capacitor, the second memory capacitor, and the transistor A plurality of memory cells are arranged.

The semiconductor memory device of the present invention described above includes a transistor formed on a semiconductor substrate, a first memory capacitor formed in a trench formed in the semiconductor substrate, and a second layer formed on an interlayer insulating film covering the transistor. A plurality of memory cells having memory capacitors are arranged.
Here, the first storage node electrode and the second storage node electrode are connected to each other by a storage node contact plug that penetrates the interlayer insulating film to have the same potential, and both are connected to one node of the transistor.

  The method of manufacturing a semiconductor memory device according to the present invention includes a step of forming a trench in a semiconductor substrate, a step of forming a first memory capacitor having a first storage node electrode in the trench, and a predetermined distance from the trench. Forming a transistor on the semiconductor substrate, forming an interlayer insulating film covering the transistor and the first memory capacitor, and storing at least the surface of the first storage node electrode on the interlayer insulating film Opening a node contact hole; forming a storage node contact plug connected to the first storage node electrode in the storage node contact hole; and connecting a storage node contact plug to the storage node contact plug on the interlayer insulating film. Forming a second memory capacitor having two storage node electrodes, In the step of forming one memory capacitor, the step of forming the transistor, the step of opening the storage node contact hole and / or the step of forming the storage node contact plug, the first storage node electrode and the second storage node An electrode is formed so as to be connected to one node of the transistor.

In the method of manufacturing a semiconductor memory device according to the present invention, a trench is formed in a semiconductor substrate, and a first memory capacitor having a first storage node electrode is formed in the trench.
Next, a transistor is formed on the semiconductor substrate at a predetermined distance from the trench, and an interlayer insulating film is formed covering the transistor and the first memory capacitor.
Next, a storage node contact hole reaching at least the surface of the first storage node electrode is opened in the interlayer insulating film, and a storage node contact plug connected to the first storage node electrode is formed in the storage node contact hole.
Next, a second memory capacitor having a second storage node electrode connected to the storage node contact plug is formed on the interlayer insulating film.
Here, in the step of forming the first memory capacitor, the step of forming the transistor, the step of opening the storage node contact hole and / or the step of forming the storage node contact plug, the first storage node electrode and the second storage node electrode Is connected to one node of the transistor.

  The semiconductor memory device of the present invention can improve capacitor capacity and data retention characteristics.

  The method for manufacturing a semiconductor memory device of the present invention can manufacture a semiconductor memory device with improved capacitor capacity and data retention characteristics.

  Embodiments of a random access memory (DRAM), which is a semiconductor memory device according to the present invention, and a manufacturing method thereof will be described below with reference to the drawings.

First Embodiment FIG. 1 is an equivalent circuit diagram of a semiconductor memory device (DRAM) according to this embodiment.
A plurality of memory cells are provided in a matrix at intersections of a plurality of word lines (WL1, WL2,...) And bit lines (BL1, BL2,...).
Each memory cell includes one transistor Tr for switching whose gate electrode is connected to a word line (WL1.WL2,...) And two memories connected in parallel to one source / drain of the transistor Tr. And capacitors (Ct, Cs). The other source / drain of the transistor Tr is connected to bit lines (BL1, BL2,...).

FIG. 2A is a schematic cross-sectional view showing the structure of the semiconductor memory device (DRAM) according to the present embodiment, and FIG. 2B is an enlarged cross-sectional view of the main part.
For example, a gate electrode 20 made of, for example, polysilicon or polycide is formed on a p-type semiconductor region 12 serving as an active region provided on a silicon semiconductor substrate via a gate insulating film 19 made of silicon oxide or the like. In addition, n-type source / drain regions including low-concentration impurity regions (21a, 21b) and high-concentration impurity regions 23 called extension regions are formed in the semiconductor region 12 on both sides of the gate electrode 20, and the semiconductor An n-channel MOS transistor having a channel formation region in the region 12 is formed. Sidewall insulating films 22 are formed on both sides of the gate electrode.

  Further, a trench 10a having a depth of, for example, about 5 to 6 μm is formed in the semiconductor substrate with a predetermined gap from the MOS transistor, and covers the inner wall surface of the trench 10a from the bottom of the trench 10a to a midway depth. Thus, the first capacitor insulating film 13 made of, for example, SiN or SiON is formed. The first plate electrode 11 which is an impurity diffusion region is formed in the semiconductor substrate in the region where the first capacitor insulating film 13 is formed, while the first conductive layer 14 is formed inside the first capacitor insulating film. Is embedded and formed.

A collar insulating film 15 is formed to cover the inner wall surface of the trench 10a from the upper end of the first capacitor insulating film 13 to the edge of the trench 10a, and is connected to the first conductive layer 14 on the inner side. A second conductive layer 17 is formed.
Further, the vicinity of the upper end of the color insulating film 15 is a thinned region 15a, and the second conductive layer 17 has an increased contact area contributing to the storage node contact in the thinned region 15a. .
The second conductive layer 17 is formed with a film thickness up to a depth in the middle of the thinned region 15a of the collar insulating film 15, and in the upper layer to the edge of the trench 10a, for example, a trench such as silicon oxide. An upper insulating film 18 is formed.

Here, a first storage node electrode is constituted by the first conductive layer 14 and the second conductive layer 17, and the first conductive layer 14 of the first storage node electrode and the first plate electrode 11 are in a first capacitance insulation. A trench-type first memory capacitor Ct is configured to face each other with the film 13 interposed therebetween.
The collar insulating film 15 is an insulating film formed to separate the trench type first memory capacitor Ct from the transistor.

A first interlayer insulating film 24 made of, for example, silicon oxide is formed so as to cover the MOS transistor and the first memory capacitor.
A bit contact hole BC is formed in the first interlayer insulating film 24 so as to penetrate the first interlayer insulating film 24 and reach the high-concentration impurity region of the transistor, and a bit contact plug 25 made of, for example, polysilicon is embedded therein. A bit line 26 is formed in pattern.

A second interlayer insulating film 27 made of, for example, silicon oxide is formed so as to cover the bit line 26. The first interlayer insulating film 24 and the second interlayer insulating film 27 together correspond to the interlayer insulating film of the present invention.
On the surface of the second conductive layer 17 constituting the first memory node electrode and one source / drain region of the transistor, penetrating through the second interlayer insulating film 27 and the first interlayer insulating film 24 and the trench upper insulating film 18. Storage node contact hole NC is opened to reach the surface of a certain low concentration impurity region 21a, and storage node contact plug 28 is connected to both the surface of second conductive layer 17 and the surface of low concentration impurity region 21a. It is embedded and formed. The storage node contact hole NC is made of, for example, polysilicon or tungsten using titanium / titanium oxide as a barrier metal.

A third interlayer insulating film 29 made of, for example, silicon oxide is formed on the second interlayer insulating film 27.
The third interlayer insulating film 29 is exposed to the vicinity of the upper end of the storage node contact plug 28, and is formed with an opening 29a serving as a second storage node electrode type of the stacked second memory capacitor.
A second storage node electrode 30 made of, for example, polysilicon is formed so as to cover the inner wall surface of the opening 29 a and connect to the storage node contact plug 28. The surface of the second storage node electrode 30 is provided with unevenness for increasing the capacitance.

A second capacitor insulating film 31 made of, for example, SiN or SiON is formed on the upper layer of the second storage node electrode 30, and a second plate electrode 32 made of, for example, polysilicon is formed on the upper layer.
As described above, the second storage node electrode 30 and the second plate electrode 32 are opposed to each other with the second capacitor insulating film 31 interposed therebetween, so that a stack type second memory capacitor Cs is formed.

  Further, for example, the first plate electrode 11 and the second plate electrode 32 may be connected in a region not shown.

According to the semiconductor memory device (DRAM) of the present embodiment configured as described above, the first storage node electrode and the second storage node electrode are connected to each other by the storage node contact plug that penetrates the interlayer insulating film and have the same potential. It is connected to one node of the transistor, that is, it has a structure in which a trench type first memory capacitor and a stack type second memory capacitor are connected in parallel, and the total cell capacity is the sum of the respective capacitor capacities. It becomes. When accumulating charges in the capacitor, the first storage node electrode and the second storage node electrode are accumulated so as to have the same potential, and when they are discharged, they are discharged so as to have the same potential.
As a result, the capacitance of the capacitor can be increased as compared with the conventional case, and the data retention characteristics can be improved.

In the interface between the storage node contact plug and the surface of the storage node electrode of the capacitor and the diffusion layer which is the source / drain region of the cell transistor, increasing the contact area is important for reducing the interface resistance.
In the DRAM of this embodiment, the contact area is increased by providing a thinned region at the upper end portion of the color insulating film 15, thereby reducing the interface resistance by one digit compared with the conventional buried strap structure. It can be reduced by ~ 2 digits.
Further, the storage node contact plug is a surface strap type in which both the surface of the storage node electrode and the diffusion layer which is the source / drain region of the cell transistor are connected, and the ON current can be increased by reducing the interface resistance. .
Further, since the BS diffusion layer as shown in FIG. 10 is not formed, the punch-through characteristics of the transistor are improved particularly when miniaturization is advanced.

Next, a manufacturing method of the DRAM of this embodiment will be described with reference to cross-sectional views showing manufacturing steps of the manufacturing method of FIGS.
First, as shown in FIG. 3A, a trench 10a having a depth of about 5 to 6 μm is formed in a pattern on a silicon semiconductor substrate 10.
Next, as shown in FIG. 3B, a silicon oxide film 10b doped with an n-type conductive impurity such as As, for example, is deposited by, eg, CVD (Chemical Vapor Deposition).
Next, a resist film (not shown) for protecting the inside of the trench is patterned by a photolithography process, and the obtained resist film is removed from the upper surface to a predetermined depth of the trench 10a by etching or the like. Next, the silicon oxide film 10b excluding the portion protected by the resist film is removed, and the resist film is further removed. Next, annealing treatment is performed to diffuse n-type conductive impurities such as As from the silicon oxide film 10b into the semiconductor substrate 10 to form the first plate electrode 11 which is an n-type conductive impurity diffusion region. In the semiconductor substrate, a portion corresponding to an upper layer than the first plate electrode 11 becomes a p-type semiconductor region 12 serving as an active region in which a transistor or the like is formed.

Next, as shown in FIG. 4A, after removing the silicon oxide film 10b, SiN or SiON or the like is deposited so as to cover the inner wall surface of the trench 10a by, for example, the CVD method. Form.
Next, polysilicon is deposited by filling the inside of the trench 10a by, for example, the CVD method, and the first conductive layer 14 is formed.
Thereafter, the first conductive layer 14 is removed from the upper surface to the depth of the upper end of the first plate electrode 11 by etching or the like. Next, the portion of the first capacitor insulating film 13 that protrudes from the first conductive layer 14 is removed.
As a result, a trench-type first memory capacitor Ct is formed in which the first conductive layer 14 and the first plate electrode 11 are opposed to each other via the first capacitor insulating film.

Next, as shown in FIG. 4B, for example, by CVD using TEOS (tetraethylorthosilicate) as a raw material, the inner wall surface of the trench 10a and the upper surface of the first conductive layer 14 are covered to form a silicon oxide film with a thickness of 30 nm. The color insulating film 15 is formed by removing the silicon oxide corresponding to the outside of the trench 10a and the upper portion of the first conductive layer 14 by anisotropic etching or the like.
Next, a resist film 16 that protects the inside of the trench is patterned by a photolithography process, and the obtained resist film is removed from the upper surface to a predetermined depth near the upper end of the trench 10a by etching or the like. Next, the color insulating film 15 is thinned by wet etching except for the portion protected by the resist film. Whereas the thickness of the non-thinned portion is 30 nm, for example, the thickness of the thinned region 15a is about 10 nm.

Next, as shown in FIG. 5A, the resist film 16 is removed, and the second conductive layer 17 is formed by depositing polysilicon by filling the inside of the trench 10a by, for example, the CVD method.
Thereafter, the second conductive layer 17 is removed from the upper surface to a depth in the middle of the thinned region 15a of the color insulating film 15 by etching or the like.

Next, as shown in FIG. 5B, an element isolation insulating film is formed in a region not shown. At this time, a trench upper insulating film 18 made of, for example, silicon oxide is formed up to the edge of the trench 10 a in the upper layer of the second conductive layer 17.
Next, for example, a gate insulating film 19 is formed by a thermal oxidation method, a gate electrode 20 is formed by a CVD method, the gate electrode 20 and the gate insulating film 19 are patterned, and an impurity ion implantation process using the gate electrode as a mask. Thus, low concentration impurity regions (21a, 21b) are formed in the semiconductor region 12 of the semiconductor substrate on both sides of the gate electrode 20.
Next, sidewall insulating films 22 are formed on both sides of the gate electrode 20, and a high concentration impurity region 23 connected to the low concentration impurity region 21b is formed by an impurity ion implantation process using the sidewall insulating film 22 as a mask. To do. At this time, the region between the gate electrode 20 and the trench portion is protected with a resist film or the like so that the high concentration impurity region is not formed, and the source / drain region on the trench side is made only of the low concentration impurity region 21a. This is to improve the data retention characteristic by lowering the electric field strength with respect to the source / drain region on the trench side.

Next, as shown in FIG. 6A, silicon oxide is deposited on the entire surface by, eg, CVD, and a first interlayer insulating film 24 is formed.
Next, a bit contact hole BC reaching the high-concentration impurity region 23 constituting the source / drain region of the transistor is patterned, and a conductor such as polysilicon is buried by, for example, a CVD method to form the bit contact plug 25.
Next, polysilicon or the like is deposited on the entire surface by, for example, a CVD method, and patterned so as to be connected to the bit contact plug 25 to form the bit line 26.

Next, as shown in FIG. 6B, the second interlayer insulating film 27 is formed by covering the bit line 26 by, for example, a CVD method and depositing silicon oxide on the entire surface.
Next, the storage node contact hole NC reaching the surface of the second conductive layer 17 constituting the first storage node electrode and the surface of the low concentration impurity region 21a which is the source / drain region on the trench side of the transistor is opened.
Next, the storage node contact hole NC is filled with a conductor such as polysilicon by CVD or the like, or a barrier metal of titanium / titanium oxide is formed by sputtering and then buried with a conductor such as tungsten. Storage node contact plug 28 is formed so as to be connected to the surface of second conductive layer 17 and the surface of low concentration impurity region 21a.

  Next, as shown in FIG. 7, a third interlayer insulating film 29 is formed on the second interlayer insulating film 27 by depositing silicon oxide, for example, by a CVD method, and the storage node contact plug 28 is formed by a photolithography process. The vicinity of the upper end is exposed to form an opening 29a serving as a second storage node electrode type of the stack type second memory capacitor.

Next, as shown in FIG. 2A, the second storage node electrode 30 connected to the storage node contact plug 28 is deposited by covering the inner wall surface of the opening 29a and depositing polysilicon or the like by CVD, for example. Form.
At this time, surface treatment or the like may be performed to provide unevenness for increasing the capacitance on the surface of the second storage node electrode 30.

Next, on the upper layer of the second storage node electrode 30, SiN or SiON or the like is deposited by, for example, the CVD method to form the second capacitor insulating film 31, and further, for example, polysilicon is deposited on the upper layer to form the second plate electrode. 32, and the second storage node electrode 30 and the second plate electrode 32 are opposed to each other with the second capacitor insulating film 31 therebetween, thereby forming a stack type second memory capacitor Cs.
As described above, the DRAM having the structure shown in FIGS. 2A and 2B can be manufactured.

  Further, for example, a plug or the like can be formed so that the first plate electrode 11 and the second plate electrode 32 are connected in a region not shown.

  According to the method of manufacturing a semiconductor memory device (DRAM) according to the above-described embodiment, it is possible to manufacture a structure in which a trench-type first memory capacitor and a stack-type second memory capacitor are connected in parallel. By the simple method as described above, the total cell capacity is the sum of the respective capacitor capacities, so that it is possible to manufacture a semiconductor memory device capable of increasing the capacitor capacity and improving the data retention characteristics.

In the DRAM manufacturing method of the present embodiment, the contact area between the storage node contact plug and the surface of the storage node electrode of the capacitor can be increased by providing a thinned region at the upper end portion of the collar insulating film 15. Thus, the interface resistance can be lowered by one or two digits compared to the conventional buried strap structure.
Further, as the surface strap type in which the storage node contact plug is connected to both the surface of the storage node electrode and the diffusion layer which is the source / drain region of the cell transistor, the ON current can be increased by reducing the interface resistance.

Second Embodiment FIG. 8A is a schematic sectional view showing a structure of a semiconductor memory device (DRAM) according to this embodiment, and FIG. 8B is an enlarged sectional view of a main part.
In the DRAM according to the present embodiment, in the trench, the collar insulating film 15 is formed in a range from the upper end of the first capacitor insulating film 13 to the vicinity of the edge of the trench 10a, and from the upper end of the collar insulating film 15 to the trench 10a. A thin BS (Buried-Strap) insulating film 15b having a thickness of, for example, about 1 nm is formed to cover the inner wall surface of the trench 10a up to the edge of the second conductive layer 17. A third conductive layer 17a made of polysilicon containing a conductive impurity such as P or As is formed.
A BS diffusion layer 17b is formed in the semiconductor region 12 so as to be connected to the impurity region 21a so as to face the third conductive layer 17a with the BS insulating film 15b interposed therebetween.
Except for the above points, the semiconductor memory device (DRAM) according to the first embodiment is substantially the same.

In the above structure, the BS diffusion layer 17b is formed by the conductive impurities such as P and As contained in the third conductive layer 17a with the trench 10a of the silicon substrate by the heat treatment process of well formation, element isolation formation and transistor formation process. It is formed by diffusing into the semiconductor region 12 through a thin BS insulating film 15b formed at the interface portion of the third conductive layer 17a.
The above contact structure is called a buried strap (BS). In the buried portion through the BS diffusion layer 17b and the thin BS insulating film 15b, the low-concentration impurity region 21a which is the source / drain region of the memory cell transistor and the trench type are formed. Electrical connection with the third conductive layer 17a constituting the storage node electrode of the first memory capacitor Ct is realized.
Further, in the DRAM of this embodiment, the storage node contact plug is a surface strap type in which it is connected to both the surface of the storage node electrode and the diffusion layer which is the source / drain region of the cell transistor. With this structure, the interface resistance can be reduced and the ON current can be increased.

  Further, similarly to the first embodiment, according to the semiconductor memory device (DRAM) of the present embodiment, the trench type first memory capacitor and the stack type second memory capacitor are connected in parallel. The total cell capacity is the sum of the respective capacitor capacities, and it is possible to increase the capacitor capacity as compared with the conventional case and improve the data retention characteristics.

Third Embodiment FIG. 9A is a schematic cross-sectional view showing the structure of a semiconductor memory device (DRAM) according to this embodiment, and FIG. 9B is an enlarged cross-sectional view of a main part.
In the DRAM according to the present embodiment, the storage node contact plug is connected only to the surface of the storage node electrode, and is not a surface strap type, but a memory cell in a buried portion via the BS diffusion layer 17b and the thin BS insulating film 15b. Electrical connection is realized between the low-concentration impurity region 21a, which is the source / drain region of the transistor, and the third conductive layer 17a constituting the first storage node electrode of the trench type first memory capacitor Ct.
Except for the above points, the semiconductor memory device (DRAM) according to the second embodiment is substantially the same.

  Similar to the first and second embodiments, the semiconductor memory device (DRAM) of this embodiment has a structure in which a trench type first memory capacitor and a stack type second memory capacitor are connected in parallel. The total cell capacity is the sum of the respective capacitor capacities, and it is possible to increase the capacitor capacity as compared with the conventional case and improve the data retention characteristics.

The present invention is not limited to the above description.
For example, a DRAM in which a memory cell has one transistor has been described. However, the present invention can also be applied to a memory cell having a plurality of transistors.
Further, the structure of the trench-type first memory capacitor and the stack-type second memory capacitor is not limited to that shown in the above embodiment. For example, in the trench type, the arrangement structure of the plate electrodes can be changed. In addition, a stack type structure such as a fin type or a single or double cylindrical type can be adopted.
In addition, various modifications can be made without departing from the scope of the present invention.

  The semiconductor memory device of the present invention can be applied to a DRAM whose capacity has been increased and miniaturized.

  The method for manufacturing a semiconductor memory device of the present invention can be applied to manufacturing a DRAM whose capacity has been increased and miniaturized.

FIG. 1 is an equivalent circuit diagram of the semiconductor memory device (DRAM) according to the first embodiment of the present invention. FIG. 2A is a schematic cross-sectional view showing the structure of the semiconductor memory device (DRAM) according to the first embodiment of the present invention, and FIG. FIGS. 3A and 3B are cross-sectional views showing the manufacturing process of the method of manufacturing the semiconductor memory device (DRAM) according to the first embodiment of the present invention. 4A and 4B are cross-sectional views showing the manufacturing process of the method of manufacturing the semiconductor memory device (DRAM) according to the first embodiment of the present invention. 5A and 5B are cross-sectional views showing the manufacturing process of the method of manufacturing the semiconductor memory device (DRAM) according to the first embodiment of the present invention. 6A and 6B are cross-sectional views showing the manufacturing process of the method of manufacturing the semiconductor memory device (DRAM) according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view showing a manufacturing process of the method of manufacturing the semiconductor memory device (DRAM) according to the first embodiment of the present invention. FIG. 8A is a schematic cross-sectional view showing the structure of a semiconductor memory device (DRAM) according to the second embodiment of the present invention, and FIG. FIG. 9A is a schematic cross-sectional view showing a structure of a semiconductor memory device (DRAM) according to the third embodiment of the present invention, and FIG. 9B is an enlarged cross-sectional view of a main part. FIG. 10 is a cross-sectional view of a main part of a DRAM having a trench type memory capacitor according to a conventional example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 10a ... Trench, 10b ... Silicon oxide film, 11 ... 1st plate electrode, 12 ... Semiconductor region, 13 ... 1st capacity | capacitance insulating film, 14 ... 1st conductive layer (1st memory node electrode), 15 ... Color insulating film, 15a ... Thinned region, 15b ... BS insulating film, 16 ... Resist film, 17 ... Second conductive layer (first storage node electrode), 17a ... Third conductive layer (first storage node electrode) , 17b ... BS diffusion layer, 18 ... trench upper insulating film, 19 ... gate insulating film, 20 ... gate electrode, 21a, 21b ... low concentration impurity region, 22 ... sidewall insulating film, 23 ... high concentration impurity region, 24 ... first interlayer insulating film (interlayer insulating film), 25 ... bit contact plug, 26 ... bit line, 27 ... second interlayer insulating film (interlayer insulating film), 28 ... storage node contact plug, 29 ... third interlayer Edge film 30 ... second storage node electrode 31 ... second capacitor insulating film 32 ... second plate electrode BC ... bit contact hole BL1, BL2 bit line Ct ... first memory capacitor Cs second Memory capacitor, NC ... Storage node contact hole, Tr ... Transistor, WL1, WL2 ... Word line

Claims (10)

A semiconductor substrate;
A transistor formed on the semiconductor substrate;
A first memory capacitor formed in a trench formed in the semiconductor substrate and having a first storage node electrode connected to one node of the transistor;
An interlayer insulating film formed to cover the transistor;
A second memory capacitor formed on the interlayer insulating film and having a second storage node electrode connected to the one node;
A storage node contact plug formed through the interlayer insulating film and connecting the first storage node electrode and the second storage node electrode;
A semiconductor memory device in which a plurality of memory cells having the first memory capacitor, the second memory capacitor, and the transistor are arranged. The transistor is
A gate electrode formed on the semiconductor substrate via a gate insulating film;
A source / drain region formed in the semiconductor substrate on both sides of the gate electrode;
2. The semiconductor memory device according to claim 1, wherein the storage node contact plug is formed to be connected to the surface of one of the source / drain regions and the surface of the first storage node electrode. The first memory capacitor includes:
A first capacitance insulating film formed to cover at least a part of the inner wall surface of the trench;
The first storage node electrode embedded in the trench via the first capacitive insulating film;
The semiconductor memory device according to claim 1, further comprising: a first plate electrode formed in the semiconductor substrate so as to face the first storage node electrode with the first capacitor insulating film interposed therebetween. The second memory capacitor is
The second storage node electrode formed on the interlayer insulating film;
A second capacitor insulating film formed on the second storage node electrode;
The semiconductor memory device according to claim 1, further comprising: a second plate electrode formed on the second capacitor insulating film. The first memory capacitor includes:
A first capacitance insulating film formed to cover at least a part of the inner wall surface of the trench;
The first storage node electrode embedded in the trench via the first capacitive insulating film;
A first plate electrode formed in the semiconductor substrate so as to face the first storage node electrode through the first capacitor insulating film,
The semiconductor memory device according to claim 4, wherein the first plate electrode and the second plate electrode are electrically connected. Forming a trench in a semiconductor substrate;
Forming a first memory capacitor having a first storage node electrode in the trench;
Forming a transistor on the semiconductor substrate at a predetermined distance from the trench;
Forming an interlayer insulating film covering the transistor and the first memory capacitor;
Opening a storage node contact hole reaching at least the surface of the first storage node electrode in the interlayer insulating film;
Forming a storage node contact plug connected to the first storage node electrode in the storage node contact hole;
Forming a second memory capacitor having a second storage node electrode connected to the storage node contact plug on the interlayer insulating film;
In the step of forming the first memory capacitor, the step of forming the transistor, the step of opening the storage node contact hole and / or the step of forming the storage node contact plug, the first storage node electrode and the second A method of manufacturing a semiconductor memory device, wherein a storage node electrode is formed to be connected to one node of the transistor. The step of forming the transistor comprises:
Forming a gate electrode on the semiconductor substrate via a gate insulating film;
Forming source / drain regions in the semiconductor substrate on both sides of the gate electrode,
In the step of opening the storage node contact hole, the storage node contact hole reaching the surface of the first storage node electrode and one of the source / drain regions is opened,
7. The storage node contact plug is formed so as to be connected to the surface of any one of the source / drain regions and the surface of the first storage node electrode in the step of forming the storage node contact plug. Manufacturing method of semiconductor memory device. Forming the first memory capacitor comprises:
Forming a first plate electrode in the semiconductor substrate in a region including a predetermined thickness from an inner wall surface of the trench;
Forming a first capacitor insulating film by covering an inner wall surface of the trench in which the first plate electrode is formed;
The method of manufacturing a semiconductor memory device according to claim 6, further comprising: filling the trench with a conductor via the first capacitor insulating film to form the first memory node electrode. Forming the second memory capacitor comprises:
Forming the second storage node electrode on the interlayer insulating film so as to connect to the storage node contact plug;
Forming a second capacitor insulating film on the second storage node electrode;
The method of manufacturing a semiconductor memory device according to claim 6, further comprising: forming a second plate electrode on the second capacitor insulating film. Forming the first memory capacitor comprises:
Forming a first plate electrode in the semiconductor substrate in a region including a predetermined thickness from an inner wall surface of the trench;
Forming a first capacitor insulating film by covering an inner wall surface of the trench in which the first plate electrode is formed;
Forming the first storage node electrode by filling the trench with a conductor via the first capacitor insulating film,
The method of manufacturing a semiconductor memory device according to claim 9, further comprising forming a conductive layer that electrically connects the first plate electrode and the second plate electrode.

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