JP2006058285A - Apparatus for detecting abnormal voltage for battery pack - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus for detecting abnormal voltage, having user-friendly abnormal voltage detecting function for a battery pack, in comparison with those of conventional technology. <P>SOLUTION: The apparatus for detecting abnormal voltage for the battery pack is provided and detects the voltage abnormality of the group battery provided with a plurality of battery blocks, comprising at least one secondary battery and connected in series. It determines whether the state is an abnormal voltage is detected, by comparing a voltage of each battery block or a battery measurement voltage as a voltage dropped from the voltage of each battery block with a predetermined reference voltage. An abnormality detecting signal is generated and includes information on a detection result. The temporal ratio of the time in the abnormal voltage state of the battery pack to a predetermined time period is calculated, based on a plurality of the abnormality detection signals. The voltage abnormality of the group battery is detected, based on the temporal ratio. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an abnormal voltage detection device for an assembled battery, and more particularly to an abnormal voltage detection device for detecting an abnormal voltage of the assembled battery.

  For electric vehicles such as electric vehicles (PEV) and hybrid electric vehicles (HEV), as a power source for motors and drive sources for various loads, it has basic characteristics such as energy density, output density, cycle life, etc. In recent years, excellent sealed nickel-metal hydride batteries (hereinafter referred to as “nickel-hydrogen batteries”) have attracted attention and are being developed for practical use. When this battery is used as a power source for an electric vehicle, a total voltage of about 100 V to 350 V is required to obtain a predetermined drive output. In the nickel-hydrogen battery, the output voltage of a single battery (that is, one cell), which is the minimum unit constituting the battery, is about 1.2 V. Therefore, the battery composed of one nickel-hydrogen battery or a battery composed of a plurality of cells. A required total voltage is obtained by an assembled battery in which a plurality of blocks are connected in series.

  The temperature of the cells constituting the assembled battery is not uniform, and a temperature difference between the cells tends to occur particularly in a use environment such as an automobile. In addition, the remaining capacity and the charging efficiency (ratio of the amount of electricity stored with respect to the amount of supplied electricity) vary from cell to cell depending on the manufacturing process and the subsequent usage state. Therefore, the actual remaining capacity (SOC: State of Charge) of the cells constituting the assembled battery varies, and the range of capacity that can be used as the assembled battery is narrowed. That is, the lifetime of the assembled battery is apparently reduced. In an assembled battery, it is important to detect the voltage for each cell or battery block constituting the assembled battery, detect whether there is an abnormality in the voltage, and perform charge / discharge control.

JP2003-303626A. Japanese Patent Laid-Open No. 9-159701.

  Patent Document 1 discloses a conventional battery pack abnormality detection device. An abnormality detection device of a conventional example is provided with an abnormality detection circuit for detecting whether or not there is an abnormality (overcharge or overdischarge) in the voltage between terminals for each battery block constituting an assembled battery, and at least one abnormality detection circuit When an abnormality is detected, an abnormality detection signal is transmitted to the charge / discharge control side. However, according to the conventional abnormality detection device, when the abnormality detection circuit fails, for example, when the abnormality cannot be detected even when the battery block is overvoltage, the user does not notice that the abnormality detection circuit has failed. The assembled battery is continuously used as it is, and as a result, the battery block may be overcharged.

  Patent Document 2 discloses a conventional battery pack overvoltage detection device. The overvoltage detection device of the conventional example can detect overvoltage for each cell or battery block constituting the assembled battery, and can determine whether the overvoltage detection function is normal or abnormal.

  However, the conventional abnormality detection device and overvoltage detection device have a single voltage threshold value for detecting an abnormality of the battery block, that is, a boundary value indicating whether or not there is an abnormality. Therefore, for example, even when the battery block constituting the assembled battery approaches the threshold value of voltage, and overdischarge or overcharge is approaching, an abnormality detection signal is not output to the outside, and the voltage of the battery block exceeds the threshold value Or at the moment when it falls below, it suddenly indicated that the battery was abnormal.

  In the conventional abnormality detection device and overvoltage detection device, when the voltage of the battery block fluctuates with time, the detection accuracy of the voltage abnormality of the assembled battery is poor, and the voltage abnormality of the assembled battery cannot be reliably detected.

  The object of the present invention is to solve the above problems and to provide an abnormal voltage detection device for an assembled battery configured by connecting a plurality of battery blocks in series, which is reliable and has higher detection accuracy than the prior art. It is an object of the present invention to provide an abnormal voltage detection device capable of detecting an abnormal voltage of a battery pack.

  It is another object of the present invention to provide an abnormal voltage detection device capable of inspecting whether or not the abnormal voltage detection function is operating normally.

  An abnormal voltage detection apparatus for an assembled battery according to the present invention is an abnormality detection apparatus for detecting an abnormal voltage of an assembled battery configured by connecting a plurality of battery blocks including at least one secondary battery in series. The battery measurement voltage, which is the voltage of each battery block or the voltage dropped from the voltage of each battery block, is compared with a predetermined reference voltage to detect whether the voltage is abnormal, and the detection result Each of the abnormality detection signals including the information of the above is generated, and based on the plurality of abnormality detection signals, a time ratio of the time when the assembled battery is in a voltage abnormal state with respect to a predetermined time period is calculated, and the temporal It has a detecting means for detecting a voltage abnormality of the assembled battery based on the ratio.

  In the abnormal voltage detection apparatus, the detection means compares each battery measurement voltage, which is a voltage of each battery block or a voltage dropped from the voltage of each battery block, with a plurality of reference voltages.

  In the abnormal voltage detection apparatus, the detection means divides the voltage of each battery block by a constant voltage source to generate each battery measurement voltage.

  In the abnormal voltage detection apparatus, the detection unit compares each battery measurement voltage, which is a plurality of voltages dropped from the voltage of each battery block, with the reference voltage.

  In the abnormal voltage detection device, the voltage abnormal state is a state in which the battery measurement voltage of at least one of the battery blocks is higher than the reference voltage, and the detection means uses each battery measurement voltage as a first reference. When a voltage abnormality of the assembled battery is detected in comparison with a voltage, the voltage abnormality of the assembled battery is detected in comparison with a second reference voltage higher than the first reference voltage.

  In the abnormal voltage detection device, the detection means compares the battery measurement voltages with the second reference voltage and detects a voltage abnormality of the assembled battery, and detects a voltage abnormality higher than the second reference voltage. The voltage abnormality of the said assembled battery is detected compared with 3 reference voltages.

  In the abnormal voltage detection device, the voltage abnormal state is a state in which the battery measurement voltage of at least one of the battery blocks is lower than the reference voltage, and the detection means detects the battery measurement voltage as a first voltage. When a voltage abnormality of the assembled battery is detected in comparison with a reference voltage, the voltage abnormality of the assembled battery is detected in comparison with a second reference voltage lower than the first reference voltage.

  In the abnormal voltage detection device, the detection means compares the battery measurement voltages with the second reference voltage to detect voltage abnormality of the assembled battery, and detects a voltage abnormality lower than the second reference voltage. The voltage abnormality of the said assembled battery is detected compared with 3 reference voltages.

  In the abnormal voltage detection device, the detection means relatively changes one of the battery measurement voltages and the reference voltage of the battery blocks, and compares the battery measurement voltages with the reference voltage. Thus, each of the abnormality detection signals is generated, and based on the plurality of abnormality detection signals, it is detected whether or not the detection means functions normally.

  In the abnormal voltage detection device, the detection means controls a voltage change circuit that relatively changes one of the battery measurement voltages and the reference voltage of the battery blocks, and controls the operation of the voltage change circuit. A signal generator for generating a serial signal including a control signal for controlling the serial signal, a serial / parallel converter for converting the serial signal into a parallel signal, and a voltage level of at least one of the parallel signals. And a level conversion circuit that converts the voltage level between the terminals of the transistors into a conversion voltage level that is a voltage level of each battery block and outputs the converted voltage level to the voltage change circuit as the control signal. And

  In the abnormal voltage detection device, the voltage level of the parallel signal includes a negative terminal voltage of the assembled battery, and the level conversion circuit uses the voltage level of the parallel signal as the unit voltage of the terminal of the battery block. The unit voltage is stepped up step by step and converted into the converted voltage levels.

  In the abnormal voltage detection device, the voltage level of the parallel signal includes a voltage level of a negative terminal of the assembled battery, and the level conversion circuit includes the parallel signal related to a first battery block of the plurality of battery blocks. A first booster circuit that boosts the voltage level of the battery block by the unit voltage using the inter-terminal voltage of the battery block as a unit voltage, and converts the voltage level to the converted voltage level; and a second battery of the plurality of battery blocks And a second booster circuit that boosts the voltage level of the parallel signal related to the block by the plurality of unit voltages and converts the boosted voltage level to the converted voltage level.

  In the abnormal voltage detection device, the level conversion circuit boosts the voltage level of the parallel signal related to a third battery block of the plurality of battery blocks by the unit voltage, and then boosts the voltage by the plurality of unit voltages. And a third booster circuit for converting to the converted voltage level.

  In the abnormal voltage detection device, the serial signal includes a start bit at the head, and the serial / parallel converter automatically starts an internal oscillator based on the start bit and generates a predetermined clock output from the internal oscillator. And reading the serial signal from the signal generator.

  In the abnormal voltage detection device, the detection means includes a first transmission element that transmits the plurality of abnormality detection signals in an electrically insulated state, and the serial signal in an electrically insulated state. A second transmission element for transmitting to the / parallel converter is further provided.

  Therefore, according to the abnormal voltage detection device for an assembled battery according to the present invention, an abnormality detection signal including information on whether each battery block is normal or not is generated, and based on the plurality of abnormality detection signals, a predetermined amount is detected. The time ratio of the time when the assembled battery is in a voltage abnormal state with respect to the time period is calculated, and the voltage abnormality of the assembled battery is detected based on the time ratio. An abnormal battery voltage can be detected with high detection accuracy. Furthermore, according to the abnormal voltage detection device for an assembled battery according to the present invention, either one of the battery measurement voltage and the reference voltage of each battery block is relatively changed, and each battery measurement voltage is changed to the reference voltage. By comparing, the abnormality detection signals are respectively generated, and based on the plurality of abnormality detection signals, it can be detected whether or not the abnormal voltage detection function functions normally.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

Embodiment 1. FIG.
With reference to FIGS. 1-10, the abnormal voltage detection apparatus 100 for the assembled batteries which concerns on Embodiment 1 of this invention is demonstrated. FIG. 1 is a block diagram showing a schematic configuration of an abnormal voltage detection apparatus 100 for an assembled battery according to Embodiment 1 of the present invention. In FIG. 1, 100 is an abnormal voltage detector, 10 is an assembled battery, 11 is a relay, 12 is an inverter, and 13 is a motor generator. Abnormal voltage detection device 100, battery pack 10, relay 11, inverter 12, and motor generator 13 are all mounted on an electric vehicle. The DC power of the assembled battery 10 is converted into AC power by the inverter 12, drives the motor generator 13, and runs the electric vehicle. The relay 11 interrupts the electrical connection between the assembled battery 10 and the inverter 12.

  The assembled battery 10 includes N battery blocks B1 to BN connected in series (N is a positive integer of 2 or more). In FIG. 1, N = 20. Each battery block B1 to BN is further configured by a series connection circuit of a plurality of secondary battery cells b1 to bM (M is a positive integer of 2 or more). In FIG. 1, M = 12. With this configuration, the assembled battery 10 is an assembled battery of 240 cells as a whole. In the first embodiment, each of the cells b1 to bM is a nickel-hydrogen battery having a nominal voltage of 1.2V, and 14.4V is obtained from each of the battery blocks B1 to BN, and a total nominal voltage of 288V is obtained from the assembled battery 10. In the present specification, the high potential side of the assembled battery 10 is referred to as the upper level, the low potential side is referred to as the lower level, the lowest battery block is referred to as B1, and the highest battery block is referred to as BN.

  The abnormal voltage detection apparatus 100 includes abnormal voltage detection units 101 to 10N, level conversion circuits 111 and 112, photocouplers P1 to PN, P11 and P12, and a control unit 150 in which input terminals and output terminals are electrically insulated from each other. Have.

  The abnormal voltage detection unit 10N includes a reference voltage generation circuit R1N, a voltage dividing circuit DN, and a comparator CN, and detects a voltage abnormality in the battery block BN. In the first embodiment, the abnormal voltage detection unit 10N detects overcharge of the battery block BN. The voltage dividing circuit DN is a circuit in which resistors Rd1 and Rd2 are connected in series. The voltage dividing circuit DN outputs a battery measurement voltage VbN, which is a voltage obtained by dividing the voltage of the battery block BN, to the inverting input terminal of the comparator CN. In the first embodiment, the voltage dividing circuit DN divides the inter-terminal voltage of the battery block BN by a quarter.

  The reference voltage generation circuit R1N includes reference voltage sources AN1, AN2 and AN3, and a switch S1N. FIG. 2 is a circuit diagram of the reference voltage generation circuit R1N. The reference voltage sources AN1, AN2, and AN3 are respectively configured by Zener diodes and resistors (ZD1 and re1, ZD2 and re2, and ZD3 and re3) having different Zener voltages. In the first embodiment, the reference voltage source AN1 generates a first reference voltage Vr1 for detecting that the battery block BN has reached a voltage (18V) in a slightly overcharged state. The first reference voltage Vr1 is equal to the battery measurement voltage VbN output by the voltage dividing circuit DN that receives the output voltage 18V of the battery block BN. The reference voltage source AN2 generates a second reference voltage Vr2 for detecting that the battery block BN has reached a voltage (20V) in a state where the battery block BN is considerably overcharged. The second reference voltage Vr2 is equal to the battery measurement voltage VbN output from the voltage dividing circuit DN that receives the output voltage 20V of the battery block BN. The reference voltage source AN3 generates a third reference voltage Vr3 for detecting that the battery block BN has become an overcharge voltage (22V) that causes a failure that cannot be recovered. The third reference voltage Vr3 is equal to the battery measurement voltage VbN output from the voltage dividing circuit DN that receives the output voltage 22V of the battery block BN. In the first embodiment, Vr1 <Vr2 <Vr3.

  The switch S1N is switched to one of the contacts a, b, and c by a 2-bit control signal from the control unit 150, and selectively selects the reference voltage output from the reference voltage source AN1, AN2, or AN3 as a non-inversion of the comparator CN. Input to the input terminal. The comparator CN is composed of a differential circuit and is driven by the voltage of the battery block BN. The output voltage VbN of the voltage dividing circuit DN is given to the inverting input terminal of the comparator CN. The comparator CN compares the battery measurement voltage VbN of the battery block BN with the three reference voltages Vr1, Vr2, and Vr3, generates an abnormality detection signal dN including information on the comparison results, and outputs the abnormality detection signal dN to the photocoupler PN. The anode of the input light emitting diode of the photocoupler PN is connected to the positive terminal of the battery block BN, and the cathode is connected to the output terminal of the comparator CN.

  Abnormal voltage detectors 101 to 10 (N-1) have the same configuration as abnormal voltage detector 10N. The reference voltage sources A11 to AN1 generate a first reference voltage Vr1 that is equal to the output voltages Vb1 to VbN of the voltage dividing circuits D1 to DN to which the voltages (18V) of the corresponding battery blocks B1 to BN are input, respectively. The reference voltage sources A12 to AN2 generate a second reference voltage Vr2 that is equal to the output voltages Vb1 to VbN of the voltage dividing circuits D1 to DN to which the voltages (20 V) of the corresponding battery blocks B1 to BN are input, respectively. The reference voltage sources A13 to AN3 generate a third reference voltage Vr3 that is equal to the output voltages Vb1 to VbN of the voltage dividing circuits D1 to DN to which the voltages (22V) of the corresponding battery blocks B1 to BN are input, respectively. The voltage dividing circuits D1 to DN all have the same voltage dividing ratio. The comparators C1 to CN, the reference voltage sources A11 to AN1, A12 to AN2, A13 to AN3, and the switches S11 to S1N are driven by the voltages of the corresponding battery blocks B1 to BN, respectively.

  The switches S11 to S1N are simultaneously switched by a 2-bit control signal from the control unit 150. The first reference voltage Vr1, the second reference voltage Vr2, or the third reference voltage Vr3 is given to the non-inverting input terminals of all the comparators C1 to CN at the same timing. The comparators C1 to CN respectively detect the low level abnormality detection signals d1 to dN when the output voltages Vb1 to VbN of the voltage dividing circuits D1 to DN exceed the voltage generated by the reference voltage source selected by the switches S11 to S1N. Are generated and output to the photocoupler PN, and vice versa, high-level abnormality detection signals d1 to dN are respectively generated and output to the photocoupler PN.

  The abnormality detection signals d1 to dN (outputs of the comparators C1 to CN) output from the abnormal voltage detection units 101 to 10N are input to the input light emitting diodes of the photocouplers P1 to PN, respectively. The photocouplers P1 to PN transmit the abnormality detection signals d1 to dN in an electrically insulated state. In the first embodiment, the output phototransistors of the photocouplers P1 to PN constitute a wired OR circuit and are connected to the control unit 150. Each abnormality detection signal d1 to dN is ORed. When the battery measurement voltages Vb1 to VbN of at least one battery block exceed the voltage generated by the reference voltage source selected by the switches S11 to S1N, the output phototransistors of at least one photocoupler P1 to PN are turned on.

  The control unit 150 includes a switch control unit 151, a display unit 152, and a relay drive unit 153. The control unit 150 inputs a logical sum signal ds that is a logical sum of the abnormality detection signals d1 to dN related to the battery blocks B1 to BN. The logical sum signal ds is normally a high level signal that is at a low level when the voltage of at least one battery block is higher than the voltage generated by the reference voltage source selected by the switches S11 to S1N. is there. The switch control unit 151 transmits control signals RC1 and RC2 to the switches S11 to S1N via the photocouplers P11 and P12 and the level conversion circuits 111 and 112. The control signals RC1 and RC2 correspond to the respective bits of the 2-bit signal for switching the switches S11 to S1N. The display unit 152 displays the state of the assembled battery 10. The display unit 152 is, for example, an LED. The relay driving unit 153 drives the relay 11 to open and close.

  A hardware configuration (not shown) of the control unit 150 will be described. The control unit 150 includes a microcomputer having a CPU (Central Processing Unit), a memory, and an I / O port, and a peripheral circuit. The controller 150 is driven by a low-voltage power source (not shown) (for example, a lead storage battery having a nominal voltage of 12V).

  The switch control unit 151 outputs control signals RC1 and RC2 to the photocoupler P11 and the photocoupler P12, respectively, and drives the input light emitting diodes of the photocouplers P11 and P12. The output phototransistors of the photocouplers P11 and P12 transmit control signals RC1 and RC2 to the level conversion circuits 111 and 112, respectively. The level conversion circuit 111 converts the voltage level of the control signal RC1 into a voltage level corresponding to the power supply voltage of the abnormal voltage detectors 101 to 10N, generates N control signals, and supplies the abnormal voltage detectors 101 to 10N to the abnormal voltage detectors 101 to 10N, respectively. Output. The level conversion circuit 112 converts the voltage level of the control signal RC2 into a voltage level corresponding to the power supply voltage of the abnormal voltage detectors 101 to 10N, generates N control signals, and supplies the abnormal voltage detectors 101 to 10N to the abnormal voltage detectors 101 to 10N, respectively. Output. The configuration of the level conversion circuits 111 and 112 is arbitrary.

  The abnormal voltage detection units 101 to 10N receive 2-bit control signals from the level conversion circuits 111 and 112, respectively, and battery measurement voltages Vb1 to VbN obtained by dividing the voltages of the battery blocks B1 to BN by the voltage dividing circuits D1 to DN. Based on the comparison result with the reference voltage selected by the 2-bit control signal, the abnormality detection signals d1 to dN are generated and output to the photocouplers P1 to PN, respectively.

  The control unit 150 inputs the logical sum signal ds of the abnormality detection signals d1 to dN via the I / O port. The logical sum signal ds is A / D converted at a predetermined sampling frequency. The CPU performs an abnormality detection process using A / D converted data based on an abnormality detection program (described later) stored in the memory. And the control signal for controlling the operation | movement of switch S11-S1N and the opening and closing of the relay 11 is output to each switch S11-S1N and the relay 11 via an I / O port. The controller 150 is electrically insulated from the high voltage assembled battery 10 by the photocouplers P1 to PN, P11, and P12. In practice, the control unit 150 often has not only an abnormality detection function of the assembled battery 10 but also a charge / discharge control function and a voltage measurement function of the battery blocks B1 to BN. However, only the abnormality detection function will be described in the first embodiment.

  The abnormality detection method will be described with reference to FIGS. 3 and 4 are flowcharts showing an abnormality detection method performed by the abnormal voltage detection apparatus 100 for an assembled battery according to Embodiment 1 of the present invention. 5, 6 and 7 are timing charts showing the operation of the switches S11 to S1N in steps S1, S4 and S9 of FIG. 3 or FIG. 4, respectively. 3 and 4 is started when the driver turns on an ignition switch (not shown) of the electric vehicle and power is supplied to the control unit 150 from a low voltage power source (not shown). It is always executed, and ends when the ignition switch is turned off.

  In step S1, the switch control unit 151 generates 2-bit control signals RC1 and RC2 for switching the switches S11 to S1N to the contacts a. As shown in FIG. 5, the switches S11 to S1N are respectively switched to the contact point a during the time period T1. The first reference voltage Vr1 is applied to the non-inverting input terminals of the comparators C1 to CN. The control unit 150 inputs the logical sum signal ds of the abnormality detection signals d1 to dN related to the battery blocks B1 to BN and performs A / D conversion. In step S2, the control unit 150 counts the number of signals NS1 when the logical sum signal ds is at a low level in the time period T1, and divides the signal number NS1 by the sampling number NT1 in the time period T1. The time ratio TR1 is calculated. By setting the sampling frequency of the logical sum signal ds to a sufficiently high frequency, the time ratio TR1 is such that the battery measurement voltage of at least one battery block is higher than the first reference voltage Vr1 for the time period T1. It is substantially the same as the proportion of the time period that is in the state. When the sampling frequency of the logical sum signal ds is low, the detection accuracy deteriorates, but the ratio of the time period in which the battery measurement voltage of at least one battery block is in a voltage abnormality state higher than the first reference voltage Vr1 is approximated. The corresponding temporal ratio TR1 can be detected. In step S3, the control unit 150 determines whether or not the assembled battery 10 is in a voltage abnormal state based on whether or not TR1 is equal to or greater than a predetermined value Nth1. If TR1 <Nth1, the process of step S2 is repeated, and if TR1 ≧ Nth1, the process proceeds to step S4. In the first embodiment, preferably, T1 = 1.0 seconds and Nth1 = 0.8.

  In step S4, the switch control unit 151 generates control signals RC1 and RC2 for alternately switching the switches S11 to S1N between the contact point a and the contact point b for a time period T2. As shown in FIG. 6, during the time period T2, the switches S11 to S1N repeat the operation of switching to the contact a for the time period ta and the operation of switching to the contact b for the time period tb. In the time period T2, the first reference voltage Vr1 and the second reference voltage Vr2 are alternately applied to the non-inverting input terminals of the comparators C1 to CN by time periods ta and tb, respectively. In the first embodiment, preferably, T2 = 2.0 seconds and ta = tb = 0.2 seconds. The control unit 150 inputs the logical sum signal ds of the abnormality detection signals d1 to dN of the battery blocks B1 to BN at the reference voltages Vr1 and Vr2, and performs A / D conversion. The controller 150 counts the number of signals NS2a when the logical sum signal ds is at a low level when the switches S11 to S1N are switched to the contact a, and the logic when the switches S11 to S1N are switched to the contact b. The number of signals NS2b when the sum signal ds is at a low level is counted. In step S5, the control unit 150 calculates a time ratio TR2a of voltage abnormality obtained by dividing the signal number NS2a by the sampling number NT2 of the time period T2 / 2, and calculates the signal number NS2b as the sampling number of the time period T2 / 2. The time ratio TR2b of the voltage abnormality formed by dividing by NT2 is calculated.

  By setting the sampling frequency of the logical sum signal ds to a sufficiently high frequency, the time ratio TR2a is a voltage at which the battery measurement voltage of at least one battery block is higher than the first reference voltage Vr1 for the time period T2 / 2. It is substantially the same as the proportion of time periods that are abnormal. When the sampling frequency of the logical sum signal ds is low, the detection accuracy deteriorates, but the ratio of the time period in which the battery measurement voltage of at least one battery block is in a voltage abnormality state higher than the first reference voltage Vr1 is approximated. The corresponding temporal ratio TR2a can be detected. By setting the sampling frequency of the logical sum signal ds to a sufficiently high frequency, the time ratio TR2b is a voltage at which the battery measurement voltage of at least one battery block is higher than the second reference voltage Vr2 for the time period T2 / 2. It is substantially the same as the proportion of time periods that are abnormal. When the sampling frequency of the logical sum signal ds is low, the detection accuracy is deteriorated, but the ratio of the time period in which the battery measurement voltage of at least one battery block is in a voltage abnormality state higher than the second reference voltage Vr2 is approximate. The corresponding temporal ratio TR2b can be detected.

  In step S6, the control unit 150 determines whether TR2a is equal to or greater than a predetermined value Nth2a. If TR2a <Nth2a, the control unit 150 returns to step S1. If TR2a ≧ Nth2a, the control unit 150 proceeds to step S7. In step S7, the control unit 150 determines whether TR2b is equal to or greater than a predetermined value Nth2b. If TR2b <Nth2b, the control unit 150 returns to step S4, and if TR2b ≧ Nth2b, the process proceeds to step S8. In the first embodiment, Nth2a = Nth2b = 0.8 is preferable. In step S6 and step S7, the control unit 150 compares each of the battery measurement voltages Vb1 to VbN with the first reference voltage Vr1 and detects a voltage abnormality of the assembled battery 10, which is higher than the first reference voltage Vr1. A voltage abnormality of the battery pack 10 is detected as compared with the second reference voltage Vr2.

  In step S <b> 8, the control unit 150 controls the inverter 12 to reduce the charging power for the assembled battery 10. Specifically, the control unit 150 suppresses regenerative braking during deceleration and braking in which the motor generator 13 functions as a generator. Alternatively, the inverter 12 is controlled so that the motor generator 13 functions as an electric motor and consumes the electric power of the assembled battery 10. Further, the display unit 152 turns on a yellow lamp, for example, displays that the assembled battery 10 is considerably overcharged, and proceeds to step S9 (FIG. 4).

  In step S9, the switch control unit 151 generates control signals RC1 and RC2 for alternately switching the switches S11 to S1N between the contact b and the contact c. As shown in FIG. 7, during the time period T3, the switches S11 to S1N repeat the operation of switching to the contact b for the time period tb and the operation of switching to the contact c for the time period tc. In the time period T3, the second reference voltage Vr2 and the third reference voltage Vr3 are alternately applied to the non-inverting input terminals of the comparators C1 to CN by time periods tb and tc. In the first embodiment, preferably, T3 = 2.0 seconds and tb = tc = 0.2 seconds. The control unit 150 inputs the logical sum signal ds of the abnormality detection signals d1 to dN of the battery blocks B1 to BN at the reference voltages Vr2 and Vr3, and performs A / D conversion. The controller 150 counts the number of signals NS3b when the logical sum signal ds is low level when the switches S11 to S1N are switched to the contact b, and the logic when the switches S11 to S1N are switched to the contact c. The number of signals NS3c when the sum signal ds is at a low level is counted. In step S10, the control unit 150 calculates a time ratio TR3b of voltage abnormality obtained by dividing the signal number NS3b by the sampling number NT3 of the time period T3 / 2, and calculates the signal number NS3c for the sampling of the time period T3 / 2. A voltage abnormality time ratio TR3c obtained by dividing by the number NT3 is calculated.

  By setting the sampling frequency of the logical sum signal ds to a sufficiently high frequency, the time ratio TR3b is a voltage at which the battery measurement voltage of at least one battery block is higher than the second reference voltage Vr2 for the time period T3 / 2. It is substantially the same as the proportion of time periods that are abnormal. When the sampling frequency of the logical sum signal ds is low, the detection accuracy is deteriorated, but the ratio of the time period in which the battery measurement voltage of at least one battery block is in a voltage abnormality state higher than the second reference voltage Vr2 is approximate. The corresponding temporal ratio TR3b can be detected.

  By setting the sampling frequency of the logical sum signal ds to a sufficiently high frequency, the time ratio TR3c is a voltage at which the battery measurement voltage of at least one battery block is higher than the third reference voltage Vr3 for the time period T3 / 2. It is substantially the same as the proportion of time periods that are abnormal. When the sampling frequency of the logical sum signal ds is low, the detection accuracy is deteriorated, but the ratio of the time period in which the battery measurement voltage of at least one battery block is in a voltage abnormality state higher than the third reference voltage Vr3 is approximated. The corresponding temporal ratio TR3c can be detected. In step S11, the control unit 150 determines whether or not TR3b is equal to or greater than a predetermined value Nth3b. If TR3b <Nth3b, the control unit 150 returns to step S4 (FIG. 3), and if TR3b ≧ Nth3b, proceeds to step S12. In step S12, the control unit 150 determines whether TR3c is equal to or greater than a predetermined value Nth3c. If TR3c <Nth3c, the process returns to step S9, and if TR3c ≧ Nth3c, the process proceeds to step S13. In the first embodiment, Nth3b = Nth3c = 0.8 is preferable. In step S11 and step S12, the control unit 150 compares each of the battery measurement voltages Vb1 to VbN with the second reference voltage Vr2 to detect a voltage abnormality of the assembled battery 10, and is higher than the second reference voltage Vr2. A voltage abnormality of the assembled battery 10 is detected in comparison with the third reference voltage Vr3.

  When a voltage abnormality is detected at the third reference voltage Vr3, one of the battery blocks B1 to BN constituting the assembled battery 10 is in an overcharged state that causes a failure that cannot be recovered. In step S <b> 13, the relay driving unit 153 turns off the relay 11 and stops supplying power from the assembled battery 10 to the motor generator 13. Further, for example, the display unit 152 turns on a red lamp to display that the assembled battery 10 is in an overcharged state.

  The abnormal voltage detection apparatus 100 for the assembled battery according to the first embodiment uses the battery measurement voltages Vb1 to VbN, which are divided by dividing the voltages of the battery blocks B1 to BN by the voltage dividing circuits D1 to DN, respectively, into three criteria. Each of the battery blocks B1 to BN is compared with the voltages Vr1, Vr2, and Vr3 to detect whether or not each of the battery blocks B1 to BN has a voltage abnormality, and abnormal detection signals d1 to dN including information on the detection result are generated. Then, at each reference voltage Vr1, Vr2, Vr3, based on the logical sum signal ds of the abnormality detection signals d1 to dN, a time ratio in which the assembled battery 10 is in a voltage abnormal state with respect to a predetermined time period is calculated. A voltage abnormality of the battery pack 10 is detected based on the time ratio. The abnormal voltage detection device 100 detects a voltage abnormality of the assembled battery 10 at each of the reference voltages Vr1, Vr2, and Vr3, and displays the state of the assembled battery 10 to the user at each voltage. The abnormal voltage detection device 100 can improve the detection accuracy of the voltage abnormality of the assembled battery 10 by changing the reference voltage and detecting the voltage abnormality step by step. The abnormal voltage detection device 100 can automatically set an appropriate reference voltage according to the current state of the assembled battery 10 and can quickly detect a change in the state of the assembled battery 10.

  FIG. 8 is a timing chart showing another operation of the switches S11 to S1N in step S4 of FIG. In step S4, the switches S11 to S1N may be switched to the contact point a for the time period taa and then switched to the contact point b for the time period tba (= T2-taa). For example, taa = tba = 0.6 seconds.

  FIG. 9 is a timing chart showing another operation of the switches S11 to S1N in step S9 of FIG. In step S9, the switches S11 to S1N may be switched to the contact point b for the time period tbb and then switched to the contact point c for the time period tcb (= T3-tbb). For example, tbb = tcb = 0.6 seconds.

  In each of the abnormal voltage detectors 101 to 10N of the first embodiment, the battery measurement voltage obtained by dividing the voltage of each of the battery blocks B1 to BN by the voltage dividing circuits D1 to DN at the inverting input terminals of the comparators C1 to CN. Vb1 to VbN were input respectively. FIG. 10 is a circuit diagram showing a part of an abnormal voltage detection device for an assembled battery according to a modification of the first embodiment of the present invention. As shown in FIG. 10, it is good also as a structure which connects the positive electrode terminal of each battery block B1-BN directly to the inverting input terminal of each comparator C1-CN. In this case, the battery measurement voltages Vb1 to VbN are the positive terminal voltages of the battery blocks B1 to BN, respectively.

  The abnormal voltage detection apparatus 100 according to the first embodiment counts the number of signals when the logical sum signal ds is at a low level for a predetermined time period, and divides the signal number by the number of samplings in the predetermined time period. The time ratio of voltage abnormality was calculated (steps S2, S4, S5, S9, S10 in FIG. 3). And the time ratio was compared with the threshold of time ratio, and it was judged whether the assembled battery 10 was in the state of voltage abnormality. In the first embodiment, the “voltage abnormality state” is a state in which the battery measurement voltages Vb1 to VbN of at least one battery block B1 to BN are higher than the reference voltages Vr1, Vr2 or Vr3 switched by the switches S11 to S1N. . Instead, the number of signals when the logical sum signal ds is at a low level for a predetermined time period is counted, the number of signals is compared with a threshold value of the number of signals, and whether the battery pack is in a voltage abnormal state or not. It may be judged. A time period in which the OR signal ds is at a low level with respect to a predetermined time period may be detected, and the time period may be compared with a threshold value of the time period to determine whether or not the battery pack is in a voltage abnormal state. .

Embodiment 2. FIG.
With reference to FIG. 3 to FIG. 7 and FIG. 11, an abnormal voltage detection device 300 for an assembled battery according to Embodiment 2 of the present invention will be described. FIG. 11 is a block diagram showing a schematic configuration of an abnormal voltage detection device 300 for an assembled battery according to Embodiment 2 of the present invention. In FIG. 11, the same reference numerals are used for portions common to FIG. 1, and description thereof is omitted. In order to generate the first, second and third reference voltages Vr1, Vr2, and Vr3, the reference voltage generation circuits R11 to R1N of the abnormal voltage detection apparatus 100 according to the first embodiment each have three reference voltage sources A11 to A11. A1n, A12 to AN2, and A13 to AN3 were provided. The second embodiment shows another configuration for generating the first, second, and third reference voltages Vr1, Vr2, and Vr3 in each abnormal voltage detection device.

  In FIG. 11, 300 is an abnormal voltage detection device, 10 is an assembled battery, 11 is a relay, 12 is an inverter, and 13 is a motor generator. The abnormal voltage detection device 300, the assembled battery 10, the relay 11, the inverter 12, and the motor generator 13 are all mounted on an electric vehicle. The DC power of the assembled battery 10 is converted into AC power by the inverter 12, drives the motor generator 13, and runs the electric vehicle.

  The abnormal voltage detection apparatus 300 includes abnormal voltage detection units 301 to 30N, level conversion circuits 111 and 112, photocouplers P1 to PN, P11 and P12, and a control unit 150. The abnormal voltage detection device 300 according to the second embodiment is obtained by replacing the abnormal voltage detection units 101 to 10N of the abnormal voltage detection device 100 (FIG. 1) according to the first embodiment with abnormal voltage detection units 301 to 30N.

  The abnormal voltage detection unit 301 includes a reference voltage generation circuit R31, a voltage dividing circuit D1, and a comparator C1, and detects a voltage abnormality in the battery block B1. In the second embodiment, the abnormal voltage detection unit 301 detects overcharge of the battery block B1. The abnormal voltage detection unit 301 is different from the abnormal voltage detection unit 101 according to the first embodiment only in the generation method of the reference voltage supplied to the non-inverting input terminal of the comparator C1. The reference voltage generation circuit R31 includes a reference voltage source A1, a switch S31, and resistors R0, R1, R2, and R3. Similarly to the reference voltage sources A11 to AN1, A12 to AN2, and A13 to AN3, the reference voltage source A1 includes a Zener diode and a resistor (see FIG. 2). One end of the resistor R0 is connected to the output terminal of the reference voltage generator A1, and the other end is connected to the switch S31. One end of each of the resistors R1, R2, and R3 is connected to the negative terminal of the battery block B1, and the other end is connected to the contacts a, b, and c of the switch S31. The voltage generated by the reference voltage source A1 is divided by the resistor R0 and any one of the resistors R1, R2, and R3 selected by the switch S31, and is given to the non-inverting input terminal of the comparator C1. In the second embodiment, the resistance values of the resistors R1, R2, and R3 are set to R1 <R2 <R3.

  In the second embodiment, when the switch S31 is switched to the contact point a, the first voltage which is equal to the output voltage Vb1 of the voltage dividing circuit D1 to which the voltage (18V) when the battery block B1 is slightly overcharged is input. The reference voltage Vr1 is input to the non-inverting input terminal of the comparator C1. When the switch S31 is switched to the contact point b, the second reference voltage Vr2 that is equal to the output voltage Vb1 of the voltage dividing circuit D1 to which the voltage (20V) when the battery block B1 is considerably overcharged is input. The signal is input to the non-inverting input terminal of the comparator C1. When the switch S31 is switched to the contact c, the third reference, which is a voltage equal to the output voltage Vb1 of the voltage dividing circuit D1 to which an overcharge voltage (22V) to the extent that the battery block B1 causes a failure that cannot be recovered, is input. The voltage Vr3 is input to the non-inverting input terminal of the comparator C1.

  Hereinafter, the abnormal voltage detection units 302 to 30N also have the same configuration as the abnormal voltage detection unit 301. The abnormal voltage detectors 302 to 30N divide the voltage generated by the reference voltage sources A2 to AN by one of the resistor R0 and the resistors R1, R2, and R3, and the non-inverting input terminals of the comparators C2 to CN To give. In each of the abnormal voltage detection units 302 to 30N, one of the resistors R1, R2, and R3 is selected by the switches S32 to S3N. The switches S31 to S3N are interlocked. Each of the reference voltage sources A1 to AN is driven by the voltage of the corresponding battery block.

  The switch control unit 151 of the control unit 150 transmits 2-bit control signals RC1 and RC2 to the switches S31 to S3N via the photocouplers P11 and P12 and the level conversion circuits 111 and 112. The control unit 150 detects the voltage abnormality of the assembled battery 10 while switching the first reference voltage Vr1, the second reference voltage Vr2, and the third reference voltage Vr3 in the same manner as the abnormal voltage detection device according to the first embodiment. (See FIGS. 3 to 7).

  The abnormal voltage detection device 300 according to the second embodiment has the same effects as the abnormal voltage detection device 100 according to the first embodiment. Furthermore, each of the abnormal voltage detection units 301 to 30N has only one reference voltage source A1 to AN, and therefore can be realized at a lower cost than the abnormal voltage detection device 100 according to the first embodiment.

Embodiment 3. FIG.
An abnormal voltage detection device 400 for an assembled battery according to Embodiment 3 of the present invention will be described with reference to FIGS. FIG. 12 is a block diagram showing a schematic configuration of an abnormal voltage detection device 400 for an assembled battery according to Embodiment 3 of the present invention. In FIG. 12, the same reference numerals are used for portions common to FIG. 1, and description thereof is omitted. The abnormal voltage detection device 400 adds to the abnormal voltage detection device 100 according to the first embodiment a function for detecting whether or not an abnormality detection process can be normally performed (hereinafter also referred to as an “abnormality detection function inspection function”). It is a thing.

  In FIG. 12, 400 is an abnormal voltage detection device, 10 is an assembled battery, 11 is a relay, 12 is an inverter, and 13 is a motor generator. The abnormal voltage detection device 400, the assembled battery 10, the relay 11, the inverter 12, and the motor generator 13 are all mounted on an electric vehicle. The DC power of the assembled battery 10 is converted into AC power by the inverter 12, drives the motor generator 13, and runs the electric vehicle.

  The abnormal voltage detection apparatus 400 includes abnormal voltage detection units 401 to 40N, level conversion circuits 111, 112, and 113, photocouplers P1 to PN, P11, P12, and P13, and a control unit 450. The abnormal voltage detection device 400 according to the third embodiment includes the abnormal voltage detection units 101 to 10N of the abnormal voltage detection device 100 (FIG. 1) according to the first embodiment as abnormal voltage detection units 401 to 40N, and the control unit 150 as a control unit. The level conversion circuit 113 and the photocoupler P13 in which the input terminal and the output terminal are electrically insulated from each other are added.

  The abnormal voltage detection unit 401 is obtained by adding a voltage drop circuit 41 to the abnormal voltage detection unit 101 of the abnormal voltage detection device 100 according to the first embodiment. The voltage drop circuit 41 includes a resistor r1, a resistor r2, and a switch S41. One end of the series connection circuit of the resistor r2 and the switch S41 is connected to the negative terminal of the battery block B1, and the other end is connected to the non-inverting input terminal of the comparator C1. The resistor r1 is connected between the switch S11 and a common connection point between the series connection circuit of the resistor r2 and the switch S41 and the non-inverting input terminal of the comparator C1. When the switch S41 is open, the abnormal voltage detection unit 401 performs the same operation as the abnormal voltage detection unit 101. When the switch S41 is closed, the reference voltage selected by the switch S11 among the first reference voltage Vr1, the second reference voltage Vr2, and the third reference voltage Vr3 is applied to the non-inverting input terminal of the comparator C1. The voltage is divided by the resistors r1 and r2, and the voltage is stepped down.

  The abnormal voltage detection units 402 to 40N are obtained by adding voltage drop circuits 42 to 4N to the abnormal voltage detection units 102 to 10N of the abnormal voltage detection device 100 according to the first embodiment, respectively. Similarly to the voltage drop circuit 41, each of the voltage drop circuits 42 to 4N includes a resistor r1, a resistor r2, and switches S42 to S4N.

  The control unit 450 is obtained by adding a voltage drop circuit control unit 454 to the control unit 150 of the abnormal voltage detection device 100 according to the first embodiment. The voltage drop circuit control unit 454 transmits a 1-bit voltage drop circuit control signal TC to the switches S41 to S4N via the photocoupler P13 and the level conversion circuit 113. The level conversion circuit 113 converts the voltage level of the control signal TC into a voltage level corresponding to the power supply voltage of the abnormal voltage detectors 401 to 40N, generates N control signals, and outputs them to the voltage drop circuits 41 to 4n, respectively. To do. All the switches S41 to S4N are interlocked.

  When the driver switches an ignition switch (not shown) of the electric vehicle from off to on and a low voltage power source (not shown) starts supplying power to the control unit 450, the controller 450 detects abnormal voltage detectors 401 to 401. Inspect whether 40N functions normally. When the abnormal voltage detectors 401 to 40N are functioning normally, the flowcharts of FIGS. 3 and 4 are executed to perform normal abnormality detection processing. 3 and 4 are flowcharts showing an abnormality detection method performed by the abnormal voltage detection apparatus 400 for an assembled battery according to the third embodiment of the present invention, which has already been described. During normal abnormality detection processing, all the switches S41 to S4N of the voltage drop circuits 41 to 4N are open.

  The abnormal voltage detection apparatus 400 according to the third embodiment causes the reference voltages Vr1, Vr2, and Vr3 to drop relative to the battery measurement voltages Vb1 to VbN by the voltage drop circuits 41 to 4N, and the battery measurement voltages Vb1 to VbN. Is compared with the respective reference voltages Vr1, Vr2, and Vr3, thereby generating abnormality detection signals d1 to dN. The controller 450 detects whether or not the abnormal voltage detection device 400 can normally detect an abnormality based on the logical sum signal ds of the abnormality detection signals d1 to dN.

  A method for detecting whether or not the abnormal voltage detection apparatus 400 can normally detect an abnormality will be described. In addition, the inspection process of the following abnormality detection function is performed in a state where all the battery blocks B1 to BN have not reached overcharge (for example, before charging or before traveling of the electric vehicle). First, in the first inspection process, the switches S41 to S4N of the abnormal voltage detectors 401 to 40N are opened, and the switches S11 to S1N are respectively switched to the contacts a. The first reference voltage Vr1 generated by each reference voltage source A11 to AN1 is applied to the non-inverting input terminals of the respective comparators C1 to CN as they are. If the output voltages of the battery blocks B1 to BN are normal and the reference voltage sources A11 to AN1, the voltage dividing circuits D1 to DN, and the comparators C1 to CN are all normal, the logical sum signal ds is at a high level.

  Next, in the second inspection process, the switches S11 to S1N are switched to the contacts b while the switches S41 to S4N are kept open. If the output voltages of the battery blocks B1 to BN are normal and the reference voltage sources A12 to AN2, the voltage dividing circuits D1 to DN, and the comparators C1 to CN are normal, the OR signal ds is at a high level. Next, in the third inspection process, the switches S11 to S1N are respectively switched to the contacts c while the switches S41 to S4N are kept open. If the output voltages of the battery blocks B1 to BN are normal and all of the reference voltage sources A13 to AN3, the voltage dividing circuits D1 to DN and the comparators C1 to CN are normal, the logical sum signal ds is at a high level.

  Next, in the fourth inspection process, the switches S41 to S4N of the abnormal voltage detectors 401 to 40N are closed, and the switches S11 to S1N are respectively switched to the contacts a. The first reference voltage Vr1 generated by each of the reference voltage sources A11 to AN1 is divided by resistors r1 and r2, and is supplied to the non-inverting input terminals of the comparators C1 to CN, respectively. The resistance values of the resistors r1 and r2 are set to values at which the voltage applied to the non-inverting input terminals of the comparators C1 to CN is sufficiently smaller than the voltage applied to the inverting input terminal. Therefore, if all of the reference voltage sources A11 to AN1, the voltage dividing circuits D1 to DN, and the comparators C1 to CN are normal, the logical sum signal ds is at a low level.

  Next, in the fifth inspection process, the switches S11 to S1N are respectively switched to the contacts b while the switches S41 to S4N are closed. If all of the reference voltage sources A12 to AN2, the voltage dividing circuits D1 to DN and the comparators C1 to CN are normal, the logical sum signal ds is at a low level. Next, in the sixth inspection process, the switches S11 to S1N are respectively switched to the contacts c while the switches S41 to S4N are closed. If all of the reference voltage sources A13 to AN3, the voltage dividing circuits D1 to DN, and the comparators C1 to CN are normal, the OR signal ds is at a low level.

  The control unit 450 controls the switches S11 to S1N and the switches S41 to S4N as in the first to sixth inspection processes, and is abnormal when the level of the logical sum signal ds in each inspection process is the same as the above. It is determined that the voltage detection units 401 to 40N are functioning normally. On the other hand, when the level of the logical sum signal ds in each inspection process is different from the above, it is determined that at least one of the abnormal voltage detection units 401 to 40N has failed. The control unit 450 displays the inspection result of the abnormality detection function of the abnormal voltage detection units 401 to 40N on the display unit 152 by lighting the lamp or the like.

  The abnormal voltage detection device 400 according to the third embodiment has the same effect as the abnormal voltage detection device 100 according to the first embodiment, and easily detects whether the abnormal voltage detection device 400 can normally perform the abnormality detection processing. There is an effect that can be done. Note that the voltage drop circuits 41 to 4N may be attached to the abnormal voltage detection units 301 to 30N of the abnormal voltage detection device 300 according to the second embodiment, and an inspection function for the abnormality detection function may be added.

  The abnormal voltage detection device 400 has a function of inspecting whether there is a failure in the abnormality detection function. Therefore, when the abnormality detection function is broken, the use of the assembled battery 10 is continued without noticing that the detection means is broken, and as a result, the battery blocks B1 to BN are overcharged or overdischarged. There is no fear.

  In the third embodiment, the voltage drop circuit control signal TC output from the voltage drop circuit control unit 454 is 1 bit. Depending on the 1-bit control signal TC, only the result of checking all the abnormal voltage detectors 401 to 40N together can be obtained. More preferably, the voltage drop circuit control signal TC output from the voltage drop circuit control unit 454 is N bits, and all abnormal voltage detection units 401 to 40N are individually inspected.

Embodiment 4 FIG.
With reference to FIG. 13, an abnormal voltage detection apparatus 500 for an assembled battery according to Embodiment 4 of the present invention will be described. FIG. 13: is a block diagram which shows schematic structure of the abnormal voltage detection apparatus for assembled batteries which concerns on Embodiment 4 of this invention. In FIG. 13, the same reference numerals are used for portions common to FIG. 12, and description thereof is omitted.

  In the abnormal voltage detection device 400 for an assembled battery according to the third embodiment, the voltage difference between the output voltage level of the lowest battery block B1 constituting the assembled battery 10 and the output voltage level of the uppermost battery block BN is 270V or more. Therefore, the voltage levels of the control signals RC1 and RC2 for controlling the switching of the switches S11 to S1N and the voltage level of the control signal TC for controlling the opening and closing of the switches S41 to S4N constituting the voltage drop circuits 41 to 4N are set to the respective switches. Level conversion circuits 111, 112, and 113 that convert the voltage levels to open and close are required. In the third embodiment, when the level conversion circuits 111, 112, and 113 are configured by high breakdown voltage circuit elements having a breakdown voltage of about 270 V at the maximum, such high breakdown voltage circuit elements are expensive and large, and thus abnormal voltage There arises a problem that the circuit scale and cost of the detection device increase. In the abnormal voltage detection apparatus 500 for an assembled battery according to the fourth embodiment, the level conversion circuit 513 is configured by an inexpensive low withstand voltage circuit element.

  In the third embodiment, the voltage drop circuit control signal TC output from the voltage drop circuit control unit 454 is 1 bit. Depending on the 1-bit control signal TC, only the result of checking all the abnormal voltage detectors 401 to 40N together can be obtained. The abnormal voltage detection device for an assembled battery according to the fourth embodiment is configured to inspect the abnormal voltage detection units 401 to 40N.

  In FIG. 13, 500 is an abnormal voltage detection device, 10 is an assembled battery, 11 is a relay, 12 is an inverter, and 13 is a motor generator. Abnormal voltage detection device 500, assembled battery 10, relay 11, inverter 12, and motor generator 13 are all mounted on an electric vehicle. The DC power of the assembled battery 10 is converted into AC power by the inverter 12, drives the motor generator 13, and runs the electric vehicle.

  The abnormal voltage detection apparatus 500 includes abnormal voltage detection units 401 to 40N, level conversion circuits 511, 512, and 513, a serial input / parallel output register 502, photocouplers PD, P1 to PN, and a control unit 550. In the abnormal voltage detection device 500 according to the fourth embodiment, a serial input / parallel output register 502 is added to the abnormal voltage detection device 400 (FIG. 12) according to the third embodiment, and the level conversion circuits 111, 112, and 113 are replaced with the level conversion circuit. 511, 512, and 513, the controller 450 is replaced with a controller 550, and the photocouplers P11, P12, and P13 are replaced with photocouplers PD. Further, the switches S41 to S4N are each constituted by an npn transistor.

  The control unit 550 is obtained by adding a parallel input / serial output register 555 to the control unit 450 of the abnormal voltage detection apparatus 400 according to the third embodiment. The switch control unit 151 generates 2-bit control signals RC1 and RC2 for switching the switches S11 to S1N. The voltage drop circuit control unit 454 generates voltage drop circuit control signals TC1 to TCN for switching the switches S41 to S4N, respectively. The parallel input / serial output register 555 receives control signals RC1, RC2, TC1 to TCN from its parallel input terminals, and uses them as data bits. The parallel input / serial output register 555 further adds a start bit to the head of the data bit and adds a stop bit after the data bit. The start bit has 10 2 bits, for example. The stop bit has, for example, 10 2 bits.

  Here, 1 is a level at which the light emitting diode of the photocoupler PD emits light, and 0 is a level at which the light emitting diode of the photocoupler PD is turned off. The parallel input / serial output register 555 outputs a serial data signal SE having a start bit, a data bit, and a stop bit to an input light emitting diode of the photocoupler PD. The start bit is a control bit for automatically starting the serial input / parallel output register 502 on the receiving side. The stop bit is a control bit for automatically stopping the serial input / parallel output register 502 on the receiving side. The stop bit may be omitted.

  The phototransistor of the photocoupler PD transmits the serial data signal SE to the serial input / parallel output register 502 in an electrically insulated state. The serial input / parallel output register 502 inputs the serial data signal SE. The serial input / parallel output register 502 automatically starts the built-in clock oscillator 503 by a start bit added to the head of the serial data signal SE, and reads the serial data signal SE with a predetermined clock output from the clock oscillator 503. . Specifically, when the phototransistor of the photocoupler PD is turned on, the serial input / parallel output register 502 detects that serial data transfer is started. Next, at the timing when the phototransistor of the photocoupler PD changes from on to off (at the timing when the start bit changes from 1 to 0), the clock oscillator 503 starts outputting the clock. The clock output from the clock oscillator 503 has the same frequency as the internal clock from which the parallel input / serial output register 555 sends serial data, and is synchronized.

  The serial input / parallel output register 502 does not output the start bit and stop bit which are control signals, and only the data bits of the serial data signal SE are transferred from the parallel output terminals Y1 to YN, Y11, Y12 to the level conversion circuits 513, 511, The data is output to 512 respectively. The parallel output terminals Y1 to YN output voltage drop circuit control signals TC1 to TCN to the level conversion circuit 513, respectively. In the fourth embodiment, N is 20. Among the parallel output terminals Y1 to YN, only the voltage drop circuit control signal corresponding to the abnormal voltage detection unit to be inspected becomes high level. The parallel output terminals Y11 and Y12 output 2-bit control signals RC1 and RC2 to the level conversion circuits 511 and 512, respectively. The control signals RC1 and RC2 are distributed to the abnormal voltage detection units 401 to 40N via the level conversion circuits 511 and 512, respectively. The configuration of the level conversion circuits 511 and 512 is similar to the configuration of the level conversion circuit 513 (described later), except that the input signal is 1 bit and there are N output signals.

  The control unit 550 is electrically insulated from the high voltage assembled battery 10 by the photocouplers PD and P1 to PN.

  Hereinafter, the level conversion circuit 513 will be described. The level conversion circuit 513 includes boosting circuits L2, L3,. The booster circuit Ln is a circuit that converts the level of the voltage drop circuit control signal TCn output from the parallel output terminal Yn into a voltage for controlling the voltage drop circuit 4n corresponding to the nth battery block from the lowest order. FIG. 13 shows only the booster circuits L2, L3, and L4.

  The emitter terminal of the phototransistor constituting the photocoupler PD and the ground terminal of the serial input / parallel output register 502 are connected to the negative terminal of the lowest battery block B1. The voltage level of the voltage drop circuit control signals TC <b> 1 to TCN includes the negative terminal voltage of the battery pack 10. The output terminal Y1 of the serial input / parallel output register 502 is directly connected to the input terminal of the voltage drop circuit 41 (the base terminal of the npn transistor S41).

  The booster circuit L2 includes an npn transistor Q21 and a pnp transistor Q22. The base terminal of the npn transistor Q21 is connected to the output terminal Y2 of the serial input / parallel output register 502, and serves as the input terminal of the booster circuit L2. The emitter terminal of npn transistor Q21 is connected to the negative terminal of battery block B1, and the collector terminal is connected to the base terminal of pnp transistor Q22. The emitter terminal of the pnp transistor Q22 is connected to the positive terminal of the battery block B2. The collector terminal of the pnp transistor Q22 is connected to the input terminal of the voltage drop circuit 42 (the base terminal of the npn transistor S42) and serves as the output terminal of the booster circuit L2.

  The booster circuit L3 includes two sets of npn transistor and pnp transistor pairs L3-1 and L3-2. The pair L3-1 includes an npn transistor Q21 and a pnp transistor Q22. The pair L3-1 has a configuration similar to that of the booster circuit L2. The pair L3-2 includes an npn transistor Q31 and a pnp transistor Q32. The base terminal of the npn transistor Q21 of the pair L3-1 is connected to the output terminal Y3 of the serial input / parallel output register 502, and serves as the input terminal of the booster circuit L3. The emitter terminal of npn transistor Q21 of pair L3-1 is connected to the negative terminal of battery block B1, and the collector terminal is connected to the base terminal of pnp transistor Q22 of pair L3-1. The emitter terminal of the pnp transistor Q22 of the pair L3-1 is connected to the positive terminal of the battery block B2, and the collector terminal is connected to the base terminal of the npn transistor Q31. The emitter terminal of npn transistor Q31 is connected to the negative terminal of battery block B2, and the collector terminal is connected to the base terminal of pnp transistor Q32. The emitter terminal of the pnp transistor Q32 is connected to the positive terminal of the battery block B3. The collector terminal of the pnp transistor Q32 is connected to the input terminal of the voltage drop circuit 43 (the base terminal of the npn transistor S43) and serves as the output terminal of the booster circuit L3.

  The booster circuit L4 includes three pairs of npn transistors and pnp transistors L4-1, L4-2, and L4-3. The pair L4-1 includes an npn transistor Q21 and a pnp transistor Q22. The pair L4-1 has a configuration similar to that of the pair L3-1. The pair L4-2 includes an npn transistor Q31 and a pnp transistor Q32. The pair L4-2 has a configuration similar to that of the pair L3-2. The pair L4-3 includes an npn transistor Q41 and a pnp transistor Q42. The base terminal of the npn transistor Q21 of the pair L4-1 is connected to the output terminal Y4 of the serial input / parallel output register 502, and serves as the input terminal of the booster circuit L4. The emitter terminal of npn transistor Q21 of pair L4-1 is connected to the negative terminal of battery block B1, and the collector terminal is connected to the base terminal of pnp transistor Q22 of pair L4-1. The emitter terminal of the pnp transistor Q22 of the pair L4-1 is connected to the positive terminal of the battery block B2, and the collector terminal is connected to the base terminal of the npn transistor Q31 of the pair L4-2. The emitter terminal of npn transistor Q31 of pair L4-2 is connected to the negative terminal of battery block B2, and the collector terminal is connected to the base terminal of pnp transistor Q32 of pair L4-2. The emitter terminal of the pnp transistor Q32 of the pair L4-2 is connected to the positive terminal of the battery block B3. The collector terminal of pnp transistor Q32 in pair L4-2 is connected to the base terminal of npn transistor Q41. The emitter terminal of npn transistor Q41 is connected to the negative terminal of battery block B3, and the collector terminal is connected to the base terminal of pnp transistor Q42. The emitter terminal of the pnp transistor Q42 is connected to the positive terminal of the battery block B4. The collector terminal of the pnp transistor Q42 is connected to the input terminal of the voltage drop circuit 44 (the base terminal of the npn transistor S44) and serves as the output terminal of the booster circuit L4.

  Similarly, the input terminal of the nth booster circuit Ln is connected to the nth output terminal Yn of the serial input / parallel output register 502, and the output terminal is the input terminal of the nth voltage drop circuit 4n (the npn transistor S4n of the npn transistor S4n). Base terminal). The booster circuit Ln includes n-1 sets of npn transistors and pnp transistors. Therefore, the level conversion circuit 513 includes N (N−1) / 2 npn transistors and N (N−1) / 2 pnp transistors. In the fourth embodiment, the level conversion circuit 513 includes 190 npn transistors and 190 pnp transistors.

  The operation of the booster circuit L2 will be described. When the signal at the input terminal of the booster circuit L2 is at a high level, the base current flows through the base terminal of the npn transistor Q21, so that the npn transistor Q21 is turned on. Along with this, the base current of the pnp transistor Q22 flows, and the pnp transistor Q22 is also turned on. The voltage at the output terminal of the booster circuit L2 (the collector terminal of the pnp transistor Q22) rises to a voltage close to the positive terminal voltage (28.8 V) of the battery block B2. That is, a high level is output from the booster circuit L2 to the switch 42.

When the signal at the input terminal of the booster circuit L2 is at a low level, the npn transistor Q21 is not turned on, so that no current flows between the base terminal of the pnp transistor Q22 and the negative terminal of the battery block B1. That is, the pnp transistor Q22 is in an off state, and a low level (voltage close to the negative terminal voltage (14.4 V) of the battery block B2) is output from the booster circuit L2 to the voltage drop circuit 42.
As described above, the booster circuit L2 uses the voltage difference between the terminals of the transistors Q21 and Q22 as the voltage level of the input signal TC2 related to the battery block B2, and allows the voltage drop circuit 42 to operate. That is, the voltage is converted into the positive terminal voltage or the negative terminal voltage of the battery block B 2 and output to the voltage drop circuit 42. The booster circuit L2 boosts the voltage level of the input signal TC2 by a unit voltage using the voltage between the terminals of the battery block B2 as a unit voltage, and converts it to a converted voltage level that is the voltage level of the battery block B2.

  The operation of the booster circuit L3 will be described. When the signal at the input terminal of the booster circuit L3 is at a high level, the base current flows through the base terminal of the npn transistor Q21, so that the npn transistor Q21 is turned on. Along with this, the base current of the pnp transistor Q22 flows, and the pnp transistor Q22 is also turned on. Since the base current of npn transistor Q31 flows, npn transistor Q31 is also turned on. Accordingly, the base current of the pnp transistor Q32 flows, and the voltage of the output terminal of the booster circuit L3 (the collector terminal of the pnp transistor Q32) rises to a voltage close to the positive terminal voltage (43.2V) of the battery block B3. That is, a high level is output from the booster circuit L3 to the switch S43.

  When the signal at the input terminal of the booster circuit L3 is at a low level, the npn transistor Q21 is not turned on, so that no current flows between the base terminal of the pnp transistor Q22 and the negative terminal of the battery block B1. That is, the pnp transistor Q22 is off. Similarly, the npn transistor Q31 and the pnp transistor Q32 are also in the off state. That is, a low level (voltage close to the negative terminal voltage (28.8 V) of the battery block B3) is output from the booster circuit L3 to the voltage drop circuit 43.

  As described above, in the booster circuit L3, the voltage level (high level) of the input signal is converted to a voltage level near the positive terminal voltage of the battery block B2 by the npn transistor Q21 and the pnp transistor Q22, and further, the npn transistor Q31 and The voltage is converted to a voltage level near the positive terminal voltage of the battery block B3 by the pnp transistor Q32 and output to the voltage drop circuit 43. The booster circuit L3 uses the voltage level between the terminals of the transistors Q21, Q22, Q31, and Q32 as the voltage level of the input signal, that is, the voltage level at which the voltage drop circuit 43 can be operated, that is, the voltage across the battery block B3. The signal is converted into a level and output to the voltage drop circuit 43.

  Hereinafter, the booster circuits L4 to LN also operate in the same manner as the booster circuits L2 and L3. That is, in the booster circuit Ln, the voltage level of the input signal rises to the positive terminal voltage level of the battery block B2 by the first set of npn transistor and pnp transistor, and the second to (n-1) th set of npn transistors The pnp transistor further increases the voltage level by the voltage across the battery block (14.4 V). The voltage level of the input signal of the booster circuit Ln is converted to the positive terminal voltage level or the negative terminal voltage level of the battery block Bn.

  In the abnormal voltage detection apparatus 500 according to the fourth embodiment, the voltage between the terminals of each battery block B1 to BN is a unit voltage, and each booster circuit L2 to LN (FIG. 13) determines the voltage level of the control signals TC2 to TCN, The voltage is stepped up step by step by one unit voltage and converted to a conversion voltage level that is a voltage level of each of the battery blocks B2 to BN.

  A method for detecting whether or not the abnormal voltage detection apparatus 500 can normally detect an abnormality will be described. In addition, the inspection process of the following abnormality detection function is performed in a state where all the battery blocks B1 to BN have not reached overcharge (for example, before charging or before traveling of the electric vehicle). First, in the first inspection process, the switches S41 to S4N of the abnormal voltage detectors 401 to 40N are opened, and the switches S11 to S1N are switched to the contacts a. The first reference voltage Vr1 generated by each of the reference voltage sources A11 to AN1 is directly applied to the non-inverting input terminals of the comparators C1 to CN. If the output voltages of the battery blocks B1 to BN are normal and the reference voltage sources A11 to AN1, the voltage dividing circuits D1 to DN, and the comparators C1 to CN are all normal, the logical sum signal ds is at a high level.

  Next, in the second inspection process, the switches S11 to S1N are respectively switched to the contacts b while the switches S41 to S4N are kept open. If the output voltages of the battery blocks B1 to BN are normal and the reference voltage sources A12 to AN2, the voltage dividing circuits D1 to DN, and the comparators C1 to CN are normal, the OR signal ds is at a high level. Next, in the third inspection process, the switches S11 to S1N are respectively switched to the contacts c while the switches S41 to S4N are kept open. If the output voltages of the battery blocks B1 to BN are normal and all of the reference voltage sources A13 to AN3, the voltage dividing circuits D1 to DN and the comparators C1 to CN are normal, the logical sum signal ds is at a high level.

  Next, in the fourth to sixth inspection processes, the abnormality detection function of the abnormal voltage detector 401 is inspected. In the fourth inspection process, the switch S41 of the abnormal voltage detection unit 401 is closed, and the switches S11 to S1N are switched to the contacts a. The first reference voltage Vr1 generated by each of the reference voltage sources A11 to AN1 is divided by resistors r1 and r2, and is supplied to the non-inverting input terminals of the comparators C1 to CN, respectively. If all of the reference voltage sources A11 to AN1, the voltage dividing circuits D1 to DN, and the comparators C1 to CN are normal, the OR signal ds is at a low level.

  Next, in the fifth inspection process, the switches S11 to S1N are respectively switched to the contacts b while the switch S41 is kept closed. If all of the reference voltage sources A12 to AN2, the voltage dividing circuits D1 to DN and the comparators C1 to CN are normal, the logical sum signal ds is at a low level. Next, in the sixth inspection process, the switches S11 to S1N are respectively switched to the contacts c while the switch S41 is closed. If all of the reference voltage sources A13 to AN3, the voltage dividing circuits D1 to DN, and the comparators C1 to CN are normal, the OR signal ds is at a low level.

  The control unit 450 controls the switches S11 to S1N and the switches S41 to S4N as in the first to sixth inspection processes, and is abnormal when the level of the logical sum signal ds in each inspection process is the same as the above. It is determined that the voltage detection unit 401 is functioning normally. If the level of the logical sum signal ds in each inspection process is different from the above, it is determined that the abnormal voltage detection unit 401 has failed.

  The control unit 450 also sequentially tests the abnormality detection function for the abnormality detection units 402 to 40N in the same manner as the abnormality detection unit 401 by the inspection processing as in the fourth to sixth inspection processes. The control unit 450 displays the inspection result of the abnormality detection function of the abnormal voltage detection units 401 to 40N on the display unit 152 by lighting the lamp or the like.

  The voltage applied to each pnp transistor and each npn transistor constituting the level conversion circuit 513 is a voltage between terminals of the battery block (14.4 V) or twice (28.8 V) thereof. Therefore, the level conversion circuit 513 can be easily made into an IC using an existing low breakdown voltage semiconductor element having a breakdown voltage of about 40V. According to the fourth embodiment, an abnormal voltage detection device for an inexpensive and small assembled battery can be provided. Furthermore, since the abnormal voltage detection device 500 generates the serial data signal SE including the control signals RC1, RC2 and TC1 to TCN, the control signals RC1, RC2 and TC1 to TCN can be transmitted using one photocoupler PD. . According to the fourth embodiment, an abnormality detection function inspection function can be added to an abnormal voltage detection device that does not have an abnormality detection function inspection function by simply adding an inexpensive and small circuit element.

  Generally, a serial input / parallel output register has a data input terminal for inputting a serial data signal, a reset terminal for inputting a reset signal, and a clock input terminal for inputting a clock. The serial input / parallel output register 502 of the present invention has only a data input terminal DATA for inputting the serial data signal SE, and does not have a reset terminal and a clock input terminal. The serial input / parallel output register 502 inputs the serial data signal SE through one transmission element PD whose input terminal and output terminal are electrically insulated from each other. According to the fourth embodiment, an abnormality detection function inspection function can be added to an abnormal voltage detection device that does not have an abnormality detection function inspection function by simply adding an inexpensive and small circuit element.

  The level conversion circuit 513 and the serial input / parallel output register 502 may be used to control the switches S31 to S3N of the abnormal voltage detection device 300 according to the second embodiment.

  Instead of the configuration of the fourth embodiment, the following configuration may be used. Control unit 550 outputs a reset signal. The reset signal output from the control unit 550 is sent to the parallel input / serial output register 555 and the serial input / parallel output register 502. The control unit 550 sends a reset signal to the serial input / parallel output register 502 via the photocoupler PR. The photocoupler PR transmits a reset signal in a state where the control unit 550 and the serial input / parallel output register 502 are electrically insulated from each other.

  When the control unit 550 outputs a reset signal, the parallel input / serial output register 555 automatically outputs the 2-bit control signal and the N-bit test unit driving signal input to the parallel terminal to the serial output register at the rising edge. The clock oscillator built in the parallel input / serial output register 555 and the serial input / parallel output register 502 automatically starts outputting the clock simultaneously. The oscillation clock frequencies of the clock oscillators built in the parallel input / serial output register 555 and the serial input / parallel output register 502 are the same, and both are synchronized. The parallel input / serial output register 555 outputs serial data, and the serial input / parallel output register 502 accurately reads the serial data input via the photocoupler PD.

Embodiment 5. FIG.
With reference to FIG. 14, the abnormal voltage detection apparatus 1000 for the assembled battery which concerns on Embodiment 5 of this invention is demonstrated. FIG. 14: is a block diagram which shows schematic structure of the abnormal voltage detection apparatus 1000 for the assembled battery which concerns on Embodiment 5 of this invention. In FIG. 14, the same reference numerals are used for portions common to FIG. 13, and description thereof is omitted.

  In the abnormal voltage detection apparatus 500 according to the fourth embodiment, the terminal voltage of each of the battery blocks B1 to BN is set as a unit voltage. Each booster circuit L2 to LN (FIG. 13) boosts the voltage levels of the control signals TC2 to TCN step by step by one unit voltage, and converts them into converted voltage levels that are the voltage levels of the battery blocks B1 to BN, respectively. . In the abnormal voltage detection apparatus 1000 according to the fifth embodiment, the level conversion circuit 1013 boosts the voltage levels of the control signals TC3 to TCN step by step by a plurality of unit voltages, and converts them into conversion voltage levels L300 to LN00. Is provided.

  The abnormal voltage detection apparatus 1000 is obtained by replacing the level conversion circuit 513 of the abnormal voltage detection apparatus 500 (FIG. 13) according to the fourth embodiment with a level conversion circuit 1013. Other configurations are the same as those of the abnormal voltage detection apparatus 500 according to the fourth embodiment.

  The configuration and operation of the level conversion circuit 1013 will be described. The level conversion circuit 1013 includes boosting circuits L2, L300, L400, L500,... And LN00. The level conversion circuit 1013 is obtained by replacing the booster circuits L3 to LN of the level conversion circuit 513 with booster circuits L300 to LN00. The booster circuit Ln00 is a circuit that converts the level of the voltage drop circuit control signal TCn output from the parallel output terminal Yn to a voltage that controls the voltage drop circuit 4n corresponding to the nth battery block from the lowest order. FIG. 14 shows only booster circuits L2, L300, L400, and L500. Hereinafter, the configuration and operation of the booster circuits L300 to LN00 will be described.

  Boost circuit L300 includes npn transistor Q33 and pnp transistor Q34. The base terminal of the npn transistor Q33 is connected to the output terminal Y3 of the serial input / parallel output register 502, and serves as the input terminal of the booster circuit L300. The emitter terminal of npn transistor Q33 is connected to the negative terminal of battery block B1, and the collector terminal is connected to the base terminal of pnp transistor Q34. The emitter terminal of the pnp transistor Q34 is connected to the positive terminal of the battery block B3. The collector terminal of the pnp transistor Q34 is connected to the input terminal of the voltage drop circuit 43 (the base terminal of the npn transistor S43) and serves as the output terminal of the booster circuit L300.

  The booster circuit L400 includes two pairs of npn transistors and pnp transistors L4-4 and L4-5. The pair L4-4 includes an npn transistor Q21 and a pnp transistor Q22. The pair L4-4 has a configuration similar to that of the booster circuit L2. The pair L4-5 includes an npn transistor Q43 and a pnp transistor Q44. The base terminal of the npn transistor Q21 of the pair L4-4 is connected to the output terminal Y4 of the serial input / parallel output register 502, and serves as the input terminal of the booster circuit L400. The emitter terminal of npn transistor Q21 of pair L4-4 is connected to the negative terminal of battery block B1, and the collector terminal is connected to the base terminal of pnp transistor Q22 of pair L4-4. The emitter terminal of the pnp transistor Q22 of the pair L4-4 is connected to the positive terminal of the battery block B2, and the collector terminal is connected to the base terminal of the npn transistor Q43. The emitter terminal of npn transistor Q43 is connected to the negative terminal of battery block B2, and the collector terminal is connected to the base terminal of pnp transistor Q44. The emitter terminal of the pnp transistor Q44 is connected to the positive terminal of the battery block B4. The collector terminal of the pnp transistor Q44 is connected to the input terminal of the voltage drop circuit 44 (the base terminal of the npn transistor S44) and serves as the output terminal of the booster circuit L400.

  The booster circuit L500 includes two sets of npn transistor and pnp transistor pairs L5-1 and L5-2. The pair L5-1 includes an npn transistor Q33 and a pnp transistor Q34. The pair L5-1 has a configuration similar to that of the booster circuit L300. The pair L5-2 includes an npn transistor Q51 and a pnp transistor Q52. The base terminal of the npn transistor Q33 of the pair L5-1 is connected to the output terminal Y5 of the serial input / parallel output register 502, and serves as the input terminal of the booster circuit L500. The emitter terminal of npn transistor Q33 of pair L5-1 is connected to the negative terminal of battery block B1, and the collector terminal is connected to the base terminal of pnp transistor Q34 of pair L5-1. The emitter terminal of the pnp transistor Q34 of the pair L5-1 is connected to the positive terminal of the battery block B3, and the collector terminal is connected to the base terminal of the npn transistor Q51. The emitter terminal of npn transistor Q51 is connected to the negative terminal of battery block B3, and the collector terminal is connected to the base terminal of pnp transistor Q52. The emitter terminal of the pnp transistor Q52 is connected to the positive terminal of the battery block B5. The collector terminal of the pnp transistor Q52 is connected to the input terminal of the voltage drop circuit 45 (the base terminal of the npn transistor S45) and serves as the output terminal of the booster circuit L500.

  Similarly, the input terminal of the nth booster circuit Ln00 is connected to the nth output terminal Yn of the serial input / parallel output register 502, and the output terminal is the input terminal of the nth voltage drop circuit 4n (the npn transistor S4n). Base terminal).

  The operation of the booster circuit L300 will be described. When the signal at the input terminal of the booster circuit L300 is at a high level, the base current flows through the base terminal of the npn transistor Q33 of the booster circuit L300, so that the npn transistor Q33 is turned on. Along with this, the base current of the pnp transistor Q34 of the booster circuit L300 flows, and the pnp transistor Q34 is also turned on. The voltage at the output terminal of the booster circuit L300 (the collector terminal of the pnp transistor Q34) rises to a voltage close to the positive terminal voltage (43.2V) of the battery block B3. That is, a high level is output from the booster circuit L300 to the switch S43.

  When the signal at the input terminal of the booster circuit L300 is at a low level, the npn transistor Q33 of the booster circuit L300 does not turn on, so that no current flows between the base terminal of the pnp transistor Q34 of the booster circuit L300 and the negative terminal of the battery block B1. Not flowing. That is, the pnp transistor Q34 is off. That is, a low level (voltage close to the negative terminal voltage (28.8 V) of the battery block B3) is output from the booster circuit L300 to the voltage drop circuit 43.

  As described above, in the booster circuit L300, the voltage level (high level) of the input signal is converted to a voltage level near the positive terminal voltage of the battery block B3 using the voltage difference between the terminals of the npn transistor Q33 and the pnp transistor Q34. And output to the voltage drop circuit 43. The booster circuit L300 converts the voltage level of the input signal into a voltage level at which the voltage drop circuit 43 can be operated, that is, a voltage level across the battery block B3, and outputs the voltage level to the voltage drop circuit 43. The booster circuit L300 boosts the voltage level of the input signal TC3 related to the battery block B3 by a voltage twice as high as the unit voltage using the voltage between the terminals of the battery blocks B1 to B3 as a unit voltage. It converts to the conversion voltage level which is level.

  The operation of the booster circuit L400 will be described. When the signal at the input terminal of the booster circuit L400 is at a high level, the base current flows through the base terminal of the npn transistor Q21 of the booster circuit L400, so that the npn transistor Q21 is turned on. Along with this, the base current of the pnp transistor Q22 of the booster circuit L400 flows, and the pnp transistor Q22 is also turned on. Since the base current of npn transistor Q43 flows, npn transistor Q43 is also turned on. Along with this, the base current of the pnp transistor Q44 flows, and the voltage of the output terminal of the booster circuit L400 (collector terminal of the pnp transistor Q44) rises to a voltage close to the positive terminal voltage (57.6V) of the battery block B4. That is, a high level is output from the booster circuit L400 to the switch S44.

  When the signal at the input terminal of the booster circuit L400 is at a low level, the npn transistor Q21 of the booster circuit L400 does not turn on, so that no current flows between the base terminal of the pnp transistor Q22 of the booster circuit L400 and the negative terminal of the battery block B1. Not flowing. That is, the pnp transistor Q22 is off. Similarly, the npn transistor Q43 and the pnp transistor Q44 are also off. That is, a low level (voltage close to the negative terminal voltage (43.2 V) of the battery block B4) is output from the booster circuit L400 to the voltage drop circuit 44.

  As described above, in the booster circuit L400, the voltage level (high level) of the input signal is converted to a voltage level near the positive terminal voltage of the battery block B2 by the pair L4-4, and further, the battery block by the pair L4-5. The voltage level is converted to a voltage level near the positive terminal voltage of B4 and output to the voltage drop circuit 44. The booster circuit L400 uses the voltage level of the input signal as the voltage level at which the voltage drop circuit 44 can be operated using the voltage difference between the terminals of the transistors Q21, Q22, Q43, Q44, that is, the voltage across the battery block B4. The signal is converted into a level and output to the voltage drop circuit 44. The booster circuit L400 boosts the voltage level of the input signal TC4 related to the battery block B4 by a unit voltage using the voltage between terminals of the battery blocks B1 to B4 as a unit voltage, and then boosts the voltage level by twice the unit voltage. The voltage is converted to a conversion voltage level that is the voltage level of the battery block B4.

  The operation of the booster circuit L500 will be described. When the signal at the input terminal of the booster circuit L500 is at a high level, the base current flows through the base terminal of the npn transistor Q33 of the booster circuit L500, so that the npn transistor Q33 is turned on. Along with this, the base current of the pnp transistor Q34 of the booster circuit L500 flows, and the pnp transistor Q34 is also turned on. Since the base current of npn transistor Q51 flows, npn transistor Q51 is also turned on. Along with this, the base current of the pnp transistor Q52 flows, and the voltage of the output terminal of the booster circuit L500 (the collector terminal of the pnp transistor Q52) rises to a voltage close to the positive terminal voltage (72.0V) of the battery block B5. That is, a high level is output from the booster circuit L500 to the switch S45.

  When the signal at the input terminal of the booster circuit L500 is at a low level, the npn transistor Q33 of the booster circuit L500 is not turned on, so that no current flows between the base terminal of the pnp transistor Q34 of the booster circuit L500 and the negative terminal of the battery block B1. Not flowing. That is, the pnp transistor Q34 is off. Similarly, the npn transistor Q51 and the pnp transistor Q52 are also off. That is, a low level (voltage close to the negative terminal voltage (57.6 V) of the battery block B5) is output from the booster circuit L500 to the voltage drop circuit 45.

  As described above, in the booster circuit L500, the voltage level (high level) of the input signal is converted to a voltage level near the positive terminal voltage of the battery block B3 by the pair L5-1, and further the battery block by the pair L5-2. The voltage level is converted to a voltage level near the positive terminal voltage of B5 and output to the voltage drop circuit 45. The booster circuit L500 uses the voltage level of the input signal as the voltage level at which the voltage drop circuit 45 can be operated using the voltage difference between the terminals of the transistors Q33, Q34, Q51, Q52, that is, the voltage across the battery block B5. The signal is converted into a level and output to the voltage drop circuit 45.

  Hereinafter, the booster circuits L600 to LN00 also operate in the same manner as the booster circuits L2, L300, L400, and L500. When a voltage level of an input signal is a high level, a circuit composed of a pair of pnp transistors and npn transistors boosts the voltage level by twice the voltage between terminals of the battery block or the voltage between terminals of the battery block. . For example, the pair L4-4 of the booster circuit L2 and the booster circuit L400 boosts the voltage level of the input signal by the voltage between the terminals of the battery block (14.4 V in the embodiment). The booster circuit L300, the pair L4-5 of the booster circuit L400, and the pair L5-1 and L5-2 of the booster circuit L500 have a voltage level of an input signal that is twice the voltage between the terminals of the battery block (in the embodiment, Boost by 28.8V). The control signals TC3, TC5, TC7,... Related to the odd-numbered battery blocks B3, B5, B7,... Among the battery blocks higher than the battery block B3 are sequentially boosted in units of twice the voltage between the terminals of the battery block. Are finally converted to levels based on the positive terminal voltage of the battery block, and output to voltage drop circuits 43, 45, 47,. The control signals TC4, TC6, TC8,... Related to the even-numbered battery blocks B4, B6, B8,... Among the battery blocks higher than the battery block B4 are sequentially boosted in units of twice the voltage between the terminals of the battery block. Finally, the voltage between the terminals of the battery block is boosted, finally converted to a level based on the positive terminal voltage of the battery block, and output to the voltage drop circuits 44, 46, 48,.

  The voltage applied to each pnp transistor and each npn transistor constituting the level conversion circuit 1013 is about a voltage (14.4V) between terminals of the battery block, about 2 times (28.8V), or about 3 times (43.2V). ). Therefore, the level conversion circuit 1013 can be easily made into an IC using an existing semiconductor element having a breakdown voltage of about 50V. According to the fifth embodiment, an abnormal voltage detection device for an inexpensive and small assembled battery can be provided.

  The configuration of the level conversion circuit 1013 is not limited to that shown in FIG. In the level drop circuit Lk according to the fourth embodiment, the voltage level of the input signal is increased by the voltage between the terminals of the battery block (14.4 V) or twice (28.8 V) thereof. Instead, in the level drop circuit according to the upper battery block, the voltage may be increased by three times or more of the voltage between the terminals of the battery block. However, the increase level of the voltage level is determined by the balance between the withstand voltage level of the pnp transistor and npn transistor constituting the booster circuit and the voltage between the terminals of the battery block. Note that the pnp transistor and the npn transistor constituting the level conversion circuit 1013 may be replaced with other switch elements.

Embodiment 6. FIG.
With reference to FIG. 15, the abnormal voltage detection apparatus 600 for assembled batteries which concerns on Embodiment 6 of this invention is demonstrated. The abnormal voltage detection device 600 for an assembled battery according to the sixth embodiment has an abnormal voltage for the assembled battery according to the third embodiment in that the abnormal voltage detection units 601 to 60N are provided instead of the abnormal voltage detection units 401 to 40N. The abnormal voltage detection device 600 for the assembled battery according to the sixth embodiment is the same as the abnormal voltage detection device 400 for the assembled battery according to the third embodiment except for the difference from the detection device 400 (FIG. 12). It is. Only the configuration of the abnormal voltage detection units 601 to 60N according to the sixth embodiment will be described.

  FIG. 15 is a diagram illustrating a schematic configuration of the abnormal voltage detection unit 60n (n is an arbitrary positive integer satisfying 1 ≦ n ≦ N) according to the sixth embodiment. The configurations of the abnormal voltage detectors 601 to 60N are all the same. The configuration of the abnormal voltage detection unit 60n will be described. The abnormal voltage detection apparatus 400 according to the third embodiment generates three reference voltages Vr1, Vr2, and Vr3 in the abnormal voltage detectors 401 to 40N, respectively, and measures the battery that has dropped from the voltages of the corresponding battery blocks B1 to BN. Comparison was made with voltages Vb1 to VbN. Instead, the abnormal voltage detection units 601 to 60N according to the sixth embodiment divide the voltages of the corresponding battery blocks B1 to BN at three different voltage dividing ratios and compare the voltages with one reference voltage.

  An abnormal voltage detection unit 60n shown in FIG. 15 includes a reference voltage generation source An, a voltage dividing circuit D61n, a pnp transistor 62n, and a comparator Cn, and detects a voltage abnormality in the battery block Bn (overcharge in the sixth embodiment). To detect. The reference voltage generation source An is composed of a Zener diode (not shown) and a resistor (not shown), as in the case of the reference voltage generation source An of the abnormal voltage detection apparatus 300 for an assembled battery according to the second embodiment, and its output. The terminal is connected to the non-inverting input terminal of the comparator Cn.

  The configuration of the voltage dividing circuit D61n will be described. A series connection circuit of resistors 611 and 612 is connected between the positive terminal of the battery block Bn and the inverting input terminal of the comparator Cn. A pnp transistor 62n is connected in parallel with the resistor 611. One ends of the three resistors 613, 614, and 615 are connected to the inverting input terminal of the comparator Cn. In the sixth embodiment, the resistance values of the three resistors 613, 614, and 615 are set such that the resistor 613> the resistor 614> the resistor 615. The common terminal of the three-point selector switch 63n is connected to the negative terminal of the battery block Bn. Three terminals a, b, and c of the three-point selector switch are connected to the other ends of the resistors 613, 614, and 615, respectively. The switches 631 to 63N are interlocked. The pnp transistors 621 to 62N are interlocked.

  The voltage drop circuit control unit 454 (see FIG. 12) generates a control signal TCa for switching on and off of the pnp transistor 62n instead of the control signal TC. The control signal TCa is input to the base of the pnp transistor 62n via the photocoupler P13 and the level conversion circuit 113. The switch control unit 151 (see FIG. 12) generates control signals RC1a and RC2a for switching the switch 63n instead of the control signals RC1 and RC2. The control signals RC1a and RC2a are input to the switch 63n via the photocoupler P11 and the level conversion circuit 111, the photocoupler P12 and the level conversion circuit 112, respectively.

  The operation of the abnormal voltage detection unit 60n will be described. In normal operation, the control signal TCa is at a high level, and the pnp transistor 62n is off. This case will be described. The switch 63n grounds the resistor 613 according to the control signals RC1a and RC2a. When the resistor 613 is grounded, the voltage of the battery block Bn is divided by the resistors 611, 612, and 613 and output to the inverting input terminal of the comparator Cn. When the voltage dividing circuit D61n inputs a voltage (18V) when the battery block Bn is slightly overcharged, the voltage output to the inverting input terminal of the comparator Cn is equal to the reference voltage output from the reference voltage source An. The comparator Cn generates and outputs an abnormality detection signal dn at a low level when the voltage of the battery block Bn is higher than 18V, and at a high level when the voltage is low.

  The switch 63n grounds the resistor 614 according to the control signals RC1a and RC2a. When the pnp transistor 62n is off and the resistor 614 is grounded, the voltage of the battery block Bn is divided by the resistors 611, 612, and 614 and output to the inverting input terminal of the comparator Cn. When the voltage dividing circuit D61n inputs a voltage (20V) in a state where the battery block Bn is considerably overcharged, the voltage output to the inverting input terminal of the comparator Cn is equal to the reference voltage output from the reference voltage source An. The comparator Cn generates an abnormality detection signal dn at a low level when the voltage of the battery block Bn is higher than 20V, and outputs it to the photocoupler Pn when the voltage is low.

  The switch 63n grounds the resistor 615 according to the control signals RC1a and RC2a. When the pnp transistor 62n is off and the resistor 615 is grounded, the voltage of the battery block Bn is divided by the resistors 611, 612, and 615 and output to the inverting input terminal of the comparator Cn. When the voltage (22 V) is input when the voltage dividing circuit D61n is overcharged to such an extent that the battery block Bn cannot recover, the voltage output to the inverting input terminal of the comparator Cn is the reference voltage source It is equal to the reference voltage output by An. The comparator Cn generates an abnormality detection signal dn at a low level when the voltage of the battery block Bn is higher than 20V, and outputs it to the photocoupler Pn when the voltage is low.

  Each abnormality detection signal d1 to dN is ORed. The controller 450 (see FIG. 12) inputs a logical sum signal ds that is a logical sum of the abnormality detection signals d1 to dN related to the battery blocks B1 to BN.

  A method for detecting whether or not the abnormal voltage detection apparatus 600 can normally detect an abnormality (inspection of an abnormality detection function) will be described. In the abnormal voltage detection device 600 of the sixth embodiment, the three battery measurement voltages generated by the voltage dividing circuits D611 to D61N are respectively compared with the reference voltages generated by the reference voltage sources A1 to AN by the pnp transistors 621 to 62N. The abnormality detection signals d1 to dN are generated by changing each battery voltage and comparing each battery measurement voltage with a reference voltage. Based on the logical sum signal ds of the abnormality detection signals d1 to dN, the control unit 450 detects whether or not the abnormal voltage detection device 600 can normally perform abnormality detection. The inspection of the abnormality detection function is performed in a state where each of the battery blocks B1 to BN has not reached overcharge, for example, before charging or before traveling of the electric vehicle. At the time of inspection of the abnormality detection function, the control signal TCa is at a low level, and the pnp transistors 621 to 62N are on. The resistor 611 is short-circuited.

  First, in the first inspection process, the pnp transistors 621 to 62N are turned on, and the resistor 613 is grounded. When the resistor 613 is grounded, when the voltage dividing circuit D61n inputs, for example, 12V (lower than 18V), the voltage that the pnp transistor 62n and the resistors 612 and 613 divide and output to the inverting input terminal of the comparator Cn is It is equal to the reference voltage output from the reference voltage source An. The comparator Cn outputs information indicating whether or not the voltage of the battery block Bn is higher than 12V to the photocoupler Pn. Since the voltage of the battery block Bn is 14.4 V as a standard, if the reference voltage generators A1 to AN, the voltage dividing circuits D611 to D61N, and the comparators C1 to CN are normal, the abnormal voltage detectors 601 to 60N are respectively Low level abnormality detection signals d1 to dN are generated. Therefore, the logical sum signal ds is at a low level.

  Next, in the second inspection process, the resistor 614 is grounded while the pnp transistors 621 to 62N are kept conductive. If the reference voltage generation units A1 to AN, the voltage dividing circuits D611 to D61N, and the comparators C1 to CN are normal, the abnormal voltage detection units 601 to 60N generate low level abnormality detection signals d1 to dN, respectively. Therefore, the logical sum signal ds is at a low level. Next, in the third inspection process, the resistor 615 is grounded while the pnp transistors 621 to 62N are kept conductive. If the reference voltage generation units A1 to AN, the voltage dividing circuits D611 to D61N, and the comparators C1 to CN are normal, the abnormal voltage detection units 601 to 60N generate low level abnormality detection signals d1 to dN, respectively. Therefore, the logical sum signal ds is at a low level.

  The control unit 450 controls the switches 631 to 63N and the pnp transistors 621 to 62N as in the first to third inspection processes, and when the level of the logical sum signal ds in each inspection process is the same as the above It is determined that the abnormal voltage detectors 601 to 60N are functioning normally. When the level of the logical sum signal ds in each inspection process is different from the above, it is determined that at least one of the abnormal voltage detection units 601 to 60N is out of order. The control unit 450 displays the inspection result of the abnormality detection function of the abnormal voltage detection units 601 to 60N on the display unit 152 by lighting the lamp or the like.

  The abnormal voltage detection device 600 according to the sixth embodiment has the same effect as the abnormal voltage detection device 100 according to the first embodiment, and also has an effect that the abnormality detection function can be easily inspected. In the sixth embodiment, the control signal TCa output from the voltage drop circuit control unit 454 is 1 bit. Depending on the 1-bit control signal TCa, only the result of checking all the abnormal voltage detectors 601 to 60N together can be obtained. More preferably, the control signal TCa generated by the voltage drop circuit control unit 454 is set to N bits, and all abnormal voltage detection units 601 to 60N are individually inspected.

  The abnormal voltage detection units 401 to 40N of the abnormal voltage detection device according to the third embodiment may be replaced with the abnormal voltage detection units 601 to 60N according to the sixth embodiment. Alternatively, a plurality of reference voltage sources may be provided so that one of the switch 63n and the pnp transistor 62n switches the reference voltage output from the reference voltage generation source, and the other switches the voltage dividing ratio of the voltage dividing circuit D61n.

Embodiment 7. FIG.
With reference to FIG. 16, the abnormal voltage detection apparatus 700 for assembled batteries which concerns on Embodiment 7 of this invention is demonstrated. The abnormal voltage detection apparatus 700 for the assembled battery according to the seventh embodiment includes the abnormal voltage detection units 701 to 70N instead of the abnormal voltage detection units 101 to 10N, and the abnormal voltage for the assembled battery according to the first embodiment. The abnormal voltage detection device 700 for the assembled battery according to the seventh embodiment is the same as the abnormal voltage detection device 100 for the assembled battery according to the first embodiment except for the difference from the detection device 100 (FIG. 1). It is. Only the configuration of the abnormal voltage detectors 701 to 70N according to the seventh embodiment will be described.

  The configurations of the abnormal voltage detection units 701 to 70N are all the same. FIG. 16 is a diagram illustrating a schematic configuration of an abnormal voltage detection unit 70n (n is an arbitrary positive integer satisfying 1 ≦ n ≦ N) of the abnormal voltage detection device 700 according to the seventh embodiment. The abnormal voltage detection unit 70n according to the seventh embodiment is different from the abnormal voltage detection unit 10n according to the first embodiment in that a voltage dividing circuit D71n is provided instead of the voltage dividing circuit Dn. Otherwise, the abnormal voltage detection unit 70n of the assembled battery according to the seventh embodiment is the same as the abnormal voltage detection unit 10n of the assembled battery according to the first embodiment. Only the voltage dividing circuit D71n according to the seventh embodiment will be described.

  In the first embodiment, the voltage dividing circuits D1 to DN are configured by resistors Rd1 and Rd2, respectively, and voltages obtained by dividing the terminal voltages of the battery blocks B1 to BN at a predetermined ratio are output to the inverting input terminals of the comparators C1 to CN. . As shown in FIG. 16, the voltage dividing circuit D71n (n is an arbitrary positive integer satisfying 1 ≦ n ≦ N) according to the seventh embodiment includes a constant voltage source 721 and a constant current source 722 at both ends of the battery block Bn. It has a configuration connected in series. The potential at the connection point between the constant voltage source 721 and the constant current source 722 is input to the inverting input terminal of the comparator Cn. The constant voltage source 721 generates a voltage drop of a constant voltage Vconst. When the voltage across the battery block Bn is Vn, the voltage dividing circuit D71n outputs the battery measurement voltage Vbn = (Vn−Vconst) to the inverting input terminal of the comparator Cn.

  The configuration of the constant voltage source 721 is arbitrary. For example, the constant voltage source 721 is a Zener diode or a band gap reference circuit. The configuration of the constant current source 722 is arbitrary. For example, the constant current source 722 is a current mirror circuit that flows a constant current based on a reference current source, or simply one resistor. By using the constant voltage source 721, the voltage dividing circuit D71n can reduce power consumption compared with the voltage dividing circuit Dn (n is an arbitrary positive integer satisfying 1 ≦ n ≦ N) configured by resistors. Since the abnormal voltage detection device 700 consumes little power in the voltage dividing circuit D71n, it prevents the remaining capacity of the battery pack 10 from being lowered when the battery pack 10 is left unattended. Loss can be prevented.

  In the seventh embodiment, the reference voltage source An1 generates a first reference voltage Vr1 for detecting that the battery block Bn has reached a voltage (18V) in a slightly overcharged state. The first reference voltage Vr1 is equal to the voltage output from the voltage dividing circuit D71n that receives the output voltage 18V of the battery block Bn. The reference voltage source An2 generates a second reference voltage Vr2 for detecting that the battery block Bn has reached a voltage (20V) in a state where the battery block Bn is considerably overcharged. The second reference voltage Vr2 is equal to the voltage output from the voltage dividing circuit D71n to which the output voltage 20V of the battery block Bn is input. The reference voltage source An3 generates a third reference voltage Vr3 for detecting that the battery block BN has become an overcharge voltage (22V) that causes a failure that cannot be recovered. The third reference voltage Vr3 is equal to the voltage output from the voltage dividing circuit D71n that receives the output voltage 22V of the battery block Bn.

  The constant current source 722 may be removed, and the voltage dividing circuit D71n may output the voltage (Vn−Vconst) to the non-inverting input terminal of the comparator Cn by the sink current flowing into the inverting input terminal of the comparator Cn. In this case, the input circuit of the comparator Cn needs to be configured to absorb the input current, and the constant voltage source 721 needs to be configured to operate normally with a weak current. According to this configuration, wasteful current consumption can be reduced.

  The voltage dividing circuit D71n according to the seventh embodiment can be applied to the voltage dividing circuits D1 to DN and D611 to D61N according to the other second to sixth embodiments. Further, instead of the configuration according to the sixth embodiment (FIG. 15), a plurality of constant voltage sources and a constant current source are connected in series at both ends of the battery block Bn, and individually according to the control signals RC1a, RC2a and TCa. The constant voltage source may be short-circuited. Thereby, the same effect as Embodiment 6 is acquired.

Embodiment 8. FIG.
With reference to FIGS. 17-19, the abnormal voltage detection apparatus 1300 for the assembled batteries which concerns on Embodiment 8 of this invention is demonstrated. The abnormal voltage detection device according to the first to seventh embodiments detects an overcharged state of the assembled battery 10. The abnormal voltage detection device 1300 according to the eighth embodiment detects an overdischarge state of the assembled battery 10. FIG. 17: is a block diagram which shows schematic structure of the abnormal voltage detection apparatus 1300 for assembled batteries which concerns on Embodiment 8 of this invention. In FIG. 17, the same reference numerals are used for portions common to FIG. 1, and description thereof is omitted.

  The abnormal voltage detection device 1300 is obtained by replacing the abnormal voltage detection units 101 to 10N of the abnormal voltage detection device 100 according to the first embodiment with abnormal voltage detection units 1301 to 130N. In other respects, the abnormal voltage detection device 1300 according to the eighth embodiment is the same as the abnormal voltage detection device 100 according to the first embodiment.

  The abnormal voltage detection unit 130N will be described. The abnormal voltage detection unit 130N includes a reference voltage generation circuit R1N, a voltage dividing circuit DN, and a comparator CN, and detects a voltage abnormality in the battery block BN. In the eighth embodiment, the abnormal voltage detection unit 130N detects overdischarge of the battery block BN. The voltage dividing circuit DN is a circuit in which resistors Rd1 and Rd2 are connected in series. The voltage dividing circuit DN divides the voltage of the battery block BN and outputs the voltage dropped to the non-inverting input terminal of the comparator CN. In the eighth embodiment, the voltage dividing circuit DN divides the inter-terminal voltage of the battery block BN by a quarter.

  The reference voltage generation circuit R1N includes reference voltage sources AN1, AN2 and AN3, and a switch S1N. In the eighth embodiment, the reference voltage source AN1 generates the first reference voltage Vr1 for detecting that the battery block BN has reached a voltage (10V) in a state where the battery block BN is slightly overdischarged. The first reference voltage Vr1 is equal to the voltage output from the voltage dividing circuit DN that receives the output voltage 10V of the battery block BN. The reference voltage source AN2 generates a second reference voltage Vr2 for detecting that the battery block BN has reached a voltage (8V) in a state where the battery block BN is excessively discharged. The second reference voltage Vr2 is equal to the voltage output from the voltage dividing circuit DN that receives the output voltage 8V of the battery block BN. The reference voltage source AN3 generates a third reference voltage Vr3 for detecting that the battery block BN has become an overdischarge voltage (6V) that causes a failure that cannot be recovered. The third reference voltage Vr3 is equal to the voltage output from the voltage dividing circuit DN that receives the output voltage 8V of the battery block BN. In the eighth embodiment, Vr1> Vr2> Vr3.

  The switch S1N is switched to one of the contacts a, b, and c by a 2-bit control signal from the control unit 150, and selectively selects the reference voltage output from the reference voltage source AN1, AN2, or AN3 as an inverting input of the comparator CN. Input to the terminal. The comparator CN is composed of a differential circuit and is driven by the voltage of the battery block BN. The output voltage VbN of the voltage dividing circuit DN is applied to the non-inverting input terminal of the comparator CN. The anode of the input light emitting diode of the photocoupler PN is connected to the positive terminal of the battery block BN, and the cathode is connected to the output terminal of the comparator CN.

  Abnormal voltage detectors 1301-130 (N-1) have the same configuration as abnormal voltage detector 130N. The reference voltage sources A11 to AN1 generate a first reference voltage Vr1 that is equal to the output voltages Vb1 to VbN of the voltage dividing circuits D1 to DN to which the voltages (10 V) of the corresponding battery blocks B1 to BN are input, respectively. The reference voltage sources A12 to AN2 generate a second reference voltage Vr2 that is equal to the output voltages Vb1 to VbN of the voltage dividing circuits D1 to DN to which the voltages (8V) of the corresponding battery blocks B1 to BN are input, respectively. The reference voltage sources A13 to AN3 generate a third reference voltage Vr3 that is equal to the output voltages Vb1 to VbN of the voltage dividing circuits D1 to DN to which the voltages (6V) of the corresponding battery blocks B1 to BN are input, respectively. The voltage dividing circuits D1 to DN all have the same voltage dividing ratio. The comparators C1 to CN, the reference voltage sources A11 to AN1, A12 to AN2, A13 to AN3, and the switches S11 to S1N are driven by the voltages of the corresponding battery blocks B1 to BN, respectively.

  The switches S11 to S1N are simultaneously switched by a 2-bit control signal from the control unit 150. The first reference voltage Vr1, the second reference voltage Vr2, or the third reference voltage Vr3 is given to the inverting input terminals of all the comparators C1 to CN at the same timing. The comparators C1 to CN generate low level abnormality detection signals d1 to dN, respectively, when the output voltage of the voltage dividing circuits D1 to DN is lower than the voltage generated by the reference voltage source selected by the switches S11 to S1N. In the opposite case, high level abnormality detection signals d1 to dN are generated and output to the photocouplers P1 to PN, respectively.

  As with the abnormal voltage device 100 according to the first embodiment, the abnormal voltage detection device 1300 performs a logical OR operation on the abnormality detection signals d1 to dN to generate a logical sum signal ds. The logical sum signal ds is normally at a high level, and is at a low level when the voltage of at least one battery block is lower than the voltage generated by the reference voltage source selected by the switches S11 to S1N. It is.

  An abnormality detection method will be described with reference to FIGS. 18 and 19 are flowcharts illustrating an abnormality detection method performed by the abnormal voltage detection apparatus 1300 for the assembled battery according to the eighth embodiment of the present invention. 18 and 19 are obtained by replacing S8 and S13 in FIGS. 3 and 4 with S8a and S13a, respectively. In other respects, the abnormality detection method performed by the abnormal voltage detection apparatus 1300 according to the eighth embodiment is the same as the abnormality detection method performed by the abnormal voltage detection apparatus 100 according to the first embodiment. Hereinafter, of the abnormality detection method performed by the abnormal voltage detection apparatus 1300 according to the eighth embodiment, only the portions different from the abnormality detection method performed by the abnormal voltage detection apparatus 100 according to the first embodiment will be described.

  The time ratio TR1 calculated in step S2 is equivalent to the ratio of the time period in which the battery measurement voltage of at least one battery block is lower than the first reference voltage Vr1 with respect to the time period T1. In step S3, the control unit 150 determines whether or not the assembled battery 10 is in a voltage abnormal state based on whether or not TR1 is equal to or greater than a predetermined value Nth1.

  The time ratio TR2a calculated in step S5 is equivalent to the ratio of the time period in which the battery measurement voltage of at least one battery block is lower than the first reference voltage Vr1 with respect to the time period T2 / 2. is there. The time ratio TR2b calculated in step S5 is equivalent to the ratio of the time period in which the battery measurement voltage of at least one battery block is lower than the second reference voltage Vr2 with respect to the time period T2 / 2. is there. In step S6 and step S7, the control unit 150 compares each of the battery measurement voltages Vb1 to VbN with the first reference voltage Vr1 and detects a voltage abnormality of the assembled battery 10, which is lower than the first reference voltage Vr1. A voltage abnormality of the battery pack 10 is detected as compared with the second reference voltage Vr2.

  The control unit 150 performs control to increase the charging power for the assembled battery 10 in step S8a (FIG. 18). Specifically, the inverter 12 is controlled so that the motor generator 13 functions as an electric motor, and the assembled battery 10 is charged with the generated electric power. Further, the display unit 152 lights a yellow lamp, for example, and displays that the assembled battery 10 is considerably discharged.

  The time ratio TR3b calculated in step S10 is equivalent to the ratio of the time period in which the battery measurement voltage of at least one battery block is lower than the second reference voltage Vr2 with respect to the time period T3 / 2. The time ratio TR3c is equivalent to the ratio of the time period in which the battery measurement voltage of at least one battery block is lower than the third reference voltage Vr3 with respect to the time period T3 / 2. In step S11 and step S12, the control unit 150 compares each of the battery measurement voltages Vb1 to VbN with the second reference voltage Vr2 and detects a voltage abnormality of the assembled battery 10, which is lower than the second reference voltage Vr2. A voltage abnormality of the assembled battery 10 is detected in comparison with the third reference voltage Vr3.

  In step S <b> 13 a (FIG. 19), the relay drive unit 153 turns off the relay 11 and stops supplying power from the assembled battery 10 to the motor generator 13. Further, for example, the display unit 152 turns on a red lamp to display that the assembled battery 10 is in an overdischarged state.

  The abnormal voltage detection apparatus 1300 for the assembled battery according to the eighth embodiment includes three reference voltages Vr1 obtained by dividing the voltages Vb1 to VbN by dividing the voltages of the battery blocks B1 to BN by the voltage dividing circuits D1 to DN, respectively. , Vr2, and Vr3 are respectively detected to detect whether or not each of the battery blocks B1 to BN has a voltage abnormality, and abnormal detection signals d1 to dN including information on the detection results are respectively generated. Then, at each reference voltage Vr1, Vr2, Vr3, based on the logical sum signal ds of the abnormality detection signals d1 to dN, a time ratio in which the assembled battery 10 is in a voltage abnormal state with respect to a predetermined time period is calculated. A voltage abnormality of the battery pack 10 is detected based on the time ratio. The abnormal voltage detection device 1300 detects a voltage abnormality of the assembled battery 10 at each of the reference voltages Vr1, Vr2, and Vr3, and displays the state of the assembled battery 10 to the user at each voltage. The abnormal voltage detection device 1300 can improve the detection accuracy of the voltage abnormality of the assembled battery 10 by changing the reference voltage and detecting the voltage abnormality step by step.

  In the above embodiment, the control unit inputs the logical sum signal ds of the abnormality detection signals d1 to dN output from each abnormal voltage detection unit from one input terminal. Instead, the control unit may input the abnormality detection signals d1 to dN output from the abnormal voltage detection units from separate input terminals.

  In the above embodiment, a P-channel MOS field effect transistor and an N-channel MOS field effect transistor may be used instead of the pnp transistor and the npn transistor.

  In the above embodiment, the reference voltage source is constituted by a Zener diode. Alternatively, the reference voltage generation source may be configured using a band gap reference circuit. Thereby, power consumption in the reference voltage source can be reduced.

  In the above embodiment, the photocoupler is used as the transmission element that transmits the signal while the input terminal and the output terminal are electrically insulated from each other. However, other transmission elements may be used. For example, a combination of a circuit that generates magnetism and a magnetic sensing element, a transformer in which a primary winding and a secondary winding are electrically isolated from each other (since a transformer cannot transmit a DC component, for example, original data and complementary data And the like can be used. When the abnormal voltage detection device of the present invention is mounted on an electric vehicle, a photocoupler that is not affected by disturbance such as magnetism is preferably used. More preferably, a photocoupler in which the light emitting diode and the phototransistor are housed in separate packages (not integrated) is used.

  Each cell b1 to bM of the assembled battery 10 may be a chargeable / dischargeable secondary battery other than the nickel-hydrogen battery. For example, you may comprise the assembled battery 10 from the cell of a lead storage battery, a nickel cadmium storage battery, or a lithium ion secondary battery.

  Although the abnormal voltage detection device for the assembled battery according to the above-described embodiment is mounted on an electric vehicle, the abnormal voltage detection device may be mounted on a device other than the electric vehicle that drives the assembled battery as a power source.

  The specific content of the abnormal voltage state of the assembled battery is arbitrary as long as it is detected by the voltage. Typically, the battery block is overcharged or overdischarged. Battery failure and degradation modes may include increased internal resistance and cell short-circuit due to loss of cell life or cell case, but all have the same voltage as overcharge or overdischarge because the voltage is higher or lower than normal cells. It can be detected as a voltage behavior.

  The abnormal voltage detection apparatus for an assembled battery according to the present invention is useful for electric vehicles (PEV), hybrid vehicles (HEV), and electric vehicles such as hybrid vehicles having a fuel cell and a secondary battery.

It is a block diagram which shows schematic structure of the abnormal voltage detection apparatus for assembled batteries which concerns on Embodiment 1 of this invention. It is a circuit diagram of the reference voltage generation circuit R1N of the abnormal voltage detection apparatus for the assembled battery according to the first embodiment of the present invention. It is a flowchart which shows the 1st part of the abnormality detection process performed by the abnormal voltage detection apparatus for assembled batteries of Embodiment 1, 2, 3 of this invention. It is a flowchart which shows the 2nd part of the abnormality detection process performed by the abnormal voltage detection apparatus for assembled batteries of Embodiment 1, 2, 3 of this invention. 4 is a timing chart showing operations of switches S11 to S1N in step S1 of FIG. 3. 4 is a timing chart showing the operation of switches S11 to S1N in step S4 of FIG. 6 is a timing chart showing the operation of switches S11 to S1N in step S9 of FIG. It is a timing chart which shows another operation | movement of switch S11-S1N in step S4 of FIG. 6 is a timing chart showing another operation of the switches S11 to S1N in step S9 of FIG. It is a circuit diagram which shows a part of abnormal voltage detection apparatus for assembled batteries which concerns on the modification of Embodiment 1 of this invention. It is a block diagram which shows schematic structure of the abnormal voltage detection apparatus for assembled batteries which concerns on Embodiment 2 of this invention. It is a block diagram which shows schematic structure of the abnormal voltage detection apparatus for assembled batteries which concerns on Embodiment 3 of this invention. It is a block diagram which shows schematic structure of the abnormal voltage detection apparatus for assembled batteries which concerns on Embodiment 4 of this invention. It is a block diagram which shows schematic structure of the abnormal voltage detection apparatus for assembled batteries which concerns on Embodiment 5 of this invention. It is a block diagram which shows schematic structure of the abnormal voltage detection part which concerns on Embodiment 6 of this invention. It is a block diagram which shows schematic structure of the abnormal voltage detection part which concerns on Embodiment 7 of this invention. It is a block diagram which shows schematic structure of the abnormal voltage detection apparatus for assembled batteries which concerns on Embodiment 8 of this invention. It is a flowchart which shows the 1st part of the abnormality detection process performed by the abnormal voltage detection apparatus for assembled batteries of Embodiment 8 of this invention. It is a flowchart which shows the 2nd part of the abnormality detection process performed by the abnormal voltage detection apparatus for assembled batteries of Embodiment 8 of this invention.

Explanation of symbols

10 ... assembled battery,
11 ... Relay,
12 ... Inverter 13 ... Motor generator,
41 to 4N: voltage drop circuit,
100, 300, 400, 500, 1000, 1300 ... abnormal voltage detection device,
101 to 10 N, 301 to 30 N, 401 to 40 N, 60 n, 70 n, 1301 to 130 N, an abnormal voltage detector,
111, 112, 113, 511, 512, 513, 1013 ... level conversion circuit,
150, 450, 550 ... control unit,
151. Switch control unit,
152 ... display section,
153 ... Relay drive unit,
454 ... Voltage drop circuit control unit,
502 ... Serial input / parallel output register,
503: Clock oscillator,
A1 to AN, A11 to AN1, A12 to AN2, A13 to AN3,... Reference voltage source,
C1 to CN: comparators
D1 to DN, D61n, D71n ... voltage dividing circuit,
L2 to LN, L300 to LN00 ... booster circuit,
P1 to PN, P11, P12, P13, PD ... photocoupler,
R11 to R1N, R31 to R3N ... reference voltage generation circuit,
S11-S1N, S31-S3N, S41-S4N, 63n ... switch,
721 ... constant voltage source,
722 ... Constant current source.

Claims (15)

In an abnormality detection device for detecting a voltage abnormality of an assembled battery configured by connecting a plurality of battery blocks composed of at least one secondary battery in series,
The battery measurement voltage, which is the voltage of each battery block or the voltage dropped from the voltage of each battery block, is compared with a predetermined reference voltage to detect whether the voltage is abnormal, and the detection result Each of the abnormality detection signals including the information of the above is generated, and based on the plurality of abnormality detection signals, a time ratio of the time when the assembled battery is in a voltage abnormal state with respect to a predetermined time period is calculated, and the temporal An abnormal voltage detection device for an assembled battery, comprising: detecting means for detecting an abnormal voltage of the assembled battery based on a ratio.   2. The abnormal voltage detection according to claim 1, wherein the detection means compares each battery measurement voltage, which is a voltage of each battery block or a voltage dropped from the voltage of each battery block, with a plurality of reference voltages. apparatus.   3. The abnormal voltage detection device according to claim 2, wherein the detection means divides the voltage of each battery block by a constant voltage source to generate each battery measurement voltage.   2. The abnormal voltage detection device according to claim 1, wherein the detection means compares each battery measurement voltage, which is a plurality of voltages dropped from the voltage of each battery block, with the reference voltage. The voltage abnormality state is a state in which the battery measurement voltage of at least one of the battery blocks is higher than the reference voltage,
The detecting means compares the measured voltage of each battery with a first reference voltage and detects a voltage abnormality of the assembled battery, and compares the detected voltage with a second reference voltage higher than the first reference voltage. The abnormal voltage detection device according to claim 2, wherein a voltage abnormality of the assembled battery is detected.   The detection means compares the measured voltage of each battery with the second reference voltage, and detects a voltage abnormality of the assembled battery, and compares it with a third reference voltage higher than the second reference voltage. The abnormal voltage detection device according to claim 5, wherein a voltage abnormality of the assembled battery is detected. The state of the voltage abnormality is a state in which the battery measurement voltage of at least one of the battery blocks is lower than the reference voltage,
The detection means compares each battery measurement voltage with a first reference voltage and detects a voltage abnormality of the assembled battery, and compares it with a second reference voltage lower than the first reference voltage. 4. The abnormal voltage detection apparatus according to claim 2, wherein a voltage abnormality of the assembled battery is detected.   The detection means compares each battery measurement voltage with the second reference voltage and detects a voltage abnormality of the assembled battery, and compares the voltage with a third reference voltage lower than the second reference voltage. The abnormal voltage detection device according to claim 7, wherein a voltage abnormality of the assembled battery is detected.   The detection means relatively changes one of the battery measurement voltage and the reference voltage of each battery block, and compares the battery measurement voltage with the reference voltage to generate the abnormality detection signal. The assembled battery according to any one of claims 1 to 8, wherein the assembled battery detects whether or not the detection unit functions normally based on each of the plurality of abnormality detection signals. Abnormal voltage detection device for. The detecting means is
A voltage change circuit for relatively changing any one of the battery measurement voltage and the reference voltage of each battery block;
A signal generator for generating a serial signal including a control signal for controlling the operation of the voltage change circuit;
A serial / parallel converter for converting the serial signal into a parallel signal;
A voltage level of at least one control signal of the parallel signals is converted into a conversion voltage level that is a voltage level of each battery block by using a voltage difference between terminals of the transistors, and the voltage change is used as the control signal. The abnormal voltage detection device according to claim 9, further comprising a level conversion circuit that outputs to the circuit. The voltage level of the parallel signal includes the negative terminal voltage of the assembled battery,
The level conversion circuit boosts the voltage level of the parallel signal step by step by the unit voltage using the voltage between the terminals of the battery block as a unit voltage, and converts the voltage level to the conversion voltage level. The abnormal voltage detection device according to claim 10. The voltage level of the parallel signal includes the voltage level of the negative terminal of the assembled battery,
The level conversion circuit is
The voltage level of the parallel signal related to the first battery block among the plurality of battery blocks is converted to the converted voltage level by boosting the voltage between the terminals of the battery block as a unit voltage by the unit voltage. 1 booster circuit;
And a second booster circuit that boosts the voltage level of the parallel signal related to the second battery block of the plurality of battery blocks by the plurality of unit voltages and converts the voltage level to the converted voltage level. The abnormal voltage detection device according to claim 10. The level conversion circuit is
A third booster that boosts the voltage level of the parallel signal related to the third battery block of the plurality of battery blocks by the unit voltage, and then boosts the voltage level by the unit voltage and converts it to the converted voltage level. The abnormal voltage detection device for an assembled battery according to claim 12, further comprising a circuit. The serial signal includes a start bit at the beginning,
The serial / parallel converter automatically starts an internal oscillator based on the start bit, and reads the serial signal from the signal generator using a predetermined clock output from the internal oscillator. The abnormal voltage detection device according to claim 10. The detecting means is
A first transmission element that transmits the plurality of abnormality detection signals in an electrically insulated state;
15. The apparatus according to claim 10, further comprising a second transmission element that transmits the serial signal to the serial / parallel converter in an electrically insulated state. Abnormal voltage detection device.

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