JP2006050415A - Image processing apparatus and threshold data storage method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform a dither processing using a plurality of threshold data simultaneously in real time. <P>SOLUTION: An image processing unit 10 comprises an address control section 11, a storage section 12, a comparison section 13, and a threshold control section. The storage section 12 includes memories m<SB>1</SB>, m<SB>2</SB>, m<SB>3</SB>, m<SB>4</SB>. The number of memories is determined in accordance with a form of a compare window applied in dither processing performed by an image processing apparatus 100. Threshold data constructing a threshold matrix are stored in the memories m<SB>1</SB>, m<SB>2</SB>, m<SB>3</SB>, m<SB>4</SB>, so that the threshold data included in a certain compare window are stored in memories different from each other, and that all the threshold data included in the compare window are simultaneously read out in one time of read operation. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for performing dither processing using a threshold matrix.

One method of halftone processing in image processing is the dither method. The dither method assigns a value indicating white or black to each pixel (pixel) of image data having gradation according to a certain rule according to the gradation value (pixel value) of the pixel. (This is called “binarization”) is a method of reproducing halftones in a pseudo manner (see, for example, Patent Document 1). Halftone processing performed using the dither method is called dither processing.
There are several types of dithering. Among them, the systematic dither method is to binarize each pixel of image data using a threshold matrix. The threshold matrix is a plurality of threshold data arranged in a matrix, and each threshold data is compared with the pixel value of each pixel of the input image data.

FIG. 24 is a diagram illustrating a threshold matrix M ₁ that is an example of the threshold matrix. In the figure, the threshold matrix M ₁ is represented by a plurality of threshold data arranged in 5 rows and 11 columns. For convenience of explanation, numbers “1” to “55” are sequentially assigned to the respective threshold data from the top of the first row.
Each threshold data has 8 bits, that is, any value from 0 to 255, and this value is compared with the pixel value (8 bits) of each pixel of the input image data. Binarization is performed in such a manner that pixels larger than the threshold data are white, and other pixels are black. Then, by continuously arranging such threshold matrixes, dither processing is performed on image data of various sizes. For example, when dither processing is performed on 32 × 32 (pixel) image data, binarization is performed based on the threshold matrix M ₁ arranged as shown in FIG. In the figure, the adjacent upper and lower threshold matrixes M ₁ are arranged so as to be shifted by two pixels. The process of making the positions of the upper and lower threshold matrices different in this way is called “shift processing”. Here, since the adjacent upper and lower threshold matrixes are shifted by 2 pixels, such a shift process is referred to as a “shift process in which the number of shift settings is 2.”

  FIG. 26 is a block diagram illustrating a configuration of a general image processing apparatus 300 that performs dither processing. As shown in the figure, the image processing unit 30 includes a storage unit 32 for storing a threshold matrix and a memory address (hereinafter also simply referred to as “address”) for reading threshold data of the threshold matrix. 32 is provided with an address control unit 31 that is designated with respect to 32, and a comparison unit 33 that binarizes the input image data by comparing it with threshold data. A CPU (Central Processing Unit) 11 controls operations of the above-described units. A ROM (Read Only Memory) 12 stores a program PRG3 describing a procedure for the image processing apparatus 300 to execute image processing.

In general, in the image processing apparatus, threshold data is read at a timing corresponding to the clock frequency of the CPU, and dither processing is sequentially performed on the input image data. Dither processing may be performed using the threshold data. For example, when dither processing is performed on image data with an input resolution of 600 × 600 (dpi) at an output resolution of 2400 × 600 (dpi), it is quadrupled in the main scanning (horizontal) direction and in the sub-scanning (vertical) direction. It is converted to 1x resolution. Therefore, 4 × 1 (pixel) threshold data is required for one input pixel. This will be described by taking the threshold value matrix M ₁ of FIG. 24 as an example. A certain pixel is binarized by four threshold data of numbers “1”, “2”, “3”, “4”, and four pixels Is output as Then, the next pixel following the above-described pixel is binarized with four threshold data with numbers “5”, “6”, “7”, and “8”, and the same processing is performed thereafter. .

  As described above, when dither processing is performed using a plurality of threshold data at the same time, in order to process the dither processing in real time, threshold data for four pixels must be simultaneously read and binarized. However, in the technique described in Patent Document 1 described above, since one threshold value data is stored in the memory area for one word, there is a problem that it takes time to read the threshold data. That is, in the technique described in Patent Document 1, only one threshold value data can be read out in one clock cycle that is a data reading cycle, and four clock cycles are required to read out threshold data for four pixels. . Accordingly, the processing time per pixel is increased, making it difficult to perform dither processing in real time.

Japanese Patent Laid-Open No. 4-205675

  The present invention has been made in view of such circumstances, and an object thereof is to provide an image processing apparatus capable of performing dither processing at a higher speed than in the past.

In order to achieve the above object, the present invention extracts threshold data of N rows and M columns in a threshold matrix as a compare window, and compares the threshold data included in the extracted compare window with pixel values of image data. An (M × N) memory in which the threshold data is stored, and by reading the threshold data one by one from each of these memories, Storage means for reading out (M × N) threshold data for each read cycle, address control means for specifying a memory address for each of the memories, and the storage means read according to the specified memory address (M And (N ×) threshold values included in a single compare window. The data is stored in (M × N) memories separately, and the address control means stores memory addresses in which (M × N) threshold data included in the compare window are stored. Is provided for each of (M × N) memories.
According to such an image processing apparatus, threshold data included in the compare window can be read out by a single read operation, so that dither processing can be performed at high speed.

  In the image processing apparatus of the present invention, as a more preferable aspect, when N ≧ 2, the (M × N) memories are divided into N groups, and k ( Threshold data from the beginning to the end of the i-th (1 ≦ i <N) row in the threshold matrix are alternately stored in the M memories belonging to the 1 ≦ k <N) th group. (M−1) threshold data that are consecutive from the first threshold data of i rows are stored, and M memories belonging to the (k + 1) th group are stored in the (i + 1) th row in the threshold matrix. Threshold data from the beginning to the end are alternately stored, and (M−1) pieces of threshold data that are continuous from the beginning threshold data in the (i + 1) th row are stored.

Further, when N = 2 and the number of rows of the threshold matrix is not divisible by N, the memory of a group different from the group storing the threshold data of the last row in the threshold matrix is stored in the memory. The threshold data of the first row of the threshold matrix is stored.
Alternatively, when N ≧ 3 and the number of rows of the threshold matrix is not divisible by N, the memory in a group different from the group storing the threshold data of the last row in the threshold matrix The threshold data of the first to (N-1) th rows of the threshold matrix are stored so as to be in different groups.
In this way, even when the compare window has a plurality of rows and spans a plurality of threshold matrixes, the threshold data included in the compare window can be read out by a single read operation.

In these cases, as a more preferable aspect, the storage means can determine the threshold data of the first row stored in a memory of a group different from the group storing the threshold data of the last row. The shift number is shifted and stored.
Alternatively, the storage means shifts and stores the threshold data of the first row to the (N−1) th row by a predetermined shift number.
In this way, the address calculation can be performed more easily when the compare window has a plurality of rows and spans a plurality of threshold matrixes.

In a more preferred aspect of the image processing apparatus of the present invention, the storage unit stores the threshold data at the head of each row of the threshold matrix in the same memory.
In this way, the address calculation for reading out the threshold data of each row of the threshold matrix is shared, and the address calculation can be performed more easily.

  The present invention is a data storage method in which a storage unit including a plurality of memories stores threshold data representing a threshold matrix used in dither processing, and the storage unit has (M × N) memories. It is also possible to provide a data storage method for separately storing N rows and M columns of threshold data that are continuous in the threshold matrix.

  The present inventors have conceived the image processing apparatus 200 having the configuration of FIG. 1 as a solution to the above-described problem. This image processing apparatus 200 shows a case where threshold data for 4 × 1 (pixels) is simultaneously dithered for one input pixel, that is, a case where the resolution in the main scanning direction is quadrupled in the dither processing. ing. A collection of threshold data that is simultaneously dithered at one timing is hereinafter referred to as a “compare window”. That is, the image processing apparatus 200 extracts a compare window from the threshold matrix, compares the threshold data included in the extracted compare window with the pixel value of the image data, and performs halftone processing. In the following, components having the same functions as those shown in FIGS. 24 to 26 are denoted by the same reference numerals, and description thereof is omitted as appropriate.

The image processing apparatus 200 includes an image processing unit 20 having an address control unit 21, a storage unit 22, a comparison unit 23, and a threshold control unit 24, and the CPU 1 executes a program PRG2 stored in the ROM 2. Is controlled by The function of the image processing unit 20 is realized by, for example, an ASIC (Application Specific Integrated Circuit). The address control unit 21 and the comparison unit 23 have substantially the same functions as the address control unit 31 and the comparison unit 33 of the image processing apparatus 300, respectively. The threshold control unit 24 buffers the threshold data read from the storage unit 22 in the buffer 241, and performs data processing such as barrel shift as necessary. The storage unit 22 includes a memory m such as a RAM (Random Access Memory), and stores threshold data constituting a threshold matrix in the memory m. Here, the method in which the storage unit 22 stores the threshold value matrix is different from that in the storage unit 32 of the image processing apparatus 300. Hereinafter, a case where the storage unit 22 stores threshold data constituting the threshold matrix M ₁ of FIG. 24 will be described as an example.

FIG. 2 is a schematic diagram showing a configuration of the memory m, and FIG. 3 is a schematic diagram showing a state where a threshold matrix M ₁ is stored in the memory m. In FIG. 2, lattice-like areas to which symbols mb _{1 to} mb ₆₄ are assigned indicate memory blocks, and 0 to 1 threshold data is stored in each memory block. The storage capacity of each memory block is 8 bits. Further, in FIG. 3, the numbers shown on the memory block mean numbers assigned to the threshold data. In order to distinguish between the memory block number and the threshold data number, in the following drawings, the memory block number is shown in italics. In the following explanation, "1", "2", ..., the threshold data number is assigned in the "n" respectively th _1, th _2, ..., specified as that th _n.

The memory m has a configuration of 32 bits × 16 words. In other words, the memory area per word of the memory m is 32 bits, and four threshold data of 8 bits per word are stored. In addition, addresses are defined in units of words in the memory m. In FIG. 2, the memory areas indicated by the memory blocks mb _{1 to} mb ₄ are address 0, and the memory areas indicated by the memory blocks mb _{5 to} mb ₈ are indicated. Address 1 is defined, and address 15 is defined in the same manner. Here, the number of memory blocks per word matches the resolution magnification in the main scanning direction in the dither processing. In this example, since the resolution in the main scanning direction is four times, the number of memory blocks per word is four.

Further, threshold data is stored in the memory m so that the head of each row of the threshold matrix M ₁ coincides with the word boundary. That is, the threshold data th ₁ , th ₁₂ , th ₂₃ , th ₃₄ and th _{45 which} are the heads of the respective rows of the threshold matrix M ₁ are stored in the top memory blocks of the addresses 0, 3, 7, 11 and 15 respectively. Yes. Then, following the portion corresponding to the end of the threshold data of each row of the threshold matrix M ₁ , the threshold data from the top of the row is stored in the memory area until the word boundary is reached.
When the threshold data is stored in the memory m as described above, for example, when the address control unit 21 designates the address 0, the threshold data th ₁ , th ₂ , th ₃ and th ₄ are simultaneously read from the memory m of the storage unit 22. Thus, a plurality of threshold data can be read out by a single read operation. That is, a plurality of threshold data can be read simultaneously in one clock cycle.

However, it has been found that the image processing apparatus 200 has some problems.
The image processing apparatus 200 can read a plurality of threshold data at the same time, but may not be able to read all the threshold data necessary for one dither process in one reading operation. For example, when performing dither processing in units of the compare window shown in Fig. 4 using the threshold matrix M ₁ is a compare window cw _1, cw _2, the threshold data for cw _3, addresses of the memory m in FIG. 3 0, By reading from each of the memory areas 1 and 2, it is possible to read all the threshold data necessary for one read operation. However, when dither processing is performed in the compare window cw ₄ , the memory address (address 0) in which the threshold data th ₂ , th ₃ , th ₄ are stored and the memory address (address 1) in which the threshold data th ₅ are stored Therefore, all the threshold data cannot be read out by one read operation. This is because data cannot be read simultaneously from two memory addresses in one memory. Therefore, when the image processing unit 20 of the image processing apparatus 200 performs this dither processing, the threshold value data at the address 0 read out by one clock cycle before is buffered in the threshold value control unit 24, and then It is necessary to form a compare window in combination with the threshold value data of address 1 to be read. Therefore, the image processing unit 20 cannot perform the operation of switching the threshold matrix every clock cycle, and when it is desired to use a plurality of threshold matrices, the image processing apparatus 200 has as many images as the number of threshold matrices. There is a problem that the processing unit 20 is required.

  In addition, the image processing apparatus 200 also has a problem that the configuration of the image processing unit 20 becomes complicated when trying to support a plurality of output resolution patterns. For example, the above is an example of outputting image data with an input resolution of 600 × 600 (dpi) at an output resolution of 2400 × 600 (dpi), and the compare window at this time is a threshold value for 4 × 1 pixels. Although it is represented by a set of data, this is a case where image data having the same input resolution is output at an output resolution of 1200 × 1200 (dpi), the compare window at this time is a set of threshold data for 2 × 2 pixels. Will be represented. Then, since the buffering patterns in the threshold control unit 24 of the image processing unit 20 are different, the circuit scale of the threshold control unit 24 must be increased in order to cope with both output resolutions. Furthermore, since the buffer writing / reading timing also changes with the change in output resolution, there arises a problem that the pipeline delay changes.

In order to solve these problems, the present inventors have invented an image processing apparatus shown below. Hereinafter, an image processing apparatus according to the present invention will be described in detail with reference to the above-described image processing apparatuses 200 and 300 as appropriate.
In the image processing apparatus of the present invention, the threshold matrix storage method and the specific operation differ depending on the shape of the compare window. Therefore, here, the case where the compare window is a set of threshold data for 4 × 1 pixels (first embodiment) and the case where the compare window is a set of threshold data for 2 × 2 pixels (second embodiment) is implemented. As an example.

(1) Configuration of First Embodiment (1-1) FIG. 5 is a block diagram showing a configuration of an image processing apparatus 100 according to the first embodiment of the present invention. As shown in FIG. 1, the image processing apparatus 100 includes an image processing unit 10, a CPU 1, and a ROM 2. The CPU 1 executes a program PRG1 stored in the ROM 2 to perform image processing to be described later. Is called.
The image processing unit 10 includes an address control unit 11, a storage unit 12, a comparison unit 13, and a threshold control unit 14. The storage unit 12 includes a plurality of memories m ₁ , m ₂ , m ₃ and m ₄ such as RAM (Random Access Memory), for example, and stores threshold data constituting a threshold matrix inside these memories. The address control unit 11 designates a memory address for reading out the threshold data for each memory in the storage unit 12. The threshold control unit 14 performs barrel shift on the threshold data read from the storage unit 12 as necessary. The comparison unit 13 has substantially the same function as the comparison unit 33 of FIG.

The image processing apparatus 100 is characterized by the aspect of the storage unit 12 that stores threshold data. In the following, an example in which the storage unit 12 stores threshold data constituting the threshold matrix M ₁ in FIG. 24 will be described.
FIG. 6 is a schematic diagram showing the memories m ₁ , m ₂ , m ₃ and m ₄ of the storage unit 12. In the figure, a memory _{m 1, m 2, m 3} , the memory areas each memory block mb1 address 0 of _{m 4 1, mb2 1, mb3} 1, mb4 1, each of memory blocks of memory area of the address 1 mb1 ₂ , mb2 ₂ , mb3 ₂ , mb4 _2, and the memory area up to the address 31 is defined in the same manner.
As shown in the figure, the memories m _{1 to} m ₄ have a configuration of 8 bits × 32 words. That is, the memory area per word of each memory is 8 bits, and one threshold value data of 8 bits per word is stored.

FIG. 7 is a schematic diagram showing a state in which threshold data constituting the threshold matrix M ₁ is stored in the memories m ₁ , m ₂ , m ₃ and m ₄ shown in FIG. As shown in the figure, threshold data of the first row of the threshold matrix M ₁ are stored in order from the memory m ₁ to the address 0 of the memory m ₄ . The threshold data that is continuous with the threshold data stored at an address in the memory m ₄ is stored in the memory m ₁ at the next address. For example, the memory block m ₄ address 0 (the memory block MB4 _1), and the threshold data th ₄ is stored, the threshold data th ₅ memory blocks m ₁ of address 1 (memory block contiguous to the threshold data mb1 ₂ ) is remembered.
Then, only “3” threshold data from the head of the row is stored so as to follow the threshold data at the end of each row of the threshold matrix M ₁ . For example, the threshold value data th ₁ at the end of the first row of the threshold matrix is stored in the memory block m _{3 at} the address 2 (memory block mb3 ₃ ), and _three threshold data th from the beginning of the first row are further stored. _The memory blocks mb4 ₃ , mb1 ₄ , and mb2 ₄ are stored so that ₁ , th ₂ , and th ₃ are continuous. As such state continues, the threshold data of each row of the threshold matrix M ₁ is stored sequentially. Note that no memory is stored in the memory area in which the threshold data is not stored, that is, the memory blocks after the address 18 of the memories m ₁ and m ₂ and the memory block after the address 17 of the memories m ₃ and m ₄ , and blank ( (Blank).

(1-2) Operation Based on the configuration described above, the image processing apparatus 100 according to the present embodiment performs dither processing. Specifically, the address control unit 11 of the image processing unit 1 specifies the address of the threshold data read from the storage unit 12, and the threshold control unit 14 performs barrel shift on the read threshold data as necessary. The comparison unit 13 compares this with each pixel of the input image data to perform dither processing. As described above, the image processing apparatus 100 has a feature in a mode of storing threshold data, stores the threshold data in a mode as shown in FIG. 7, and is designated by the address control unit 11 from here. By reading out the threshold data, dither processing can be performed at a higher speed than before. Hereinafter, a read operation of threshold data stored in the storage unit 12 will be described in detail.

FIG. 8 is a diagram showing a compare window applied to reading threshold data in the present embodiment. Here, how the threshold data is actually read from the memory when the dither process is performed using the compare windows cw _{1 to} cw ₅ will be described with reference to the drawings.

FIG. 9 is a diagram for explaining a read operation from the memory when dither processing is performed using the compare windows cw ₁ , cw _2, and cw ₃ . First, as shown in FIG. 8, the threshold data included in the compare window cw ₁ are th ₁ , th ₂ , th ₃ and th ₄ . These threshold data are stored in the memory blocks mb1 ₀ , mb2 ₀ , mb3 ₀ and mb4 ₀ at the address 0 of the memories m ₁ , m ₂ , m ₃ and m ₄ , respectively, as shown in FIG. Yes. Therefore, the address control unit 11 instructs all the memories in the storage unit 12 to read the memory area at the address 0. In response to this instruction, the storage unit 12 can simultaneously read the threshold data th ₁ , th ₂ , th ₃ and th ₄ . This is because in each of the memories m ₁ , m ₂ , m ₃ and m ₄ , only one memory address for reading the threshold data is designated. The read threshold data is supplied from the storage unit 12 to the comparison unit 13 in the order of the memories m ₁ , m ₂ , m ₃ and m ₄ , that is, th ₁ , th ₂ , th ₃ and th ₄ . The comparison unit 13 performs dither processing according to the order in which threshold data is supplied. In this case, since the order in which the threshold data is supplied matches the order of the threshold data represented by the compare window cw ₁ , barrel shift by the threshold control unit 14 is not necessary. Further, in the case of the compare windows cw ₂ and cw ₃ , only the address of the memory block storing the threshold data to be read is different, and the specific operation is the same as in the case of the above-described compare window cw _1. Therefore, the description thereof is omitted.

Next, a case where dither processing is performed using the compare windows cw ₄ and cw ₅ will be described.
FIG. 10 is a diagram for explaining a read operation from the memory when dither processing is performed using the compare windows cw ₄ and cw ₅ . First, as shown in FIG. 8, the threshold data included in the compare window cw ₄ are th ₂ , th ₃ , th ₄ and th ₅ . As shown in FIG. 10, among these threshold data, the threshold data th ₂ , th ₃ and th ₄ are the memory blocks mb2 ₀ , mb3 ₀ and the addresses 0 of the memories m ₂ , m ₃ and m ₄ , respectively. MB4 ₀ to be stored, threshold data th ₅ is stored in the memory block mb1 ₁ of address 1 memory m _1. Therefore, the address control unit 11 instructs the memory m ₁ of the storage unit 12 to read out the memory area at address 1, and the memory area at address 0 for the memories m ₂ , m _3, and m ₄ . Instruct to read. Also in this case, only one memory address for reading the threshold value data is designated in each of the memories m ₁ , m ₂ , m ₃ and m ₄ . Therefore, the threshold data th ₂ , th ₃ , th ₄ and th ₅ are read out simultaneously.

When these threshold data are arranged in the read order (m ₁ , m ₂ , m ₃ , m ₄ ), they become th ₅ , th ₂ , th ₃ , th ₄ . On the other hand, since the dither processing is performed in the order represented by the compare window cw _4, that is, the order of th ₂ , th ₃ , th ₄ , and th ₅ , the reading order of the threshold data is different from the order of the dither processing. Therefore, here, the threshold control unit 14 performs a barrel shift.
FIG. 11 is a diagram for explaining the barrel shift performed by the threshold control unit 14. The threshold control unit 14 shifts the first 8 bits corresponding to the threshold data th ₅ from the data string of the threshold data arranged in the order of th ₅ , th ₂ , th ₃ , th ₄ to the end of this data string. (See FIG. 11 (1)). Then, the data string of the threshold data is arranged in the order of th ₂ , th ₃ , th ₄ , and th ₅ , and the comparison with the image data input in the comparison unit 13 becomes possible.

Next, a case where dither processing is performed using the compare window cw ₅ will be described. As shown in FIG. 8, the threshold data included in the compare window cw ₅ are th ₁₂ , th ₁₃ , th ₁₄ and th ₁₅ . These threshold data, as shown in FIG. 10, stored in the threshold data th _12, th ₁₃ memory m _3, m ₄ address 3 of memory blocks mb3 ₃ respectively, MB4 _3, threshold data th ₁₄ , Th ₁₅ are stored in the memory blocks mb1 ₄ , mb2 ₄ at the address 4 of the memories m ₁ , m ₂ , respectively. Therefore, the address control unit 11 instructs the memories m ₁ and m ₂ of the storage unit 12 to read out the memory area at address 4, and the memory area at address 3 is allocated to the memories m ₃ and m ₄ . Instruct to read. Thereby, the threshold data th ₁₂ , th ₁₃ , th ₁₄ and th ₁₅ are read out simultaneously.

These threshold data are th ₁₄ , th ₁₅ , th ₁₃ , and th ₁₂ when arranged in the order of reading. Since the dither processing is performed in the order represented by the compare window cw ₅ , that is, th ₁₂ , th ₁₃ , th ₁₄ , th ₁₅ , the threshold control unit 14 performs barrel shift here. Specifically, the threshold control unit 14 calculates the first 16 bits corresponding to the threshold data th ₁₄ and th ₁₅ from the data string of threshold data arranged in the order of th ₁₄ , th ₁₅ , th ₁₂ and th _13. A barrel shift is performed so that the last 16 bits corresponding to the threshold data th ₁₂ and th ₁₃ are replaced (see FIG. 11B). Then, the data string of the threshold data is arranged in the order of th ₁₂ , th ₁₃ , th ₁₄ , and th ₁₅ , and the comparison with the image data input in the comparison unit 13 becomes possible.
For other compare windows, the threshold data can be read out in substantially the same manner as in the case of the compare windows cw _{1 to} cw ₅ described above.

As described above, in the image processing apparatus 100 according to the present embodiment, the storage unit includes a plurality of memories, and in consideration of the order and position where the threshold data is arranged in the threshold matrix, these The threshold data is distributed and stored in a plurality of memories. Accordingly, threshold data necessary for one dither process can be read simultaneously in one clock cycle, so that a high-speed dither process can be performed.
Further, according to the image processing apparatus 100 of the present embodiment, threshold data necessary for one dither process can be read at one timing, so that it is not necessary to provide a buffer in the image processing unit 10 and one clock cycle. It is possible to perform an operation of switching the threshold matrix every time. Therefore, even when a plurality of threshold matrixes are used in the dither processing, the memory capacity of the storage unit need only be increased as long as the image processing apparatus 100 is configured. It is not necessary to increase the number of units (as an example, a storage unit 12a storing threshold matrixes M ₁ and M ₂ is shown in FIG. 12). That is, according to the image processing apparatus 100 of the present embodiment, various dither processes can be performed with an inexpensive and simple configuration.

(2) Second Embodiment Next, an embodiment in which the compare window used in the dither processing performed by the image processing apparatus is a set of threshold data for 2 × 2 pixels will be described. The image processing apparatus according to the present embodiment has a configuration similar to that of the image processing apparatus 100 according to the first embodiment described above. Therefore, here, the description will focus on the parts that are different from the image processing apparatus 100 of the first embodiment described above, the same components as those in the image processing apparatus 100 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

(2-1) Configuration FIG. 13 is a block diagram showing the configuration of the image processing apparatus 101 according to the second embodiment of the present invention. As shown in the figure, the image processing apparatus 101 of the present embodiment has the same configuration as the image processing apparatus 100 of the first embodiment described above except for the storage unit 15. The storage unit 15 includes memories m ₁₁ , m ₁₂ , m _21, and m ₂₂ , and stores a threshold matrix inside the memory.
The memories m ₁₁ , m ₁₂ , m ₂₁ and m ₂₂ have a configuration of 8 bits × 32 words, like the memories m ₁ , m ₂ , m ₃ and m ₄ of the image processing apparatus 100. The memory area per word of each memory is 8 bits, and one threshold data of 8 bits per word is stored. In the following description, the memory area at address 0 of the memories m ₁₁ , m ₁₂ , m ₂₁ , and m _{22 is} the memory block mb 11 ₁ , mb 12 ₁ , mb 21 ₁ , mb 22 ₁ , and the memory area at the address 1 is the memory block mb 11, respectively. ₂ , mb12 ₂ , mb21 ₂ , mb22 ₂ and so on up to address 31 in the same manner.

Further, for convenience of explanation, in this embodiment, the memories m ₁₁ and m ₁₂ are considered as group 1, and the memories m ₂₁ and m ₂₂ are considered as group 2, so that the memories are divided into two groups. This is because the aspect of the threshold data matrix stored in the memory can be understood more easily. Hereinafter, as an example, it is assumed that threshold data stored in the memory of the storage unit 15 is threshold data constituting the threshold matrix M ₁ in FIG.

FIG. 14 is a schematic diagram showing a state in which threshold data is stored in the memories m ₁₁ , m ₁₂ , m ₃₁ and m ₂₂ . In the figure, the number written in each memory block indicates the threshold data number.
As shown in the figure, the threshold data of the first row of the threshold matrix M ₁ are stored in order from address 0 to address 5 of the memories m ₁₁ and m ₁₂ of the group 1, and the threshold data of the second row is stored. The addresses are stored in order from address 0 to address 5 of the memories m ₂₁ and m ₂₂ of group 2. The threshold data of the third row is stored in order from address 6 to address 11 of the memories m ₁₁ and m ₁₂ of the group 1 so as to follow the threshold data of the first row. The threshold data of the fourth row and the fifth row are stored in order from the address 6 to the address 11 of the memories m ₂₁ and m ₂₂ of the group 2 and from the address 12 to the address 17 of the memories m ₁₁ and m ₁₂ of the group 1, respectively. ing. Further, the threshold data of the first row are stored in the same way as described above at addresses 12 to 17 of the memories m ₂₁ and m ₂₂ of the group 2. Incidentally, to follow the threshold data of the last row of the threshold matrix M _1, (see for example, the memory block MB12 _6, MB22 ₆ and MB12 ₁₂₎ to "1" number only is stored threshold data from the beginning of the line. Further, no data is stored in a memory area where threshold data is not stored, that is, a memory block after the address 18 of the memories m _{11 to} m ₂₂ , and remains blank (blank).

(2-2) Operation With the configuration described above, the image processing apparatus 101 according to the present embodiment performs dither processing. Specifically, the address control unit 11 of the image processing unit 1 specifies the address of the threshold data read from the storage unit 15, and the threshold control unit 14 performs a barrel shift on the read threshold data as necessary. The comparison unit 13 compares this with each pixel of the input image data to perform dither processing. From here, the reading operation of the threshold data stored in the storage unit 15 will be described in detail.

FIG. 15 is a diagram showing a compare window applied to reading of threshold data in the present embodiment. Here, how the threshold data is actually read from the memory when the dither process is performed using the compare windows cw _{1 to} cw ₁₀ will be described with reference to the drawings.

FIG. 16 is a diagram for explaining a read operation from the memory when dither processing is performed using the compare windows cw _{1 to} cw ₆ and cw ₈ . First, as shown in FIG. 15, the threshold data included in the compare window cw ₁ are th ₁ , th ₂ , th ₁₂ and th ₁₃ . These threshold data are stored in the memory blocks mb11 ₁ , mb12 ₁ , mb21 ₁ and mb22 ₁ at the address 0 of the memories m ₁₁ , m ₁₂ , m ₂₁ and m ₂₂ , respectively, as shown in FIG. Yes. Therefore, the address control unit 11 transmits an instruction to read the memory area at the address 0 to all the memories in the storage unit 15. Thereby, the threshold data th ₁ , th ₂ , th ₁₂ and th ₁₃ are read out simultaneously. The read threshold data is sent to the comparison unit 13 in the order of the memories m ₁₁ , m ₁₂ , m ₂₁ , m ₂₂ , that is, th ₁ , th ₂ , th ₁₂ and th _13. By being supplied, dither processing is performed in the order represented by the compare window cw ₁ . Therefore, in this case, barrel shift by the threshold control unit 14 is not necessary. In the case of the compare windows cw _{2 to} cw ₆ and cw ₈ , only the addresses of the memory blocks that store the threshold data to be read are different from the addresses 1 to 5 and 6, respectively. Since this is the same as in the case of the window cw ₁ , the description thereof is omitted.

Next, a case where dither processing is performed using the compare window cw ₇ will be described.
FIG. 17 is a diagram for explaining a read operation from the memory when dither processing is performed using the compare windows cw ₇ and cw ₉ . As shown in FIG. 15, the threshold data included in the compare window cw ₇ are th ₂ , th ₃ , th ₁₃ and th ₁₄ . As shown in FIG. 17, the threshold data th ₂ is stored in the memory block mb12 ₁ at the address 0 of the memory m _{12 in} the group 1 and the threshold data th ₃ is stored in the memory m _{11 in the} group 1 as shown in FIG. Is stored in the memory block mb11 ₂ of the address 1 of FIG. The threshold data th ₁₃ is stored in the memory block MB22 ₁ address 0 of the memory m ₂₂ Group 2, the threshold data th ₁₄ is stored in the memory block MB21 ₂ of address 1 of the memory m ₂₁ Group 2. Therefore, the address control unit 11 transmits an instruction to read the memory area of the address 0 to the memories m ₁₂ and m ₂₂ of the storage unit 15, and the memory of the address 1 to the memories m ₁₁ and m ₂₁ . An instruction to read the area is transmitted. Thereby, the threshold data th ₂ , th ₃ , th ₁₃ and th ₁₄ are read out simultaneously.

These threshold data become th ₃ , th ₂ , th ₁₄ , th ₁₃ when arranged in the order of reading (m ₁₁ , m ₁₂ , m ₂₁ , m ₂₂ ). Since the dither processing is performed in the order represented by the compare window cw ₇ , that is, th ₂ , th ₃ , th ₁₃ , and th ₁₄ , the threshold control unit 14 performs a barrel shift here.
FIG. 18 is a diagram for explaining the barrel shift performed by the threshold control unit 14. The threshold control unit 14 corresponds to the 8-bit data corresponding to the threshold data th ₃ and the threshold data th ₂ with respect to the data string of the threshold data arranged in order of th ₃ , th ₂ , th ₁₄ , th _13. The 8-bit data corresponding to the threshold data th ₁₄ and the 8-bit data corresponding to the threshold data th ₁₃ are simultaneously replaced (see FIG. 18 (1)). . Then, the data string of the threshold data is arranged in the order of th ₂ , th ₃ , th ₁₃ , th ₁₄ , and the comparison with the image data input in the comparison unit 13 becomes possible.

Next, a case where dither processing is performed using the compare window cw ₉ will be described. As shown in FIG. 15, the threshold data included in the compare window cw ₉ are th ₄₅ , th ₄₆ , th ₃ and th ₄ . These threshold data, as shown in Figure 17, is stored in the memory block MB11 _13, MB12 ₁₃ threshold data th _45, th ₄₆ memory m ₁₁ each group 1, m ₁₂ address 12, the threshold value Data th ₃ and th ₄ are stored in the memory blocks mb21 ₁₄ and mb22 ₁₄ of the address 13 of the memories m ₂₁ and m ₂₂ of the group 2, respectively. Therefore, the address control unit 11 transmits an instruction to read the memory area of the address 12 to the memories m ₁₁ and m ₁₂ of the storage unit 15 and the memory of the address 13 to the memories m ₂₁ and m ₂₂ . An instruction to read the area is transmitted. Thereby, the threshold data th ₄₅ , th ₄₆ , th ₃ and th ₄ are read out simultaneously. The read threshold data is supplied to the comparison unit 13 in the order of the memories m ₁₁ , m ₁₂ , m ₂₁ , m ₂₂ , that is, th ₄₅ , th ₄₆ , th _3, and th _4. dither processing is performed in the order represented by the cw _9. Therefore, in this case, barrel shift by the threshold control unit 14 is not necessary.

Next, a case where dither processing is performed using the compare window cw ₁₀ will be described.
19, in the case of performing the dither processing using the compare window cw _10, is a diagram for explaining a read operation from the memory. As shown in FIG. 15, the threshold data included in the compare window cw ₁₀ are th ₁₃ , th ₁₄ , th ₂₄ and th ₂₅ . These threshold data, as shown in Figure 19, the threshold data th ₁₃ is stored in the memory block MB22 ₁ address 0 of the memory m ₂₂ of group 2, memory m ₂₁ threshold data th ₁₄ Group 2 Are stored in the memory block mb21 ₂ at address 1. Further, the threshold data th ₂₄ is stored in the memory block mb12 ₇ at the address 6 of the memory m _{12 in} the group 1, and the threshold data th ₂₅ is stored in the memory block mb 11 ₈ at the address 7 in the memory m ₁₁ of the group 1. Therefore, the address control unit 11 has an address 0 for the memory m _{22 in} the storage unit 15, an address 1 for the memory m ₂₁ , an address 6 for the memory m ₁₂ , and an address for the memory m ₁₁ . 7 is transmitted to read the memory area. Thereby, the threshold data th ₁₃ , th ₁₄ , th ₂₄ and th ₂₅ are read out simultaneously.

These threshold data become th ₂₅ , th ₂₄ , th ₁₄ , th ₁₃ when arranged in the order of reading (m ₁₁ , m ₁₂ , m ₂₁ , m ₂₂ ). Since the dither processing is performed in the order represented by the compare window cw ₁₀ , that is, th ₁₃ , th ₁₄ , th ₂₄ , and th ₂₅ , the threshold control unit 14 performs a barrel shift here. First, the threshold control unit 14, th _25, th _24, th _14, th against ₁₃ data string of threshold data are arranged in the order of the threshold data th of 8 bits corresponding to the ₁₄ data and the threshold data th ₁₃ 8 bits of data corresponding to the threshold data th ₂₅ and 8 bits of data corresponding to the threshold data th ₂₄ are simultaneously replaced (FIG. 18 (2)). reference). After that, the threshold control unit 14 extracts the first 16 bits corresponding to the threshold data th ₂₄ and th ₂₅ and the threshold data th from the threshold data row arranged in the order of th ₂₄ , th ₂₅ , th ₁₃ and th _14. Barrel shift is performed so as to replace the last 16 bits corresponding to ₁₃ and th ₁₄ (see FIG. 18 (3)). Then, the data string of the threshold data is arranged in the order of th ₁₃ , th ₁₄ , th ₂₄ , and th ₂₅ , and the comparison with the image data input in the comparison unit 13 is possible.
For other compare windows, the threshold data can be read out in substantially the same manner as in the case of the compare windows cw _{1 to} cw ₁₀ described above.

As described above, according to the image processing apparatus 101 of the present embodiment, threshold data necessary for one dither process can be simultaneously read in one clock cycle, as in the first embodiment. Similar to the image processing apparatus 100 of the first embodiment described above, it is possible to perform various dither processes at a high speed while having an inexpensive and simple configuration.
Also in the image processing apparatus 101 according to the present embodiment, as in the case of the image processing apparatus 100 according to the first embodiment, a plurality of addresses are not designated in the same memory, so that threshold data is buffered. There is no need to do. Therefore, even if the output resolution in the dither processing becomes a plurality of patterns in this way, pipeline delay does not occur.

(3) Threshold Data Storage Method As described in the first and second embodiments, the image processing apparatus according to the present invention is characterized by the threshold matrix storage method. The threshold matrix storage method is not limited to the method shown in the first and second embodiments described above, and the present invention can be applied even when any compare window of any threshold matrix is applied in dither processing. The method can be applied. Therefore, here, a method of storing the threshold matrix will be generalized and described.

First, the number of memories required in the image processing apparatus is determined by the size of the compare window applied in the dither processing. Here, if the number of pixels in the main scanning direction of the compare window is M and the number of pixels in the sub-scanning direction is N, the compare window is a set of threshold data of N rows and M columns. × N ”. In the first and second embodiments described above, each of the compare windows is represented by 4 × 1 (= 4) and 2 × 2 (= 4) pixels, and thus all use four memories.
In the second embodiment, the memory is divided into two groups, but the number of groups in this grouping is also determined by the size of the compare window applied in the dither process. That is, here, the number of groups is represented by the number of pixels N in the sub-scanning direction of the compare window. In the second embodiment, since the number of pixels in the sub-scanning direction of the compare window is “2”, the memory is divided into “2” groups. In the first embodiment, the number of pixels in the sub-scanning direction of the compare window is “1”, and it is not necessary to perform grouping. Therefore, the description has been given without particularly showing the concept of grouping.

Next, a specific arrangement (that is, storage) procedure of threshold data will be described.
The arrangement of the threshold data is performed based on the group unit described above. That is, the threshold data of the i-th (1 ≦ i <N) row of the threshold matrix are alternately arranged in a plurality of memories in the same group, and when another group exists, the threshold value of the (i + 1) -th row. The data is arranged in a memory of a group different from the group in which the threshold data of the i-th row is arranged. Therefore, in the second embodiment, the threshold data in the first row of the threshold matrix is group 1, the threshold data in the second row is group 2, the threshold data in the third row is group 1, and so on. The two rows of threshold data are alternately arranged so as not to be continuous in the same group. In short, when the value of N in the compare window of N rows and M columns is 2 or more, the threshold data of the i-th row on the threshold mat risk and the threshold data of the (i + 1) -th row are stored in the same memory. Since these threshold data may not be read simultaneously, the threshold data of two consecutive rows are stored in memories of different groups (k-th group and k + 1-th group; 1 ≦ k <N). That is why.

As described above, the threshold data of each row of the threshold matrix is arranged. At this time, after all the threshold data is arranged for each row, the threshold data corresponding to the head portion of each row is redundantly added and arranged. To do. The redundant threshold data corresponds to threshold data of the memory blocks mb4 ₃ , mb1 ₄ , mb2 _{4 and the} like in the first embodiment described above (see FIG. 7), and in the second embodiment. The threshold data of the memory blocks mb12 ₆ , mb22 ₆ , mb12 ₁₂ etc. correspond to this (see FIG. 14).
As described above, the threshold data is arranged redundantly when the compare window extends over a plurality of threshold matrixes (for example, the compare window cw _{3 in} the first embodiment and the compare window cw ₆ in the second embodiment). In such a case) contributes to speeding up the read operation. For example, if there is no redundantly added threshold data in the first embodiment, reading of the compare window cw ₃ requires at least two reading operations.

  The number of threshold data arranged redundantly is also determined by the size of the compare window applied in the dither processing. That is, when the number of pixels in the main scanning direction of the compare window is M, the number of threshold data arranged redundantly is represented by “M−1”. In the first and second embodiments described above, the number of pixels in the main scanning direction of the compare window is “4” and “2”, respectively. (= 4-1) "and" 1 (= 2-1) ".

Then, after the threshold data of all the rows of the threshold matrix are arranged as described above, if the number of rows of the threshold matrix is not divisible by N, the threshold data for “N−1” rows from the beginning of the threshold matrix is stored. Arrangement is continued again following the threshold data of the last row (N is the number of pixels in the sub-scanning direction of the compare window). At this time, if “N−1” is plural (that is, N is 3 or more), the threshold data from the first row to the (N−1) th row of the threshold value matrix are different from each other. Placed in a group. In the second embodiment, the threshold data for “1 (= 2-1)” rows arranged from address 12 to address 17 of the memories m ₂₁ and m ₂₂ of group 2 correspond to this. In the first embodiment, since the number of pixels in the sub-scanning direction of the compare window is “1”, the above arrangement is not performed.

The above description is summarized as follows. In this case as well, the number of pixels in the main scanning direction of the compare window is M, and the number of pixels in the sub-scanning direction is N. The operation when N = 1 is different from the other cases, and will be described separately.
(A) When N = 1 A-1) “M” memories are provided inside the image processing unit.
A-2) The threshold value data of each row of the threshold value matrix is alternately arranged for “M” memories.
A-3) After the threshold data at the end of each row of the threshold matrix, “M−1” pieces of threshold data are continuously arranged from the top of the row.
(B) When N ≧ 2 B-1) “M × N” memories are provided inside the image processing unit.
B-2) Divide “M × N” memories into “N” groups.
B-3) The threshold data of each row of the threshold matrix are alternately arranged for “N” groups. At this time, threshold data is alternately arranged for “M” memories in each group.
B-4) In each “N” group, after the threshold data at the end of each row of the threshold matrix, “M−1” threshold data are continuously arranged from the top of the row.
B-5) When the number of rows in the threshold matrix is not divisible by N, if threshold data for each row in the threshold matrix is arranged, threshold data for “N−1” rows from the beginning of the threshold matrix is used as the threshold for the last row. Reposition to follow the data. At this time, the above 4) is also performed.

By arranging the threshold data under such a procedure, the threshold matrix can be read at high speed in the same manner as in the first and second embodiments described above, regardless of the threshold matrix and the compare window. Become.
For example, FIG. 20 shows that when the number of pixels in the main scanning direction of the compare window is 3 and the number of pixels in the sub-scanning direction is 2, the threshold data constituting the threshold matrix M ₃ shown in FIG. It is the figure which showed the mode that it memorize | stored. As can be seen from these figures, by arranging threshold data as shown in FIG. 20, even when dither processing is performed using the threshold matrix M ₃ and a 3 × 2 pixel compare window, one dither is performed. Threshold data required for processing can be read simultaneously in one clock cycle.

  From the above, the following conclusions can be drawn. That is, in order to be able to simultaneously read out threshold data necessary for one dither process in one clock cycle (the shortest readable cycle), a threshold value for forming a compare window is stored in the storage unit of the image processing apparatus. It is only necessary to provide the same number of memories as the number of data and arrange the threshold data included in a certain compare window so as not to overlap on the same memory. In this way, since a plurality of different threshold data are not read from the same memory, it is possible to read all of the threshold data forming the compare window by one address designation.

(4) Modifications The present invention is not limited to the above-described embodiments, and various modifications can be made. An example is shown below.
In the first embodiment described above, as shown in FIG. 7, the memory storing the threshold data at the beginning of each row of the threshold matrix varies, but the threshold data at the beginning of each row is the same. It can also be stored in memory.
FIG. 22 is a diagram showing a state in which threshold data at the beginning of each row of the threshold matrix is stored in the same memory m ₁ . It is assumed that the compare window applied at this time is 4 × 1 pixels.
In the figure, the memory block mb3 ₄ and mb4 _{4 at} address 3 are blanked so that the threshold data at the beginning of each row of the threshold matrix is stored in the memory m ₁ . In this way, the address calculation for reading out the threshold data of each row of the threshold matrix is shared, and the address calculation can be performed more easily. For example, the address calculation for reading out the threshold data included in the compare window cw ₁ and the address calculation for reading out the threshold data included in the compare window cw ₂ are different only in the designated address (that is, the row). The logic of operation is all the same. Therefore, it is possible to simplify the address calculation in the dither processing.

In the above-described second embodiment, as shown in FIG. 15, the shift process is performed when the dither process is performed. Here, the number of shift settings for this shift process is two.
At this time, the address calculation is performed by shifting the threshold value data of the first row of the threshold value matrix stored in the addresses 12 to 17 of the memories m ₂₁ and m ₂₂ of the group 2 in accordance with the shift setting number S of the shift process. Can be easily. Specifically, as shown in FIG. 23, the threshold data in the first row of the threshold matrix to be stored from the address 12 to the address 17 of the memories m ₂₁ and m ₂₂ of the group 2 is 2 (= shift setting number S). ) Shift by the number of pieces. In this case, the address calculation at the time of reading the threshold value data is the same for the group 1 and the group 2 when the compare window cw ₉ (see FIG. 15) is read, for example, in the case of the second embodiment described above. It can be seen that it is simpler than (see FIG. 17).

The image processing apparatus according to the present invention is preferably mounted on an image forming apparatus such as an electrophotographic system. In the image processing apparatus according to the present invention, color signals of one or more colors based on image data are input in the image forming apparatus, and dither processing is executed on each color signal. At this time, the functions of the CPU and ROM in the image processing apparatus may be realized by the CPU and ROM included in the image forming apparatus itself. In other words, the image processing apparatus according to the present invention can be provided as a module such as an ASIC having only a configuration of an image processing unit (for example, 10 in FIG. 5 or 10 ′ in FIG. 13).
The application of such an image processing apparatus is not limited to the above-described image forming apparatus, and can naturally be mounted on a computer or the like that executes image processing.

It is the block diagram which showed the structure of the image processing apparatus by the present inventors. FIG. 2 is a schematic diagram illustrating a configuration of a memory in the image processing apparatus of FIG. 1. FIG. 3 is a schematic diagram showing a state in which a threshold matrix is stored in the memory of FIG. 2. It is the figure which showed the compare window at the time of performing a dither process. 1 is a block diagram illustrating a configuration of an image processing apparatus according to a first embodiment of the present invention. It is the schematic diagram which showed the structure of the memory of the memory | storage part in the image processing apparatus which concerns on the embodiment. It is the schematic diagram which showed the state which memorize | stored the threshold value matrix in memory in the same embodiment. It is the figure which showed the compare window applied to reading of threshold value data in the same embodiment. FIG. 10 is a diagram for describing a read operation from a memory when performing a dither process using a compare window in the embodiment. FIG. 10 is a diagram for describing a read operation from a memory when performing a dither process using a compare window in the embodiment. It is a figure for demonstrating the barrel shift which a threshold value control part performs in the embodiment. It is the figure which illustrated the memory | storage part which memorize | stored the some threshold value matrix. It is the block diagram which showed the structure of the image processing apparatus which concerns on the 2nd Embodiment of this invention. It is the schematic diagram which showed the state which memorize | stored the threshold value matrix in memory in the same embodiment. It is the figure which showed the compare window applied to reading of threshold value data in the same embodiment. FIG. 10 is a diagram for describing a read operation from a memory when performing a dither process using a compare window in the embodiment. FIG. 10 is a diagram for describing a read operation from a memory when performing a dither process using a compare window in the embodiment. It is a figure for demonstrating the barrel shift which the threshold value control part 14 performs in the same embodiment. FIG. 10 is a diagram for describing a read operation from a memory when performing a dither process using a compare window in the embodiment. It is the figure which showed the example which has arrange | positioned threshold data according to a predetermined | prescribed procedure. It is the figure which showed the threshold value matrix used in the example of FIG. It is the figure which showed the state which memorize | stored the threshold value data of the head of each line of a threshold value matrix in the same memory. It is the figure which showed the memory at the time of shifting and arrange | positioning threshold value data according to the shift setting number. It is the figure which showed an example of the threshold value matrix. It is the figure which showed arrangement | positioning of the threshold value matrix in the case of performing a dither process with respect to image data. It is the block diagram which showed the structure of the general image processing apparatus which performs a dither process.

Explanation of symbols

100, 101, 200, 300 ... Image forming device, 10, 10 ', 20, 30 ... Image processing device, 1 ... CPU, 2 ... ROM, 11, 21, 31 ... Address control unit, 12, 15, 22, 32 ... Storage unit, 13, 23, 33 ... Comparison unit, 14, 24 ... Threshold control unit.

Claims (8)

An image processing apparatus that extracts threshold data of N rows and M columns in a threshold matrix as a compare window and compares the threshold data included in the extracted compare window with pixel values of image data to perform halftone processing. ,
By having (M × N) memories in which the threshold data is stored and reading out the threshold data one by one from each of these memories, (M × N) threshold data is obtained for each data read cycle. Storage means for reading;
Address control means for specifying a memory address for each of the memories;
Comparing means for comparing (M × N) pieces of threshold data read by the storage means with the pixel values according to a designated memory address;
(M × N) threshold data included in one of the compare windows are stored in (M × N) of the memories separately,
The image processing apparatus, wherein the address control means designates a memory address in which (M × N) threshold data included in the compare window are stored for (M × N) memories. When N ≧ 2, the (M × N) memories are divided into N groups,
Threshold data from the beginning to the end of the i-th (1 ≦ i <N) row in the threshold matrix is stored in the M memories belonging to the k (1 ≦ k <N) -th group among the N groups. Alternately stored, and (M−1) pieces of threshold data that are consecutive from the threshold data at the beginning of the i-th row are stored,
In the M memories belonging to the (k + 1) th group, threshold data from the beginning to the end of the (i + 1) th row in the threshold matrix are alternately stored, and further, threshold data at the beginning of the (i + 1) th row are stored. The image processing apparatus according to claim 1, wherein (M−1) continuous threshold data are stored. If N = 2 and the number of rows in the threshold matrix is not divisible by N,
The image processing apparatus according to claim 2, wherein threshold data of the first row of the threshold matrix is stored in a memory of a group different from a group storing threshold data of the last row in the threshold matrix. If N ≧ 3 and the number of rows in the threshold matrix is not divisible by N,
In the memory of a group different from the group storing the threshold data of the last row in the threshold matrix, the threshold data of the first to (N-1) th rows of the threshold matrix are different from each other. The image processing apparatus according to claim 2, stored in the image processing apparatus. The storage means stores the threshold data of the first row stored in a memory of a group different from the group storing the threshold data of the last row by shifting the determined number of shifts. 3. The image processing apparatus according to 3. The image processing apparatus according to claim 4, wherein the storage unit shifts and stores the threshold data of the first row to the (N−1) th row by a determined shift number. The image processing apparatus according to claim 2, wherein the storage unit stores the threshold data at the head of each row of the threshold matrix in the same memory. A storage unit comprising a plurality of memories is a data storage method for storing threshold data representing a threshold matrix used in dither processing,
A data storage method in which threshold data of N rows and M columns continuous in the threshold value matrix are separately stored in (M × N) memories of the storage unit.

Images