JP2006049711A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide at a low price a semiconductor device having a formed highly accurate analog IC wherein complete-depletion type high-speed MOS transistors and high withstanding voltage MOS transistors are mounted in a mixed way on an SOI substrate. <P>SOLUTION: In the semiconductor device, bleeder resistances are formed in its monocrystal-silicon-device forming layer present above an SOI substrate. On the top surfaces of the respective bleeder resistances, resistance-value fixing electrodes are so formed out of the gate insulating films and the gate electrodes of high-speed MOS transistors as to make their potentials equal to the ones of the bleeder resistances positioned thereunder. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a semiconductor integrated circuit formed on an SOI substrate.

  Currently, semiconductor integrated circuits formed on SOI substrates are widely known. In particular, a high-speed MOS transistor has superior characteristics compared to a conventional MOS transistor formed on a single crystal silicon substrate by utilizing a fully depleted mode.

  An N-type polycrystalline silicon thin film is widely known as a material for the gate electrode. Furthermore, with the aim of high performance such as obtaining a lower threshold voltage, a P-type polycrystalline silicon thin film is used for the gate electrode of the P-type MOS transistor, and an N-type polycrystalline silicon is used for the gate electrode of the N-type MOS transistor. A so-called homopolar gate type CMOS circuit using a thin film is also used in part.

In addition, analog ICs such as voltage detectors often use bleeder resistors composed of a plurality of polycrystalline silicon resistors connected in series. It is difficult to obtain and it is difficult to manufacture a high-precision analog IC. Therefore, there is an example in which a desired resistance value is obtained by fixing the potential of a conductor placed on the upper surface or the lower surface of the polycrystalline silicon resistor (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 9-32229 (FIG. 1)

  However, in a conventional semiconductor integrated circuit formed on an SOI substrate, a single-crystal silicon device formed on a single-crystal silicon substrate through a buried oxide film is formed as an SOI substrate, particularly when a full depletion mode is used. The layer thickness should be about 1000 mm or less. For this reason, it is difficult to provide a high breakdown voltage element or an ESD protection element for preventing ESD breakdown (electrostatic breakdown) in a thin single crystal silicon device formation layer because the element is destroyed.

  In addition, in a conventional semiconductor integrated circuit formed on an SOI substrate, no consideration is given to scribing, and defects such as cracking and chipping may occur in a dicing process of cutting out an IC chip.

  Further, in a semiconductor integrated circuit formed on a conventional SOI substrate, since the potential of the single crystal silicon substrate is set constant over the entire surface of the chip, among the MOS transistors formed in the single crystal silicon device formation layer, the P type Alternatively, a back bias is always applied to either of the N-type MOS transistors. For this reason, the problem that circuit design becomes difficult may occur.

  As a material for the gate electrode, an N-type polycrystalline silicon thin film is widely known. From the relation of the work function of the single crystal silicon forming the gate electrode and the channel region, the leakage current control of the P-type MOS transistor is particularly important. It is difficult to shorten the gate length (so-called L length) of the transistor due to the characteristics related to the above, and thus it is difficult to obtain a large drain current. One solution is to use a P-type polycrystalline silicon thin film for the gate electrode of the P-type MOS transistor and to obtain the gate electrode of the N-type MOS transistor, aiming for high performance such as obtaining a lower threshold voltage of the transistor. In some cases, so-called homopolar gate type CMOS circuits using an N-type polycrystalline silicon thin film are also used. However, this has a problem that the manufacturing process is complicated and the cost of the IC chip is increased.

  In addition, in an analog IC such as a voltage detector, a bleeder resistor made up of a plurality of polycrystalline silicon resistors is often used. Even if an electrode is provided and the potential is fixed, the polycrystalline silicon resistor is greatly affected by grains, and it is difficult to form a resistor having the same resistance value with high accuracy.

  Accordingly, an object of the present invention is to provide a semiconductor device in which a high-precision analog IC in which a fully-depleted high-speed MOS transistor and a high-breakdown-voltage MOS transistor are mixedly mounted on an SOI substrate is resistant to ESD destruction and dicing. The purpose is to provide a low-cost and high-performance form by preventing cracks and cracks in the process.

  In order to solve the above problems, the present invention takes the following means.

  An SOI substrate comprising a silicon substrate, a buried oxide film formed on the silicon substrate, and a single crystal silicon device forming layer formed on the buried oxide film; and formed in the single crystal silicon device forming layer; A fully depleted high-speed MOS transistor having a first gate electrode formed on the single crystal silicon device formation layer via a first gate insulating film; the single crystal silicon device formation layer and the buried oxide film; A high voltage MOS transistor having a second gate electrode formed on the removed silicon substrate and having a second gate electrode formed on the silicon substrate, and the single crystal silicon device forming layer are patterned. A high-concentration impurity region is formed as a contact at both ends, and a plurality of resistors each arranged in series A bleeder resistor and a contact provided at one end of each of the resistors, and are formed via an insulating film formed simultaneously with the first gate insulating film on the respective resistors. And a first resistance value fixing electrode electrode formed by patterning simultaneously with the first gate electrode.

The semiconductor integrated circuit formed on the SOI substrate in the present invention includes a laser trimming fuse element, a laser trimming positioning pattern, a fully depleted high-speed MOS transistor, a high voltage MOS transistor, an ESD protection element, And a bleeder resistor formed by a plurality of resistors.
Further, the laser trimming fuse element and the bleeder resistance are formed by a single crystal silicon device forming layer on the SOI substrate, and a resistance value fixing electrode is formed on the upper surface of each bleeder resistance, The same potential was set.

  Further, the fully depleted high-speed MOS transistor is formed in the single crystal silicon device formation layer, and the high breakdown voltage MOS transistor and the ESD protection element are removed from the single crystal silicon device formation layer and the buried oxide film on the SOI substrate. A gate electrode of a fully depleted high-speed MOS transistor including both an N-type MOS transistor and a P-type MOS transistor, and both an N-type MOS transistor and a P-type MOS transistor are formed on a single crystal silicon substrate. At least one of the gate electrodes of the high voltage MOS transistor was formed of a P-type polycrystalline silicon thin film or a composite film of a P-type polycrystalline silicon thin film and a refractory metal thin film.

  The fully-depleted high-speed MOS transistor is composed of an N-type fully-depleted high-speed MOS transistor and a P-type fully-depleted high-speed MOS transistor, and is a single crystal below the N-type fully-depleted high-speed MOS transistor. The silicon substrate and the single crystal silicon substrate under the P-type fully depleted high-speed MOS transistor are electrically separated by at least one well region, and the potential of the well region or the potential of the single crystal silicon substrate is The source potential of the fully depleted high-speed MOS transistor located on the upper part of each of the high-speed MOS transistors is the same.

  Furthermore, in the scribe region of the semiconductor integrated circuit, the single crystal silicon device formation layer and the buried oxide film were removed.

  Furthermore, the scribe region of the semiconductor integrated circuit from which the single crystal silicon device formation layer and the buried oxide film have been removed, the high breakdown voltage MOS transistor formation region, the ESD protection element formation region, and the single crystal silicon device formation layer on the SOI substrate The single crystal silicon device forming layer and the edge of the buried oxide film have a tapered shape at the boundary with the region where the buried oxide film exists.

  As a result, a semiconductor device in which a high-precision analog IC in which a fully-depleted high-speed MOS transistor and a high-breakdown-voltage MOS transistor are mixedly mounted on an SOI substrate is resistant to ESD breakdown, and cracks are not generated in the dicing process. Can be provided in a cheap and high-performance form.

BEST MODE FOR CARRYING OUT THE INVENTION

  In a semiconductor integrated circuit formed on an SOI substrate, the semiconductor integrated circuit includes a laser trimming fuse element, a laser trimming positioning pattern, a fully depleted high-speed MOS transistor, a high voltage MOS transistor, and ESD protection. An element and a bleeder resistance formed by a plurality of resistors were formed.

  The bleeder resistance is formed by a single crystal silicon device forming layer on the SOI substrate, and a resistance value fixing electrode is arranged on the upper surface of each bleeder resistance via a thin gate oxide film, and the bleeder resistance located below the bleeder resistance. And the same potential.

  In addition, the fully depleted high-speed MOS transistor is formed in the single crystal silicon device formation layer, and the high breakdown voltage MOS transistor and the ESD protection element are removed from the single crystal silicon device formation layer and the buried oxide film on the SOI substrate. The gate electrode of the fully depleted high-speed MOS transistor including both the N-type MOS transistor and the P-type MOS transistor, the N-type MOS transistor, and the P-type MOS transistor are formed on a single crystal silicon substrate. At least one of the gate electrodes of the high breakdown voltage MOS transistor included was formed of a P-type polycrystalline silicon thin film or a composite film of a P-type polycrystalline silicon thin film and a refractory metal thin film.

  The fully-depleted high-speed MOS transistor is composed of an N-type fully-depleted high-speed MOS transistor and a P-type fully-depleted high-speed MOS transistor, and is a single crystal below the N-type fully-depleted high-speed MOS transistor. The silicon substrate and the single crystal silicon substrate under the P-type fully depleted high-speed MOS transistor are electrically separated by at least one well region, and the potential of the well region or the potential of the single crystal silicon substrate is The source potential of each of the fully depleted high-speed MOS transistors located above them is the same as the source potential.

  Furthermore, in the scribe region of the semiconductor integrated circuit, the single crystal silicon device formation layer and the buried oxide film were removed.

  Furthermore, the scribe region of the semiconductor integrated circuit from which the single crystal silicon device formation layer and the buried oxide film have been removed, the high breakdown voltage MOS transistor formation region, the ESD protection element formation region, and the single crystal silicon device formation layer on the SOI substrate The single crystal silicon device forming layer and the edge of the buried oxide film have a tapered shape at the boundary with the region where the buried oxide film exists.

  As a result, a semiconductor device in which a high-precision analog IC in which a fully-depleted high-speed MOS transistor and a high-breakdown-voltage MOS transistor are mixedly mounted on an SOI substrate is resistant to ESD breakdown, and cracks are not generated in the dicing process. Can be provided in a cheap and high-performance form.

  Embodiments of the present invention will be described below with reference to the drawings. The description will be given with reference to FIG. 1, which is a schematic cross-sectional view of a semiconductor device.

First, the fully depleted high-speed MOS transistor region 210 will be described.
A source region 201, a drain region 202, and a channel region 203 are formed in a single crystal silicon device formation layer 103 formed on the single crystal silicon substrate 101 via a buried oxide film 102. Further, a gate electrode 205 is disposed above the channel region 203 via a gate oxide film 206 to form a MOS transistor. Here, the film thickness of the single crystal silicon device forming layer 103 is set to, for example, 500 mm so as to be completely depleted. Further, the aluminum film 105 is connected to the source region 201 and the drain region 202 through a contact hole 204 opened in the intermediate insulating film 104 made of a BPSG film or the like. In the high-speed MOS transistor region 210, a protective film 806 made of a silicon nitride film or the like is formed on the uppermost layer.

  Here, the potential of the channel region 203 may be floating or may be fixed depending on circumstances. In addition, the bottoms of the source region 201 and the drain region 202 are desirably formed so as to be in contact with the buried oxide film 102 for the purpose of reducing the capacitance. However, the depletion layer may be formed to a depth that is in contact with the buried oxide film 102 when a voltage is applied, and the bottom thereof may be separated from the buried oxide film 102.

  Now, a fully depleted high-speed MOS transistor according to the present invention will be described with reference to FIG.

  A P-type MOS transistor 211 having a source region 201, a drain region 202, and a channel region 203 in a single-crystal silicon device formation layer 103 formed on a P-type single crystal silicon substrate 101 via a buried oxide film 102, and an N-type transistor A type MOS transistor 212 is formed. Here, an N well region 911 is formed in the vicinity of the surface of the P type single crystal silicon substrate 101, which is under the P type MOS transistor 211.

  Although not shown, the potential of the N well region 911 is connected to be the same as that of the source region 201 of the P-type MOS transistor 211 located thereabove. On the other hand, the potential of the P-type single crystal silicon substrate 101 is connected so as to be the same as that of the source region 201 of the N-type MOS transistor 212 located thereabove.

  By adopting such a structure, the single crystal silicon substrate 101 works as if it is a gate electrode on the back surface through the buried oxide film 102 with respect to the P-type MOS transistor 211 and the N-type MOS transistor 212. The so-called back gate effect can be prevented.

  Further, FIG. 2 illustrates an example in which the single crystal silicon substrate is P type and an N well is formed therein, but conversely, the single crystal silicon substrate may be N type and a P well region may be formed therein. Further, an N well and a P well may be formed to be electrically separated without being restricted by the conductivity type of the substrate. Further, depending on the product and application, the wells may be divided into a plurality of potentials and set several potentials. Other explanations will be replaced by the same reference numerals as those in FIG.

  Next, returning to FIG. 1 again, the high voltage MOS transistor and ESD protection circuit region 310 will be described. A source region 301, a drain region 302, and a channel region 303 are formed on the single crystal silicon substrate 101, and a gate electrode 305 is disposed on the channel region 303 with a gate oxide film 306 interposed therebetween to form a MOS transistor. ing. That is, these circuits are formed on the surface of the single crystal silicon substrate 101 from which the buried oxide film 102 and the single crystal silicon device formation layer 103 are removed.

  Further, the aluminum film 105 is connected to the source region 301 and the drain region 302 through a contact hole 304 opened in the intermediate insulating film 104 made of a BPSG film or the like. A protective film 106 made of a silicon nitride film or the like is formed on the uppermost layer in the high voltage MOS transistor and ESD protection circuit region 310 as in the high speed MOS transistor region 201.

  Here, unlike the high-speed MOS transistor region 201, in the high-voltage MOS transistor and ESD protection circuit region 310, the single crystal silicon device formation layer 103 and the buried oxide film 102 are removed, and elements are directly formed on the single crystal silicon substrate 101. It is characteristic that it is formed. Thereby, although not particularly shown, a high voltage MOS transistor suitable for a high operating voltage such as a DDD structure or a LOCOS drain structure can be easily formed. Further, the gate oxide film 306 may be formed thicker than the gate oxide film 206 in the high-speed MOS transistor region 210. Although an ESD protection circuit is not particularly shown, an off-transistor, a diode, or the like having a heat capacity and a junction area, which has sufficient resistance against ESD, is formed by forming it on the single crystal silicon substrate 101. be able to.

  In FIG. 1, for simplicity, only one fully depleted high-speed MOS transistor and one high-breakdown-voltage MOS transistor are shown. However, in actuality, each CMOS is composed of both an N-type MOS transistor and a P-type MOS transistor. It has a structure. At least one of the gate electrodes 205 of both the N-type MOS transistor of the fully-depleted high-speed MOS transistor and the P-type MOS transistor, the N-type MOS transistor of the high breakdown voltage MOS transistor, and the gate electrodes 305 of both of the P-type MOS transistors One is formed of a P-type polycrystalline silicon thin film or a composite film of a P-type polycrystalline silicon thin film and a refractory metal thin film. The reason is described below.

  By using P-type polycrystalline silicon for the gate electrode in the P-type MOS transistor, the channel of E (enhancement) type PMOS becomes a surface channel from the relationship between the work function of the single crystal silicon forming the channel and the gate electrode. In the channel type PMOS, even if the threshold voltage is set to, for example, −0.5 V or more, the sub-threshold coefficient is not extremely deteriorated, and both low voltage operation and low power consumption are possible.

  On the other hand, in the N-type MOS transistor, the channel of the E-type NMOS is a buried channel because of the work function relationship between the gate electrode of the P-type polycrystalline silicon and the P-type single crystal silicon forming the channel. In this case, arsenic having a small diffusion coefficient can be used as a threshold control donor impurity, so that the channel becomes a very shallow buried channel. Therefore, even if the threshold voltage is set to a small value of, for example, 0.5 V or less, it is necessary to use boron having a large diffusion coefficient and a large ion implantation projection range as a threshold control acceptor impurity. As compared with the case of the E-type PMOS using the N-type polycrystalline silicon as the gate electrode, the deterioration of the subthreshold and the increase in the leakage current can be remarkably suppressed.

  As described above, the CMOS according to the present invention using the P-type polycrystalline silicon as the gate electrode is a more effective technique for low voltage operation and lower power consumption than the conventional CMOS using the N-type polycrystalline silicon as the gate electrode. It will be understood.

  In addition, so-called homopolar gate CMOS technology is generally known for low voltage operation and low power consumption, but in forming a homopolar gate, it is usually necessary to make the gate electrode into P type and N type. Compared with this single-pole gate process, at least two mask steps are required. The standard number of mask processes for a single-pole gate CMOS is about 10 times. However, by using the same-pole gate, the process cost is increased by approximately 20%, and the present invention is also provided from a comprehensive viewpoint of the performance and cost of a semiconductor device. It can be said that a CMOS using a gate electrode of P-type polycrystalline silicon is effective.

  In addition, it is generally difficult for the P-type polycrystalline silicon thin film to have a lower resistance than the N-type polycrystalline silicon thin film. For this reason, since there is a problem that a single film becomes a relatively high resistance film, it is desirable to reduce the resistance as a composite film with a refractory metal in a circuit that emphasizes high-speed operation.

  Next, the bleeder resistance region 410 will be described. A low-concentration impurity region 402 sandwiched between a pair of high-concentration impurity regions 401 is formed in a single-crystal silicon device formation layer 103 formed on the single-crystal silicon substrate 101 with a buried oxide film 102 interposed therebetween. Is forming. Although only one is shown in FIG. 1 for simplicity, a bleeder resistor is actually formed by a plurality of resistors.

  Further, the aluminum film 105 is connected to the high concentration impurity region 401 through a contact hole 404 opened in the intermediate insulating film 104 made of a BPSG film or the like. Here, the aluminum film 105 connected to one high-concentration impurity region 401 is disposed so as to cover the low-concentration impurity region 402 that determines the resistance value of the resistor, thereby stabilizing the resistance value.

  This is to prevent the resistance value of the resistor from changing due to the potential difference between the conductor close to the resistor and the resistor itself. When all of the plurality of resistors forming the bleeder resistance are manufactured in a similar manner so that the potential of the aluminum film 105 on the resistor is not the power supply potential or the ground potential but the potential of one end of the bleeder resistance, There is almost no potential difference between the aluminum film 105 positioned above the resistor and the resistor itself, and each resistor processed to the same size and shape exhibits the same resistance value. By forming a bleeder resistance circuit using these resistors, voltage division with high accuracy becomes possible.

  Furthermore, in the present invention, the resistance value fixing electrode is provided on the upper part of the bleeder resistor, and the potential thereof is made the same as that of the lower bleeder resistor, thereby further improving the accuracy. This will be described with reference to FIG.

FIG. 3 is a diagram showing one embodiment of the bleeder resistance of the semiconductor device according to the present invention.
A first resistance value fixing electrode 331 and a second resistance value fixing electrode 332 are respectively disposed on portions corresponding to the upper portions of the first resistor 411 and the second resistor 412 via a thin gate oxide film 306. Provided. If these are formed of the same material as the gate electrode 205 of the high-speed MOS transistor region 210 in FIG. 1, the process can be simplified.

A potential of one end of the first resistor 411 and a potential of the first resistance value fixing electrode 331;
The potential of one end of the second resistor 412 and the potential of the second resistance value fixing electrode 332 are wired to be the same. As a result, when all of the plurality of resistors forming the bleeder resistance are manufactured in the same manner, there is almost no potential difference between the resistance value fixing electrode located above each resistor and the resistor itself. Each resistor processed into the dimension and shape shows the same resistance value.

  Compared to the bleeder resistance by the conventional polycrystalline silicon thin film, the present invention forms the resistor by the single crystal silicon device forming layer 103 itself, so that the influence of the grain of the polycrystalline silicon thin film can be eliminated, and more uniform. Can be obtained. On the other hand, since the resistance value is lowered by adding less impurities than the polycrystalline silicon thin film, there is also a problem that it is easily affected by the potential of electrodes (or equivalent ones) positioned above and below the resistor.

In the present invention, in addition to making the potential difference between the aluminum film 105 located above each resistor and the resistor itself almost non-existent, an electrode for fixing the resistance value is arranged through a thin oxide film. However, by making this potential the same as that of each of the resistors installed at the lower part, it is possible to perform voltage division with higher accuracy.
This makes it possible to form a bleeder resistance circuit with higher accuracy.

  1 and 3, the case where a resistor having a high resistance value provided with a low concentration impurity region 402 sandwiched between a pair of high concentration impurity regions 401 has been described. However, a high resistance value is necessary. For applications that do not exist, the entire resistor may be formed of the high concentration impurity region 401. A protective film 806 made of a silicon nitride film or the like is formed on the uppermost layer of the bleeder resistance region 410.

  Next, returning to FIG. 1, the fuse region 510 will be described. A single crystal silicon fuse 501 is formed in a single crystal silicon device formation layer 103 formed on the single crystal silicon substrate 101 via a buried oxide film 102. The single crystal silicon fuse 501 has a high impurity concentration in order to have good conductivity and reduce the resistance value as much as possible.

  The aluminum film 105 is connected to both ends of the single crystal silicon fuse 501 through contact holes 504 opened in the intermediate insulating film 104 made of a BPSG film or the like. The protective film 806 made of a silicon nitride film or the like formed in the uppermost layer of the fuse region 510 has a portion corresponding to the laser irradiation region 505 removed. This is because the energy of the laser beam irradiated at the time of laser trimming is absorbed by the protective film 806, thereby preventing the single crystal silicon fuse 501 from being hindered.

  Next, the scribe area 801 will be described. In FIG. 1, a scribe region 801 is a portion to be cut in a subsequent dicing step (step of cutting out an IC chip). A scribe region 801 starts from the end of the semiconductor integrated circuit internal region 701. Here, in the scribe region 801, the single crystal silicon device formation layer 103 and the buried oxide film 102 are removed. Desirably, as shown in FIG. 1, the intermediate insulating film 104, the aluminum film 105, the protective film 106, and the like are also removed.

  This is because, when the scribe region 801 that is a part to be cut off in the dicing process and the semiconductor integrated circuit internal region 701 are connected by the continuous single crystal silicon device forming layer 103, cracks are caused due to variations in the dicing process. When a force that causes damage such as chipping works, cracks and chipping propagate to the internal area 701 of the semiconductor integrated circuit, which breaks an important IC chip or causes malfunction. This is to prevent this.

  In particular, since an IC manufactured on an SOI substrate has a thin buried oxide film 102 and a single crystal silicon device formation layer 103 on the single crystal silicon substrate 101, the buried oxide film 102 and the single crystal silicon device forming the upper layer are formed. The layer 103 is easily cracked and chipped, so care must be taken.

  It is important to prevent cracking and chipping of the IC chip so as not to leave the same continuous film between the scribe region 801 which is a margin in the dicing process and the semiconductor integrated circuit internal region 701 which becomes the IC chip. In particular, with respect to an IC formed on an SOI substrate, it is necessary to remove the single crystal silicon device formation layer 103 and the buried oxide film 102 in the scribe region 801 as shown in FIG. . More preferably, as shown in FIG. 1, the intermediate insulating film 104, the aluminum film 105, the protective film 806, and the like are also removed. Further, when various marks or test patterns need to be formed in the scribe region 801, a region where the corresponding film is removed is provided between the scribe region 801 and the semiconductor integrated circuit internal region 701. In addition, it is preferable that the same film does not continuously bridge the scribe region 801 and the semiconductor integrated circuit internal region 701.

  Finally, the scribe region 801 of the semiconductor integrated circuit from which the single crystal silicon device formation layer 103 and the buried oxide film 102 have been removed, the high breakdown voltage MOS transistor / ESD protection element formation region 310, and the high-speed MOS transistor region 210, etc. The shape of the edges of the single crystal silicon device formation layer 102 and the buried oxide film 103 at the boundary between the crystalline silicon device formation layer 103 and the region where the buried oxide film 102 exists will be described.

  FIG. 4 is a view showing the edge portions of the single crystal silicon device forming layer 102 and the buried oxide film 103 of the semiconductor device according to the present invention. In FIG. 4, the single crystal silicon device forming layer edge portion 92 and the buried oxide film edge portion 91 have a tapered shape, and the cross-sectional shape of the portion is gentle. This prevents disconnection of wirings such as the aluminum wiring 105 disposed in an upper layer such as the single crystal silicon device formation layer 103, and the single crystal silicon device formation layer 103 is peeled or chipped in the scribe region 801 or the like. Can also be prevented.

It is typical sectional drawing of the semiconductor device of this invention. It is a figure which shows one Example of the fully depleted type high-speed MOS transistor of this invention. It is a figure which shows one Example of the bleeder resistance of the semiconductor device by this invention. It is a figure which shows the single crystal silicon device formation layer of the semiconductor device by this invention, and the edge part of a buried oxide film.

Explanation of symbols

91 buried oxide film edge portion 92 single crystal silicon device forming layer edge portion 101 single crystal silicon substrate 102 buried oxide film 103 single crystal silicon device forming layer 104 intermediate insulating film 105 aluminum film 111 p-type single crystal silicon substrate 201 source region 202 drain Region 203 Channel region 204 Contact hole 205 Gate electrode 206 Gate oxide film 210 High-speed MOS transistor region 211 P-type MOS transistor 212 N-type MOS transistor 301 Source region 302 Drain region 303 Channel region 304 Contact hole 305 Gate electrode 306 Gate oxide film 310 High Withstand voltage MOS transistor and ESD protection circuit region 331 First resistance value fixing electrode 332 Second resistance value fixing electrode 401 High concentration impurity region 402 Low Impurity region 404 contact hole 410 bleeder resistance region 411 first resistor 412 second resistor 421 aluminum film 422 covering the top surface of the first resistor aluminum film 501 covering the top surface of the second resistor Fuse 504 Contact hole 505 Laser irradiation region 510 Fuse region 601 Laser trimming positioning pattern region 701 Semiconductor integrated circuit internal region 801 Scribe region 806 Protective film 911 N well region

Claims (6)

An SOI substrate comprising a silicon substrate, a buried oxide film formed on the silicon substrate, and a single crystal silicon device forming layer formed on the buried oxide film;
A fully-depleted high-speed MOS transistor having a first gate electrode formed on the single-crystal silicon device formation layer and formed on the single-crystal silicon device formation layer via a first gate insulating film;
A high breakdown voltage MOS having a second gate electrode formed on the silicon substrate via a second gate insulating film formed on the silicon substrate from which the single crystal silicon device forming layer and the buried oxide film have been removed. A transistor,
Forming the single crystal silicon device forming layer by patterning, forming high-concentration impurity regions as contacts at both ends, and a bleeder resistor composed of a plurality of resistors each arranged in series;
Electrically connected to a contact provided at one end of each of the resistors, and formed on the respective resistors via an insulating film formed simultaneously with the first gate insulating film; And a first resistance-fixing electrode electrode formed by patterning simultaneously with the gate electrode.   The fully-depleted high-speed MOS transistor includes an N-type MOS transistor and a P-type MOS transistor, and the first gate electrode of at least one of the N-type MOS transistor and the P-type MOS transistor is P-type polycrystalline silicon. The semiconductor device according to claim 1, wherein the semiconductor device is formed of a thin film.   The fully-depleted high-speed MOS transistor includes an N-type MOS transistor and a P-type MOS transistor, and the first gate electrode of at least one of the N-type MOS transistor and the P-type MOS transistor is P-type polycrystalline silicon. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed of a composite film of a thin film and a refractory metal thin film. The N-type MOS transistor is composed of an N-type MOS transistor and a P-type MOS transistor, and the N-type MOS transistor is electrically separated by at least one well region, and the potential of the well region or the silicon device formation layer is respectively formed above the well region. 3. The semiconductor device according to claim 2, wherein the semiconductor device has the same source potential as that of the N-type and P-type MOS transistors.   The semiconductor device according to claim 1, wherein the high voltage MOS transistor forms an electrostatic discharge protection circuit.   2. The semiconductor device according to claim 1, wherein the high breakdown voltage MOS transistor has a drain region comprising a low concentration impurity region and a high concentration impurity region.

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