JP2006047101A - Timepiece precision correction device - Google Patents

Timepiece precision correction device Download PDF

Info

Publication number
JP2006047101A
JP2006047101A JP2004228126A JP2004228126A JP2006047101A JP 2006047101 A JP2006047101 A JP 2006047101A JP 2004228126 A JP2004228126 A JP 2004228126A JP 2004228126 A JP2004228126 A JP 2004228126A JP 2006047101 A JP2006047101 A JP 2006047101A
Authority
JP
Japan
Prior art keywords
time
reference time
division ratio
frequency division
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2004228126A
Other languages
Japanese (ja)
Other versions
JP4651988B2 (en
Inventor
Ryoji Sawada
亮治 澤田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Document Solutions Inc
Original Assignee
Kyocera Mita Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Mita Corp filed Critical Kyocera Mita Corp
Priority to JP2004228126A priority Critical patent/JP4651988B2/en
Publication of JP2006047101A publication Critical patent/JP2006047101A/en
Application granted granted Critical
Publication of JP4651988B2 publication Critical patent/JP4651988B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Electric Clocks (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timepiece precision correction device capable of restraining an acquisition frequency for a reference time to a low level, using an inexpensive oscillator of low precision. <P>SOLUTION: This timepiece precision correction device, for acquiring the reference time from an outside at prescribed timing, and for updating the reference time to the present time, includes the oscillator for outputting a prescribed frequency of clock pulse, a dividing counter for dividing the clock pulse by a dividing ratio set in a dividing ratio register to output a fundamental timer pulse, a time output means for accumulation-counting the fundamental timer pulses to output the present time, and a dividing ratio correction means for calculating the dividing ratio on the basis of a difference between the acquired reference time and the present time, and for setting the calculated dividing ratio in the dividing ratio register. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、電子機器内に内蔵される時計機能の精度を修正する時計精度修正装置に関する。   The present invention relates to a clock accuracy correction device that corrects the accuracy of a clock function built in an electronic apparatus.

従来からコンピュータネットワークに接続される情報処理装置において、時刻サーバから基準時刻を取得して、内部に実装された時計の時刻を補正する技術が知られている。これは、情報処理装置が有する内蔵時計において、時間の経過とともに発生する標準時刻との誤差が、あらかじめ設定した許容範囲内に収まるように、内蔵時計ごとに修正時間間隔を算出し、修正の間隔を動的に変化させ、また誤差を想定することにより、ネットワークに負荷をかけることなく自己修正を行うものである（例えば、特許文献１参照）。
特開平１０−０９１２７５号公報 2. Description of the Related Art Conventionally, in an information processing apparatus connected to a computer network, a technique for acquiring a reference time from a time server and correcting the time of a clock mounted inside is known. This is because the correction time interval is calculated for each built-in clock so that the error from the standard time that occurs with the passage of time in the built-in clock possessed by the information processing device falls within the preset allowable range. Is automatically changed and a self-correction is performed without imposing a load on the network (see, for example, Patent Document 1).
JP-A-10-091275

ところで、電子機器内の時計の精度を高く保つには、高精度の発振器を原振とした基本タイマを用いて、外部から取得する基準時刻を取得後に、内部の時計を更新したり、外部から基準時刻を取得する時間間隔を短くする方法等がある。
しかしながら、高精度の発振器は高価であるため、電子機器の製造コストが高くなるという問題がある。また、基準時刻を取得する間隔を短くすると、基準時刻を出力する時刻サーバの負荷が増大するとともに、ネットワークのトラフィックが増大するという問題もある。 By the way, in order to keep the accuracy of the clock in the electronic device high, the internal timer can be updated or the external clock can be updated after acquiring the reference time acquired from the outside using a basic timer with a high-precision oscillator as the original oscillation. There is a method of shortening the time interval for acquiring the reference time.
However, since a high-precision oscillator is expensive, there is a problem that the manufacturing cost of the electronic device increases. Further, if the interval for acquiring the reference time is shortened, there is a problem that the load on the time server that outputs the reference time increases and the network traffic increases.

本発明は、このような事情に鑑みてなされたもので、精度の低い安価な発振器を用いて、基準時刻の取得頻度を低く抑えることができる時計精度修正装置及び制御プログラムを提供することを目的とする。   The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a clock accuracy correction device and a control program that can suppress the frequency of obtaining a reference time by using an inexpensive oscillator with low accuracy. And

請求項１に記載の発明は、外部から所定のタイミングで基準時刻を取得して、該基準時刻を現在時刻に更新する時計精度修正装置において、所定の周波数のクロックパルスを出力する発振器と、前記クロックパルスを分周比レジスタに設定されている分周比により分周して基本タイマパルスを出力する分周カウンタと、前記基本タイマパルスを累積カウントして現在時刻を出力する時刻出力手段と、取得した基準時刻と前記現在時刻と差から前記分周比を算出し、算出した分周比を前記分周比レジスタに設定する分周比補正手段とを備えたことを特徴とする。   The invention according to claim 1 is a clock accuracy correction device that acquires a reference time from the outside at a predetermined timing and updates the reference time to the current time. An oscillator that outputs a clock pulse of a predetermined frequency; A frequency dividing counter that divides a clock pulse by a frequency dividing ratio set in a frequency dividing ratio register and outputs a basic timer pulse; a time output unit that cumulatively counts the basic timer pulse and outputs a current time; The frequency division ratio is calculated from a difference between the acquired reference time and the current time, and frequency division ratio correction means for setting the calculated frequency division ratio in the frequency division ratio register is provided.

請求項２に記載の発明は、前記分周比補正手段は、取得した基準時刻と前記現在時刻と差に基づいて、外部から基準時刻を取得するタイミングを決定することを特徴とする。   The invention according to claim 2 is characterized in that the frequency division ratio correcting means determines the timing for acquiring the reference time from the outside based on the difference between the acquired reference time and the current time.

請求項３に記載の発明は、前記分周比補正手段は、次回の基準時刻取得までの間に時刻出力手段から出力する現在時刻の誤差が所定値を超えない範囲で前記基準時刻を取得するタイミングを決定することを特徴とする。   According to a third aspect of the present invention, the frequency division ratio correcting unit acquires the reference time within a range in which an error of the current time output from the time output unit does not exceed a predetermined value until the next reference time acquisition. The timing is determined.

請求項４に記載の発明は、所定の周波数のクロックパルスを出力する発振器と、前記クロックパルスを分周比レジスタに設定されている分周比により分周して基本タイマパルスを出力する分周カウンタと、前記基本タイマパルスを累積カウントして現在時刻を出力する時刻出力手段とを備え、外部から所定のタイミングで基準時刻を取得して、該基準時刻を現在時刻に更新する時計精度修正装置を制御する制御プログラムであって、取得した基準時刻と前記現在時刻と差から前記分周比を算出し、算出した分周比を前記分周比レジスタに設定する分周比補正処理をコンピュータに行わせることを特徴とする。   According to a fourth aspect of the present invention, there is provided an oscillator for outputting a clock pulse having a predetermined frequency, and a frequency division for dividing the clock pulse by a frequency division ratio set in a frequency division ratio register and outputting a basic timer pulse. A clock accuracy correction device comprising: a counter; and a time output unit that cumulatively counts the basic timer pulses and outputs a current time, acquires a reference time from the outside at a predetermined timing, and updates the reference time to the current time A computer program for dividing ratio correction processing for calculating the dividing ratio from the difference between the acquired reference time and the current time, and setting the calculated dividing ratio in the dividing ratio register. It is made to perform.

請求項５に記載の発明は、前記分周比補正処理は、取得した基準時刻と前記現在時刻と差に基づいて、外部から基準時刻を取得するタイミングを決定することを特徴とする。   The invention according to claim 5 is characterized in that the division ratio correction process determines a timing for acquiring a reference time from the outside based on a difference between the acquired reference time and the current time.

本発明によれば、安価な発振器を使用することが可能となるため、電子機器の製造コストを低く抑えることができる。また稼働時間が延びるにつれて時計の精度を高めることができるため、基準時刻を出力する時刻サーバの負荷とネットワークのトラフィックを低く抑えることができるという効果が得られる。また、修正動作中の出力誤差が所定値をこえないようにしたため、出力時刻を使用しながら修正動作を行うことができ、製品出荷時の調整や使用開始前の修正動作を行う必要がないという効果も得られる。   According to the present invention, since an inexpensive oscillator can be used, the manufacturing cost of the electronic device can be kept low. In addition, since the accuracy of the clock can be increased as the operating time is extended, the load of the time server that outputs the reference time and the traffic on the network can be suppressed. In addition, since the output error during the correction operation does not exceed the predetermined value, the correction operation can be performed while using the output time, and there is no need to perform adjustment at the time of product shipment or correction operation before starting the use. An effect is also obtained.

以下、本発明の一実施形態による時計精度修正装置を図面を参照して説明する。図１は同実施形態の構成を示すブロック図である。この図において、符号１は、５０ＭＨｚのクロックパルスを出力する発振器である。符号２は、発振器１より出力されるクロックパルスを分周して基本タイマパルスを出力する分周カウンタであり、分周比は変更可能であり、初期値として、５０ＭＨｚを５０Ｈｚに分周する（分周比１Ｍクロック）ように設定されている。符号３は、分周カウンタ２の分周比を保持する分周比レジスタであり、分周カウンタ２は、このレジスタに保持されている分周比を用いて、クロックパルスの分周処理を行う。符号４は、分周カウンタ２の分周比を記憶する不揮発性のメモリである。符号５は、分周カウンタ２が出力する基本タイマパルスを累積カウントして現在の時刻を出力する時刻出力部である。符号６は、基準時刻を出力する時刻サーバである。符号７は、時刻サーバ６に対して基準時刻取得要求を送信し、時刻サーバ６から出力される基準時刻データをネットワークを介して受信する時刻取得部である。符号８は、時刻取得部７が取得した基準時刻と時刻出力部５から出力される現在時刻との差から分周カウンタ２が出力する基本タイマパルスの精度を求め、この精度に基づいて割り出した修正分周比を分周比レジスタ３に保持するとともに、メモリ４に基本タイマパルスの精度情報を記憶する分周比補正部である。
以下の説明において発振器１は、最大で±０．５％の誤差を有しているものとして説明する。 A timepiece accuracy correcting apparatus according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment. In this figure, reference numeral 1 denotes an oscillator that outputs a clock pulse of 50 MHz. Reference numeral 2 denotes a frequency division counter that divides the clock pulse output from the oscillator 1 and outputs a basic timer pulse. The frequency division ratio can be changed, and 50 MHz is divided into 50 Hz as an initial value ( The division ratio is 1M clock). Reference numeral 3 denotes a frequency division ratio register that holds the frequency division ratio of the frequency division counter 2, and the frequency division counter 2 performs a clock pulse frequency division process using the frequency division ratio held in the register. . Reference numeral 4 is a non-volatile memory that stores the frequency division ratio of the frequency division counter 2. Reference numeral 5 denotes a time output unit that cumulatively counts the basic timer pulses output from the frequency dividing counter 2 and outputs the current time. Reference numeral 6 denotes a time server that outputs a reference time. Reference numeral 7 denotes a time acquisition unit that transmits a reference time acquisition request to the time server 6 and receives reference time data output from the time server 6 via a network. Reference numeral 8 determines the accuracy of the basic timer pulse output from the frequency division counter 2 from the difference between the reference time acquired by the time acquisition unit 7 and the current time output from the time output unit 5, and calculated based on this accuracy. The frequency division ratio correction unit stores the corrected frequency division ratio in the frequency division ratio register 3 and stores the accuracy information of the basic timer pulse in the memory 4.
In the following description, it is assumed that the oscillator 1 has an error of ± 0.5% at the maximum.

次に、図２を参照して、時計精度の修正動作を説明する。まず、分周比補正部８は、メモリ４に初期値として発振器１の特性に基づく基本タイマ精度情報を記憶する（ステップＳ１）。基本タイマ精度情報とは、分周カウンタ２が出力する基本タイマパルスの精度である。すなわち、基本タイマパルスは、初期状態において、５０ＭＨｚ＋０．５％のクロックパルスを出力する発振器１を用いているため、最大で２００パルス当たり１パルスの誤差が生じることになり、これが基本タイマ精度である。   Next, the operation for correcting the clock accuracy will be described with reference to FIG. First, the frequency division ratio correction unit 8 stores basic timer accuracy information based on the characteristics of the oscillator 1 as an initial value in the memory 4 (step S1). The basic timer accuracy information is the accuracy of the basic timer pulse output from the frequency dividing counter 2. That is, since the basic timer pulse uses the oscillator 1 that outputs a clock pulse of 50 MHz + 0.5% in the initial state, an error of one pulse per 200 pulses occurs at maximum, which is the basic timer accuracy. .

次に、時刻取得部７は、時刻サーバ６に対して基準時刻取得要求を送信し、時刻サーバ６から基準時刻を取得する（ステップＳ２）。そして、時刻取得部７は、取得した基準時刻を時刻出力部５へ通知する（ステップＳ３）。これにより、時刻出力部５が出力する現在時刻が基準時刻に更新される。次に、分周比補正部８は、メモリ４に記憶されている基本タイマ精度情報を基に、次の基準時刻取得間隔を設定し、時刻取得部７へ通知する（ステップＳ４）。基準時刻取得間隔は、新たに基準時刻を取得するまでの間の時計の誤差を±１秒以内に収めるための値である。そして、分周比補正部８は、基本タイマ時間間隔を基準時刻取得間隔で除算して、得られた値を新たな基本タイマ精度情報として、メモリ４へ記憶する（ステップＳ５）   Next, the time acquisition unit 7 transmits a reference time acquisition request to the time server 6, and acquires the reference time from the time server 6 (step S2). Then, the time acquisition unit 7 notifies the acquired reference time to the time output unit 5 (step S3). As a result, the current time output by the time output unit 5 is updated to the reference time. Next, the frequency division ratio correction unit 8 sets the next reference time acquisition interval based on the basic timer accuracy information stored in the memory 4, and notifies the time acquisition unit 7 (step S4). The reference time acquisition interval is a value for keeping the clock error within ± 1 second until a new reference time is acquired. Then, the frequency division ratio correction unit 8 divides the basic timer time interval by the reference time acquisition interval, and stores the obtained value in the memory 4 as new basic timer accuracy information (step S5).

次に、時刻取得部７は、分周比補正部８から通知された基準時刻取得間隔に基づいて、時刻サーバ６より基準時刻を取得する（ステップＳ６）。時刻取得部７は、ここで取得した基準時刻を分周比補正部８へ通知する。これを受けて、分周比補正部８は、現在時刻出力部５から出力される現在時刻と取得した基準時刻との差から修正分周比を算出する（ステップＳ７）。そして、分周比補正部８は、算出した修正分周比を分周レジスタ３とメモリ４へ書き込む（ステップＳ８）。これにより、分周カウンタ２の分周比が変更されて、基本タイマパルスの精度が向上する。   Next, the time acquisition unit 7 acquires the reference time from the time server 6 based on the reference time acquisition interval notified from the frequency division ratio correction unit 8 (step S6). The time acquisition unit 7 notifies the frequency division ratio correction unit 8 of the reference time acquired here. In response, the frequency division ratio correction unit 8 calculates a corrected frequency division ratio from the difference between the current time output from the current time output unit 5 and the acquired reference time (step S7). Then, the frequency division ratio correction unit 8 writes the calculated corrected frequency division ratio into the frequency division register 3 and the memory 4 (step S8). As a result, the frequency division ratio of the frequency division counter 2 is changed, and the accuracy of the basic timer pulse is improved.

次に、具体的な値を用いて処理動作を説明する。
まず、基準時刻取得間隔の初期値を２００秒（＝２０ｍ秒×１万）とする。この初期値は、次の基準時刻取得までの誤差を±１秒以内に収めるための値である。そして、２００秒後の誤差が＋１秒（＋０．５％）であったとすると、分周比を１Ｍ×１．００５＝１００５０００クロックに補正する。この時点で２００秒のスケールでは一見誤差の補正ができたように見えるが、実際には発振器の誤差は最大で＋０．５％であり実際の誤差の値は未知である。したがって、さらに基本タイマの１単位である±２０ｍ秒（２００秒±２０ｍ秒であるので±０．０１％）の誤差範囲の誤差を補正するために、次の基準時刻取得間隔を１万秒後（２０ｍ秒×５０万）とする。これも次の基準時刻取得までの誤差を±１秒以内に収めるための値である。 Next, the processing operation will be described using specific values.
First, the initial value of the reference time acquisition interval is set to 200 seconds (= 20 milliseconds × 10,000). This initial value is a value for keeping the error until the next reference time acquisition within ± 1 second. If the error after 200 seconds is +1 second (+ 0.5%), the frequency division ratio is corrected to 1M × 1.005 = 1005000 clocks. At this point, it seems that the error can be corrected at a scale of 200 seconds, but in reality, the error of the oscillator is + 0.5% at the maximum, and the actual error value is unknown. Therefore, in order to further correct the error in the error range of ± 20 msec, which is one unit of the basic timer (± 0.01% because it is 200 sec ± 20 msec), the next reference time acquisition interval is 10,000 seconds later. (20 milliseconds x 500,000). This is also a value for keeping the error until the next reference time acquisition within ± 1 second.

次に、１万秒後の誤差が−１秒（−０．０１％）であった場合、分周比を１００５０００×０．９９９９＝１００４８９９．５クロックとする。端数の０．５を切り上げるとすれば分周比は１００４９００クロックとなる。そして、５０万秒後の誤差が＋１秒（＋０．０００２％）であった場合は、分周比を１００４９００×１．０００００２＝１００４９０２．１クロックとし、端数の０．１を切り上げるとすれば分周比は１００４９０３クロックとなる。この時点で上記と同様に更に±２０ｍ秒（５０万秒で±２０ｍ秒なので±４×１０−６％）の誤差範囲の誤差が考えられるが、誤差が±１秒に収まるように次の取得時間を算出して更に分周比を補正しようとすると、次の取得時間２５００万秒後に−１秒（−４×１０−６％）あった場合、分周比は１００４９０３×（１−４×１０−８）＝１００４９０２．９６となり、分周比の設定可能能力を超えたため、この取得時間２５００万秒後の分周比修正は無意味となる。従って、上記取得時間５０万秒後に行った分周比修正で１００４９０３クロックを得た時点で分周比修正の処理を終了する。この処理によって、結果的に発振器１が有している誤差＋０．４９０３％に対して補正を行ったことになる。 Next, when the error after 10,000 seconds is −1 second (−0.01%), the frequency division ratio is set to 1005000 × 0.9999 = 1004899.5 clocks. If the fraction of 0.5 is rounded up, the frequency division ratio is 1004900 clocks. If the error after 500,000 seconds is +1 second (+ 0.0002%), the division ratio is set to 1004900 × 1.000002 = 1004902.1 clocks, and the fractional value is rounded up to 0.1. The frequency ratio is 10000303 clock. At this point, an error in the error range of ± 20 msec (± 4 × 10 −6 % because it is ± 20 msec for 500,000 seconds) is considered as above, but the next acquisition is made so that the error is within ± 1 sec. When calculating the time and further correcting the division ratio, if the next acquisition time is 25 million seconds and −1 second (−4 × 10 −6 %), the division ratio is 1000033 × (1−4 × 10 −8 ) = 1100602.96, which exceeds the ability to set the division ratio, so that the modification of the division ratio after 25 million seconds is meaningless. Therefore, the division ratio correction processing is terminated when 10000303 clocks are obtained by the division ratio correction performed after the acquisition time of 500,000 seconds. As a result of this processing, the error + 0.49033% of the oscillator 1 is corrected.

このように、本発明では補正の精度は発振器１ではなく分周カウンタ２によって決まり、発振器１に生じた誤差に基づいて、分周比を段階的に補正することによって時計の精度を次第に向上させることができる。もちろん、最初の基準時刻取得間隔を十分に長い時間（上記の例では１Ｍ秒）とすれば、一回の補正で補正作業を終了することができるが、この修正動作の間に生じる出力時刻のずれが大きくなるため、修正動作中に出力される時刻は実質的に使用することができない。しかし、本発明の修正方法を用いれば、修正動作中の出力誤差を１秒以内に収めるようにして、出力時刻を使用しながら修正動作を行うことができるため、製品出荷時の調整や使用開始前の修正動作を行う必要がない。   Thus, in the present invention, the accuracy of correction is determined not by the oscillator 1 but by the frequency dividing counter 2, and the accuracy of the timepiece is gradually improved by correcting the frequency dividing ratio stepwise based on the error generated in the oscillator 1. be able to. Of course, if the first reference time acquisition interval is set to a sufficiently long time (1 M seconds in the above example), the correction work can be completed by one correction, but the output time generated during this correction operation can be terminated. Since the deviation becomes large, the time output during the correction operation cannot be used substantially. However, if the correction method of the present invention is used, the output error during the correction operation can be kept within one second and the correction operation can be performed while using the output time. There is no need to perform the previous corrective action.

また、分周比補正部８が、図２に示すステップＳ３〜Ｓ８の処理動作を繰り返し行うことにより、時刻出力部５から出力される現在時刻の精度を向上させることが可能になる。また、基本タイマパルスの精度が向上することにより、基準時刻を取得する間隔を延ばすことが可能になるため、時刻サーバ６と時刻取得部７との間の通信トラフィックを低減することができる。   Further, the frequency division ratio correction unit 8 can repeatedly improve the accuracy of the current time output from the time output unit 5 by repeatedly performing the processing operations of steps S3 to S8 shown in FIG. Further, since the accuracy of the basic timer pulse is improved, it is possible to extend the interval for acquiring the reference time, so that the communication traffic between the time server 6 and the time acquisition unit 7 can be reduced.

なお、図１における処理部の機能を実現するためのプログラムをコンピュータ読み取り可能な記録媒体に記録して、この記録媒体に記録されたプログラムをコンピュータシステムに読み込ませ、実行することにより時計精度修正処理を行ってもよい。なお、ここでいう「コンピュータシステム」とは、ＯＳや周辺機器等のハードウェアを含むものとする。また、「コンピュータシステム」は、ホームページ提供環境（あるいは表示環境）を備えたＷＷＷシステムも含むものとする。また、「コンピュータ読み取り可能な記録媒体」とは、フレキシブルディスク、光磁気ディスク、ＲＯＭ、ＣＤ−ＲＯＭ等の可搬媒体、コンピュータシステムに内蔵されるハードディスク等の記憶装置のことをいう。さらに「コンピュータ読み取り可能な記録媒体」とは、インターネット等のネットワークや電話回線等の通信回線を介してプログラムが送信された場合のサーバやクライアントとなるコンピュータシステム内部の揮発性メモリ（ＲＡＭ）のように、一定時間プログラムを保持しているものも含むものとする。   1 is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read into a computer system and executed, thereby executing clock accuracy correction processing. May be performed. Here, the “computer system” includes an OS and hardware such as peripheral devices. The “computer system” includes a WWW system provided with a homepage providing environment (or display environment). The “computer-readable recording medium” refers to a portable medium such as a flexible disk, a magneto-optical disk, a ROM, and a CD-ROM, and a storage device such as a hard disk built in the computer system. Further, the “computer-readable recording medium” refers to a volatile memory (RAM) in a computer system that becomes a server or a client when a program is transmitted via a network such as the Internet or a communication line such as a telephone line. In addition, those holding programs for a certain period of time are also included.

また、上記プログラムは、このプログラムを記憶装置等に格納したコンピュータシステムから、伝送媒体を介して、あるいは、伝送媒体中の伝送波により他のコンピュータシステムに伝送されてもよい。ここで、プログラムを伝送する「伝送媒体」は、インターネット等のネットワーク（通信網）や電話回線等の通信回線（通信線）のように情報を伝送する機能を有する媒体のことをいう。また、上記プログラムは、前述した機能の一部を実現するためのものであっても良い。さらに、前述した機能をコンピュータシステムにすでに記録されているプログラムとの組み合わせで実現できるもの、いわゆる差分ファイル（差分プログラム）であっても良い。   The program may be transmitted from a computer system storing the program in a storage device or the like to another computer system via a transmission medium or by a transmission wave in the transmission medium. Here, the “transmission medium” for transmitting the program refers to a medium having a function of transmitting information, such as a network (communication network) such as the Internet or a communication line (communication line) such as a telephone line. The program may be for realizing a part of the functions described above. Furthermore, what can implement | achieve the function mentioned above in combination with the program already recorded on the computer system, and what is called a difference file (difference program) may be sufficient.

本発明の一実施形態の構成を示すブロック図である。It is a block diagram which shows the structure of one Embodiment of this invention. 図１に示す装置の動作を示すフローチャートである。It is a flowchart which shows operation | movement of the apparatus shown in FIG.

符号の説明Explanation of symbols

１・・・発振器、２・・・分周カウンタ、３・・・分周比レジスタ、４・・・メモリ、５・・・時刻出力部、６・・・時刻サーバ、７・・・時刻取得部、８・・・分周比補正部
DESCRIPTION OF SYMBOLS 1 ... Oscillator, 2 ... Frequency division counter, 3 ... Frequency division register, 4 ... Memory, 5 ... Time output part, 6 ... Time server, 7 ... Time acquisition Part, 8... Division ratio correction part

Claims (5)

外部から所定のタイミングで基準時刻を取得して、該基準時刻を現在時刻に更新する時計精度修正装置において、
所定の周波数のクロックパルスを出力する発振器と、
前記クロックパルスを分周比レジスタに設定されている分周比により分周して基本タイマパルスを出力する分周カウンタと、
前記基本タイマパルスを累積カウントして現在時刻を出力する時刻出力手段と、
取得した基準時刻と前記現在時刻と差から前記分周比を算出し、算出した分周比を前記分周比レジスタに設定する分周比補正手段と
を備えたことを特徴とする時計精度修正装置。 In a clock accuracy correction device that acquires a reference time at a predetermined timing from the outside and updates the reference time to the current time,
An oscillator that outputs clock pulses of a predetermined frequency;
A frequency dividing counter that divides the clock pulse by a frequency dividing ratio set in a frequency dividing ratio register and outputs a basic timer pulse;
Time output means for cumulatively counting the basic timer pulses and outputting the current time;
A clock accuracy correction comprising: frequency division ratio correction means for calculating the frequency division ratio from a difference between the acquired reference time and the current time, and setting the calculated frequency division ratio in the frequency division ratio register. apparatus. 前記分周比補正手段は、取得した基準時刻と前記現在時刻と差に基づいて、外部から基準時刻を取得するタイミングを決定することを特徴とする請求項１に記載の時計精度修正装置。   2. The timepiece accuracy correction apparatus according to claim 1, wherein the frequency division ratio correcting unit determines a timing for acquiring a reference time from the outside based on a difference between the acquired reference time and the current time. 前記分周比補正手段は、次回の基準時刻取得までの間に時刻出力手段から出力する現在時刻の誤差が所定値を超えない範囲で前記基準時刻を取得するタイミングを決定することを特徴とする請求項２に記載の時計精度修正装置。   The frequency division ratio correcting unit determines a timing for acquiring the reference time in a range in which an error of a current time output from the time output unit does not exceed a predetermined value until the next reference time acquisition. The timepiece accuracy correction apparatus according to claim 2. 所定の周波数のクロックパルスを出力する発振器と、前記クロックパルスを分周比レジスタに設定されている分周比により分周して基本タイマパルスを出力する分周カウンタと、前記基本タイマパルスを累積カウントして現在時刻を出力する時刻出力手段とを備え、外部から所定のタイミングで基準時刻を取得して、該基準時刻を現在時刻に更新する時計精度修正装置を制御する制御プログラムであって、
取得した基準時刻と前記現在時刻と差から前記分周比を算出し、算出した分周比を前記分周比レジスタに設定する分周比補正処理を
コンピュータに行わせることを特徴とする制御プログラム。 An oscillator that outputs a clock pulse of a predetermined frequency, a frequency dividing counter that divides the clock pulse by a frequency dividing ratio set in a frequency dividing ratio register and outputs a basic timer pulse, and accumulates the basic timer pulse A control program for controlling a clock accuracy correcting device that includes a time output unit that counts and outputs the current time, acquires a reference time from the outside at a predetermined timing, and updates the reference time to the current time,
A control program for calculating a frequency division ratio from a difference between an acquired reference time and the current time and causing a computer to perform frequency division ratio correction processing for setting the calculated frequency division ratio in the frequency division ratio register . 前記分周比補正処理は、取得した基準時刻と前記現在時刻と差に基づいて、外部から基準時刻を取得するタイミングを決定することを特徴とする請求項４に記載の制御プログラム。
5. The control program according to claim 4, wherein the division ratio correction processing determines a timing for acquiring a reference time from the outside based on a difference between the acquired reference time and the current time.
JP2004228126A 2004-08-04 2004-08-04 Clock accuracy correction device Expired - Fee Related JP4651988B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004228126A JP4651988B2 (en) 2004-08-04 2004-08-04 Clock accuracy correction device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004228126A JP4651988B2 (en) 2004-08-04 2004-08-04 Clock accuracy correction device

Publications (2)

Publication Number Publication Date
JP2006047101A true JP2006047101A (en) 2006-02-16
JP4651988B2 JP4651988B2 (en) 2011-03-16

Family

ID=36025816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004228126A Expired - Fee Related JP4651988B2 (en) 2004-08-04 2004-08-04 Clock accuracy correction device

Country Status (1)

Country Link
JP (1) JP4651988B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008051761A (en) * 2006-08-28 2008-03-06 Advanced Telecommunication Research Institute International Time synchronizing system
JP2009026377A (en) * 2007-07-19 2009-02-05 Clarion Co Ltd Onboard information playback device, portable information playback device and control method and control program of onboard information playback device
JP2009165069A (en) * 2008-01-10 2009-07-23 Oki Semiconductor Co Ltd Frequency correction circuit and clock installation using the circuit
JP2010527547A (en) * 2007-06-13 2010-08-12 ヴェーデクス・アクティーセルスカプ Hearing aid configured to issue a notification and notification issuing method
EA015659B1 (en) * 2008-04-14 2011-10-31 Пгс Оншор, Инк. Method for reducing cumulative timing error of oscillator frequency by adjusting clock frequency
WO2012176583A1 (en) * 2011-06-22 2012-12-27 東北電力株式会社 Multiple-point simultaneous-measurement method, multiple-point simultaneous-measurement system and internal clocks used therein for electric power station

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1091275A (en) * 1996-09-17 1998-04-10 Hitachi Ltd Automatic correction system for system clock
JP2000171577A (en) * 1998-12-08 2000-06-23 Hudson Soft Co Ltd Timepiece with accuracy improving function
JP2003207586A (en) * 2002-01-16 2003-07-25 Seiko Epson Corp Electronic equipment and its internal time information control method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1091275A (en) * 1996-09-17 1998-04-10 Hitachi Ltd Automatic correction system for system clock
JP2000171577A (en) * 1998-12-08 2000-06-23 Hudson Soft Co Ltd Timepiece with accuracy improving function
JP2003207586A (en) * 2002-01-16 2003-07-25 Seiko Epson Corp Electronic equipment and its internal time information control method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008051761A (en) * 2006-08-28 2008-03-06 Advanced Telecommunication Research Institute International Time synchronizing system
JP2010527547A (en) * 2007-06-13 2010-08-12 ヴェーデクス・アクティーセルスカプ Hearing aid configured to issue a notification and notification issuing method
JP2009026377A (en) * 2007-07-19 2009-02-05 Clarion Co Ltd Onboard information playback device, portable information playback device and control method and control program of onboard information playback device
JP2009165069A (en) * 2008-01-10 2009-07-23 Oki Semiconductor Co Ltd Frequency correction circuit and clock installation using the circuit
EA015659B1 (en) * 2008-04-14 2011-10-31 Пгс Оншор, Инк. Method for reducing cumulative timing error of oscillator frequency by adjusting clock frequency
WO2012176583A1 (en) * 2011-06-22 2012-12-27 東北電力株式会社 Multiple-point simultaneous-measurement method, multiple-point simultaneous-measurement system and internal clocks used therein for electric power station
JP2013029488A (en) * 2011-06-22 2013-02-07 Tohoku Electric Power Co Inc Multi-point simultaneous measurement method for electric power station, multi-point simultaneous measurement system, and internal clock used therefor
US9459591B2 (en) 2011-06-22 2016-10-04 CVEngineering Corporation Multipoint simultaneous measurement method and multipoint simultaneous measurement system in electric power station, and internal clock used therefor

Also Published As

Publication number Publication date
JP4651988B2 (en) 2011-03-16

Similar Documents

Publication Publication Date Title
TWI352817B (en) Methods and apparatus for obtaining gnss time
JP2624176B2 (en) Electronic clock and time correction method
JP4468089B2 (en) Time data acquisition device, computer program, and server
US10416706B2 (en) Calibration unit for calibrating an oscillator, oscillator arrangement and method for calibrating an oscillator
JP4651988B2 (en) Clock accuracy correction device
JP6704548B1 (en) Communication system, communication device and program
JP2017015399A (en) Electronic watch, and program
US7118269B2 (en) Method of correcting a real-time clock of an electronic apparatus
JP2012047705A (en) Time correction device and control method
JP2003207586A (en) Electronic equipment and its internal time information control method
JP4628440B2 (en) Device with clock generation function, reference frequency setting method, and reference frequency adjustment method
WO2021135303A1 (en) Fpga-based design method and device for equally dividing interval
JP6871048B2 (en) Time setting device, time setting method and program
JP2021189037A (en) Real time clock circuit, real time clock module, electronic apparatus and correction method for real time clock circuit
JPWO2009040945A1 (en) Monitoring device and program
KR100819735B1 (en) Computer system and control method thereof
JP2020150356A (en) Counter device, system time calculation device, information processing equipment, control method, time calculation method, and program
US20060153008A1 (en) Control device and control method capable of external synchronization
JP2007067676A (en) Temperature compensation method,correction value determining circuit and temperature compensated oscillation circuit
JP3990331B2 (en) Time correction control circuit, time correction control method, and time correction control program
JP2002216280A (en) Telemeter monitoring device
JP6529788B2 (en) Oscillator
CN116346275A (en) Pulse time calibration method, system, device and medium
JP2019129498A (en) Time distribution device and time adjustment method
JP2005069948A (en) Electronic timepiece, its stepping compensation method, and recording time correction method therefor

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070730

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100118

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100126

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100325

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100928

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101015

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20101207

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20101215

R150 Certificate of patent or registration of utility model

Ref document number: 4651988

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131224

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131224

Year of fee payment: 3

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131224

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees