JP2006042273A - Reception processing apparatus, receiving device, control program, and recording medium with control program recorded thereon - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reception processing apparatus, receiving device, control program and recording medium with control program recorded thereon by which a data output speed can be flexibly changed in accordance with the operating speed of a processing means such as a decoder. <P>SOLUTION: A data accumulation means 33 temporarily accumulates data received by a network connection means 32 before outputting to a decoder 37. A clock means 34 generates a clock to be used as a reference for determining time for data outputting to the decoder 37. A count means 35 counts clock information of the clock means 34 and outputs a count value adjusted according to predetermined rules to a data output means 36. On the basis of the count value counted by the count means 35 and time information contained in the received data, the data output means 36 outputs the data accumulated in the data accumulation means 33 to the decoder 37. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a reception processing device, a reception device, a control program, and a recording medium on which the control program is recorded, and in particular, a reception processing device, a reception device, a control program, and a control program used in a network such as an IP data communication network. The present invention relates to a recording medium that records

  In recent years, a technique for transferring real-time data such as AV (Audio Visual) data using an IP (Internet Protocol) packet in a home network has been spreading. When transferring by IP packet, there is a difference between the amount of data transmitted per unit time and the amount of data to be reproduced due to a clock shift between the encoder (encoding circuit) and the decoder (decoding circuit). This may cause problems such as degradation of image quality.

  FIG. 15 is a diagram showing a schematic configuration of an MPEG2-TS (Moving Picture Experts Group 2-Transport Stream) system generally used in real-time stream transmission of digital data.

  As illustrated in FIG. 15, a transmission device 200 and a reception device 300 are connected to the communication network 100. The communication network 100 is assumed to have a small delay variation (jitter). The transmission device 200 includes an encoder 201 and a transmission buffer 202. The receiving apparatus 300 includes a decoder 310 having a PLL (Phase Locked Loop) circuit 311.

  Transmitting apparatus 200 outputs data signal DT1 in accordance with transmission clock signal CLKs from transmission clock 210. The data signal DT1 is transferred to the receiving device 300 via the communication network 100. The data signal DT1 includes a synchronization signal called a PCR (Program Clock Reference) signal.

  Receiving device 300 receives data signal DT1 including the PCR signal, and extracts the value included in the PCR signal and the information about the time when the PCR signal was input inside decoder 310. The PLL circuit 311 reproduces the transmission clock signal CLKs as the clock signal of the decoder clock 312 based on the PCR information. As a result, it is possible to eliminate the deviation between the transmission side clock and the reception side clock.

  However, the above-described synchronization method using PCR information is an effective technique under the condition that the jitter in the communication network is within a certain range. Therefore, it is not effective in a network such as an IP data communication network. In order to solve the above problem, a method called an adaptive clock method is used (see, for example, Patent Document 1).

  FIG. 16 is a diagram showing a schematic configuration of an MPEG2-TS system when the adaptive clock method is used.

  As illustrated in FIG. 16, a transmission device 200 and a reception device 301 are connected to the communication network 101. The transmission apparatus 200 includes an encoder 201 and a transmission buffer 202, as in FIG. The reception device 301 includes a decoder 310 having a PLL circuit 311 and a reception buffer 320.

  Transmitting apparatus 200 outputs data signal DT2 in accordance with transmission clock signal CLKs from transmission clock 210. The data signal DT2 is transferred to the receiving device 301 via the communication network 101.

  The reception device 301 temporarily buffers the reception buffer 320 before receiving the data signal DT2 by the decoder 301. The reception buffer 320 outputs the buffered data signal DT2 to the decoder 310 in accordance with the reception clock signal CLKr from the reception clock 330. Note that the reception clock signal CLKr and the clock signal of the decoder clock 312 are generally separate clocks.

  With the above configuration, the clock signal of the decoder clock 312 is synchronized with the reception clock signal CLKr. Therefore, unlike the case of FIG. 15, the transmission clock signal CLKs and the reception clock signal CLKr are generally different. As a result, the data in the reception buffer 320 increases or decreases in the long term.

  In order to deal with such a problem, the reception buffer 320 varies the data output speed to the decoder 310, that is, the frequency of the reception clock signal CLKr, according to the buffer amount of the data signal DT2.

Specifically, when the buffer amount exceeds the upper limit threshold, the buffer overflow (overrun) phenomenon is avoided by increasing the data output speed. In addition, when the buffer amount falls below the lower limit threshold, the data output speed is reduced to avoid the phenomenon of data shortage (underrun).
JP 2002-165148 A

  The conventional transmission / reception system performs a process of switching the data output speed to a predetermined value regardless of the operation speed of the decoder.

  FIG. 17 is a diagram showing fluctuations in the data output speed to the decoder 310 when the adaptive clock method of FIG. 16 is used.

  As shown in FIG. 17, when the buffer amount of the reception buffer 320 exceeds the upper limit threshold, the data output speed to the decoder 310 is set to the high level. The data output speed at the high level is set to be always higher than the transmission speed based on the transmission clock signal CLKs. Conversely, when the buffer amount of the reception buffer 320 exceeds the lower threshold, the data output speed to the decoder 310 is set to a low level. The data output speed at the low level is set to be always lower than the transmission speed based on the transmission clock signal CLKs.

  As described above, when the data output speed to the decoder is switched in two steps of high and low, a significant change occurs in the data output speed at the switching timing. Therefore, it may not be applicable to a decoder that cannot quickly follow a large input change.

  The present invention has been made in order to solve the above-mentioned problems, and its object is to receive processing that can flexibly change the data output speed in accordance with the operating speed of the processing means such as a decoder. An apparatus, a receiving device, a control program, and a recording medium recording the control program are provided.

  The present invention is a reception processing device for receiving data via a communication network and processing the received data in a processing means, the data storage means for storing received data, and processing the received data output from the data storage means Data output means for performing output processing on the means. The data output means changes the output speed of the reception data output to the processing means according to the data processing speed of the processing means.

  Preferably, clock means for controlling the operation of the data output means is further provided. The data processing speed of the processing means is determined based on the difference between the operating frequency of the clock means and the clock frequency for controlling the processing means.

  Preferably, it further comprises counting means for counting the number of clocks of the clock means. The data output means, based on the time stamp value of the received data for correcting the processing speed of the processing means and the count value of the counting means when the time stamp is input to the processing means, Change the output speed.

  Preferably, the data output means changes the output speed of the reception data output to the processing means at every predetermined time interval.

  Preferably, the data output means changes the output speed of the reception data output to the processing means until the processing speed of the processing means reaches a predetermined speed.

  Preferably, the data output means changes the output speed of the reception data to be output to the processing means when the reception data stored in the data storage means reaches a predetermined amount.

  Preferably, the data output means performs a first correction process for controlling the output speed of the reception data output to the processing means to increase when the reception data stored in the data storage means reaches a predetermined upper limit value. And second correction processing means for controlling the output speed of the reception data output to the processing means to decrease when the reception data stored in the data storage means reaches a predetermined lower limit value.

  According to another aspect of the present invention, there is provided a receiving device for receiving data via a communication network, wherein a reception processing unit that receives reception data and a reception data output from the reception processing unit is decoded. And a decoder. The reception processing unit includes data storage means for storing received data, and data output means for outputting the received data output from the data storage means to the decoder. The data output means changes the output speed of the reception data output to the decoder according to the data processing speed of the decoder.

  According to another aspect of the present invention, there is provided a control program for receiving data via a communication network and processing the received data in the processing means, the step of storing the received data, and the processing means for storing the stored received data And a step of changing the output speed of received data to be output to the processing means in accordance with the data processing speed of the processing means.

  According to another aspect of the present invention, there is provided a computer-readable recording medium recording a control program for receiving data via a communication network and processing the received data in a processing unit, and storing the received data. And causing the computer to execute a step of outputting the accumulated received data to the processing means and a step of changing the output speed of the reception data output to the processing means in accordance with the data processing speed of the processing means.

  According to the present invention, it is possible to flexibly change the data output speed in accordance with the operation speed of the processing means such as a decoder.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  In the embodiment of the present invention, in the real-time communication via a communication network with a large delay variation, in order to avoid buffer overrun / underrun, output speed control by buffering (for example, adaptive clock method) is performed. think about. In such a case, a receiving apparatus capable of reducing the influence on the image quality and the like due to the change in the data output speed will be described below.

  In the embodiment of the present invention, an example of MPEG2 real-time stream transmission using RTP (Real Time Protocol) through an IP (Internet Protocol) network will be described. However, the present invention is not limited to this.

  FIG. 1 is a diagram schematically showing a configuration of a network system in which a receiving apparatus 12 according to an embodiment of the present invention operates.

  The network system is a network to which various household devices such as a television, a hard disk recorder (hereinafter referred to as HDR), and a digital tuner are connected. In the network system, for example, communication is performed using a network protocol such as IP.

  As shown in FIG. 1, a transmission device 11, a reception device 12, and devices 13 and 14 are connected to the communication network 10. The transmission device 11 performs real-time stream transmission with the reception device 12 via the communication network 10. As the transmission device 11, for example, a video, HDR, or digital tuner with a communication function can be considered. The receiving device 12 receives real-time data transmitted from the transmitting device 11 via the communication network 10. As the receiving device 12, for example, a television or a liquid crystal projector having a communication function can be considered. The devices 13 and 14 are other devices connected to the communication network 10.

  FIG. 2 is a block diagram illustrating a specific configuration of the transmission device 11 and the reception device 12 illustrated in FIG.

  With reference to FIG. 2, the transmission device 11 includes an encoder 21 and a transmission processing unit 24. The encoder 21 encodes a predetermined input in accordance with an encoding rule defined in MPEG2, and outputs MPEG2 data. The encoder 21 includes a clock unit 22 and an encoding unit 23. The clock means 22 counts the encoding time. The encoding means 23 encodes input data.

  The transmission processing unit 24 converts the data output from the encoder 21 into a format that can be transmitted on the network, and outputs the data to the communication network. The transmission processing unit 24 includes a processing unit 25 and a network connection unit 26. The processing means 25 adds a plurality of headers to the MPEG2 data output from the encoder 21. The network connection unit 26 outputs the IP packet generated by the processing unit 25 to the communication network. The network connection means 26 is, for example, an Ethernet (registered trademark) card.

  FIG. 3 is a diagram showing an example of a frame format of MPEG2 data to which a plurality of headers are added by the processing means 25.

  As shown in FIG. 3, the MPEG2 data includes an IP header, a TCP (Transmission Control Protocol) header, and an RTP header as an example. The RTP header includes a sequence number, a time stamp, and various other signals. The time stamp represents the output time to the decoder 37 of the receiving device 12.

  Returning to FIG. 2, the reception device 12 receives real-time stream data from the transmission device 11. The receiving device 12 includes a reception processing unit 31 and a decoder 37. The reception processing unit 31 receives data transmitted from the communication network. The reception processing unit 31 includes a network connection unit 32, a data storage unit 33, a clock unit 34, a count unit 35, and a data output unit 36.

  The network connection unit 32 is a unit that connects the communication network and the reception device 12 and receives data transmitted from the transmission device 12. The network connection means 32 is, for example, an Ethernet (registered trademark) card. The data storage means 33 includes a buffer for temporarily storing data received by the network connection means 32 before output to the decoder 37, and a control means for controlling the buffer.

  The clock means 34 generates a clock used as a reference for determining a data output time to the decoder 37. The counting means 35 counts the clock information of the clock means 34 and outputs a count value adjusted according to a predetermined rule to the data output means 36. The data output means 36 outputs the data accumulated in the data accumulation means 33 to the decoder 37 based on the count value counted by the counting means 35 and the time information included in the received data.

  The decoder 37 decodes the received data. The decoder 37 includes a decoding unit 38 and a clock unit 39. The decoding unit 38 decodes the MPEG2 data output from the data output unit 36. The clock means 39 generates clock information for reproducing the received data from the time information included in the data output from the data output means 36 and the timing at which the data is input to the decoder 37, and decodes it. To the converting means 38.

  FIG. 4 is a functional block diagram showing specific processing functions of the reception processing unit 31 shown in FIG.

  Referring to FIG. 4, reception processing unit 31 includes network connection means 32, data storage means 33, clock means 34, counting means 35, and data output means 36 as described in FIG. . The data storage means 33 has data reception processing means 41. The counting unit 35 includes a clock count processing unit 42. The data output unit 36 includes a buffering processing unit 43, a data output processing unit 44, a first correction unit 45, and a second correction unit 46.

  As shown in FIG. 4, each means of the reception processing unit 31 described in FIG. 2 has processing function means for causing each means to function inside, and the respective means operate in cooperation with each other. Reception processing is realized.

  When the reception processing unit 21 is activated, the data reception processing means 41, the clock count processing means 42, and the buffering processing means 43 are activated. The data reception processing means 41 and the clock count processing means 42 are always executed, and the buffering processing means 43 activates the data output processing means 44 when a predetermined condition is met. Further, the data output processing unit 44 activates the first correction unit 45 and the second correction unit 46 when a predetermined condition is met.

  Next, detailed operations when the receiving device 12 receives real-time data will be sequentially described with reference to flowcharts.

  FIG. 5 is a flowchart showing the reception processing operation of the data reception processing means 41 included in the data storage means 33.

  Referring to FIG. 5, when data reception processing unit 41 is activated, it is determined in step S502 whether data (next packet) has been received from network connection unit 32 or not. If the next packet has been received, the process proceeds to step S504. If the next packet has not been received, the determination process in step S502 is performed again. The determination process in step S502 is continued until the next packet is received.

  In step S504, the received data is written into the buffer of the data storage means 33. When the writing is completed, the process proceeds to step S506. In step S506, the buffer write position (buffer_tail) is advanced by one (see FIG. 9), and the time stamp value included in the RTP header of the received data is written in the variable ta_rtp_ts. When step S506 ends, a series of processing from step S502 is repeated.

  FIG. 6 is a flowchart showing the count processing operation of the clock count processing means 42 included in the counting means 35.

  Referring to FIG. 6, when the clock count processing means 42 is activated, the clock input from the clock means 34 is acquired in step S602. When the clock input is acquired, the variable C0 for counting the clock of the clock means 34 is incremented in step S604. In step S606, it is determined whether or not the clock correction value buf_adjust is zero.

  When buf_adjust is zero, the clock is not corrected. In step S616, the count information COUNT is incremented, and the process returns to step S602. When buf_adjust is not zero, the correction process 1 or the correction process 2 is being executed, and the count information COUNT is corrected. Specifically, in step S608, a clock correction period T is calculated.

  The clock correction value buf_adjust is the number of clocks to be corrected per second. For this reason, T = K / buf_adjust is the period for correction with respect to the number K that the reference clock is clocked up per second. The correction of the clock is performed once every time the input from the clock means 34 is performed T times.

  In step S610, it is determined whether it is time to correct the count value C0 of the reference clock. If it is not time to correct, the count information COUNT is incremented in step S616, and the process returns to step S602.

  If it is time to correct, it is determined in step S612 whether the value of the clock correction period T is greater or less than zero. Thus, it is determined whether to increase or decrease the count-up speed.

  If the value of the clock correction period T is greater than zero, it is determined that the count-up speed is to be slowed down, and the process returns to step S602 without incrementing the value of the count information COUNT. If the value of the clock correction period T is smaller than zero, it is determined that the count-up speed is increased. In step S614, the value of the count information COUNT is incremented by 2, and the process returns to step S602.

  FIG. 7 is a flowchart showing the buffering operation of the buffering processing means 43 included in the data output means 36.

  Referring to FIG. 7, when the buffering processing unit 43 is activated, it is determined in step S702 whether or not the first packet has been written in the buffer in the data storage unit 33. If the first packet has been written, the current count value acquired from the counting means 35 is written in the variable fr_rtp_ti in step S704. After writing the variable fr_rtp_ti, in step S706, the time stamp value included in the RTP header of the first packet is written in the variable fr_rtp_ts and the variable he_rtp_ts. Thereafter, in step S708, the output start time is calculated.

  The output start time (start_ti) is set so that a predetermined time (MAX_SAVE; see FIG. 10) elapses from the time (fr_rtp_ti) when the first packet is received. MAX_SAVE is normally set to a time corresponding to the maximum jitter assumed on the network (for example, 300 milliseconds). If the first packet has not been written in step S702 or the processing in step S708 is completed, the process proceeds to step S710.

  In step S710, it is determined whether the count value acquired from the counting unit 35 exceeds the output start time (start_ti). If the count value exceeds the output start time, the buffering process is terminated and the process proceeds to the data output process. If the count value does not exceed the output start time, the process returns to step S702 to repeat a series of processes. Note that once the processing of steps S704 to S708 is completed, the first packet is confirmed, so the determination processing in step S702 is always NO.

  FIG. 8 is a flowchart showing the reception processing operation of the data output processing means 44 included in the data output means 36.

  Referring to FIG. 8, when data output processing unit 44 is activated, in step S802, the head position of the buffer in data storage unit 33 (packet at the position of buffer_head) is extracted from the buffer. In step S804, the RTP time stamp of the extracted packet is compared with the count value acquired from the counting means 35, and it is determined whether or not the extracted packet has reached the output start time.

  If the extracted packet has reached the output start time, the extracted packet is written into the decoder 37 in step S806. If the extracted packet has not reached the output start time, the process of step S804 is repeated until the output start time is reached.

  When the packet is written in the decoder 37 in step S806, the read position (buffer_head) from the buffer is incremented (see FIG. 9) in step S808, and the time stamp value of the data of the first packet is written in the variable he_rtp_ts. Next, in step S810, it is determined whether or not the correction process 2 by the second correction unit 46 is continuing.

  If the correction process 2 is continuing (UNDER_REVISE = TRUE), the correction process 2 is executed in step S820. If the correction process 2 is not ongoing (UNDER_REVISE = FALSE), it is determined in step S812 whether or not the current buffer amount is smaller than the lower limit threshold (UNDER_ADJUST; see FIG. 10).

  When the current buffer amount is smaller than the lower limit threshold value, correction processing 2 is executed in order to avoid underrun in step S820. If the current buffer amount is not less than the lower limit threshold value, the process advances to step S814 to determine whether or not the correction process 1 by the first correction unit 45 is continuing.

  If the correction process 1 is continuing (OVER_REVISE = TRUE), the correction process 1 is executed in step S818. If the correction process 1 is not continuing (OVER_REVISE = FALSE), it is determined in step S816 whether or not the current buffer amount is larger than the upper limit threshold (OVER_ADJUST; see FIG. 10).

  If the current buffer amount is larger than the upper limit threshold value, correction processing 1 is executed in step S818 to avoid overrun. If the current buffer amount is not larger than the upper limit threshold value, the process returns to step S802 to continue the processing. Further, even after the correction process 1 in step S818 and the correction process 2 in step S820 are completed, the process returns to step S802 and the process is continued.

  FIG. 9 is a schematic diagram showing a write position (buffer_tail) and a read position (buffer_head) in the buffer of the data storage means 33.

  As described with reference to FIG. 5, after the writing of the received data to the buffer of the data storage unit 33 is completed, the writing position (buffer_tail) of the buffer is advanced by one. Further, as described with reference to FIG. 8, after the packet extracted from the received data is written to the decoder 37, the position of reading from the buffer of the data storage means 33 (buffer_head) is incremented.

  FIG. 10 is a diagram showing various predetermined values for the maximum buffer amount in the buffer of the data storage means 33.

  As shown in FIG. 10, the output start position (MAX_SAVE), the minimum value that varies with network jitter (UNDER_ADJUST), and the maximum value that varies with network jitter (OVER_ADJUST) are determined with respect to the maximum buffer amount. Note that the output start position (MAX_SAVE) in FIG. 10 is a buffer amount corresponding to the time corresponding to the maximum jitter described in FIG.

  FIG. 11 is a flowchart showing the correction process 1 of the first correction unit 45 included in the data output unit 36.

  The first correction unit 45 is activated when the buffer amount of the data storage unit 33 exceeds the upper limit threshold OVER_ADJUST. The first correction unit 45 executes a process for increasing the operating speed of the clock count unit 35 in order to avoid overrun.

  Referring to FIG. 11, when first correcting means 45 is activated, it is determined in step S902 whether correction process 1 is ongoing. If the correction process 1 is not continuing (OVER_REVISE = FALSE), it is determined that the correction process 1 will be started, and the process proceeds to step S904.

  In step S904, initialization is performed by substituting the predetermined value ΔF for the correction value buf_adjust of the clock. buf_adjust is a value referred to by the clock count processing means 42 and represents the number of clocks to be corrected per second. That is, the count information COUNT output from the count unit 35 is a value adjusted by buf_adjust per second with respect to the clock output from the clock unit 34. The data output means 36 outputs data to the decoder 37 based on the count information COUNT of the count means 35. Therefore, the current data output speed can be acquired from buf_adjust.

  The decoder 37 adjusts the operation speed of the clock output from the clock means 39 following the data output speed of the data output means 36. A certain amount of time is required for the operation speed of the clock means 39 to converge with respect to the change in the data output speed. Accordingly, it is possible to estimate the adjusted operation speed of the clock means 39 by evaluating the value of buf_adjust after a lapse of a predetermined time since the change of buf_adjust.

  In step S906, the number of execution loops of the correction process 1 is set. In step S906, since the correction process 1 has just started, the number of execution loops is set to 1. In step S908, a time for changing the correction value buf_adjust (for example, after 100 milliseconds) is set.

  As a result, the next correction value can be changed after the operating speed of the clock means 39 converges. As a result, it is possible to control the data output speed of the data output means 36 to vary within a predetermined range with respect to the operating speed of the clock means 39. In step S910, in order to show that the correction process 1 is continuing, a flag is set to OVER_REVISE = TRUE, and the process ends.

  On the other hand, if the correction process 1 is continuing in step S902 (OVER_REVISE = TRUE), it is determined in step S912 whether or not the next correction execution time has come. If the next correction execution time is not reached, the process is terminated. If the next correction execution time is reached, the clock correction value buf_adjust is increased by a predetermined value ΔF in step S914.

  In step S916, the number of execution loops of the correction process 1 is incremented. Next, in step S918, it is determined whether or not the number n of execution loops has reached the prescribed correction number N of the correction process 1. If the specified number of corrections N has been reached, a flag is set to OVER_REVISE = FALSE in step S920, and the correction process 1 ends. If the prescribed number of corrections N has not been reached, the execution time of the next correction process 1 is set in step S922, and the process ends.

  FIG. 12 is a flowchart showing the correction process 2 of the second correction unit 46 included in the data output unit 36.

  The second correction means 46 is activated when the buffer amount of the data storage means 33 falls below the lower limit threshold UNDER_ADJUST. The second correction means 46 executes a process for reducing the operating speed of the clock count means 35 in order to avoid underrun.

  Referring to FIG. 12, when the second correction means 46 is activated, it is determined in step S1002 whether or not the correction process 2 is continuing. If the correction process 2 is not continuing (UNDER_REVISE = FALSE), it is determined that the correction process 2 will be started, and the process proceeds to step S1004.

  In step S1004, initialization is performed by substituting a predetermined value −ΔF for the correction value buf_adjust of the clock. buf_adjust is a value referred to by the clock count processing means 42 and represents the number of clocks to be corrected per second. In step S1006, since the correction process 2 has just started, the number of execution loops is set to 1. In step S1008, a time for changing the correction value buf_adjust next (for example, after 100 milliseconds) is set.

  As a result, the correction value of the clock per unit time can be changed at a predetermined time period. As a result, it is possible to perform control to change the operating speed of the clock means 39 step by step in a predetermined number of times. In step S1010, in order to indicate that the correction process 2 is continuing, a flag is set to UNDER_REVISE = TRUE, and the process ends.

  On the other hand, if the correction process 2 is continuing in step S1002 (UNDER_REVISE = TRUE), it is determined in step S1012 whether or not the next correction execution time has come. If the next correction execution time is not reached, the process is terminated. If it is the next correction execution time, the clock correction value buf_adjust is decreased by a predetermined value ΔF in step S1014.

  In step S1016, the number of execution loops of the correction process 2 is incremented. Next, in step S1018, it is determined whether or not the number n of execution loops has reached the prescribed correction number N of the correction process 2. If the specified number of corrections N has been reached, a flag is set to UNDER_REVISE = FALSE in step S1020, and the correction process 2 is terminated. If the specified number of corrections N has not been reached, the execution time of the next correction process 2 is set in step S1022, and the process ends.

When the operating frequency of the clock means 39 is 27 MHz (27 × 10 ⁶ Hz), for example, if the clock is changed by 500 nsec (500 × 10 ⁻⁹ sec) every 100 msec (0.1 sec), the correction value of the clock ΔF is
ΔF = 27 × 10 ⁶ × 500 × 10 ⁻⁹ /0.1=135 (Hz)
Is calculated. Further, assuming that the error of the transmission clock is 27 MHz ± 30 ppm defined by MPEG2, the operating frequency of the clock means 39 is (27M + 810) Hz at the fastest and (27M−810) Hz at the slowest. It becomes. Therefore, the difference in operating frequency of the clock means 39 is 1620 Hz at the maximum.

  The difference in operating frequency of the clock means 39 is divided by the clock correction value ΔF. Therefore, if the specified number of corrections N is set to N = 1620/135 = 12, for example, the receiving apparatus 12 operates without problems in the environment of the embodiment of the present invention.

  FIG. 13 is a diagram showing an example of a computer system for realizing the functions of the receiving device 12 according to the embodiment of the present invention.

  The computer system shown in FIG. 13 includes a computer main body 71, a display device 72, an FD drive 73 in which an FD (Flexible Disk) 74 is mounted, a keyboard 75, a mouse 76, and a CD-ROM (Compact Disc-Read Only). A CD-ROM device 77 on which a (Memory) 78 is mounted, and a network communication device 79.

  A program for realizing the function of the receiving device 12 (hereinafter referred to as a control program) is supplied by a recording medium such as the FD 74 or the CD-ROM 78. When the control program is executed by the computer main body 71, the above-described reception process is performed. Further, the control program may be supplied from the other computer to the computer main body 71 via the communication line and the network communication device 79.

  The recording medium is not limited to the FD 74 and the CD-ROM 78, but may be a magnetic tape, an MO (Magnetic Optical disk), an MD (Mini Disc), a DVD (Digital Versatile Disc), an IC (Integrated Circuit) card, or the like. There may be.

  FIG. 14 is a diagram showing fluctuations in the data output speed to the decoder 37 of the receiving device 12 according to the embodiment of the present invention.

  As shown in FIG. 14, in receiving apparatus 12 according to the embodiment of the present invention, an upper limit is set for a single change width of the data output speed to decoder 37. Further, the level of the next data output speed is determined based on the data output speed of the previous level.

  By repeating the change of the output speed a plurality of times, the data output speed to the decoder 37 is controlled so as to be faster (or slower) than the transmission speed based on the reception clock of the reception device 12. A specific method for controlling the data output speed to the decoder 37 is as described in the flowcharts of FIGS.

  By controlling the data output speed to the decoder 37 as described above, it is possible to eliminate a change in the data output speed that deviates from the demand of the decoder. As a result, it is possible to prevent an abnormal operation of the decoder due to image quality degradation or the like. Also, buffering control can be applied to a decoder that is limited in local frequency fluctuations. In the embodiment of the present invention, an example is shown in which the correction value of the clock in one correction is fixed to ΔF. However, ΔF may be varied based on the current operation speed of the decoder. Good.

  As described above, according to the embodiment of the present invention, an upper limit is set for a single change width of the data output speed to the decoder, and the level of the next data output speed is determined based on the data output speed of the previous level. Therefore, it is possible to eliminate a change in the data output speed that deviates from the requirement of the decoder, and to prevent an abnormal operation of the decoder due to image quality degradation or the like.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include meanings equivalent to the scope of claims for patent and all modifications within the scope.

It is the figure which showed schematically the structure of the network system with which the receiver 12 by embodiment of this invention operate | moves. FIG. 2 is a block diagram illustrating specific configurations of a transmission device 11 and a reception device 12 illustrated in FIG. 1. It is the figure which showed an example of the frame format of MPEG2 data to which the some header was added by the process means 25. FIG. FIG. 3 is a functional block diagram illustrating specific processing functions of a reception processing unit 31 illustrated in FIG. 2. 5 is a flowchart showing a reception processing operation of data reception processing means 41 included in the data storage means 33. 4 is a flowchart showing a count processing operation of a clock count processing means 42 included in the counting means 35. 4 is a flowchart showing a buffering operation of a buffering processing unit 43 included in the data output unit 36. 4 is a flowchart showing a reception processing operation of a data output processing unit 44 included in the data output unit 36. 6 is a schematic diagram showing a write position and a read position in a buffer of the data storage means 33. FIG. It is the figure which showed the various predetermined value with respect to the maximum buffer amount in the buffer of the data storage means. 5 is a flowchart showing a correction process 1 of a first correction unit 45 included in a data output unit 36. It is the flowchart which showed the correction process 2 of the 2nd correction means 46 which the data output means 36 has. It is the figure which showed an example of the computer system for implement | achieving the function of the receiver 12 by embodiment of this invention. It is the figure which showed the fluctuation | variation of the data output speed to the decoder 37 of the receiver 12 by embodiment of this invention. It is the figure which showed the schematic structure of the MPEG2-TS system generally used by the real-time stream transmission of digital data. It is the figure which showed the schematic structure of the MPEG2-TS system at the time of using an adaptive clock method. FIG. 17 is a diagram showing fluctuations in the data output speed to the decoder 310 when the adaptive clock method of FIG. 16 is used.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Communication network 11,200 Transmitter, 12,300,301 Receiver, 13,14 Equipment, 21,201 Encoder, 22,34,39 Clock means, 23 Encoding means, 24 Transmission processing part, 25 Processing means, 26, 32 Network connection means, 31 reception processing section, 33 data storage means, 35 count means, 36 data output means, 37, 310 decoder, 38 decoding means, 41 data reception processing means, 42 clock count processing means, 43 buffer Ring processing means, 44 Data output processing means, 45 First correction means, 46 Second correction means, 71 Computer main body, 72 Display device, 73 FD drive, 74 FD, 75 Keyboard, 76 Mouse, 77 CD-ROM device, 78 CD-ROM, 79 Work communication device, 100 communication network, 202 transmission buffer, 210 transmit clock, 311 PLL circuit, 312 a decoder clock, 320 reception buffer 330 receives the clock.

Claims (10)

A reception processing device that receives data via a communication network and processes the received data in a processing means,
Data storage means for storing the received data;
Data output means for outputting the received data output from the data storage means to the processing means;
The reception processing apparatus, wherein the data output means changes an output speed of the reception data output to the processing means according to a data processing speed of the processing means. Clock means for controlling the operation of the data output means,
The reception processing apparatus according to claim 1, wherein the data processing speed of the processing unit is determined based on a difference between an operating frequency of the clock unit and a clock frequency for controlling the processing unit. A counter for counting the number of clocks of the clock means;
The data output means is based on the time stamp value of the received data for correcting the processing speed of the processing means and the count value of the counting means when the time stamp is input to the processing means. The reception processing apparatus according to claim 1, wherein an output speed of the reception data output to the means is changed.   The reception processing apparatus according to claim 1, wherein the data output unit changes an output speed of the reception data to be output to the processing unit at predetermined time intervals.   The reception processing apparatus according to claim 4, wherein the data output means changes an output speed of the reception data output to the processing means until a processing speed of the processing means reaches a predetermined speed.   4. The data output unit according to claim 1, wherein the data output unit changes an output speed of the reception data output to the processing unit when the reception data stored in the data storage unit reaches a predetermined amount. The reception processing device according to 1. The data output means includes
First correction processing means for controlling the output speed of the reception data output to the processing means to increase when the received data stored in the data storage means reaches a predetermined upper limit;
Second correction processing means for controlling the output speed of the reception data output to the processing means to decrease when the reception data stored in the data storage means reaches a predetermined lower limit value. The reception processing device according to claim 6. A receiving device for receiving data via a communication network,
A reception processing unit for receiving the received data;
A decoder for decoding the received data output from the reception processing unit,
The reception processing unit
Data storage means for storing the received data;
Data output means for outputting the received data output from the data storage means to the decoder;
The receiving device, wherein the data output means changes an output speed of the reception data to be output to the decoder according to a data processing speed of the decoder. A control program for receiving data via a communication network and processing the received data in a processing means,
Storing the received data;
Outputting the stored received data to the processing means;
A control program for executing a step of changing an output speed of the reception data output to the processing means according to a data processing speed of the processing means.   A computer-readable recording medium on which the control program according to claim 9 is recorded.

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