JP2006041760A - Optical signal latch circuit and optical signal latch array - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical signal latch circuit capable of reducing the mounting area sharply, and to provide an optical signal latch array employing it. <P>SOLUTION: A switching element TG for receiving input is provided on the input side of one inverter (input section inverter) INV<SB>1</SB>in a latch circuit where two inverters INV<SB>1</SB>and INV<SB>2</SB>are connected in loop. A photodiode PD is connected in reverse bias with the connection node (input node) IN of the switching element TG for receiving input and the input section inverter INV<SB>1</SB>. A refresh switching element M<SB>1</SB>for switching the reverse bias refresh voltage Vcc being applied to a photodiode PD on/off is provided. Since the voltage at the input node IN of the photodiode PD is applied directly to the input section inverter INV<SB>1</SB>not through a buffer, mounting area can be reduced sharply. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an optical signal latch circuit that converts an input optical signal into an electrical digital signal and latches the value, and is particularly suitable for mounting on an optically reconfigurable gate array or the like that requires a small mounting area. The present invention relates to an optical signal latch circuit.

  In recent years, research and development of optically reconfigurable gate arrays (ORGA) have been promoted as techniques for dramatically reducing the reconfiguration time of the logical structure of a circuit (for example, Patent Documents 1 to 4). reference). The optically reconfigurable gate array has two parts: an optical unit that outputs information on the logical structure of the circuit as an optical signal pattern, and a VLSI unit that configures the logical structure of the circuit according to the optical signal pattern. This is a device that reconfigures the logical structure of the VLSI unit in parallel with the optical signal pattern from the unit.

  In these optically reconfigurable gate arrays, optical signal latch circuits including photodiodes are provided at various locations in a chip (logic circuit chip) on which a logic circuit as a VLSI portion is mounted. The optical signal pattern including the logic circuit configuration information is converted into an electrical signal by the photodiode of the optical signal latch circuit. The logic circuit configuration information thus input is held in a latch circuit provided in the optical signal latch circuit. Then, the logic circuit is reconfigured by switching the circuit connection in accordance with the logic circuit configuration information held in the latch circuit.

As the configuration of the latch circuit, for example, those described in Patent Documents 5 to 7 are known, and these are widely used in various circuits. FIG. 6 is a diagram illustrating a circuit configuration of an optical signal latch circuit configured by applying a conventional latch circuit. When writing an optical signal, first refresh signal (¬REFRESH) and 0 level, the transistor M ₁ for refreshing the on state. As a result, the refresh voltage Vcc is applied to the photodiode PD. In the present specification, a signal with the symbol “¬” represents a negative logic signal, and in the drawings, an overline is added to the signal name. Since the photodiode PD is reverse-biased, the photodiode PD functions as a capacitor and charges are accumulated.

Next, refresh signal (¬REFRESH) and 1 level to turn OFF the transistor M _1. At this time, the photodiode PD holds charge due to its capacitance, and the cathode-side node IN holds 1 level voltage.

  In this state, an optical signal is input to the photodiode PD. When the optical signal is 1, the photodiode PD is irradiated with light, the photodiode PD is discharged, and the voltage at the node IN becomes 0 level. When the optical signal is 0, the photodiode PD is not irradiated with light, and the voltage at the node IN is maintained at 1 level. Therefore, the voltage at the node IN is an inverted value of the optical signal.

The voltage of the node IN is input to the transmission gate TG via the buffer BUFF. Transmission gate is constituted by the pMOS transistor _{M 2} and the nMOS transistor _{M 3} Prefecture, each transistor, the gate signal (¬GATE, GATE) is input. The output side of the transmission gate TG is connected to an input terminal of an inverter INV ₁ of a latch formed by connecting _two inverters INV ₁ and INV ₂ in a loop.

When the voltage of the node IN is held in the latch, the gate signal (GATE) is set to 1 level. At this time, transmission gate is turned on, the output of the buffer BUFF is applied to the input terminal of the inverter INV _1. Here, the driving capability of the buffer BUFF is constituted larger than the driving capability of the inverter _INV 1, INV _2. Therefore, the input voltage of the inverter INV ₁ is forced to be the output voltage of the buffer BUFF. When the input to the latch is completed, the gate signal (GATE) is set to 0 level. Thereby, the voltage of the node IN is held in the latch.

  The voltage held in the latch is taken out as a holding signal CS from the output terminal of the inverter INV1. Since the holding signal CS is an inverted value of the voltage at the node IN, the value of the optical signal input to the photodiode PD is output as the holding signal CS.

As described above, when the conventional latch circuit is used, the output of the photodiode PD is once received by the buffer BUFF, and then the output is input to the latch via the transmission gate TG at the subsequent stage.
JP 2002-353317 A US Pat. No. 5,959,747 US Pat. No. 6,057,703 US Pat. No. 6,072,608 Japanese Patent Laid-Open No. 8-37449 Japanese Patent Laid-Open No. 5-26800 JP-A-11-97984

  By the way, as in an optically reconfigurable gate array (see Patent Documents 1 to 4), a large number of optical signal latch circuits are provided in a chip on which a logic circuit is mounted, and the optical signal is directly applied to the chip by irradiating the chip with the optical signal. In an input element, it is necessary to mount an extremely large number of optical signal latch circuits in a chip. Therefore, in such an element, since the optical signal latch circuit occupies a large part of the mounting area of the entire chip, it is extremely important to reduce the mounting area of each optical signal latch circuit as much as possible in order to improve the gate density. It is a difficult task.

  However, in the optical signal latch circuit configured by applying the above conventional latch circuit, the phototransistor itself does not have the drive capability to drive the inverter, so there is a buffer that always inputs the output of the phototransistor to the latch circuit. Necessary. Accordingly, an extra mounting area for mounting the buffer is required, which hinders the reduction of the mounting area of the entire optical signal latch circuit.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an optical signal latch circuit and an optical signal latch array using the optical signal latch circuit capable of significantly reducing the mounting area as compared with the prior art.

  The first configuration of the optical signal latch circuit according to the present invention includes a latch circuit in which an even number of inverters are connected in a loop, and one inverter in the latch circuit (hereinafter referred to as “input unit inverter”). An input receiving switching element that is provided on the input side and disconnects the loop of the latch circuit, and a connection node (hereinafter referred to as “input node”) between the input unit inverter and the input receiving switching element. A bias-connected photodiode and a refresh switching element for turning on and off a refresh voltage in a reverse bias direction applied to the photodiode are provided.

  According to this configuration, when the value of the optical signal is latched in the optical signal latch circuit, first, the input receiving switching element is turned off and the loop of the latch circuit is cut off. Then, the refresh transistor is turned on, and a refresh voltage in the reverse bias direction is applied to the photodiode. As a result, the voltage between both terminals of the photodiode becomes a refresh voltage, and charges are accumulated in the capacitor of the photodiode.

  In this state, an optical signal is input to the photodiode. When the optical signal is 1, the photodiode is irradiated with light, and the photodiode is discharged. Accordingly, the logic level of the connection node (hereinafter referred to as “input node”) between the photodiode and the refresh switching element is inverted. On the other hand, when the optical signal is 0, the photodiode is not irradiated with light, so that the logic level of the input node is maintained.

  The voltage of the input node is directly input to the input unit inverter. At this time, since the input receiving switching element is in the OFF state and the loop of the latch circuit is in the disconnected state, each inverter in the latch circuit is driven by the input node voltage of the photodiode, and the logic level is determined.

  After the logic level of each inverter is determined, the input receiving switching element is turned on, and the loop of the latch circuit is connected. Thereby, the logic level of the optical signal is stably latched by the latch circuit.

  As described above, in the present invention, the input node voltage of the photodiode is directly input to the input unit inverter without passing through the buffer, so that the mounting area can be significantly reduced as compared with the conventional case.

  Here, a transmission gate, a MIS (Metal Insulator Semiconductor) switch (including a MOS (Metal Oxide Semiconductor) switch), etc. can be used as the “input receiving switching element” and the “refresh switching element”. . Although the number of inverters constituting the latch circuit is not particularly limited as long as it is an even number, it is preferably two or four from the viewpoint of reducing the mounting area of the optical signal latch circuit. Although the circuit configuration of the inverter is not particularly limited, it is preferable to use a CMIS (Complementary Metal Insulator Semiconductor) type inverter that can reliably transmit a logical value and has a small mounting area.

  A second configuration of the optical signal latch circuit according to the present invention is characterized in that, in the first configuration, the latch circuit is formed by connecting two inverters in a loop shape.

  In particular, by using two inverter loops as the latch circuit, the mounting area of the optical signal latch circuit can be minimized.

  A third configuration of the optical signal latch circuit according to the present invention is the same as that of the first or second configuration, except that one of the inverters in the latch circuit is connected to the output receiving switching element on the output side. Each of the MIS transistors has a gate terminal connected to the output terminal of the preceding inverter, a drain terminal connected to the input terminal of the input unit inverter via the input receiving switching element, A voltage corresponding to the same logical value as the logical value of the input node when the refresh voltage is applied between both terminals of the photodiode is applied to the source terminal.

  With this configuration, the inverter having the input receiving switching element connected to the output side is replaced with one MIS transistor (including a MOS transistor), so that the mounting area of the optical signal latch circuit can be further reduced. it can.

  Since the “ON state occurs when a refresh voltage is applied between both terminals of the photodiode”, the logical value of the input node when the refresh voltage is applied between both terminals of the photodiode is 1. In this case, the p-type is used for the MIS transistor, and in the case of 0, the n-type is used for the MIS transistor.

  The first configuration of the optical signal latch array according to the present invention is a latch circuit in which an even number of inverters are connected in a loop and an input of one inverter in the latch circuit (hereinafter referred to as “input unit inverter”). And a reverse bias applied to a connection node between the input inverter and the input reception switching element (hereinafter referred to as “input node”). A plurality of optical signal latch circuits each including a connected photodiode and a refresh switching element that turns on and off a refresh voltage in a reverse bias direction applied to the photodiode, and a switching element (hereinafter referred to as a “block block”). A refresh switching element ”) is connected in series with a reverse bias connection. And a gate opening signal including an output buffer circuit having an input terminal connected to a connection node between the refresh photodiode and the block refresh switching element. And a switching circuit for receiving an input of each of the optical signal latch circuits is opened and closed by an output of an output buffer circuit of the gate opening signal generation circuit.

  In an optically reconfigurable gate array or the like, an optical signal may be input to the entire chip, but in many cases, an optical signal is input only to some circuit blocks of the chip. In such a case, by using the gate opening signal generation circuit, by turning off only the input receiving switching element of the optical signal latch circuit of the circuit block for inputting the optical signal, the optical signal is transmitted only to the necessary circuit block. It is possible to latch and mask the unnecessary circuit blocks so that the data latched by the irradiation light is not lost. In addition, selection of which circuit block is to be written can be performed by inputting an optical signal to the refresh photodiode.

  A second configuration of the optical signal latch array according to the present invention is characterized in that, in the first configuration, the latch circuit has two inverters connected in a loop.

  A third configuration of the optical signal latch array according to the present invention is the same as the first or second configuration, except that one of the inverters in the latch circuit is connected to the output receiving switching element on the output side. Each of the MIS transistors has a gate terminal connected to the output terminal of the preceding inverter, a drain terminal connected to the input terminal of the input unit inverter via the input receiving switching element, A voltage corresponding to the same logical value as the logical value of the input node when the refresh voltage is applied between the two terminals of the photodiode is applied to the source terminal, and the refresh is performed between the two terminals of the photodiode. It is characterized in that it is turned on when a voltage is applied.

  As described above, according to the optical signal latch circuit of the present invention, the input node voltage of the photodiode is directly input to the first inverter without passing through the buffer. It can be made smaller.

  Further, according to the optical signal latch array of the present invention, by using the gate opening signal generation circuit, the optical signal is latched only in the necessary circuit block, and the unnecessary circuit block is latched by the light sneak in error. The masked data can be masked so that it is not lost.

  In addition, the optical reconfiguration gate array irradiates the entire area of the chip with a multiple pattern of optical signals, and only the circuit block to be reconfigured at a certain point in time, only the optical signal belonging to the circuit block in the multiple pattern Can be used for the purpose of not latching the optical signal for other circuit blocks. Thereby, one multiplex pattern can be used as circuit reconfiguration information of a plurality of circuit blocks at a plurality of timings, and the optical memory can be effectively used.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  1 is a diagram illustrating a circuit configuration of an optical signal latch circuit according to a first embodiment of the present invention. FIG. 1A shows an inverting input type configuration, and FIG. 1B shows a non-inverting input type configuration.

In FIG. 1, the optical signal latch circuit according to this embodiment includes two inverters INV ₁ and INV ₂ , a transmission gate TG that is an input receiving switching element, a photodiode PD, and a pMOS type that is a refresh switching element. and it includes a transistor _{M 1.} Also, transmission gate TG is composed of pMOS transistor _{M 2} and an nMOS transistor _{M 3} Prefecture.

Inverter output side (input inverter) INV ₁ is connected to the input side of the inverter INV _2, the output side of the inverter INV ₂ are connected to the input side of the inverter INV ₁ through the transmission gate TG, the inverters INV ₁ , INV ₂ and the transmission gate TG form a loop-shaped latch circuit.

Photodiode PD is reverse biased connected to the input side of the inverter INV _1. Further, a refresh switching element (transistor M ₁ ) for turning on and off a refresh voltage in the reverse bias direction applied to the photodiode PD is connected to the input side of the inverter INV ₁ . Hereinafter, the node on the input side of the inverter INV ₁ to which the photodiode PD and the transistor M ₁ are connected is referred to as an “input node” and is represented by the symbol “IN”.

In the case of the inverting input type (FIG. 1A), the anode of the photodiode PD is grounded and the cathode is connected to the input node IN. The drain of the transistor M ₁ is connected to the input node IN, the source of the transistor M ₁ is connected to a power supply voltage.

On the other hand, in the case of the non-inverting input type (FIG. 1B), the cathode of the photodiode PD is connected to the power supply voltage, and the anode is connected to the input node IN. The source of the transistor M ₁ is connected to the input node IN, a drain of the transistor M ₁ is grounded.

The gate of the transistor M _1, the refresh signal (¬REFRESH) is input. The gate signals (¬GATE, GATE) are input to the transistors M ₂ and M ₃ of the transmission gate TG.

The output of the latch circuit is taken out from the output side of the inverter INV ₁ or INV ₂ . If the inverting input type (FIG. 1 (a)), the non-inverting output from the output side of the inverter INV ₁ to (CS), it is possible to take out the inverted output from the output side of the inverter INV ₂ (¬CS). On the other hand, if the non-inverting input type (FIG. 1 (b)), the non-inverting output from the output side of the inverter INV ₂ a (CS), it is possible to take out the inverted output from the output side of the inverter INV ₁ (¬CS).

  FIG. 2 is a timing chart showing the operation of the inverting input type optical signal latch circuit shown in FIG. Since the operation of the non-inverting input type optical signal latch circuit is the same as that of the inverting input type optical signal latch circuit, only the operation of the inverting input type optical signal latch circuit will be described here as a representative.

  As an initial state, it is assumed that the gate signal (GATE) is 1 level (¬GATE is 0 level), the refresh signal (¬REFRESH) is 1 level, and the optical signal is OFF.

Before entering the optical signal, at time t _1, first gate signal (GATE) is set to 0 level. At this time, the transmission gate TG is turned off, and the loops of the inverters INV ₁ and INV ₂ are disconnected.

Then, at time _{t 2, the} refresh signal (¬REFRESH) and 0 levels. Thus, the transistor _{M 1} is turned on, the voltage of the input node IN is the power supply voltage Vcc (i.e., 1 level). Accordingly, the non-inverted output (CS) becomes 0 and the inverted output (¬CS) becomes 1.

Then, at time _{t 3,} back into the 1-level refresh signal (¬REFRESH). As a result, although the input of the power supply voltage Vcc to the photodiode PD is completed, the voltage across the photodiode PD is kept at Vcc by the charge stored in the capacitor of the photodiode PD.

Then, an optical signal is input to the photodiode. In the example of FIG. 2, 1 is input as an optical signal from time t _3. As a result, the photodiode PD becomes conductive, the stored charge is discharged, and the voltage at the input node IN becomes 0 level. Accordingly, the non-inverted output (CS) is 1 and the inverted output (¬CS) is 0.

Inverted output (CS) is 1, after inverting output (¬CS) is established to 0, the gate signal is 1 level at time t _4. As a result, the transmission gate TG is turned on, and the loops of the inverters INV ₁ and INV ₂ are connected. When the loops of the inverters INV ₁ and INV ₂ are connected, this loop functions as a latch circuit, and the input value of the optical signal is stably held.

As described above, according to the optical signal latch circuit of the present embodiment, the input node voltage of the photodiode PD is directly input to the inverter INV ₁ without passing through the buffer. It can be made smaller.

In the example of FIG. 1, but using transmission gates TG as input reception switching element, the input reception switching element FIGS. 3 (a) or FIG. 3 MOS switch as shown in (b) M ₂ May be used. Further, the switching element (MOS transistor M ₆ ) shown in FIG. 3 or FIG. 3B can be used instead of the inverter INV ₂ . As a result, the mounting area of the optical signal latch circuit can be further reduced.

In the case of the optical signal latch circuit shown in FIG. 3, the MOS transistor M ₆ does not completely transmit the inversion of the output logic value of the inverter (input inverter) INV _{1 in} the preceding stage.

That is, when the refresh voltage Vcc is applied between both terminals of the photodiode PD, the output logic value of the inverter INV ₁ is an inversion of the logic value of the input node IN. In this case, MOS transistor M ₆ is turned on, its drain terminal functions as an inverter output voltage corresponding to the same logical value as the logical value of the input node IN is. On the other hand, when in the state in which the photodiode PD is discharged, MOS transistor M ₆ is turned off, the drain terminal becomes a high impedance state. Therefore, in this case, the inversion of the output logic value of the inverter INV ₁ is not transmitted.

However, when the refresh is by the refresh signal (¬REFRESH), because always refresh voltage Vcc between both terminals of the photodiode PD is applied, the logical value of the drain terminal of the MOS transistor M ₆ is the input node IN The logical value is the same as the logical value. Then, the value of the optical signal input to the photodiode PD is equal 0 (unirradiated), the logical value of the drain terminal of the MOS transistor M ₆ is maintained. Therefore, when the MOS switch M ₂ in this state on (conducting state), the loop connection of the latch circuit, data is in a state of being stably latch. On the other hand, when the value of the optical signal input to the photodiode PD 1 (irradiation), the photodiode PD is discharged and the drain terminal of the MOS transistor M ₆ is in a high impedance state. In this case, the stray capacitance of the wiring between the MOS transistor _{M 6} and the MOS switch _{M 2,} the drain terminal of the MOS transistor _{M 6} is maintained at the logical value of the refresh. However, the stray capacitance so much smaller than the capacitors included in the photodiode PD, the MOS switch M ₂ on (conductive state) Tosureba logical value is inverted. In this case, MOS loop portions at the latch circuit of the transistor M ₆ is in a state of being cut, because the potential difference between the terminals of the photodiode PD is zero, this state is stably maintained.

  Therefore, an optical signal can be stably latched also by a circuit as shown in FIG. 3A or 3B.

  FIG. 4 is a diagram illustrating a circuit configuration of the optical signal latch array according to the second embodiment of the present invention. The optical signal latch array of this embodiment includes n (n ≧ 2) optical signal latch circuits LATCH1 to LATCHn similar to the optical signal latch circuit shown in FIG.

Further, a refresh photodiode RPD, a pMOS transistor M ₄ which is a block refresh switching element, an nMOS transistor M ₅ used for resetting, inverters INV ₃ and INV ₄ , and an inverted AND gate NAND The gate opening signal generation circuit GOSC is provided.

Refresh photodiode RPD is reverse biased connected to the transistor M ₄ in series. The anode of the refresh photodiode RPD is grounded and a cathode connected to the drain of the transistor M _4. The source of the transistor M ₄ is connected to the power supply voltage. Hereinafter, the connection point between the refreshing photodiode RPD and the transistor _{M 4} of "connection node GIN". The gate terminal of the transistor M ₄ is a block refresh signal (¬Block REFRESH) is input.

Transistor M ₅ for resetting, in parallel with the refresh photodiode RPD, is connected between the connection node GIN and the ground terminal. The gate terminal of the transistor M ₅ for reset, the reset signal (RESET) is input. The transistors M ₅ for resetting is intended to be used to electrically clear data of all light signal latch circuit LATCH1～LATCHn, not to be necessarily required in the present invention.

An input terminal of the inverter INV ₃ is connected to the connection node GIN, and an input terminal of the inverter INV ₄ is connected to the output terminal of the inverter INV ₃ . The inverter INV ₃ and the inverter INV ₄ constitute an output buffer circuit.

Output signals of the inverter INV ₃ and the inverter INV ₄ (gate signals ¬GATE and GATE, respectively) are the transistors M ₂ and M ₃ of the transmission gates TG of the optical signal latch circuits LATCH1 to LATCHn (see FIG. 1A). )It is connected to the. Accordingly, the transmission gates TG of the optical signal latch circuits LATCH1 to LATCHn are opened and closed by the output signals (gate signals ¬GATE and GATE) of the gate opening signal generation circuit GOSC.

The inverting AND gate NAND has two input terminals, one is connected to the output terminal of the inverter INV _3, and the other refresh signals (REFRESH) is input.

  The operation of the optical signal latch array of the present embodiment configured as described above will be described below.

  In the initial state, it is assumed that the block refresh signal (¬ Block REFRESH) is 1, the refresh signal (REFRESH) is 0, and no optical signal is input.

First, the reset signal (RESET) is set to 1 and the refresh signal (REFRESH) is set to 1 level only during time t _{1 to} t ₂ (hereinafter referred to as “electrical reset operation”). During the reset signal (RESET) is 1, the transistor M ₅ becomes conductive. During this time, the charge accumulated in the refresh photodiode RPD is discharged. Accordingly, the potential of the connection node GIN is 0 level, the gate signal GATE is 0 level, and the gate signal ¬GATE is 1 level. Further, the transmission gates TG of the optical signal latch circuits LATCH1 to LATCHn are turned off. While the refresh signal (REFRESH) is 1, the transistors M ₁ (see FIG. 1A) of the optical signal latch circuits LATCH1 to LATCHn are turned on. At this time, the transmission gate TG is non-conductive, and the power supply voltage Vcc is applied to the photodiode PD in the reverse bias direction. As a result, the photodiode PD is charged and the input node INi (i = 0 to n−1) is reset to 1 level. At the same time, the non-inverted output (CS) is reset to 0 and the inverted output (¬CS) is reset to 1. Reset signal at time t ₂ (RESET) and the refresh signal (REFRESH) is zero. As a result, the transistors M ₁ and M ₅ are turned off.

The electrical reset operation is executed when all the optical signal latch circuits LATCH1 to LATCHn are electrically reset. This electrical reset operation is required at the time of device initialization in the optically reconfigurable date array. However, this electrical reset operation is not necessarily required if the system configuration is such that an optical signal is emitted synchronously when the power is turned on to forcibly input data to all the optical signal latch circuits in the chip. Therefore, such a case, the transistor M ₅ for resetting can be omitted.

Next, the block refresh signal (¬ Block REFRESH) is set to 0 level only between times t ₃ and t ₄ . Thus, the transistor M ₄ is rendered conductive, the power supply voltage Vcc is applied to the reverse bias direction to the refresh photodiode RPD. As a result, charges are accumulated in the refresh photodiode RPD. The potential of the connection node GIN is 1 level, the gate signal GATE is 1 level, and the gate signal ¬GATE is 0 level. Further, the transmission gates TG of the optical signal latch circuits LATCH1 to LATCHn are turned on. Block refresh signal (¬Block REFRESH) is a 1-level at time t _4.

Next, during time t _{4 to} t ₆ , an optical signal is input to the refresh photodiode RPD. When the optical signal is 1, the refresh photodiode RPD is irradiated with light, and when the optical signal is 0, the refresh photodiode RPD is not irradiated with light. Here, it is assumed that 1 is input as an optical signal, and the refresh photodiode RPD is irradiated with light. When the refresh photodiode RPD is irradiated with light, the refresh photodiode RPD is discharged, the potential of the connection node GIN becomes 0 level, the gate signal GATE becomes 0 level, and the gate signal ¬GATE becomes 1 level. Further, the transmission gates TG of the optical signal latch circuits LATCH1 to LATCHn are turned off. As a result, each optical signal latch circuit LATCH1 to LATCHn can be written by the optical signal.

Then, only during the time _t 7 ~t _8, refresh signal (REFRESH) and 1 level. As a result, the output of the inverting AND gate NAND becomes 0 only during times t _{7 to} t ₈ , and the transistors M _{1 of the} respective optical signal latch circuits LATCH ₁ to LATCHn are turned on to charge the photodiode PD.

Then, during time t _{7 to} t ₈ , an optical signal is input to the photodiode PD of each of the optical signal latch circuits LATCH 1 to LATCHn. As a result, the input nodes INi (i = 0 to n−1) of the optical signal latch circuits LATCH1 to LATCHn have a level corresponding to the optical signal. That is, when the optical signal is 1, the photodiode PD is discharged and becomes 0 level, and when the optical signal is 0, it is held at 1 level. In the example of FIG. 5, since 1 is input as an optical signal, the potential of the input node INi is 0 level. Accordingly, the non-inverted output (CS) is 1. Finally, at time _{t 10,} the block refresh signal (¬Block REFRESH) and 0 levels. As a result, the transmission gate TG is turned on, and the latch loops of the optical signal latch circuits LATCH1 to LATCHn are turned on. Therefore, the data written by the optical signal is stably held.

If the refresh photodiode RPD is not irradiated with light at times t _{4 to} t ₆ , the potential of the connection node GIN is held at 1 level, and the latch loops of the optical signal latch circuits LATCH 1 to LATCHn are in a conductive state. To be kept. Further, since 0 is continuously input as the gate signal (¬GATE) to one input terminal of the inverted AND gate NAND, the output of the inverted AND gate NAND is 1 even if the refresh signal (REFRESH) becomes 1 level. Keep the level. Therefore, the photodiode PD of each of the optical signal latch circuits LATCH1 to LATCHn is not refreshed and cannot be written by the optical signal. That is, writing is masked.

  As described above, according to the optical signal latch array of the present embodiment, writing to each of the optical signal latch circuits LATCH1 to LATCHn can be masked or unmasked by the optical signal to the refresh photodiode RPD. Therefore, it is possible to write an optical signal to each optical signal latch circuit by unmasking only the optical signal latch circuit of the circuit block to be written.

  In this embodiment, the example in which the circuit of FIG. 1A is used as the optical signal latch circuits LATCH1 to LATCHn has been described. However, as the optical signal latch circuits LATCH1 to LATCHn, the circuit of FIG. The circuits 3 (a) and (b) can also be used.

1 is a diagram illustrating a circuit configuration of an optical signal latch circuit according to Embodiment 1 of the present invention. 3 is a timing chart illustrating an operation of the inverting input type optical signal latch circuit illustrated in FIG. FIG. 6 is a diagram illustrating another circuit configuration of the optical signal latch circuit according to the first embodiment of the present invention. It is a figure showing the circuit structure of the optical signal latch array which concerns on Example 2 of this invention. 5 is a timing chart showing the operation of the optical signal latch array shown in FIG. It is a figure showing the circuit structure of the optical signal latch circuit comprised by applying the conventional latch circuit.

Explanation of symbols

PD photodiode RPD refresh photodiode M _{1 to} M ₅ switching elements (transistors)
TG transmission gate INV _{1 to} INV ₄ inverter BUFF buffer IN input node NAND NAND gate LATCH 1 to LATCHn optical signal latch circuit GOSC gate open signal generation circuit

Claims (6)

A latch circuit in which an even number of inverters are connected in a loop; and
An input receiving switching element that is provided on the input side of one inverter in the latch circuit (hereinafter referred to as an “input unit inverter”), and disconnects the loop of the latch circuit;
A photodiode reverse-biased to a connection node (hereinafter referred to as “input node”) between the input unit inverter and the input receiving switching element;
A refresh switching element for turning on and off a refresh voltage in a reverse bias direction applied to the photodiode;
An optical signal latch circuit comprising: 2. The optical signal latch circuit according to claim 1, wherein the latch circuit comprises two inverters connected in a loop. The inverter in the latch circuit is provided with one MIS transistor instead of the input receiving switching element connected to the output side,
The MIS transistor is
The gate terminal is connected to the output terminal of the preceding inverter,
A drain terminal is connected to the input terminal of the input unit inverter via the input receiving switching element,
A voltage corresponding to the same logical value as the logical value of the input node when the refresh voltage is applied between both terminals of the photodiode is applied to the source terminal,
3. The optical signal latch circuit according to claim 1, wherein the optical signal latch circuit is turned on when the refresh voltage is applied between both terminals of the photodiode. A latch circuit in which an even number of inverters are connected in a loop; and
An input receiving switching element that is provided on the input side of one inverter in the latch circuit (hereinafter referred to as an “input unit inverter”), and disconnects the loop of the latch circuit;
A photodiode reverse-biased to a connection node (hereinafter referred to as “input node”) between the input unit inverter and the input receiving switching element;
A refresh switching element for turning on and off a refresh voltage in a reverse bias direction applied to the photodiode;
A plurality of optical signal latch circuits comprising:
A photodiode (hereinafter referred to as “refresh photodiode”) reversely biased in series with a switching element (hereinafter referred to as “block refresh switching element”);
And an open gate signal generation circuit comprising an output buffer circuit having an input terminal connected to a connection node between the refresh photodiode and the block refresh switching element,
The input signal switching element of each optical signal latch circuit is opened and closed by the output of the output buffer circuit of the gate opening signal generation circuit. 5. The optical signal latch array according to claim 4, wherein the latch circuit includes two inverters connected in a loop. The inverter in the latch circuit includes one MIS transistor instead of the inverter having the input receiving switching element connected to the output side,
The MIS transistor is
The gate terminal is connected to the output terminal of the preceding inverter,
A drain terminal is connected to the input terminal of the input unit inverter via the input receiving switching element,
A voltage corresponding to the same logical value as the logical value of the input node when the refresh voltage is applied between both terminals of the photodiode is applied to the source terminal,
6. The optical signal latch array according to claim 4, wherein the optical signal latch array is turned on when the refresh voltage is applied between both terminals of the photodiode.

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