JP2006041580A - Semiconductor integrated circuit for communication - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a communication purpose semiconductor integrated circuit capable of making oscillation over a wide frequency range with high accuracy and selecting an operating frequency band of a VCO in a short period of time without increasing an occupied area. <P>SOLUTION: The semiconductor integrated circuit for communication is provided with an oscillation circuit including: an oscillator; and a variable frequency divider capable of frequency-dividing an oscillation signal by an optional frequency division ratio (an integer + a fraction F/G). The integrated circuit is further provided with: a frequency division ratio calculation circuit for calculating the frequency division ratio given to the variable frequency divider on the basis of an external transmission start instruction and external operating frequency band information; and a band selection circuit that compares a phase of an output signal of a fixed frequency divider circuit for frequency-dividing a reference signal with a phase of an output signal from the variable frequency divider circuit to select the oscillation frequency band of the oscillator in a state that the variable frequency divider is operated by a frequency division ratio calculated by the frequency division ratio calculation circuit and a potential with a prescribed level is supplied to the oscillator as a control voltage, and after the oscillated frequency band of the oscillator is selected by the band selection circuit, the control voltage or a control current of the oscillator is switched into an output of a frequency control circuit to activate the oscillation circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technology effective when applied to a semiconductor integrated circuit incorporating an on-chip VCO (Voltage Controlled Oscillator) and a PLL (Phase Locked Loop) circuit including a VCO in a loop. The present invention relates to an effective technique for use in an offset PLL communication semiconductor integrated circuit incorporating a transmission VCO and a PLL circuit for up-converting the frequency of a transmission signal in a communication system.

  In a wireless communication system such as a cellular phone, for communication that performs frequency down-conversion or up-conversion by synthesizing a high-frequency local oscillation signal with a reception signal or transmission signal, or modulation of a transmission signal or demodulation of a reception signal A semiconductor integrated circuit (hereinafter referred to as a high frequency IC) is used. In such a high-frequency IC, the transmission I and Q signals are orthogonally modulated with a carrier wave of an intermediate frequency, and the feedback signal from the output side of the transmission VCO is mixed with the high-frequency oscillation signal from the RFVCO to correspond to a frequency difference (offset). There is an offset PLL system that down-converts the signal to an intermediate frequency signal, and compares the phase of the signal with the signal after the quadrature modulation to control the transmission VCO according to the phase difference.

  Such an offset PLL type high frequency IC requires an IFVCO that generates a carrier wave of an intermediate frequency in addition to the transmission VCO and the RFVCO. Since VCO requires a relatively large occupation area, many conventional high frequency ICs use an external VCO (Patent Document 1). However, when an external VCO is used, the number of parts increases, which hinders downsizing. Thus, it has been proposed to incorporate a VCO in the chip. However, if all the three VCOs are incorporated in the chip, the chip size increases and the chip cost increases.

  On the other hand, in recent mobile phones, for example, dual band systems capable of handling signals in two frequency bands such as 880 to 915 MHz band GSM (Global System for Mobile Communication) and 1710 to 1785 MHz band DCS (Digital Cellular System). There is a mobile phone. Recently, in addition to GSM and DCS, there is a demand for a triple-band mobile phone that can handle PCS (Personal Communication System) signals in the 1850 to 1915 MHz band, for example. Is expected to be required. A voltage-controlled oscillation circuit (VCO) used in a mobile phone that can handle such a plurality of systems needs to have a wide oscillation frequency range.

Here, when trying to cope with all frequencies with one VCO, there is a problem that the sensitivity of the oscillation frequency with respect to the control voltage of the VCO (hereinafter referred to as control sensitivity) becomes high and becomes weak against external noise and power supply voltage fluctuation. Accordingly, an invention has been proposed in which the VCO control sensitivity can be reduced while maintaining a desired oscillation frequency range by switching the VCO to a plurality of (for example, 16) frequency bands. Patent Document 2).
Japanese Patent Application Laid-Open No. 2003-158452 JP 2004-12749 A JP 2003-152535 A

  In order to reduce the chip size of a high-frequency IC with a built-in VCO, the present inventors reduce the number of VCOs by using a common RFVCO and IFVCO. Specifically, the RFVCO oscillation signal is divided to generate an intermediate frequency signal. We studied to reduce IFVCO by generating. As a result, the division ratio can be set by a relatively simple logic circuit as long as an integer division ratio can be set as a variable frequency divider (counter) in the PLL loop including the VCO. When an integer frequency division ratio is set, the oscillation frequency can be switched only at the same frequency interval as the frequency of the reference signal. On the other hand, when RFVCO and IFVCO are shared, it is necessary to switch the oscillation frequency more finely. Therefore, the variable frequency divider must be operated with a division ratio including a decimal number.

  However, if a logic circuit that sets a division ratio including a decimal number is incorporated in a high-frequency IC, the scale of the logic circuit increases and hinders the reduction of the chip size. A method is also conceivable in which a memory is provided in the high-frequency IC and all the frequency division ratios corresponding to the used frequencies are stored in the memory in advance. It must be increased, leading to an increase in chip size. In addition, a method of giving a division ratio including a decimal number from the outside of the chip (baseband circuit) is also conceivable. However, if this is done, the functions required of the baseband circuit for determining the transmission frequency increase, and the high frequency IC is There is a problem that the burden on the designer of the communication system to be used becomes very large.

  Furthermore, in the PLL, since the voltage of the loop filter is directly applied to the control terminal of the VCO, if the thermal noise of the resistive element constituting the loop filter is large and the control sensitivity of the VCO is high, the thermal noise generated by the resistive element is There is a problem that it appears in the output of the VCO. Therefore, the control frequency of the VCO is lowered by increasing the oscillation frequency band of the VCO and reducing the rate of change of the oscillation frequency with respect to the change of the control voltage in each frequency band, and the resistance element constituting the loop filter is increased. Even so, it is conceivable that the influence of thermal noise is less likely to appear in the output of the VCO.

  As a method for determining the oscillation frequency band to be used in the VCO that can switch the oscillation frequency band, the actual frequency is measured in advance for all the frequency bands and stored in the memory, and the used frequency band is selected. A method has been proposed (Patent Document 3). However, in this prior application selection method, as the VCO frequency band increases, the measurement time becomes longer and the power consumption increases, and the capacity of the memory for storing the measurement results must be increased. There is a problem of increasing the size.

SUMMARY OF THE INVENTION An object of the present invention is to provide a communication semiconductor integrated circuit that can oscillate with high accuracy over a wide frequency range, and that can select a VCO operating frequency band in a short time without increasing the occupied area. High frequency IC).
Another object of the present invention is to divide an RFVCO oscillation signal without an IFVCO to generate an intermediate frequency carrier wave, perform orthogonal modulation on transmission I and Q signals with the intermediate frequency carrier wave, and then use the transmission VCO. Simplified logic circuit for setting a division ratio including decimal numbers for a variable frequency divider (counter) in a PLL loop in a communication semiconductor integrated circuit device (high frequency IC) that performs up-conversion to a desired transmission frequency for transmission This is to reduce the chip size.

Still another object of the present invention is to divide an RFVCO oscillation signal without an IFVCO to generate an intermediate frequency carrier wave, orthogonally modulate transmission I and Q signals with the intermediate frequency carrier wave, and then transmit the VCO for transmission. In a communication semiconductor integrated circuit device (high frequency IC) that performs up-conversion to a desired transmission frequency and transmits, the function required for an external circuit, that is, a control circuit for determining the transmission frequency is reduced, thereby burdening the system designer. There is to reduce.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

The following is a brief description of an outline of typical inventions disclosed in the present application.
That is, a communication provided with an oscillation circuit having an oscillator and a variable frequency divider capable of dividing an oscillation signal of the oscillator by a frequency division ratio (I + F / G) represented by an integer part I and a fractional part F / G. In a semiconductor integrated circuit for use, a frequency division ratio calculation circuit for calculating a frequency division ratio to be given to the variable frequency divider based on a transmission start command and use frequency band information supplied from the outside, and the frequency division ratio calculation circuit A fixed divider that divides the phase of the output signal of the variable divider circuit and the reference signal in a state where the variable divider is operated with the calculated division ratio and a potential of a predetermined level is supplied as a control voltage to the oscillator. A band selection circuit that compares the phase of the output signal of the peripheral circuit and selects the oscillation frequency band of the oscillator, and after the oscillation frequency band of the oscillator is selected by the band selection circuit, the control voltage of the oscillator or Before control current Those configured to operate the oscillation circuit by switching the output of the frequency control circuit.

  According to the above-described means, since the variable frequency divider that can divide by an arbitrary frequency division ratio (I + F / G) is provided, it can oscillate with high accuracy over a wide frequency range and can be used in real time. In order to select the band, it is not necessary to measure the actual frequency for all the frequency bands in advance and store it in the memory and select the use frequency band, so the occupied area is not increased and the frequency of the VCO is set each time. Since there is no need to measure, the frequency band used for the VCO can be determined in a short time.

  Also, an oscillation circuit that generates an oscillation signal having a frequency according to a value set from the outside, and a frequency division circuit that divides the oscillation signal generated by the oscillation circuit to generate an intermediate frequency signal are provided. In an offset PLL communication semiconductor integrated circuit device (high-frequency IC), the oscillation circuit is an oscillator (RFVCO) and an oscillation signal of the oscillator is divided into an arbitrary division ratio (I + F consisting of an integer part I and a fractional part F / G). / G) and a variable frequency divider (counter) capable of frequency division.

  According to the above-described means, since the RFVCO oscillation signal is divided to generate the intermediate frequency carrier wave, it is not necessary to incorporate the IFVCO in the chip, so that the chip size can be reduced. In addition, since the dividing ratio of the variable divider can be automatically generated inside the semiconductor chip and given to the variable divider, information generated and given by an external device such as a baseband circuit can be reduced. The burden on the user (set maker), that is, the system designer can be reduced.

  Preferably, the denominator G and numerator F of the fractional part F / G are selected from a combination of a plurality of integers prepared in advance corresponding to the band information and the division ratio setting information of the divider circuit. To be generated based on one of the integers. As a result, the scale of the frequency division ratio generating circuit for generating the frequency division ratio of the variable frequency divider including decimal numbers represented by the integer part I and the fractional part F / G can be reduced, and the chip size can be increased. Can be suppressed.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
In other words, according to the present invention, a semiconductor integrated circuit for communication that can oscillate with high accuracy over a wide frequency range and can select a VCO operating frequency band in a short time without increasing the occupied area. (High frequency IC) can be realized.

  In addition, since the RFVCO oscillation signal is divided to generate an intermediate frequency carrier wave, it is not necessary to incorporate the IFVCO in the chip, and the frequency divider including a decimal is included in the variable frequency divider (counter) in the PLL loop. Since the logic circuit for setting the ratio can be simplified, a communication semiconductor integrated circuit (high frequency IC) with a small chip size can be realized.

  Furthermore, a communication semiconductor integrated circuit (high frequency IC) capable of reducing the function required of an external control circuit such as a baseband LSI for determining a transmission frequency and thereby reducing the burden on the system designer is realized. be able to.

Next, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows an example of a multiband communication semiconductor integrated circuit device (high frequency IC) to which the present invention is applied and a wireless communication system using the same.
As shown in FIG. 1, the system includes a signal radio transmission / reception antenna 100, a transmission / reception switching switch 110, high-frequency filters 120a to 120d including a SAW filter for removing unnecessary waves from the received signal, and amplifying the transmission signal. High-frequency power amplifier circuit (power module) 130, high-frequency IC 200 that demodulates a received signal or modulates a transmission signal, an in-phase component I signal and a quadrature component Q for an audio signal or data signal to be transmitted A baseband circuit 300 that performs baseband processing such as converting received I and Q signals converted into signals or demodulated into audio signals and data signals, and sending signals for controlling the high-frequency IC 200, and the like.

  The high frequency IC 200 and the baseband circuit 300 are each configured as a semiconductor integrated circuit on separate semiconductor chips. Although not particularly limited, in the system of the present embodiment, the high frequency IC 200 and the high frequency power amplifier circuit 130 are operated by the power supply voltage Vreg supplied from the same voltage regulator.

  Further, although not particularly limited, the high-frequency IC 200 of this embodiment is configured to be capable of modulating / demodulating signals in four frequency bands by three communication systems of GSM850, GSM900, DCS1800, and PCS1900. In response to this, the high-frequency filter passes a filter 120a that passes the received signal in the frequency band of PCS1900, a filter 120b that passes the received signal in the frequency band of DCS1800, and a received signal in the frequency band of the GSM system. Filters 120c and 120d are provided.

The high-frequency IC 200 according to the present embodiment is roughly composed of a reception system circuit RXC, a transmission system circuit TXC, and a control system circuit CTC composed of circuits common to the transmission / reception system such as other control circuits and clock generation circuits. The
The reception system circuit RXC is a local oscillation signal generated by low noise amplifiers 211a, 211b, 211c, and 211d that amplify reception signals in each frequency band of PCS, DCS, and GSM, and a high-frequency oscillation circuit (RFVCO) 262 described later. Frequency division phase shift circuit 210 that divides φRF and generates quadrature signals that are 90 ° out of phase with each other, and frequency division phase shift circuit 210 generates reception signals amplified by low noise amplifiers 211a, 211b, 211c, and 211d. Mixers 212a and 212b that perform demodulation and down-conversion by mixing the orthogonal signals, high gain amplification units 220A and 220B that amplify the demodulated I and Q signals and output to the baseband circuit 300, respectively, Off to cancel the input DC offset of the amplifiers in the gain amplifiers 220A and 220B And the like Tsu door cancellation circuit 213. The receiving system circuit RXC of this embodiment employs a direct conversion method in which a received signal is directly down-converted into a baseband frequency band signal.

  The high gain amplifying unit 220A has a configuration in which a plurality of low pass filters LPF11, LPF12, LPF13, LPF14 and gain control amplifiers PGA11, PGA12, PGA13 are alternately connected in series, and the amplifier AMP1 is connected to the final stage. The demodulated I signal is amplified and output to the baseband circuit 300. Similarly, the high gain amplifying unit 220B has a configuration in which a plurality of low pass filters LPF21, LPF22, LPF23, LPF24 and gain control amplifiers PGA21, PGA22, PGA23 are alternately connected in series, and an amplifier AMP2 is connected to the final stage. The demodulated Q signal is amplified and output to the baseband circuit 300.

  The offset cancel circuit 213 is provided corresponding to each of the gain control amplifiers PGA11 to PGA23, and converts an output potential difference between the input terminals into a digital signal in a state where the input terminals are short-circuited, and these AD conversion circuits. A DA converter circuit (DAC) that generates an input offset voltage for setting the DC offset of the outputs of the corresponding gain control amplifiers PGA11 to PGA11 to "0" based on the conversion result by the above, and applies the differential input to these differential inputs; The circuit includes a control circuit that controls the conversion circuit (ADC) and the DA conversion circuit (DAC) to perform an offset cancel operation.

  The control system circuit CTC includes a control circuit (control logic) 260 for controlling the entire chip, a reference oscillation circuit (DCXO) 261 for generating a reference oscillation signal φref, and a local unit for generating a high-frequency oscillation signal φRF for frequency conversion. A high frequency oscillation circuit (RFVCO) 262 as an oscillation circuit, an RF synthesizer 263 that constitutes a PLL circuit together with the high frequency oscillation circuit (RFVCO) 262, and a frequency division ratio of a variable frequency divider in the RF synthesizer 263 are generated and given. Frequency dividing circuits DVD1 and DVD2 for dividing the oscillation signal φRF generated by the ratio generating circuit 264 and RFVCO 262, mode changeover switches SW1 and SW2, and the like are provided.

  Switches SW1 and SW2 switch the connection state between the GSM mode for transmission / reception according to the GSM system and the DCS / PCS mode for transmission / reception according to the DCS or PCS system, and select the frequency division ratio of the transmitted signal. Therefore, these switches SW 1 and SW 2 are controlled by signals from the control circuit 260.

  The control circuit 260 is supplied with a clock signal CLK for synchronization, a data signal SDATA, and a load enable signal LEN as a control signal from the baseband circuit 300, and the control circuit 260 is enabled with the load enable signal LEN. When asserted to the level, the data signal SDATA transmitted from the baseband circuit 300 is sequentially taken in synchronization with the clock signal CLK, and a control signal inside the chip is generated in accordance with a command included in the data signal SDATA. Although not particularly limited, the data signal SDATA is transmitted serially.

  Since the reference oscillation signal φref is required to have high frequency accuracy, an external crystal resonator is connected to the reference oscillation circuit 261. A frequency such as 26 MHz or 13 MHz is selected as the reference oscillation signal φref. A crystal resonator having such a frequency is a general-purpose component and can be easily obtained. The RF synthesizer 263 includes a frequency divider, a phase comparison circuit, a charge pump, a loop filter, and the like.

  The transmission circuit TXC divides the oscillation signal φRF generated by the RFVCO 262 to generate an oscillation signal φIF having an intermediate frequency such as 160 MHz, for example, and the signal divided by the frequency divider 231 Further, a frequency-dividing phase shift circuit 232 that divides and generates quadrature signals that are 90 ° out of phase with each other, and a modulation circuit 233a that modulates the generated quadrature signal with an I signal and a Q signal supplied from the baseband circuit 300. , 233b, an adder 234 that synthesizes the modulated signal, a transmission oscillation circuit (TXVCO) 240 that generates a transmission signal φTX having a predetermined frequency, and a transmission signal φTX that is output from the transmission oscillation circuit (TXVCO) 240. The feedback signal extracted by the couplers 280a and 280b and the high-frequency oscillation signal generated by the high-frequency oscillation circuit (RFVCO) 262 An offset mixer 235 that generates a signal having a frequency corresponding to the frequency difference by mixing the signal φRF ′ obtained by dividing φRF, and an output of the offset mixer 235 and a signal TXIF synthesized by the adder 234 A GSM transmission signal by dividing the output of a phase comparator 236 that detects a phase difference by comparison, a loop filter 237 that generates a voltage corresponding to the output of the phase detector 236, and a transmission oscillation circuit (TXVCO) 234 And the transmission output buffer circuits 239a and 239b.

  In the transmission system circuit of this embodiment, the transmission I and Q signals are orthogonally modulated with a carrier wave of an intermediate frequency, and the feedback signal from the output side of the TXVCO 240 is mixed with the signal φRF ′ obtained by dividing the high-frequency oscillation signal φRF of the RFVCO 262. Thus, after down-converting to an intermediate frequency signal corresponding to the frequency difference (offset), the phase of the signal and the signal after the quadrature modulation are compared, and the offset PLL method is used to control the TXVCO 240 according to the phase difference. ing. The phase detector 236, the loop filter 237, the TXVCO 240, and the offset mixer 235 constitute a transmission PLL circuit (TX-PLL) that performs frequency conversion (up-conversion). The BFF is a buffer that amplifies the feedback signal extracted by the couplers 280a and 280b and supplies the amplified feedback signal to the mixer 235.

  In the multiband wireless communication system of the present embodiment, for example, the control circuit 260 changes the frequency φRF of the oscillation signal of the high-frequency oscillation circuit 262 according to the band and channel used during transmission / reception in response to a command from the baseband circuit 300. By switching the switches SW1 and SW2 according to the GSM mode or the DCS / PCS mode, the frequency of the oscillation signal supplied to the reception system circuit RXC or the reception system circuit TXC is changed, thereby switching the transmission / reception frequency. Is done. Further, a control signal for switching the changeover switches SW1 and SW2 according to the transmission / reception frequency band is supplied from the control circuit 260 to SW1 and SW2. In this embodiment, the frequency division ratio NIF of the frequency dividing circuit 231 is set by a control signal from the control circuit 260.

  The oscillation frequency of the RFVCO 262 is set to a different value between the reception mode and the transmission mode. In the transmission mode, the oscillation frequency fRF of the RFVCO 262 is set to, for example, 3616 to 3716 MHz for GSM850, 3840 to 3980 MHz for GSM900, 3610 to 3730 MHz for DCS, and 3860 to 3980 MHz for PCS. In the case of GSM in the peripheral circuits DVD1 and DVD2, the frequency is divided by ¼, and in the case of DCS and PCS, the frequency is divided by ½ and supplied to the offset mixer 235 as φRF ′ through the switches SW1 and SW2.

  In the offset mixer 235, a difference signal corresponding to the frequency difference (fRF′−fTX) between φRF ′ and the transmission oscillation signal φTX from the TXVCO 240 is output and supplied to the phase comparator 236, and the frequency of the difference signal is calculated. The transmission PLL (TX-PLL) operates so as to match the frequency of the modulation signal TXIF. In other words, the TXVCO 240 is controlled to oscillate at a frequency corresponding to the difference between the frequency (fRF / 4 or fRF / 2) of the oscillation signal φRF ′ from the RFVCO 262 and the frequency (fTX) of the modulation signal TXIF.

  In the reception mode, the oscillation frequency fRF of the RFVCO 262 is set to, for example, 3476 to 3576 MHz for GSM850, 3700 to 3840 MHz for GSM900, 3610 to 3730 MHz for DCS, and 3860 to 3980 MHz for PCS. In this case, the frequency is divided by 1/2 by the frequency dividing circuit DVD1, and in the case of DCS and PCS, it is supplied to the frequency dividing phase shift circuit 210 as it is, and is frequency-divided and phase-shifted and supplied to the mixers 212a and 212b as quadrature signals. Is done.

  The RFVCO 262 is composed of an LC resonance type oscillation circuit or the like, and a plurality of capacitor elements constituting the LC resonance circuit are provided in parallel via the switch elements, and the switch elements are selectively turned on by a band switching signal. The oscillation frequency can be switched stepwise by switching the value of C of the connected capacitive element, that is, the LC resonance circuit. Further, in the RFVCO 262, the capacitance value of the variable capacitance element is changed by the control voltage from the loop filter in the RF synthesizer 263, and the oscillation frequency is continuously changed.

FIG. 2 shows an RF-PLL circuit including the RF synthesizer 263 and the RFVCO 262 and one embodiment.
The PLL circuit of this embodiment is generated by a variable frequency dividing circuit 631 that divides the oscillation signal φRF of the RFVCO 262 by 1 / N and a reference oscillation circuit (DCXO) 261 that generates a reference oscillation signal φref such as 26 MHz. A phase comparison circuit 632 that detects the phase difference between the reference oscillation signal φref and the signal φdiv divided by the variable frequency dividing circuit 631, a charge pump 633 that generates and outputs a current Id corresponding to the detected phase difference, A loop filter 634 that generates a voltage corresponding to the detected phase difference output from the charge pump 633, and a voltage smoothed by the loop filter 634 is fed back to the RXVCO 262 as an oscillation control voltage Vt, and a frequency corresponding to Vt. It is configured to oscillate. The variable frequency dividing circuit 631 can be constituted by a counter.

  Further, the PLL circuit of this embodiment includes a changeover switch 635 that applies a predetermined voltage VDC to the RFVCO 262 in a state in which a loop is opened before oscillation starts, and a fixed that divides the reference oscillation signal φref by a predetermined division ratio. A frequency dividing circuit 636 and a discriminating circuit for determining the phase advance / delay of the signal φr ′ divided by the frequency divider circuit and the signal φdiv divided by the variable frequency divider 631 are used from the phase advance / delay. An automatic band selection circuit 637 for determining a frequency band (band) is provided.

  Further, in order to set the frequency dividing ratio of the variable frequency dividing circuit 631, in this embodiment, the channel information CH indicating the set frequency supplied from the outside and the band indicating whether the used band is GSM850, GSM900, DCS or PCS. A part for calculating and setting the frequency division ratio of the variable frequency dividing circuit 631 from the information BND, the mode information T / R indicating transmission or reception, and the frequency division ratio setting information NIF set in the IF divider 231. A frequency ratio generation circuit (frequency division ratio setting logic) 264 is provided. The frequency division ratio generation circuit 264 includes a frequency division ratio calculation unit 641, a sigma delta modulator 642 that receives fractional data, and an adder 643. The channel information CH is input from the baseband circuit 300 as a value obtained by dividing the transmission frequency or the reception frequency by 100 kHz.

In the present embodiment, the frequency division ratio NIF of the IF frequency divider 231 is any one of “40”, “44”, “48”, and “52”. The reason will be described below.
For example, when the use band is DCS, the mode is transmission, and the transmission frequency is 1713.6 MHz, in the case of DCS, the transmission frequency band is 1710.2 MHz to 1784.8 MHz, and the reception frequency band is 1805.2 MHz to 1879. .8 MHz. Further, if the frequency of the oscillation signal φRF of the RFVCO 262 is fRF, the frequency of the oscillation signal φTX of the transmission VCO 234 is fTX, and the frequency fIF of the intermediate frequency signal φIF after the IF frequency divider 231 is fRF, '−fTX = fIF, and in DCS, fRF ′ = fRF / 2, fRF = fIF × NIF. Therefore, when NIF = 44 is set, the frequency fIF of the intermediate frequency signal φIF after the IF frequency divider 231 is fIF = 2fTX / (NIF-2) = fTX / 21 = 1713.6 MHz / 21 = 81. 6 MHz, and the 22nd harmonic and the 23rd harmonic are 1795.2 MHz and 1876.8 MHz, respectively.

  Therefore, in this case, there is no problem with the 22nd harmonic, but the 1876.8 MHz of the 23rd harmonic falls within the range of 1805.2 MHz to 1879.8 MHz of the reception frequency band. As a spurious signal appears in the output through the mixer 234 and the transmission VCO 234, the amount of signal leakage to the reception frequency band increases and the reception band noise may not satisfy the specifications. Therefore, when the frequency division ratio NIF is set to “40”, the 20th harmonic and the 21st harmonic are problematic, but they are 1803.8 MHz and 1894.0 MHz, respectively. Therefore, in this case, the reception frequency band is out of the range of 1805.2 MHz to 1879.8 MHz, and the problem of signal leakage to the reception frequency band is avoided.

  The same applies to the case where the transmission frequency is set to another frequency. By shifting the frequency division ratio NIF of the IF frequency divider 231, signal leakage to the reception frequency band of the harmonic component of the intermediate frequency signal φIF is prevented. It can be avoided. Hereinafter, this is referred to as a local frequency side step. The inventors of the present invention should take any one of “40”, “44”, “48” or “52” as the frequency division ratio NIF of the IF frequency divider 231 of the IF frequency divider 231. The frequency division ratio NIF is found to be “40”, “44”, “48” by finding that the harmonic frequency of the intermediate frequency signal φIF can be removed from the reception frequency band regardless of which frequency is set as the transmission frequency. It is decided to be either “or” or “52”.

  Which division ratio is set from among the combinations of the plurality of division ratios NIF “40”, “44”, “48”, and “52” is based on a command from the baseband circuit 300 side. Therefore, when a high frequency IC manufacturer selects a transmission frequency in advance, a frequency plan indicating which division ratio should be set is prepared and presented to the user, that is, the system designer. It is desirable to make it.

  According to such a method, by creating a frequency plan that enables an optimal side step and presenting it to the user, the signal to the reception frequency band that may greatly change in characteristics due to the layout of the IC is obtained. A system with little leakage can be realized.

Next, a method for setting the frequency division ratio N to the variable frequency divider 631 in the high frequency IC of the embodiment will be described.
The relationship between the oscillation frequency fRF of the RFVCO 262 and the frequency fRX of the received signal in the receiving system circuit of the high frequency IC of the present embodiment is given by the following equation depending on the presence of the frequency dividing circuit DVD1, the switch SW1, and the frequency dividing phase shift circuit 210.
For GSM850 and GSM900: fRF = 4 · fRX (1)
For DCS1800 and PCS1900: fRF = 2 · fRX (2)

On the other hand, since the transmission system circuit is an offset PLL system, the relationship between the oscillation frequency fRF of the RFVCO 262 and the frequency fTX of the transmission signal is generated by dividing the oscillation signal φRF of the RFVCO 262 to generate an intermediate frequency signal φIF used for orthogonal modulation. The frequency division ratio NIF of the IF frequency divider 231 can be expressed by the following equation.
In the case of GSM850 and GSM900, from fRF / 4-fTX = fRF / NIF,
fRF = (1/4/1 / NIF) ⁻¹ · fTX (3)
In the case of DCS1800 and PCS1900, fRF / 2−fTX = fRF / NIF
fRF = (1 / 2-1 / NIF) ⁻¹ · fTX (4)

Also, channel information CH is given in the form of the following equation.
For GSM850 and GSM900 CH = fRX / 100kHz ...... (5-1)
CH = fTX / 100kHz ...... (5-2)
For DCS1800 and PCS1900 CH = fRX / 200kHz, CH = fTX / 200kHz (6-1)
CH = fRX / 200kHz, CH = fTX / 200kHz (6-2)

Therefore, from the equations (1) and (5-1), in the case of GSM850 and GSM900 reception modes,
fRF = 4 · 100kHz · CH = 0.4MHz · CH (7)
From the equations (2) and (6-1), in the case of the DCS1800 and PCS1900 reception modes,
fRF = 2 · 200kHz · CH = 0.4MHz · CH (8)
From the equations (1) and (5-2), in the case of the transmission mode of GSM850 and GSM900,
fRF = (1/4/1 / NIF) ⁻¹ · 100 kHz · CH (9)
From Equations (2) and (6-2), in the case of DCS1800 and PCS1900 transmission modes,
fRF = (1 / 2-1 / NIF) ⁻¹ · 200 kHz · CH (10)
Holds.

Here, if the oscillation signal φref of the reference oscillation circuit (DCXO) 261 is 26 MHz, the frequency division ratio N of the variable frequency divider 631 can be expressed by the following equation.
For GSM850 and GSM900 reception modes:
N = fRF / 26 = (0.4 / 26) .CH = CH / 65 (11)
In the case of DCS1800 and PCS1900 reception modes,
N = fRF / 26 = (0.4 / 26) .CH = CH / 65 (12)
For GSM850 and GSM900 transmission modes:
N = (1 / 4-1 / NIF) ⁻¹ · CH / 65 (13)
In case of DCS1800 and PCS1900 transmission modes,
N = (1 / 2-1 / NIF) ⁻¹ · CH / 65 (14)

  From equations (11) and (12), it can be seen that the denominator of the frequency division ratio N of the variable frequency divider 631 in the reception mode can be expressed by “65”. In the equations (13) and (14), the frequency division ratio NIF of the IF divider 231 is a combination of “40”, “44”, “48”, “52” by the side step as described above. One of them is selected. Therefore, from the equation (13), it can be seen that the denominator of the frequency division ratio N of the variable frequency divider 631 in the transmission mode of GSM850 and GSM900 can be expressed as “585”, “650”, “715”, and “780”. Further, from the equation (14), it can be seen that the denominators of the frequency division ratio N of the variable frequency divider 631 in the DCS1800 and PCS1900 transmission modes can be expressed as “1235”, “1365”, “1495”, and “1625”.

From the above, in order to realize the combination of the denominators of the variable frequency divider 631 in all transmission and reception with one circuit, the least common multiple of 65,585,650... 1625 may be used as the denominator. It gets bigger. Therefore, in this embodiment, an increase in circuit area is suppressed as follows.
(1) The denominator is determined by “case division” from the band information and the frequency division ratio NIF of the IF divider 231.
(2) The order of the denominator is unified to about 1200 to 1700 in consideration of the range of 1235 to 1755 in the transmission mode of DCS1800 and PCS1900 for common use of the algorithm.
(3) The frequency division ratio error caused by matching the denominator order as described above is adjusted by the numerator.

  FIG. 3 shows a configuration example of the frequency division ratio calculation unit 641. The frequency division ratio calculation unit 641 is a multiplier MLT1 that obtains a value obtained by multiplying channel information CH by X, a multiplier MLT2 that multiplies a value determined from the band information BND and the frequency division ratio information NIF by a constant (65 times), and multiplication. The divider DIV1 that halves the output of the multiplier MLT2 and outputs the integer part thereof, the adder ADD1 that adds the output of the multiplier MLT1 and the integer part output from the divider DIV1, and the adder ADD1 Is divided by the output of the multiplier MLT2 to output a "quotient" and a "remainder", and a value obtained by subtracting the output of the divider DIV1 from the "remainder" output from the divider DIV2 And a subtractor ASC1 for outputting. The value of the “quotient” output from the divider DIV2 is the integer part data I, the value output from the subtractor ASC1 is the numerator data F, and the output of the multiplier MLT2 is the denominator data G. Each is supplied to the peripheral 631. In this specification, “F / G” composed of numerator data F and denominator data G is referred to as fractional part data.

  The multiplier MLT1 and the multiplier MLT2 are provided with decoders DEC1 and DEC2, respectively. The decoder DEC1 decodes information T / R indicating whether transmission or reception, band information BND, and frequency division ratio information NIF, and multiplies them. The value M applied to the input channel information CH is output by the device MLT1. The decoder DEC2 decodes the band information BND and the frequency division ratio information NIF and outputs a value Y that is multiplied by a constant (65 times) by the multiplier MLT2. FIG. 4 shows the relationship between the input and output of the decoder DEC1, and FIG. 5 shows the relationship between the input and output of the decoder DEC2.

  4 and 5, for example, when the mode is GSM transmission and the division ratio NIF is “44”, it can be seen that X of the multiplier MLT1 is “22” and Y of the multiplier MLT2 is “20”. . Accordingly, when the channel information CH is “8274” (transmission frequency is 827.4 MHz), the output CH × 22 of the multiplier MLT1 is “182028”, and the denominator data G that is the output of the multiplier MLT2 is “1300”. Therefore, the output of the divider DIV1 is “650”, the output of the adder ADD1 is “182678”, the integer data I output from the divider DIV2 is “140”, and is output from the subtractor ASC1. The molecular data F is “28”.

  Here, the adder ADD1 and the subtractor ASC1 are provided for performing an offset operation for setting the fractional part data in the range of −650 to +649, not in the range of 0 to 1299. This is because the DC component can be reduced when the average value is in the vicinity of ± 0 rather than in the vicinity of 650.

Next, a more detailed configuration of the sigma delta modulator 642 and the method of generating the division ratio N in the division ratio generation circuit 264 of the above embodiment will be described.
As shown in FIG. 6, the sigma delta modulator 642 of this embodiment includes an adder ADD2 that adds the input numerator data F and the feedback data, a 1-bit quantizer QTG1 that quantizes the addition result, An arithmetic unit ALU1 that multiplies the output of the quantizer QTG1, a subtractor ASC2 that obtains a difference between the output of the arithmetic unit ALU1 and the output of the adder ADD2, and delays the obtained difference to add the adder. The delay unit DLY1 feeds back to the ADD2, operates in synchronization with the reference clock φref, converts the input fractional data into data in the time axis direction, and outputs the data.

  The quantizer QTG1 and the arithmetic unit ALU1 are supplied with the denominator data G from the frequency division ratio calculation unit 641, and when the input is larger than the denominator data G, the quantizer QTG1 outputs "+1" and the input is When it is in the range of 0 to G, “0” is output, and when the input is smaller than 0, “−1” is output. On the other hand, the arithmetic unit ALU1 has its gain (multiplier) set to the same value as the denominator data G given from the division ratio calculation unit 641, and outputs the input multiplied by G. The arithmetic unit ALU1 may be a multiplier, but can also be configured by a register for setting G and a selector for selecting and outputting the register value or its sign inverted value or "0" according to the input.

Here, the operation of the sigma-delta modulator 642 when the numerator data F input from the frequency division ratio calculation unit 641 is “28” and the denominator data G is “1300” will be described with reference to FIG.
When the numerator data F is “28”, the output of the adder ADD2 increases stepwise by “28” every clock as shown in FIG. 7B. Since the quantizer QTG1 outputs “+1” when the input is larger than the denominator data G, the quantizer QTG1 outputs “+1” when the output of the adder ADD2 exceeds G (= 1300). That is, “+1” is output every 1300/28 (≈47) clocks. As a result, the sigma delta modulator 642 outputs “+1” only 28 times for 1300 times of the reference clock φref.

  That is, it can be seen that the sigma delta modulator 642 of this embodiment outputs “+1” by the number of the numerator data F during the period of the number of clocks of the denominator data G. This is because G ÷ G / F = F is obtained by dividing the period G of the reference clock φref by the value G / F obtained by dividing the threshold value G of the quantizer QTG1 by the input change amount F. Is also obvious.

  9 shows integer part data I, numerator data F, denominator data G, and fractional part data output from sigma delta modulator 642 output from frequency division ratio calculating part 641 in frequency division ratio generating circuit 264. Relationship of output frequency division ratio N (= I + F / G) of adder 643 that adds F / G, integer part data I and fractional part data F / G, and outputs the frequency division ratio to variable frequency divider 631 It is shown.

  As shown in FIG. 9, when I = 140, F = 28, and G = 1300, “141” is output to the variable frequency divider 631 only 28 times for 1300 times of the reference clock φref, and the remaining “140” is output 1272 times. That is, “141” is supplied to the variable frequency divider 631 from the frequency division ratio generation circuit 264 as the frequency division ratio N only 28 times in 1300 times of the reference clock φref, and the remaining 1272 times out of 1300 times are “140”. "Is supplied from the frequency division ratio generation circuit 264 to the variable frequency divider 631 as the frequency division ratio N. According to the supplied frequency division ratio N, the variable frequency divider 631 divides the oscillation signal φRF to form a signal φdiv. The signal φdiv thus formed is a signal formed by dividing the oscillation signal φRF by the variable frequency divider 631 by a division ratio (140 + 28/1300) below the decimal point when a certain time period is seen. Can be considered substantially the same.

  By the way, in the first-order sigma-delta modulator of the embodiment of FIG. 6, for example, “141” is regularly output only 28 times in 1300 times, so that the modulated frequency dividing ratio is periodically repeated. That is, there is a fixed pattern with a predetermined frequency. Although this periodic fixed pattern has a relatively low frequency, it is not desirable because it appears as spurious at the output of the RF-PLL including the variable frequency divider 231.

  Therefore, it is desirable to use a high-order sigma-delta modulator as described below in order to remove the periodic fixed pattern contained in the first-order sigma-delta modulator and perform noise shaping. I found. However, even if a higher-order modulator is used as the higher-order sigma-delta modulator, the noise shaping effect is reduced and the circuit scale becomes too large. Therefore, the third-order sigma-delta modulator is used.

FIG. 8 shows a configuration example of a third-order sigma delta modulator used in the second embodiment of the present invention.
The sigma delta modulator of this embodiment includes three sets of an adder ADD2, a 1-bit quantizer QTG1, an arithmetic unit ALU1, a subtractor ASC2, and a delay unit DLY1 that constitute the primary sigma delta modulator of FIG. The second stage adder ADD22 receives the output of the first stage delay unit DLY1 instead of F, and the third stage adder ADD23 outputs the output of the second stage delay unit DLY2 instead of F. Is added by the adder ADD3 with the value obtained by differentiating the output of the third-stage 1-bit quantizer QTG3 by the differentiator DFR1 and the output of the second-stage 1-bit quantizer QTG2 The value obtained by differentiating the value by the differentiator DFR2 and the output of the first-stage 1-bit quantizer QTG1 are added by the adder ADD4 and output. The delay units DLY4 and DLY5 are provided to match the delay amounts of the first stage, the second stage, and the third stage.

  By using the third-order sigma-delta modulator, the low frequency fixed pattern included in the fractional part data F / G cannot be seen, and the one diffused to the higher frequency is output. Specifically, for example, when I = 140, F = 28, and G = 1300, “141” is output to the variable frequency divider 631 only 28 times for 1300 times of the reference clock φref, “142”, “143”, etc. are output in the middle of the output of “”, and “138” is output as many times as the number of appearances of “142” so as to cancel it, and the same as the number of appearances of “143”. “137” is output by the number of times. In other words, on average, “141” is output 28 times.

  As a result, when the third-order sigma-delta modulator is used, the same frequency division ratio N as that when the first-order sigma-delta modulator is used is given to the variable frequency divider 631, and the output of the sigma-delta modulator is also provided. Therefore, the spurious on the output of the RF-PLL is reduced, and a noise shaping effect can be obtained. Instead of outputting “142” or “143” and “138” or “137” which cancels it, “141” is output N times (N ≧ 29) more than 1300 times of φref and “139” is output. (N−28) times may be output, and on average, “141” may be output only 28 times for 1300 times of φref.

  Although not particularly limited, the sigma delta modulator of this embodiment can selectively supply the output of the differentiator DFR2 or the value of all zero to the adder ADD4 between the differentiator DFR2 and the adder ADD4. A selector SEL1 is provided. When the output of the differentiator DFR2 is selected, the circuit is operated as a third-order sigma-delta modulator. When an all-zero value is selected, the circuit is operated as a first-order sigma-delta modulator. It is comprised so that it can be made to.

  Next, a third embodiment of the present invention will be described with reference to FIG. In this embodiment, a register REG0 and an adder ADD0 are added to the preceding stage of the sigma delta modulator 642 of the embodiment of FIG. 6, thereby enabling adjustment of the oscillation frequency of the RF-PLL. Specifically, the fractional data D can be set in the register REG0, the numerator data F and the decimal data D are added by the adder ADD0 and supplied to the adder ADD2, and the fractional part of the division ratio The data can be expanded in the decimal direction. Thereby, for example, when “28” is set as the molecular data F and “0.025” is set as the decimal data D, the sigma delta modulator 642 outputs “+1” only 28025 times per 1300000 times. Thus, fine adjustment (fine tuning) of the oscillation frequency of the RF-PLL becomes possible.

  The mobile phone has a phenomenon that the power supply voltage is lowered at the time of transmission using a power amplifier that consumes a large amount of power compared to at the time of reception without using the power amplifier. This phenomenon occurs not only when the battery voltage is used as the power supply voltage but also when the voltage converted by the DC-DC converter is used. For this reason, the frequency of the reference oscillation circuit (DCXO) 261 that generates the reference oscillation signal φref is different slightly between transmission and reception. However, applying this embodiment and setting the decimal data D in the register REG0 makes it possible to avoid such a frequency shift.

  The decimal data D to be set in the register REG0 is determined by measuring the oscillation frequency of the reference oscillation circuit when the power supply voltage is changed in advance, and is rewritten as an EPROM or flash memory in the baseband circuit 300. It may be stored in a possible non-volatile memory, and when the band information BND and the division ratio information NIF are given from the baseband circuit 300 to the high frequency IC 200, the decimal data D is also sent simultaneously and set in the register REG0. . A multiplier may be provided instead of the adder ADD0, and a value such as 1.001 may be set in the register REG0 so that the numerator data F becomes a value including a fractional part.

  FIG. 11 shows a configuration example of the divider DIV2 constituting the frequency division ratio calculation unit 641. The divider DIV2 of this embodiment is realized by repeating subtraction and shift instead of performing division by the numerator data supplied from the adder ADD1 and the denominator data supplied from the multiplier MLT2. With this configuration, the circuit scale is reduced.

Specifically, the divider DIV2 includes a 19-bit X register 411 for setting the numerator data XR (CH · X) supplied from the adder ADD1, and a denominator data YR (65Y) supplied from the multiplier MLT2. An 11-bit Y register 412 that sets the value, a bit shifter 413 that shifts the denominator data YR captured in the Y register 412 to the upper side by a maximum of M bits, a down counter 414 that gives a shift amount M in the bit shifter 413, A comparison circuit 415 for comparing the magnitude of the numerator data XR fetched into the X register 411 and the denominator data YRS shifted by the bit shifter 413, and a value YXRS (partial quotient) indicating the magnitude of the comparison result by the comparison circuit 415 are sequentially added. An adder 416 for storing, a Q register 417 for holding the addition result, and a divider D And a timing control circuit 418 that controls the overall operation V2. By shifting the denominator data YR by M bits to the upper side by the bit shifter 413, the shifted denominator data YRS becomes data having a weight of ^2M .

When the comparison result is “1”, that is, XR ≧ YRS, the comparison circuit 415 calculates “1” having a weight of 2 ^M as a partial quotient YXRS and a difference “XR−YRS” as a partial quotient YXRM. When the comparison result is “0”, that is, XR <YRS, “0” is output as the partial quotient YXRS, and “XR” is output as the remainder YXRM of the partial quotient. The control circuit 418 returns the difference “XR−YRS” to the X register 411 when the comparison result by the comparison circuit 415 is “1”, that is, XR ≧ YRS, and when the comparison result is “0”, that is, XR <YRS. The selector SEL2 in the previous stage of the X register 411 is controlled so that “XR” is returned to the X register 411. The control circuit 418 decrements, that is, decrements, the value M of the counter 414 by “1” every time the comparison operation by the comparison circuit 415 is performed.

The value of “M” is the maximum value among integers satisfying XR ≧ YR × 2 ^M, that is, XR / YR ≧ 2 ^M , based on the relationship between the numerator data XR and the denominator data YR captured in the registers 411 and 412. The For example, when the number of bits of the numerator data XR is 19 and the number of bits of the denominator data YR is 11, the maximum value of XR is 2 ¹⁹ and the maximum value of YR is 2 ¹¹ , so XR / YR = 2 ^From 19/2 ¹¹ = 524288/2048 = 256 = 2 ⁸ , M = 8. In the divider DIV2 of this embodiment, when the comparison operation by the comparison circuit 415 is executed (M + 1) times, that is, 9 times, all the operations are completed, and the value held in the Q register 417 at that time is the “quotient” of the division. “YXRM output from the comparison circuit 415 is the“ remainder ”of the division. The timing control circuit 418 operates in response to a 26 MHz clock signal generated based on the reference oscillation signal φref from the reference oscillation circuit 261, generates an operation reset signal RES and operation clocks CLK1 and CLK2, and includes an internal circuit of the divider DIV2. Supply to the circuit.

Next, the procedure of determining the selection band by the automatic band selection circuit 637 in the frequency division ratio generation logic 264 having the divider DIV2 of FIG. 11 and the PLL circuit of FIG. This will be described using a chart.
12 to 14, FIG. 12 shows the division ratio generation timing in the division ratio generation logic 264. 13 shows the procedure for determining the selected band by the automatic band selection circuit 637. FIG. 14 shows the procedure for mode control by the control circuit 260 and the startup of each VCO in the high frequency IC of FIG. 1 having the PLL circuit of FIG. Show. The division ratio generation in the division ratio generation logic 264 in FIG. 12 is performed immediately before the start of the selection band determination operation in FIG. 13 (period t6′-t61), and the selection band determination operation in FIG. This is performed at the beginning of the warm-up period “Warm up” (period t6-t7) before the transmission mode Tx.

  Before describing the division ratio generation operation of FIG. 12, first, the procedure of mode control by the control circuit 260 and the startup of each VCO in the high frequency IC will be described using the timing chart of FIG. 14A shows the operation of RFVCO, IFVCO, and TXVCO in a conventional high-frequency IC that has an IFVCO and performs frequency measurement of the VCO and performs band selection based on the measurement value, and FIG. The operation of RFVCO and TXVCO in an example high frequency IC is shown.

  When the system is turned on, supply of power to the high frequency IC (200) is started. For example, a command “Word4” is supplied from the baseband IC (300) to the high frequency IC after the power supply is turned on. Then, a circuit such as a register in the high frequency IC is reset by the control circuit (260), and the high frequency IC enters an idle mode (sleep state waiting for a command) (timing t1 in FIG. 14).

  In this state, the oscillation operation of each VCO is stopped. In a conventional high-frequency IC that performs VCO calibration, when a command (Word 7) including a predetermined bit code instructing measurement of the VCO is supplied from the baseband IC during the idle mode “Idle”, RFVCO and IFVCO frequency measurement processing (measurement and storage) is performed, but nothing is done in the high-frequency IC 200 of this embodiment (timing t2 in FIG. 14).

  In the conventional high frequency IC, the frequency measurement of each band of RFVCO and IFVCO is performed in parallel. Thereafter, the frequency of the TXVCO for transmission is measured using the counter used for the frequency measurement of the IFVCO. Therefore, the RFVCO frequency measurement ends earlier. After transmitting the measurement start command “Word7”, the baseband IC sends “Word5, 6” instructing the initial setting when a suitable time has elapsed (timing t3 in FIG. 14). When the TXVCO frequency measurement is completed, the control circuit is notified of the completion, and the control circuit initializes the inside of the high frequency IC for transmission / reception operation after the measurement is completed.

  When this initial setting is completed, the command “Word1” including the frequency information of the used channel is supplied from the baseband IC to the high frequency IC, and the control circuit enters the warm-up mode “Warm up” for starting the VCO (see FIG. 14 timing t4). This command also includes a bit for instructing transmission or reception. When receiving, the RFVCO (262) uses the selected band based on frequency information from the baseband. Then, the RFVCO is oscillated and the RF-PLL loop is locked.

  Thereafter, when a command “Word2” for instructing the reception operation is sent from the baseband IC, the reception mode “Rx” is entered, and the reception system circuit RXC is operated to amplify and demodulate the reception signal (FIG. 14). Timing t5). In the conventional high frequency IC, when "Word1" is supplied, the RF VCO frequency is measured and then the RF synthesizer is locked. Since this frequency measurement is performed for all bands, the binary search method is used. Therefore, it takes a longer time to determine the band to be used than the high-frequency IC of this embodiment that determines the band to be used. If the number of RFVCO bands is 16, for example, it was still in time, but if the number of bands increases to a number such as 256, the RF synthesizer lockup will not be in time for the start of reception. There is a fear. On the other hand, in the high frequency IC of the present embodiment, the band to be used is determined by the binary search method, so that even if the number of bands is large, the lockup of the RF synthesizer can be surely terminated before the start of reception.

  Next, when the reception mode “Rx” ends, a command “Word1” including frequency information is supplied from the baseband IC (300), and the control circuit (260) again enters a warm-up mode “Warm up” for starting the VCO. (FIG. 14, timing t6). When the bit indicating transmission or reception in this command indicates transmission, in the conventional high frequency IC, the IF VCO is activated to lock the IF synthesizer, and based on the frequency information from the baseband IC. The band used for RFVCO and TXVCO is selected. Then, after the band is determined, the RF synthesizer and the TX-PLL loop are locked. On the other hand, in the high frequency IC of the present embodiment, based on the frequency information (CH, T / R, NIF, BND) included in “Word1” in response to the start of the warmup mode “Warmup” by the command “Word1”. After the RFVCO frequency division ratio is generated and the band used for the RFVCO and TXVCO is selected, the RF synthesizer and the TX-PLL loop are locked.

  After that, when “Word3” instructing the transmission operation is sent from the baseband IC 300 to the high frequency IC 200, and “Word3” is received, the control circuit 260 enters the transmission mode and modulates and amplifies the transmission signal (FIG. 14 timing t7). The control circuit 260 also performs switching control of the switches SW1, SW2, etc. depending on whether it is GSM or DCS / PCS. The reception mode “Rx” and the transmission mode “Tx” are executed in units of time called time slots (for example, 577 μsec).

  When the high-frequency IC 200 of this embodiment receives a command “Word1” indicating that “T / R” is transmitted from the baseband IC 300, generation of the RFVCO division ratio is started. As shown in FIG. 12, the division ratio is generated by performing the above-described operation nine times in the divider DIV2 in FIG. 11, and calculating “quotient” Q and “remainder” YXRM. “Q is integer part data I, and“ remainder ”YXRM minus 65 Y / 2 is supplied to sigma delta modulator 642 together with denominator data G as numerator data F. Then, the I / F / G obtained by adding the F / G generated by the sigma delta modulator 642 and the integer part data I by the adder 643 is used as the frequency division ratio N from the frequency division ratio generation logic 264 to the variable frequency divider 631. The variable frequency divider 631 generates and outputs a clock φdiv obtained by dividing the oscillation signal φRF by the frequency division ratio N from the RFVCO 262.

Next, the procedure for determining the selected band by the automatic band selecting circuit 637 in the RF synthesizer 263 will be described with reference to the timing chart of FIG.
When the frequency division ratio generation logic 264 finishes generating the frequency division ratio of the variable frequency divider 631, the control circuit 260 supplies the signal BSS instructing the automatic band selection circuit 637 to start the automatic band selection operation. . Then, the automatic band selection circuit 637 outputs a switch switching signal SC and a reset signal RT for switching the changeover switch 635 on the PLL loop to the fixed voltage VDC side, and from the division ratio generation logic 264 to the variable frequency division circuit 631. Is started to be supplied (timing t61). When the changeover switch 635 is switched to the fixed voltage VDC side, the fixed voltage VDC is supplied to the VCO 262 as the control voltage Vt, and the VCO starts oscillating at a frequency corresponding to the fixed voltage VDC.

  In this embodiment, at the same time, a switching signal is supplied to the sigma delta modulator 642 of FIG. 8 so as to perform the first order sigma delta modulation operation from the third order sigma delta modulation. As described above, when operating as a third-order sigma-delta modulator, the average frequency division ratio of the variable frequency divider 631 is constant, but the frequency division ratio varies locally. On the other hand, in the automatic band selection, in order to determine the advance and delay of the phase of the clock φr ′ obtained by dividing the clock φdiv divided by the variable divider 631 and the reference oscillation signal φr by 1/65 by the fixed divider 636, If the frequency division ratio of the variable frequency divider 631 varies, the phase may shift and correct phase determination may not be performed. Therefore, in this embodiment, at the time of automatic band selection, the sigma delta modulator 642 is operated as a primary sigma delta modulator.

  Further, in the automatic band selection circuit 637, a frequency counter and a control circuit that counts the reference oscillation signal φr from the reference oscillation circuit 261 and performs a timer operation, an output φ1 of the variable frequency dividing circuit 631, and a fixed frequency dividing circuit 636 A phase advance / delay determination circuit that compares the output φr ′ to determine whether the phase of φ1 is advanced or delayed from the phase of φr ′, and a VCO band switching circuit that switches the band of the VCO 262 according to the determination result of the determination circuit 372 When the frequency counter has elapsed 5 μs (microseconds) after the reset signal RT is input, a timer signal is sent to the control circuit. This time of 5 μs is the time required for the voltage of the loop filter 634 to stabilize at the fixed voltage VDC. When 5 μs has elapsed, the control circuit gives a signal instructing the VCO band switching circuit to send the band switching control signals VB0 to VB7 to the VCO 262. As a result, the capacitive element selectively connected in the VCO 262 is switched and the selected band is designated (timing t62). Here, the first designated band is the center band # 127 of 256 bands # 0 to # 255.

  Next, the control circuit in the automatic band selection circuit 637 waits for a short time (for example, 0.5 μs) required for band switching of the VCO 262 and then resets the reset signal RES to the variable frequency dividing circuit 631 and the fixed frequency dividing circuit 636. Send. The variable frequency dividing circuit 631 and the fixed frequency dividing circuit 636 are counter circuits, and the variable frequency dividing circuit 631 and the fixed frequency dividing circuit 636 are once reset to “0” by the reset signal RES, and the reset is released to start counting. To do. When the set division ratios “N” and “65” are counted, pulses φdiv and φr ′ are output, respectively. Since the fixed frequency dividing circuit 636 operates by the accurate reference oscillation signal φr (26 MHz) from the reference oscillation circuit 13, the frequency of the output pulse φr ′ is 400 kHz and the period is 2.5 μs. These output pulses φdiv and φr ′ are supplied to the phase advance / delay determination circuit, and the advance / delay determination circuit has the rising edge of the output pulse φdiv of the variable frequency dividing circuit 631 from the rising edge of the output pulse φr ′ of the fixed frequency dividing circuit 636. To determine whether it is moving forward or late.

  When the phase advance / delay determination circuit determines that the output pulse φdiv of the variable frequency dividing circuit 631 is delayed, the VCO band switching circuit designates a band switching control signal for designating a higher frequency band to the VCO 262. A signal instructing to send VB0 to VB7 is given (timing t63). On the other hand, if it is determined that the output pulse φdiv of the variable frequency dividing circuit 631 is advanced, the phase advance / delay determination circuit 22 instructs the VCO band switching circuit 23 to specify a band of a frequency lower than the current to the VCO 11. Provides a signal to command to send signals VB0-VB7. The band specified by the second band switching control signals VB0 to VB7 is # 191 in the middle of # 127 and # 255 when φdiv is delayed, and is the middle of # 127 and # 0 when φdiv is advanced. # 63.

  When a band switching command is issued, the control circuit waits for a short time (for example, 0.5 μs) required for band switching of the VCO 262, and then sends the reset signal RES to the variable frequency dividing circuit 631 and the fixed frequency dividing circuit 636 again. send. Then, the variable frequency dividing circuit 631 and the fixed frequency dividing circuit 636 are once reset to “0” and restart counting. When the set frequency division ratio N and “65” are counted, pulses φdiv and φr ′ are output, respectively, and the rise of the output pulse φdiv of the variable frequency divider 631 is detected by the fixed frequency divider 636 by the advance / delay discrimination circuit. It is determined whether the output pulse φr ′ is ahead or behind the rising edge.

  When it is determined that the output pulse φdiv of the variable frequency dividing circuit 631 is delayed, the band switching control signals VB0 to VB7 for specifying a higher frequency band to the VCO 262 for the advance / delay determination circuit VCO band switching circuit. Is given to send the signal (timing t64). On the other hand, when it is determined that the output pulse φdiv of the variable frequency dividing circuit 631 is advanced, the advance / delay determination circuit instructs the VCO band switching circuit to specify a band having a frequency lower than the current to the VCO 262. Give a signal to send VB7. The band designated by the third band switching control signals VB0 to VB7 is # 159 in the middle of # 127 and # 191, # 123 in the middle of # 191 and # 255, # 95 in the middle of # 127 and # 63 or It is # 31 in the middle of # 63 and # 0.

  By repeating the above operation eight times, a band suitable for the designated oscillation frequency (frequency corresponding to the frequency division ratio N) is selected from the 256 bands (timing t65). In the eighth determination, the band selected in the seventh determination or a band that is only one higher than the band (or a band lower by one) is selected. With the above operation, the band used for the VCO 262 is determined, the switch 635 on the PLL loop is switched from the fixed voltage VDC to the charge pump 633 side, and the normal PLL frequency pull-in operation is started. Note that the final selected band may be determined by further adding an offset to the band selected in the eighth determination. This offset is for compensating for a determination error caused by a shift in the reset operation between the variable frequency dividing circuit 631 and the fixed frequency dividing circuit 636 due to the reset signal RES.

  At the same time, a switching signal is supplied to the sigma delta modulator 642 in FIG. 8 so that the primary sigma delta modulation operation and the tertiary sigma delta modulation operation are performed. Further, at this time, the inside of the sigma delta modulator 642 is reset. As described above, during the band selection operation, the sigma delta modulator 642 is operated as a primary sigma delta modulator, whereby the clock φdiv and the reference oscillation signal φr divided by the variable frequency divider 631 are fixed. Thus, it is possible to correctly determine the phase advance / delay of the clock φr ′ divided by 1/65 at 636. Moreover, in the high frequency IC to which the PLL circuit of the present embodiment is applied, the voltage immediately before the switch 635 is switched from the fixed voltage VDC to the charge pump 633 side becomes a value very close to the loop filter voltage, that is, the fixed voltage VDC. The frequency acquisition is also completed in a very short time.

  Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto. For example, in the above-described embodiment, the decoders DEC1 and DEC2 that generate values to be multiplied by the inputs in the multipliers MLT1 and MLT2 provided in the frequency division ratio generation circuit 641 have been described. Instead of providing DEC1 and DEC2, a value corresponding to the output of the decoder (see FIGS. 4 and 5) may be provided from the baseband circuit 300 to the high frequency IC 200.

  In the above embodiment, the frequency division ratio NIF of the IF divider 231 is given from the baseband circuit 300 outside the chip. The frequency division ratio NIF may be automatically determined within the chip from the indicated information T / R, band information BND, and channel information CH, and set in the IF frequency divider 231.

  Further, in the above-described embodiment, the high frequency IC in which the transmission system circuit and the reception system circuit are formed on the same semiconductor chip has been described. However, the transmission system circuit and the RF-PLL are built in and formed on separate semiconductor chips. The present invention can also be applied to a circuit in which an oscillation signal generated by the RF-PLL is supplied to a reception system circuit. Further, although the description has been given of the case where the oscillation circuit (DCXO) 261 for generating the reference signal φref is formed on the same semiconductor chip as the transmission system circuit and the reception system circuit, the reference signal φref is given from the outside of the chip. Anyway.

  In the above description, the invention made mainly by the present inventor has been described as being applied to the frequency dividing circuit constituting the RF-PLL in the high frequency IC which is the field of use behind the invention. The present invention can be generally applied to a variable frequency divider that divides a frequency by a division ratio composed of a part and a decimal part. In the embodiments, the case where the present invention is applied to a high-frequency IC used in a wireless communication system such as a mobile phone has been described. However, the present invention is not limited to this, and the reception signal or The present invention can also be applied to a high-frequency IC having a PLL circuit that generates a high-frequency signal that is combined with a transmission signal and performs frequency conversion and modulation / demodulation.

1 is a block diagram illustrating an example of a multiband communication semiconductor integrated circuit (high frequency IC) to which the present invention is applied and a communication system using the same. FIG. It is a block diagram which shows the structural example of the synthesizer of RF-PLL in the high frequency IC of an Example, and a division ratio setting logic. It is a block diagram which shows the structural example of the frequency division ratio calculation part which comprises the frequency division ratio setting logic of FIG. It is explanatory drawing which shows the relationship between the input and output of a decoder accompanying the multiplier MLT1 which comprises the frequency division ratio calculation part of FIG. It is explanatory drawing which shows the relationship between the input and output of a decoder accompanying the multiplier MLT2 which comprises the frequency division ratio calculation part of FIG. FIG. 3 is a block diagram showing a configuration example of a sigma delta modulator constituting the frequency division ratio setting logic of FIG. 2. 7 is a timing chart showing operation timing of the sigma delta modulator of FIG. 6. It is a block diagram which shows the structural example of the 3rd-order sigma-delta modulator used for the 2nd Example of this invention. 3 is a timing chart showing operation timings of the frequency division ratio setting logic of FIG. 2. It is a block diagram which shows the structural example of the sigma delta modulator in the 3rd Example of this invention. It is a block diagram which shows the structural example of the divider which comprises a frequency division ratio calculation part. It is a timing chart which shows the division ratio production | generation timing in a division ratio production | generation logic. It is a timing chart which shows the procedure of the selection band determination by an automatic band selection circuit. It is a timing chart which shows the procedure of the mode control in the high frequency IC for GSM, and starting of each VCO.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Transmission / reception antenna 110 Transmission / reception switching switch 120 Filter 130 High frequency power amplifier circuit 200 High frequency IC
211 Low Noise Amplifier 212 Demodulation & Down-Conversion Mixer 213 High Gain Amplifier 231 IF Divider 233 Modulation & Up-Conversion Mixer 235 Offset Mixer 240 Transmission Oscillator (TXVCO)
260 Control circuit 261 Reference oscillation circuit 262 Oscillation circuit (RFVCO)
263 Synthesizer 264 Divide ratio generation logic 631 Variable divider circuit 632 Phase comparison circuit 633 Charge pump 634 Loop filter 637 Band selection circuit

Claims (11)

An oscillation circuit, a variable frequency dividing circuit capable of dividing an oscillation signal of the oscillation circuit by a frequency division ratio (I + F / G) including an integer part I and a fractional part F / G, and an output signal of the variable frequency dividing circuit A PLL circuit having a phase comparison circuit that detects a phase difference of a reference signal and a frequency control circuit that outputs a voltage according to the phase difference detected by the phase comparison circuit and controls the oscillation frequency of the oscillation circuit. A semiconductor integrated circuit for communication,
A frequency division ratio calculating circuit for calculating a frequency dividing ratio to be given to the variable frequency dividing circuit based on a transmission start command and use frequency band information supplied from the outside;
The variable frequency dividing circuit is operated according to the frequency dividing ratio calculated by the frequency dividing ratio calculating circuit, and the phase of the output signal of the variable frequency dividing circuit is supplied in a state where a predetermined level of potential is supplied as a control voltage to the oscillation circuit. A band selection circuit that compares the phase of a signal obtained by dividing a reference signal by a predetermined division ratio and selects an oscillation frequency band of the oscillation circuit;
After the oscillation frequency band of the oscillation circuit is selected by the band selection circuit, the oscillation circuit is operated by switching the control voltage of the oscillation circuit from the predetermined level potential to the output voltage of the frequency control circuit. A communication semiconductor integrated circuit device.   A frequency dividing circuit that divides the oscillation signal generated by the oscillation circuit to generate an intermediate frequency signal; a modulation circuit that modulates the signal divided by the frequency dividing circuit with a transmission baseband signal; A first frequency conversion circuit that converts a signal modulated by the modulation circuit into a transmission signal having a higher frequency, a signal extracted from the output side of the first frequency conversion circuit, and a signal divided by the frequency divider circuit A second frequency conversion circuit that synthesizes and generates a signal having a frequency corresponding to the frequency difference between those signals; and a phase difference between the signal converted by the second frequency conversion circuit and the signal modulated by the source modulation circuit. 2. A second phase comparison circuit for detecting, wherein the first frequency conversion circuit oscillates at a frequency corresponding to a phase difference detected by the second phase comparison circuit. Semiconductor integrated circuit for communication.   A second frequency dividing circuit for frequency-dividing the oscillation signal generated by the oscillation circuit; and a received signal and the signal divided by the second frequency dividing circuit to synthesize the received signal into a low-frequency signal. The communication semiconductor integrated circuit according to claim 2, further comprising a three-frequency conversion circuit.   The frequency division ratio generation circuit generates the integer part I and the fractional part F / G based on externally supplied frequency band information, mode information indicating transmission or reception, and channel information, and generates the variable part. 4. The communication semiconductor integrated circuit device according to claim 1, wherein the communication semiconductor integrated circuit device is applied to a peripheral circuit.   The denominator G of the fractional part F / G is generated based on any integer selected from a plurality of integer combinations prepared in advance corresponding to the band information and the setting information related to the frequency division ratio. 5. The communication semiconductor integrated circuit device according to claim 4, wherein the communication semiconductor integrated circuit device is configured as described above.   The frequency division ratio generation circuit divides a value selected from a combination prepared in advance corresponding to use frequency band information, channel information, and mode information by the selected denominator G to obtain a quotient as an integer part I. A divide ratio calculation circuit that outputs the remainder as a numerator F, a delta-sigma modulation circuit that generates a fractional part F / G by delta-sigma modulation of the numerator F using the denominator G, and the delta-sigma 6. The communication semiconductor integrated circuit according to claim 5, comprising an adder circuit that synthesizes and outputs an output of a modulation circuit and the integer part I.   The frequency division ratio calculation circuit is prepared in advance corresponding to a shift circuit that sequentially bit shifts the selected denominator G, a value shifted by the shift circuit, the used frequency band information, channel information, and mode information. A comparison operation circuit that performs a magnitude comparison operation with a value selected from among the combinations or a return value and generates the return value, and repeatedly executes the bit shift and the size comparison operation with the integer part I. The communication semiconductor integrated circuit according to claim 6, wherein the molecule F is generated.   The delta sigma modulation circuit is a second or higher order delta sigma modulation circuit, and the selection operation of the oscillation frequency band of the oscillation circuit by the band selection circuit causes the delta sigma modulation circuit to operate as a primary delta sigma modulation circuit. The communication semiconductor integrated circuit according to claim 6, wherein the communication semiconductor integrated circuit is performed.   The delta-sigma modulation circuit includes an addition circuit that adds the input numerator data F and the feedback data, a 1-bit quantization circuit that quantizes the addition result, an arithmetic circuit that multiplies the output of the quantization circuit, A subtracting circuit for obtaining a difference between an output of the arithmetic circuit and the output of the adding circuit; and a delay circuit for delaying the obtained difference, and the difference delayed by the delay circuit is supplied to the adding circuit as the feedback data 9. The communication semiconductor integrated circuit according to claim 8, wherein the communication semiconductor integrated circuit is configured as described above.   The delta-sigma modulation circuit includes a plurality of sets of the addition circuit, the 1-bit quantization circuit, the arithmetic circuit, the subtraction circuit, and the delay circuit, and outputs another set of quantization circuits to another set of quantization circuits. The outputs obtained by differentiating the output of the subtracting circuit by the subtracting circuit are sequentially added and output, and instead of the output of the subtracting circuit, an all-zero value is added and output to obtain a first-order delta-sigma modulation circuit. The communication semiconductor integrated circuit according to claim 9, wherein the communication semiconductor integrated circuit operates. An oscillation circuit, a variable frequency dividing circuit capable of dividing an oscillation signal of the oscillation circuit by a frequency division ratio (I + F / G) represented by an integer part I and a fractional part F / G, A PLL having a phase comparison circuit that detects a phase difference between an output signal and a reference signal, and a frequency control circuit that outputs a voltage corresponding to the phase difference detected by the phase comparison circuit and controls the oscillation frequency of the oscillation circuit A communication semiconductor integrated circuit comprising a circuit,
A frequency division ratio calculating circuit for calculating a frequency dividing ratio to be given to the variable frequency dividing circuit based on a transmission start command and use frequency band information supplied from the outside;
The variable frequency dividing circuit is operated according to the frequency dividing ratio calculated by the frequency dividing ratio calculating circuit, and the phase of the output signal of the variable frequency dividing circuit is supplied in a state where a predetermined level of potential is supplied as a control voltage to the oscillation circuit. A band selection circuit that compares the phase of a predetermined signal and selects an oscillation frequency band of the oscillation circuit;
After the oscillation frequency band of the oscillation circuit is selected by the band selection circuit, the oscillation circuit is operated by switching the control voltage of the oscillation circuit from the predetermined level potential to the output voltage of the frequency control circuit. A communication semiconductor integrated circuit device.

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