JP2006041318A - Wiring structure and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress mismatching in characteristic impedance, when the shape of a wiring pattern changes. <P>SOLUTION: A wiring structure comprises a wiring pattern 11 (first wiring pattern) formed on the surface of an insulating board 1, and an auxiliary wiring pattern 12 (second wiring pattern) that is formed inside the insulating board 1, corresponding to the portion in which the width of the wiring pattern 11 changes and is electrically connected to the wiring pattern 11 in parallel. In electronic equipment, an electronic component is connected to an electrode land 10, making continuity with the wiring pattern 11 in the wiring structure. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a wiring structure and an electronic device in which a wiring pattern is formed on an insulating substrate, and more particularly to a wiring structure and an electronic device that can suppress impedance mismatch between the wiring pattern and an electronic component.

  2. Description of the Related Art In recent years, signal processing in electronic devices has been rapidly performed and miniaturized, and consideration of transmission lines has become important in wiring design on printed wiring boards. As signal transmission speeds increase, ensuring signal quality on printed wiring boards has become important, and as size reduction (narrow pitch), it becomes difficult to ensure specified wiring specifications. ing.

In general, it is difficult to draw wiring from a semiconductor component (chip size package or the like) having an area array arrangement with a narrow pitch. As a countermeasure against this, as shown in FIG. 6, the width of the wiring pattern 11 is partially narrowed so that the gap between the electrode lands 10 is passed.
In addition, as shown in Patent Document 1, there is an example in which drawing is realized by making the outer peripheral semiconductor component land into an oval shape.

here,
A characteristic impedance mismatch is a cause of signal reflection. Typical occurrence points of characteristic impedance mismatch on the printed wiring board are as follows.
(1) Connection part from the semiconductor component (output side) to the printed wiring board.
(2) Wiring width changing point on the printed wiring board, branch point, lead-out part from narrow pitch component, signal branch point.
(3) A connection part from the printed wiring board to the semiconductor component (input side).

  In the case of (1) above, the characteristic impedance is the output impedance of the semiconductor component <printed wiring board pattern, and in the case of (3), the printed wiring board pattern <the input impedance of the semiconductor component.

Conventionally, means for suppressing signal reflection include the following.
<1> Addition of various termination circuits (for example, insertion of series resistors, parallel termination, addition of other termination circuits).
<2> Optimization of wiring form (for example, shortening of wiring length, equal-length branching wiring)

Japanese Patent Laid-Open No. 11-26919

  However, in the above <1>, addition of parts is required, and therefore, when applied to a bus wiring that transmits a plurality of signals in parallel, an area required for the wiring is increased. In addition, the cost increases due to the addition of parts. Further, in the above <2>, in the case of a multi-pin narrow-pitch component, the distance between the components becomes long due to the component size restriction, and there are cases where the required wiring length cannot be shortened. Further, in the case of the equal-length branch type wiring, it is necessary to match the wiring length after branching, which causes a problem that a large wiring area is required.

  The present invention has been made to solve such problems. That is, the present invention provides a first wiring pattern formed on the surface of the insulating substrate and an inner portion of the insulating substrate corresponding to a portion where the width of the first wiring pattern is changed. And a second wiring pattern electrically connected in parallel. Further, the electronic device is formed by connecting an electronic component to an electrode land that is electrically connected to the first wiring pattern of the wiring structure.

  In the present invention as described above, the second wiring pattern is connected in parallel corresponding to the portion where the width of the first wiring pattern changes or the branching portion, so that the characteristic impedance of the first wiring pattern can be reduced. The shift can be compensated by the second wiring pattern.

  Therefore, the present invention has the following effects. In other words, the second impedance pattern is formed in the insulating substrate where mismatching of characteristic impedance occurs in a portion where the line width of the first wiring pattern formed on the surface of the insulating substrate must be narrowed or a portion where it must branch. The wiring pattern can compensate for this, and the characteristic impedance mismatch in the first wiring pattern can be eliminated without mounting a special component on the surface. In particular, even if there is a place where it is difficult to secure the wiring width in the surface direction of the insulating substrate due to the lead-out portion from the minimized narrow-pitch component and through vias densely, the characteristic impedance can be matched without additional mounting of the termination component It becomes possible. Accordingly, it is possible to provide an electronic device that can cope with high-speed and small signal transmission.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1A and 1B are schematic views for explaining a wiring structure according to the present embodiment, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along line AA shown in FIG. In this wiring structure, a wiring pattern (first wiring pattern) 11 formed on the surface of the insulating substrate 1 and electrode lands 10 which are conductive with the wiring pattern 11 and serve as pads for electrical connection with a semiconductor element or the like. And an auxiliary wiring pattern (second wiring pattern) 12 formed inside the insulating substrate 1 corresponding to a portion where the line width of the wiring pattern 11 changes.

  The line width of the wiring pattern 11 formed on the surface of the insulating substrate 1 is very thin from the viewpoint of miniaturization, and is provided at a narrow pitch. Therefore, a gap between the electrode lands 10 formed at the end of each wiring pattern 11 is provided. Is also very narrow. In such an arrangement, when the wiring pattern 11 is routed to the other electrode land 10 through between the adjacent electrode lands 10, it is necessary to make it thinner than a normal line width in order to pass the gap between the electrode lands 10. In some conventional techniques, the gap between the electrode lands is widened by making the shape of the electrode lands oval. However, since the terminals on the semiconductor element side connected to the electrode lands are ball-shaped, It will be different from the shape, which will lead to a decrease in soldering strength.

  In the present embodiment, since the wiring pattern 11 is passed through the gap between the electrode lands 10 in a state where the circular electrode land 10 is used, the characteristic impedance mismatch occurring at the portion where the line width of the wiring pattern 11 is narrowed is eliminated. From the viewpoint, there is a feature in that the auxiliary pattern 12 is formed inside the insulating substrate 1.

  The auxiliary pattern 12 is configured to connect the wiring pattern 11 before and after the line width changes by the via hole 20 and to be electrically connected to the wiring pattern 11 in parallel. That is, two via holes 20 that are electrically connected to the wiring pattern 11 and extend in the depth direction of the insulating substrate 1 are formed before and after the portion where the line width of the wiring pattern 11 changes, and the conductor between the two via holes 20 is formed. As a result of the connection, the auxiliary wiring pattern 12 is provided in parallel with the wiring pattern 11 inside the insulating substrate 1 corresponding to the portion where the line width of the wiring pattern 11 changes.

  In the portion where the line width of the wiring pattern 11 changes, a mismatch in preset characteristic impedance occurs. By connecting the auxiliary wiring pattern 12 in parallel corresponding to this portion, the wiring pattern 11 As for the portion where the line width changes, the characteristic impedance is shifted in a matching direction by parallel connection with the auxiliary wiring pattern 12.

  Specifically, the width, thickness, number, and material of the auxiliary wiring pattern 12 are adjusted so that the characteristic impedance of the portion formed by the wiring pattern 11 and the auxiliary wiring pattern 12 is the same as that of the other portions.

  Since the auxiliary wiring pattern 12 is formed inside the insulating substrate 1, it can be manufactured in a process of forming a multilayer wiring. In addition, by configuring the auxiliary wiring pattern 12 and the wiring pattern 11 with the same material, it is possible to realize a configuration for suppressing characteristic impedance mismatch without the need to separately mount parts on the surface or use different materials.

  Here, the relationship between the characteristic impedance and the pattern line width will be described. FIG. 2 is a schematic cross-sectional view showing a micro strip wiring in which a wiring pattern (surface wiring pattern) is formed on the surface of an insulating substrate and a plane layer (Ground or power supply) is formed on the back surface. For example, in order to realize a wiring pattern having a characteristic impedance of 50Ω when the thickness T1 of the surface wiring pattern is 0.03 mm, the thickness H1 of the insulating substrate is 0.225 mm, and the relative dielectric constant εr is 4.5. Requires 0.38 mm as the line width W1.

  The characteristic impedance of the micro strip wiring shown in FIG.

In Equation 1, Z ₀ is the characteristic impedance of the surface wiring pattern, εr is the relative dielectric constant of the insulating substrate, T is the thickness of the surface wiring pattern, and H is the thickness of the insulating substrate from the plane layer to the surface wiring pattern (FIG. 2). It corresponds to H1 shown in FIG.

  FIG. 3 is a schematic cross-sectional view showing an embedded micro strip wiring in which a wiring pattern (internal wiring pattern) is formed inside the insulating substrate and a plane layer is formed on the back surface. For example, when the thickness T2 of the surface wiring pattern is 0.025 mm, the thickness H of the insulating substrate from the plane layer to the internal wiring pattern is 0.1 mm, and the relative dielectric constant εr is 4.5, the characteristic impedance of 50Ω In order to realize such a wiring pattern, a line width W1 of 0.14 mm is required.

  The characteristic impedance of the embedded micro strip wiring shown in FIG.

In Equation 2, Z ₀ is the characteristic impedance of the internal wiring pattern, εr is the relative dielectric constant of the insulating substrate, T is the thickness of the internal wiring pattern, and H is the thickness of the insulating substrate from the plane layer to the internal wiring pattern (FIG. 3). It corresponds to H shown in FIG.

  As described above, when wiring is performed using one pattern each of the surface wiring pattern and the internal wiring pattern, when the electrode land is arranged at a pitch of 0.5 mm, for example, in the line width realizing the characteristic impedance of 50Ω, the electrode land It is impossible to pass a wiring pattern of this line width between them. Therefore, the wiring pattern must be thinned at the portion passing between the electrode lands, resulting in characteristic impedance mismatch.

  In the present embodiment, since the auxiliary wiring pattern 12 is connected in parallel inside the insulating substrate 1 corresponding to the portion where the line width of the wiring pattern 11 formed on the surface becomes narrow, mismatch of characteristic impedance is caused by these wiring patterns. Can be suppressed.

  FIG. 4 is a schematic cross-sectional view when a wiring pattern (surface wiring pattern) is formed on the surface of an insulating substrate, and wiring patterns (internal wiring patterns) are connected in parallel inside. Here, it is assumed that the line width of the surface wiring pattern is narrowed so as to pass between the electrode lands, and the line width is 0.05 mm. Surface wiring pattern thickness T1, internal wiring pattern thickness T2, insulating substrate thickness H1 from the plane layer to the surface wiring pattern, insulating substrate thickness H from the plane layer to the internal wiring pattern, relative dielectric constant εr When the above example is the same, the characteristic impedance of each one of the surface wiring pattern and the internal wiring pattern is 108Ω for the surface wiring pattern and 76Ω for the internal wiring pattern. That is, the surface wiring pattern is 108Ω-50Ω = 58Ω and the internal wiring pattern is 76Ω-50Ω = 26Ω with respect to the target 50Ω.

  On the other hand, when each 0.05 mm surface wiring pattern and internal wiring pattern are connected in parallel, the characteristic impedance in the section connected in parallel is 45Ω, which is a deviation of 5Ω from the target 50Ω. It will be over.

  Calculation of the characteristic impedance when the surface wiring pattern and the internal wiring pattern are connected in parallel is as shown in the following equations 3 to 5.

Here, the calculation is performed in the case where the wiring T ₁ as the surface wiring pattern and the wiring T ₂ as the internal wiring pattern are connected in parallel as shown in FIG. 5, and Equation 3 represents the characteristic impedance Z _{0 (T1) of} the wiring T ₁ , the number 4 wire T ₂ of the characteristic impedance _{Z0 (T2),} the number 5 is a formula for the characteristic impedance Z ₀ of the parallel-connected sections.

  In this way, by providing the auxiliary wiring pattern in parallel connection corresponding to the part where the line width of the wiring pattern becomes narrow, mismatching of characteristic impedance can be suppressed, and the electronic component is connected to the electrode land that conducts with this wiring pattern. As a result, a circuit with impedance matching can be configured, and an electronic device capable of high-speed signal transmission can be provided. In addition, by forming the auxiliary wiring pattern inside the insulating substrate, it is possible to eliminate the mismatch of characteristic impedance without connecting any parts to the surface and without affecting the wiring pattern formed on the surface. Thus, it is possible to meet the demand for miniaturization of circuit boards and electronic devices.

  In the above description, the example in which the auxiliary wiring pattern is provided mainly corresponding to the part where the line width of the wiring pattern becomes narrow is shown. However, it corresponds to the part causing the characteristic impedance mismatch such as the part where the wiring pattern branches. Thus, an auxiliary wiring pattern may be provided.

  In addition, the specific numerical values shown above are merely examples, and in the present invention, the characteristic impedance of the auxiliary wiring pattern 12 due to the part where the line width of the wiring pattern 11 formed on the surface of the insulating substrate 1 changes or the part where it branches off is shown. Any other numerical value can be applied as long as the line width, material, and length compensate for the deviation.

It is a schematic diagram explaining the wiring structure which concerns on this embodiment. It is a schematic cross section which shows the Micro strip wiring in which the surface wiring pattern was formed. It is a schematic cross section which shows Embedded Micro strip wiring in which the internal wiring pattern was formed. It is a schematic cross section which shows the state by which the surface wiring pattern and the internal wiring pattern were connected in parallel. It is a schematic cross section explaining calculation of characteristic impedance. It is a schematic top view explaining a prior art example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 10 ... Electrode land, 11 ... Wiring pattern, 12 ... Auxiliary wiring pattern, 20 ... Via hole

Claims (8)

A first wiring pattern formed on the surface of the insulating substrate;
A second wiring pattern formed inside the insulating substrate corresponding to a portion where the width of the first wiring pattern changes, and electrically connected in parallel with the first wiring pattern. Wiring structure. A first wiring pattern formed on the surface of the insulating substrate;
The second wiring pattern is formed inside the insulating substrate corresponding to a portion where the first wiring pattern branches, and is electrically connected in parallel to the first wiring pattern. Wiring structure. The wiring structure according to claim 1, wherein the second wiring pattern has a line width that compensates for a deviation in characteristic impedance at a portion where the width of the first wiring pattern changes. The wiring structure according to claim 1, wherein the first wiring pattern and the second wiring pattern are made of the same material. A first wiring pattern formed on the surface of the insulating substrate;
A second wiring pattern formed inside the insulating substrate corresponding to a portion where the width of the first wiring pattern changes, and electrically connected in parallel with the first wiring pattern;
An electronic device comprising: an electronic component connected to an electrode land electrically connected to the first wiring pattern. A first wiring pattern formed on the surface of the insulating substrate;
A second wiring pattern formed inside the insulating substrate corresponding to a portion where the first wiring pattern branches, and electrically connected in parallel with the first wiring pattern;
An electronic device comprising: an electronic component connected to a land that is electrically connected to the first wiring pattern. The electronic apparatus according to claim 5, wherein the second wiring pattern compensates for a deviation between the characteristic impedance of the first wiring pattern and the impedance of the electronic component. The electronic device according to claim 5, wherein the first wiring pattern and the second wiring pattern are made of the same material.

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