JP2006041297A - Mechanical characteristic deciding method of insulating thin film material - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for deciding the mechanical characteristics of an insulating film material by using a parameter related to the mechanical characteristics of an insulating film material except elastic modulus and hardness which shows a relation to a failure generated upon employing a semiconductor device. <P>SOLUTION: The mechanical characteristics deciding method of an insulating thin film material employed for a semiconductor device comprises an indenter pushing energy obtaining process (A102, S104), wherein an indenter is pushed to obtain the indenter pushing energy based on a load from no-load to the maximum load and the amount of displacement, and an elastic recovery energy obtaining process (A106, S108) wherein an elastic recovery energy is obtained based on respective loads and amounts of displacement upon releasing the pushed indenter from the maximum load to no-load. The mechanical characteristic of the insulating material thin film is decided (S112) by a value obtained by dividing a difference between the indenter pushing energy and the elastic recovery energy by the indenter pushing energy. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for determining mechanical properties of an insulating material thin film, and more particularly to a method for determining the mechanical strength of a low dielectric constant insulating film on which a Cu wiring is formed in a semiconductor device.

  With the miniaturization and speeding up of semiconductor devices, the wiring structure has been increased from a single layer structure to a multilayer structure, and semiconductor devices having a metal wiring structure of five or more layers have been developed and produced. However, as miniaturization progresses, so-called inter-wiring parasitic capacitance and signal transmission delay due to wiring resistance become a problem. In recent years, with the increase in the number of layers, the influence of signal transmission delay due to the wiring structure on the speeding up of the semiconductor device has increased, and various methods have been taken as a workaround. In general, the signal transmission delay can be expressed by the product of the inter-wiring parasitic capacitance and the wiring resistance. In order to reduce the wiring resistance, a shift from a conventional aluminum (Al) wiring to a copper (Cu) wiring having a low resistance has been studied.

  Since Cu is difficult to finely process by the dry etching method frequently used in the formation of Al alloy wiring, Cu film is deposited on the insulating film subjected to the groove processing, and other than the portion embedded in the groove A so-called damascene method, in which the Cu film is removed by chemical mechanical polishing (CMP) to form a buried wiring, is mainly employed. In general, a Cu film is formed by forming a thin seed layer by sputtering or the like and then forming a laminated film having a thickness of about several hundreds of nanometers by electrolytic plating.

In addition, in order to reduce the capacitance between wirings, instead of the conventional insulating film by CVD (Chemical Vapor Deposition) method using silicon oxide (SiO ₂ ), a SiOF film by CVD method can be used, CVD method or spin coating can be used. It has been studied to use an organic silicon oxide film or an organic resin (polymer) film by a method as a low dielectric constant insulating film (low-k film). A method of manufacturing a semiconductor device having a multilayer wiring structure in which such a low-k film and a Cu wiring are combined is as follows.

FIG. 9 is a process sectional view showing a method of manufacturing a semiconductor device having a multilayer wiring structure in which a conventional low-k film and a Cu wiring are combined.
In FIG. 9, a method for forming a device portion or the like is omitted.
In FIG. 9A, a first insulating film 221 is formed on a substrate 200 made of a silicon substrate by a method such as CVD.
In FIG. 9B, a groove structure (opening H) for forming a Cu metal wiring or a Cu contact plug is formed in the first insulating film 221 by photolithography and dry etching.
In FIG. 9C, a barrier metal film 240 and a Cu seed film are deposited on the first insulating film 221 by a physical vapor deposition (PVD) method or a CVD method, and a Cu film 260 is deposited by a plating method. And annealed at a temperature of 150 ° C. to 400 ° C. for about 30 minutes.
In FIG. 9D, the Cu film 260 and the barrier metal film 240 are removed by chemical mechanical polishing (CMP), and planarization is performed, thereby forming an embedded wiring made of Cu in the opening H that is a groove.
In FIG. 9E, after the reducing plasma treatment is performed on the surface of the Cu film 260, a second insulating film 281 is formed.
Furthermore, when forming multilayer Cu wiring, it is common to repeat these processes and to laminate. Here, most of the first insulating film 221 and the second insulating film 281 are low-k films.

In general, it is said that the relative dielectric constant of the SiOF film can be reduced to about 3.3 (the relative dielectric constant of the conventionally used SiO ₂ film is 3.9), but the dielectric constant is lowered to that. This is extremely difficult in practice from the viewpoint of the stability of the film. On the other hand, the low dielectric constant insulating film, for example, the organic silicon oxide film that introduces a methyl group into SiO ₂ can reduce the relative dielectric constant to about 2.5 by adjusting the amount of the methyl group. In addition, since it is possible to lower the relative dielectric constant to about 2.0 by introducing vacancies in the film, studies are currently being actively conducted.

On the other hand, in a semiconductor device using a low dielectric constant insulating film, for example, when heat treatment is performed on the low dielectric constant insulating film on which the Cu wiring is formed, cracks may occur in the low dielectric constant insulating film due to thermal expansion of Cu. is there. The formation of such cracks is said to depend on the mechanical properties of the low dielectric constant insulating film.
At present, most of the mechanical characteristics of low dielectric constant insulating films are discussed in terms of elastic modulus and hardness for which evaluation methods are almost established.

  As a method of measuring the modulus of elasticity and hardness, the hardness and modulus of elasticity are determined from the work that the indenter pressed into the surface of the material to be measured up to the maximum load (loading) and the work that the film pressed into the indenter during unloading. A method for obtaining a ratio and measuring the elastic modulus and hardness using the ratio is disclosed (for example, see Patent Document 1).

  Further, a method for obtaining an elastic modulus from a ratio between a deflection amount of a substrate on which a thin film is formed and a deflection amount of the substrate after the thin film is removed is disclosed (for example, see Patent Document 2).

In addition, as a method for forming a low dielectric constant film, a method using a crystalline organic film containing tetrafluoro-p-xylylene is disclosed (for example, see Patent Document 3).
JP 2001-349815 A JP 2003-232709 A JP 2003-273096 A

  However, there are cases where the problems caused by the mechanical characteristics of the low dielectric constant insulating film as described above cannot be explained only by the elastic modulus and hardness. For example, although the elastic modulus is almost the same, a crack is generated in the low dielectric constant insulating film, and some of the Cu exudes and some does not exude. Therefore, it is desired to derive parameters related to the mechanical characteristics of the low dielectric constant insulating film that show a correlation with defects occurring when used in semiconductor devices, other than the elastic modulus and hardness.

  The present invention overcomes the above-mentioned problems and uses parameters relating to the mechanical properties of the insulating material film that show a correlation with defects occurring when used in semiconductor devices, other than the elastic modulus and hardness. It is an object of the present invention to provide a method for determining mechanical properties of a conductive material film.

The mechanical property determination method of the insulating material thin film of the present invention is:
In a method for determining mechanical properties of an insulating material thin film used in a semiconductor device,
An indenter pushing energy acquisition step of pushing an indenter into the insulating material thin film, obtaining an indenter pushing energy based on a load from no load to a maximum load and a displacement amount of the insulating material thin film at each load;
Elastic recovery energy for acquiring elastic recovery energy based on each load when the indenter pushed into the insulating material thin film is unloaded from the maximum load to no load and the amount of displacement of the insulating material thin film at each load Acquisition process;
With
The mechanical property of the insulating material thin film is determined by a value obtained by dividing a difference between the indenter indentation energy and the elastic recovery energy by the indenter indentation energy.

  By using the value obtained by dividing the difference between the indenter indentation energy and the elastic recovery energy by the indenter indentation energy, that is, the energy dissipation value (in terms of percentage, the energy dissipation rate), other than the elastic modulus and hardness, The mechanical characteristics of the insulating material thin film can be determined by a parameter indicating a correlation with a defect generated when used in a semiconductor device.

  In particular, if the value is 0.1 or less, it is determined that the insulating material thin film has mechanical characteristics that can be used for a semiconductor device.

  If the energy dissipation value is 0.1, that is, if the energy dissipation rate is 10% or less, the low dielectric constant insulating film will not crack as will be described later. Therefore, if the energy dissipation rate is 10% or less, it can be determined that the insulating material thin film has mechanical characteristics that can be used for a semiconductor device.

  In particular, in the method for determining mechanical properties of an insulating material thin film, the mechanical properties are determined for an insulating material thin film having a relative dielectric constant smaller than 3.9.

  It is particularly effective to determine the mechanical characteristics by this method for an insulating material thin film having a relative dielectric constant of less than 3.9, which has a problem that cannot be determined by elastic modulus and hardness.

  Similarly, in the method for determining mechanical characteristics of an insulating material thin film, the mechanical characteristics are determined for an insulating material thin film made of either an organic silicon oxide film or an organic polymer film. .

  It is particularly effective to determine the mechanical characteristics by this method for the organic silicon oxide film and the organic polymer film which are materials for forming the low dielectric constant film.

  As described above, according to the present invention, it is possible to determine the mechanical characteristics of the insulating material thin film with parameters indicating a correlation with defects occurring when used in a semiconductor device other than the elastic modulus and hardness. Therefore, a highly reliable semiconductor device using a low dielectric constant insulating film having excellent mechanical characteristics can be shown.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a flow of a method for determining mechanical properties of an insulating material thin film in the first embodiment.
As a flow of the mechanical property determination method of the insulating material thin film, an indenter press-in test is performed on the insulating material thin film to be determined, and a load-displacement curve from a load of 0 to the maximum load (indentation energy acquisition process) A press-fit curve acquisition step (S102) for acquiring a press-fit curve), a press-fit energy calculation step (S104) for calculating press-fit energy at the time of indenter press-in, and a load-displacement curve (unload) at the time of indenter removal as an elastic recovery energy acquisition step Curve unloading curve acquisition step (S106), an elastic recovery energy calculation step (S108) when removing the indenter, an energy dissipation rate calculation step (S110), and a determination step (S112).

FIG. 2 is a diagram illustrating an example of a press-fitting and unloading curve obtained in an indenter press-fitting test for a low dielectric constant insulating film.
First, as a press fit curve acquisition step, an indenter is pushed into an insulating material thin film to be judged, and a load from no load to a maximum load and a displacement amount of the insulating material thin film at each load are acquired. And the obtained load and displacement amount are plotted, and a load-displacement curve (press-fit curve) is acquired. In FIG. 2, in the press-fitting curve, the displacement at no load is “0”, and the displacement at the maximum load is “hmax”.

Subsequently, as the press-fit energy calculation step, the indenter pushing energy is acquired based on the load from no load to the maximum load and the displacement amount of the insulating material thin film at each load.
FIG. 3 is a diagram showing a calculation formula for calculating the indenter pushing energy.
Energy E ₁ required to push the indenter to press-fit depth hmax at the maximum press-fitting is obtained by integrating the load P from zero to hmax along the press-fitting curve.

  As the unloading curve acquisition step, each load when the indenter pushed into the insulating material thin film is unloaded from the maximum load to no load and the displacement amount of the insulating material thin film at each load are acquired. And the obtained load and displacement amount are plotted, and a load-displacement curve (unloading curve) is acquired. In FIG. 2, in the unloading curve, the displacement under no load is “hr”.

Subsequently, as the elastic recovery energy calculation step, elastic recovery energy is acquired based on each load when unloading from the maximum load to no load and the amount of displacement of the insulating material thin film at each load.
FIG. 4 is a diagram showing a calculation formula for calculating elastic recovery energy.
During indenter removal, energy E ₂ by elastic recovery is obtained by integrating the load P along the unloading curve from a depth hr of indentation produced on the film surface after the indenter unloading to hmax.

It is considered that the difference between these energies (energy E ₁ required to push the indenter-energy E ₂ due to elastic recovery) includes energy dissipated in the film due to plastic deformation and energy stored in the film due to residual stress. It is done. That is, it can be said that this energy difference represents a physical quantity related to the plastic deformation of the film, and if this quantity is used, the low dielectric constant insulating film has a different viewpoint from the conventionally evaluated elastic modulus and hardness. It is considered that the correlation between the mechanical characteristics and the defects caused when the low dielectric constant insulating film is adopted in the semiconductor device can be shown.

  Here, the press-fit energy calculation step is performed before the unloading curve acquisition step, but it goes without saying that the unloading curve acquisition step may be performed first or simultaneously. Similarly, it goes without saying that either the press-fit energy calculation step or the elastic recovery energy calculation step may be performed first or simultaneously.

Then, as the energy dissipation rate calculating step calculates the energy dissipation rate value α to the difference between the indentation energy E ₁ and the elastic recovery energy E ₂ divided by the indentation energy E _1.
FIG. 5 is a diagram showing a calculation formula for calculating the energy dissipation ratio value.
Here, since it is convenient to express it as a percentage, it is desirable to express it as an energy dissipation rate expressed as% (percent) by multiplying α by 100.

  And as a determination process, the mechanical characteristic of the said insulating material thin film is determined by energy dissipation ratio value (alpha) or an energy dissipation rate. As a threshold value for determination, it is desirable that the α value is 0.1 or less, that is, the energy dissipation rate is 10% or less. Therefore, if the energy dissipation rate is 10% or less, it is determined that the insulating material thin film has mechanical characteristics that can be used for a semiconductor device. When the energy dissipation rate is 10% or less, the metal can be prevented from exuding when used in a semiconductor device.

Hereinafter, an example in which the semiconductor devices using the insulating material thin films having the energy dissipation rates of 7% and 15% are compared will be described. Here, the film is formed by using a so-called dial damascene method in which a via and a wiring are simultaneously formed.
FIG. 6 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device.
In FIG. 6A, as an insulating film forming step, a SiC film 275 serving as a base film using silicon carbide (SiC) is formed on the lower wiring layer by a CVD method. Here, the film is formed by the CVD method, but other methods may be used. The SiC film 275 also has a function as an etching stopper. Since it is difficult to generate the SiC film, a silicon carbonate (SiOC) film may be used instead of the SiC film. Alternatively, a silicon carbonitride (SiCN) film or a silicon nitride (SiN) film can be used.
The lower layer wiring is formed on the substrate 200, and on the lower layer wiring interlayer insulating film on which the base SiC film 212, the p-lowk film 220, and the cap SiO ₂ film 222 are formed, the barrier metal film 240, the seed film 250, A Cu film 260 is formed. As the substrate 200, for example, a substrate such as a silicon wafer having a diameter of 300 mm is used. The substrate 200 may be formed with contact plugs or other layers.

Then, a p-lowk film 280 using a porous insulating material to be determined is formed on the SiC film 275. By forming the p-lowk film 280, an interlayer insulating film having a relative dielectric constant k lower than 3.9 can be obtained. Since it is necessary to realize a method for determining mechanical characteristics, particularly strength, for an insulating film having a relative dielectric constant k lower than 3.9, an insulating film having a relative dielectric constant k lower than 3.9 is used. It is desirable. In particular, the relative dielectric constant of the low dielectric constant insulating film is preferably in the range of 1.5 to 3.5. As a material of the p-lowk film 280 whose relative dielectric constant k can be lower than 3.9, a SiOF film by a CVD method, an organic silicon oxide film or an organic resin (polymer) film by a CVD method or a spin coating method is used. Is desirable. As the organic silicon oxide film, for example, a film obtained by introducing a methyl group into SiO ₂ may be used.

  Here, as the p-lowk film 280, a porous organic silicon oxide film having an energy discrete rate of 7%, an elastic modulus of 7 GPa, and a relative dielectric constant of 2.5 is adopted. As a comparative object, a film using a porous organic silicon oxide film having an energy discrete rate of 15%, an elastic modulus of 7 GPa, and a relative dielectric constant of 2.5 was also prepared.

After surface modification of the surface of the p-lowk film 280 by helium (He) plasma irradiation, an SiC film 284 serving as an etching stopper is formed on the p-lowk film 280 by a CVD method. Similarly, a p-lowk film 285 using a porous insulating material is formed on the SiC film 284, and an SiO ₂ film 290 serving as a cap film is formed thereon. By forming the SiO ₂ film 290, the p-lowk film 285 that cannot be directly subjected to lithography can be protected, and a pattern can be formed in the p-lowk film 285. Such cap CVD films include SiO ₂ films, SiC films, SiOC films, SiCN films, etc., but from the viewpoint of reducing damage, the SiO ₂ film is excellent, and from the viewpoint of reducing the dielectric constant, the SiOC film has improved breakdown voltage. From the viewpoint, the SiC film and the SiCN film are excellent. Furthermore, it is possible to use SiO ₂ film and the SiC film laminated film of, or SiO ₂ film and the SiCO film laminated film of, or a laminated film of SiO ₂ film and SiCN film. Further, a part or all of the cap CVD film may be removed by CMP in a planarization step described later.

In FIG. 6B, as an opening forming process, a groove opening H ₁ for upper layer wiring which is a wiring groove structure for producing a damascene wiring (here, dual damascene wiring) by a lithography process and a dry etching process; forming an opening H ₂ was opened and a via hole for connecting with upper layer wiring to the lower layer wiring. An exposed SiO ₂ film 290 and a p-lowk film located below the exposed SiO ₂ film 290 with respect to the substrate 200 on which the resist film is formed on the SiO ₂ film 290 through a lithography process such as a resist coating process and an exposure process (not shown). 285 may be formed by removing the underlying SiC film 284 as an etching stopper by an anisotropic etching method. Thereafter, via holes may be similarly formed by removing the p-lowk film 280 and the base SiC film 275.

FIG. 7 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device.
In FIG. 7 (a), a barrier metal film 242 using the SiO ₂ film 290 and on the barrier metal material in the openings _{H 1} and the opening _{H 2.} Tantalum nitride (TaN) is deposited in a sputtering apparatus using a sputtering method which is one of physical vapor deposition (PVD) methods, and a barrier metal film 242 is formed. Then, by PVD method such as sputtering, the openings H ₁ and the inner walls of the openings H ₂ where the barrier metal film 242 is formed using the Cu thin film that becomes the cathode electrode of the next electrolytic plating process as a seed film and the substrate surface Deposit (form). Then, a seed layer as a cathode electrode, a Cu film 262 is deposited in the opening H ₁ and the opening portion H ₂ and the substrate surface by electrochemical deposition such as electroless plating. After the deposition, annealing is performed.

In FIG. 7B, as a planarization step, the Cu film 262, the seed film, and the barrier metal film 242 deposited on the surface of the SiO ₂ film 290 by the CMP method are removed by polishing, and the process shown in FIG. A buried structure is formed.

FIG. 8 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device.
In FIG. 8, in order to prevent the diffusion of Cu, an upper layer wiring is formed, and an SiC film 292 is formed on the SiO ₂ film 290 on which Cu appears on the surface.

Two types of semiconductor devices having the same elastic modulus and different energy discrete rates manufactured as described above were compared.
As a result, first, in the structure employing the p-lowk film 280 having an energy discrete rate of 15%, the metal seeped out, whereas the p-lowk film 280 having an energy discrete rate of 7% was employed. No such oozing was seen in the structure. The reason for this is that Cu embedded in the via expands during the thermal process, but stress is applied to the p-lowk film 280, and the strength of the p-lowk film 280 cannot withstand the stress, resulting in cracks. It is probable that the metal exuded from the metal. It is considered that such a difference is caused by the energy discrete rate defined as described above, that is, the strength against plastic deformation, although the elastic moduli of both are substantially the same.

In this embodiment, the p-lowk film 280 which is a via formation layer is applied, but the p-lowk film 285 and the SiO ₂ film 290 which are wiring formation layers, or the SiC film 284 and the SiC film 275 which are via formation layers. The same effect can be obtained by applying this method, and it may be applied to both the via formation layer and the wiring formation layer. The same effect can be obtained by application to the p-lowk film 220, the SiC film 212, and the SiO ₂ film 222, which are lower wiring layers.

  In the method of the above-described embodiment, a porous organic insulating film is cited as an example of the interlayer insulating film to be formed. However, the film material or precursor thereof used in the present invention is not limited to the porous organic silicon oxide film, The film is not particularly limited as long as it is cured and insulated by heat or the like after coating.

  As described above, according to the present invention, a low dielectric constant having an energy dissipation rate of 10% or less defined by a weight-displacement curve and an unload-displacement curve in an indenter indentation test for a low dielectric constant insulating film used in a semiconductor device. By employing the insulating film, a highly reliable semiconductor device having a low dielectric constant insulating film layer excellent in mechanical strength can be provided.

  In the above description, as a material for the wiring layer in each of the above embodiments, in addition to Cu, a material mainly composed of Cu used in the semiconductor industry, such as a Cu—Sn alloy, a Cu—Ti alloy, and a Cu—Al alloy. The same effect can be obtained using.

  The embodiments have been described above with reference to specific examples. However, the present invention is not limited to these specific examples.

  For example, the film thickness of the interlayer insulating film and the size, shape, number, and the like of the opening can be appropriately selected and used as required in the semiconductor integrated circuit and various semiconductor elements.

  In addition, any semiconductor device manufacturing method that includes the elements of the present invention and whose design can be changed as appropriate by those skilled in the art is included in the scope of the present invention.

  In addition, for the sake of simplicity of explanation, techniques usually used in the semiconductor industry, such as a photolithography process, cleaning before and after processing, are omitted, but it goes without saying that these techniques are included.

FIG. 3 is a diagram showing a flow of a method for determining mechanical properties of an insulating material thin film in the first embodiment. It is a figure which shows an example of the press-fit and unloading curve obtained by the indenter press-fit test with respect to a low dielectric constant insulating film. It is a figure which shows the calculation formula for calculating indenter pushing energy. It is a figure which shows the calculation formula for calculating elastic recovery energy. It is a figure which shows the calculation formula for calculating an energy dissipation ratio value. It is sectional drawing which shows a part of manufacturing process of a semiconductor device. It is sectional drawing which shows a part of manufacturing process of a semiconductor device. It is sectional drawing which shows a part of manufacturing process of a semiconductor device. It is process sectional drawing which shows the manufacturing method of the semiconductor device which has the multilayer wiring structure which combined the conventional low-k film | membrane and Cu wiring.

Explanation of symbols

200 Substrate 212, 275, 284, 292 SiC film 220, 280, 285 p-lowk film 221, 281 Insulating film 222, 290 SiO ₂ film 240, 242 Barrier metal film 250 Seed film 260, 262 Cu film

Claims (4)

In a method for determining mechanical properties of an insulating material thin film used in a semiconductor device,
An indenter pushing energy acquisition step of pushing an indenter into the insulating material thin film, obtaining an indenter pushing energy based on a load from no load to a maximum load and a displacement amount of the insulating material thin film at each load;
Elastic recovery energy for acquiring elastic recovery energy based on each load when the indenter pushed into the insulating material thin film is unloaded from the maximum load to no load and the amount of displacement of the insulating material thin film at each load Acquisition process;
With
A method for determining mechanical properties of an insulating material thin film, comprising: determining mechanical properties of the insulating material thin film based on a value obtained by dividing a difference between the indenter pressing energy and the elastic recovery energy by the indenter pressing energy.   2. The mechanical property of an insulating material thin film according to claim 1, wherein if the value is 0.1 or less, it is determined that the insulating material thin film has mechanical properties that can be used in a semiconductor device. Judgment method.   2. The method of determining mechanical properties of an insulating material thin film according to claim 1, wherein the mechanical properties of the insulating material thin film having a relative dielectric constant smaller than 3.9 are determined. Mechanical property determination method.   2. The method of determining mechanical properties of an insulating material thin film, wherein mechanical properties are determined for an insulating material thin film made of either an organic silicon oxide film or an organic polymer film. A method for determining mechanical properties of the insulating material thin film as described.

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