JP2006040982A - Vertical charge-controlled semiconductor device with low output capacitance - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power MOSFET device having improved characteristics such as low output capacitance, high breakdown voltage, and improved heat performance. <P>SOLUTION: In one embodiment, MOSFET contains at least two trench regions filled up with an insulator which are formed in a first semiconductor region apart from each other in the lateral direction so as to form a drift region; and at least one resistive element arranged along the periphery of each trench region filled up with an insulator. The ratio of the width of trench regions filled up with an insulator to the width of the drift region is so adjusted as to minimize the output capacitance of the MOSFET. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  Power field effect transistors such as MOSFETs (metal oxide semiconductor field effect transistors) are well known in the semiconductor industry. One type of power MOSFET is a DMOS (Double Diffused Metal Oxide Semiconductor) transistor. A cross-sectional view of a portion of one known cell array of various DMOS transistors is shown in FIG. As shown, n-type epitaxial layer 102 covers n-type substrate 100 and a drain contact is made to n-type region 100. The trench filled with polysilicon extends from the top surface to the epitaxial layer 102. The trench polysilicon 106a, 106b is insulated from the epitaxial layer by oxide layers 104a, 104b. The source regions 108a and 108b of the p-type body regions 110a and 110b are adjacent to the trench and on the upper surface. Polysilicon gate 114 overlies source regions 108a, b, extends over the surface portions of body regions 110a, b, and extends over the surface area of the region between the two trenches, commonly referred to as the mesa drift region. Metal layer 116 electrically shorts source regions 108a, b to body regions 110a, b and trench polysilicon 106a, b. The surface area of the body regions 110a, b just below the gate 114 defines the channel region of the transistor. The area between the body regions 110a and 110b under the gate 114 is usually called a JFET region.

  When a positive voltage is applied to the gate and drain and the source and body regions are grounded, the channel region is inverted. Thus, current begins to flow from the drain to the source through the drift region and the surface channel region.

  The maximum forward blocking voltage, hereinafter referred to as “breakdown voltage”, is determined by the avalanche breakdown voltage of the reverse-biased body-drain junction. The DMOS structure of FIG. 1 has a high breakdown voltage due to a trench filled with polysilicon. Polysilicon 106a, b is pushed deeper into the drift region into the depletion layer formed as a result of the reverse-biased body-drain junction. By increasing the depletion region depth without increasing the electric field, the breakdown voltage is increased without having to resort to reducing the doping concentration of the drift region. Otherwise, the drift region increases the transistor on-resistance.

  A disadvantage of the structure of FIG. 1 is the high output capacity Coss, which makes it less suitable for applications such as power amplifier radio frequency (RF) devices in wireless communication base stations. The output capacitance Coss of the structure of FIG. 1 is mainly (i) the capacitance between oxides between the polysilicon of the trench and the drift region (ie, Cox), and (ii) in the body-drift region junction in series therewith. Made from capacitance between depletion regions. While Cox is a fixed capacitance, the depletion capacitance is inversely proportional to the body-drain bias.

  The breakdown voltage of a power MOSFET depends not only on the cell structure, but also on how the device terminates at the outer edge. In order for the overall device breakdown voltage to be high, the outer edge breakdown voltage must be at least as high as the cell breakdown voltage. Therefore, for any cell structure, a corresponding termination structure that exhibits a high breakdown voltage is required.

  In most amplifier circuits, a significant amount of thermal energy is generated in the transistor. For best class AB RF power amplifiers available, only 50% efficiency is typical. An important factor in designing power devices for high frequency applications is the thermal performance of the device. Due to the different device performance requirements, the power MOSFET cells are packed densely, resulting in heat concentration and low heat transfer rates in the active region.

  Accordingly, power MOSFET devices having improved characteristics such as low output capacitance, high breakdown voltage, and improved thermal performance are desired.

  In accordance with the present invention, a MOSFET cell structure and an edge termination structure and a method of manufacturing the same are described, and in particular, its features and advantages include substantially reduced output capacitance, high breakdown voltage, and improved heat. Show performance.

  In some embodiments, the MOSFET includes a trench region filled with at least two insulators spaced laterally in the first semiconductor region so as to form a drift region therebetween, and the two insulators are filled. At least one resistance element disposed along the outer periphery of each of the trench regions formed. The ratio of the width of each trench region filled with insulator to the width of the drift region is adjusted so that the output capacitance of the MOSFET is minimized.

  In another embodiment, the MOSFET includes a first semiconductor region having a first surface, a first trench region extending from the first surface to the first semiconductor region, and along a sidewall of the first trench region. And at least one floating discontinuous region.

  In another embodiment, the MOSFET includes a first semiconductor region having a first surface, a first trench region extending from the first surface to the first semiconductor region, and along a sidewall of the first trench region. And a first plurality of regions.

  In another embodiment, a MOSFET includes a first semiconductor region having a first surface, and a trench region filled with first and second insulators each extending from the first surface to the first semiconductor region. including. Each of the regions filled with the first and second insulators has an outer layer of silicon of a conductivity type opposite to that of the first semiconductor region. The trench regions filled with the first and second insulators are spaced apart to form a drift region therebetween in the first semiconductor region, and the respective volumes of the first and second trench regions are It becomes larger than a quarter of the volume of the drift region.

  In another embodiment, the MOSFET includes a first semiconductor region on the substrate. The first semiconductor region has a first surface. The MOSFET further includes a trench region filled with first and second insulators each extending from the first surface to a predetermined depth within the first semiconductor region. Each of the trench regions filled with the first and second insulators has an outer layer of doped silicon material, and the outer layer of doped silicon material extends along the bottom surface of the trench region filled with insulator. The insulating material along the bottom surface of the trench region that is discontinuous and filled with an insulator is in direct contact with the first semiconductor region. The outer layer of silicon material has a conductivity type opposite to that of the first semiconductor region.

  In another embodiment, a MOSFET includes a first semiconductor region having a first surface, a trench region filled with a first insulator extending from the first surface to the first semiconductor region, And a strip of semi-insulating material along the sidewalls of the trench region filled with the insulator. The strip of semi-insulating material is insulated from the first semiconductor region.

  According to the embodiment of the present invention, the MOSFET is formed as follows. The first epitaxial layer is formed on the substrate. The first doped region is formed in the first epitaxial layer. The first doped region has a conductivity type opposite to that of the first epitaxial layer. The second epitaxial layer is formed on the first doped region and the first epitaxial region. A first trench region extending from the surface of the second epitaxial layer through the first and second epitaxial layers and the first doped region is formed, and the first doped region is formed on a sidewall of the first trench region. Divided into two floating discontinuous regions along.

  According to another embodiment, the MOSFET is formed as follows. The first epitaxial layer is formed on the substrate. The first and second doped regions are formed in the first epitaxial layer. The first and second doped regions have a conductivity type opposite to that of the first epitaxial layer. The second epitaxial layer is formed on the first and second doped regions and the first epitaxial region. First and second trench regions are formed, the first trench region extending through the first and second epitaxial layers and the first doped region, wherein the first doped region is the first trench region. And the second trench region extends through the first and second epitaxial layers and the second doped region, and the second doped region is divided into the first and second epitaxial regions. Divided into two floating discontinuous regions along the sidewalls of the two trench regions.

  In another embodiment, the MOSFET is formed as follows. The first trench is formed in the first semiconductor region. The first doped region is formed along the lower portion of the first trench. The first trench extends deeper within the first semiconductor region, and for the first doped region, the two floating discontinuous regions remain along the sidewalls of the first trench.

  In another embodiment, the MOSFET is formed as follows. The first semiconductor region is formed on the substrate. The first semiconductor region has a first surface. A first trench is formed extending from the first surface to a predetermined depth in the first semiconductor region. A layer of doped silicon material is formed along the sidewalls of the trench. The layer of doped silicon material has a conductivity type opposite to that of the first semiconductor region.

  The following detailed description and the accompanying drawings provide a better understanding of the nature of the invention.

  A MOSFET according to the present invention comprises a trench region filled with at least two insulators spaced laterally from a first semiconductor region so as to form a drift region therebetween, and filled with the two insulators. At least one resistive element disposed along the outer periphery of each of the trench regions, and the ratio of the width of each of the trench regions filled with the insulator to the width of the drift region is the output capacitance of the MOSFET Is adjusted to be minimized, thereby achieving the above objective.

  A MOSFET according to the present invention includes a first semiconductor region having a first surface, a first trench region extending from the first surface to the first semiconductor region, and sidewalls of the first trench region. And at least one floating discontinuous region along, thereby achieving the above objective.

  A MOSFET according to the present invention includes a first semiconductor region having a first surface, a first trench region extending from the first surface to the first semiconductor region, and sidewalls of the first trench region. A first plurality of regions along, thereby achieving the above objective.

  The first plurality of regions are such that a depletion region formed in the first semiconductor region during the operation mode of the MOSFET extends to the first semiconductor region away from the first surface. , Spaced along the outer wall of the first trench region.

  A body region extending from the first surface to the first semiconductor region, the body region having a conductivity type opposite to a conductivity type of the first semiconductor region; and the body region A source region having the same conductivity type as the first semiconductor region, and a second trench region extending from the first surface to the first semiconductor region. A gate of the second trench region extending between a portion of the body region, wherein the gate has a channel region extending perpendicular to the first surface between the source and the first semiconductor region. And a gate overlying the source and the first semiconductor region so as to be formed in the body region therebetween.

  First and second body regions each extending from the first surface to the first semiconductor region, wherein the first body region forms a JFET region therebetween. First and second body regions spaced laterally from the region, the first and second body regions having a conductivity type opposite to that of the first semiconductor region; First and second source regions in the first and second body regions, respectively, wherein the first and second source regions have the same conductivity type as the first semiconductor region, And a second source region.

  A gate extending over the JFET region and a portion of the first and second body regions, but insulated from the JFET region and a portion of the first and second body regions, the gate comprising: The first and second sources such that a channel region is formed along the respective body surface of the first and second body regions between the corresponding source and the JFET region. A gate may be further included overlying the region.

  A gate extending over each of the first and second body regions but insulated from the first and second body regions, wherein the channel region is between the corresponding source and the JFET region And the gate is discontinuous across the surface of the JFET region between the first body region and the second body region. A certain gate may be further included.

  A first gate extending over the first body region but insulated from the first body region, the first gate having a first channel region and the first source; A first gate overlying each of the first source and JFET regions to be formed along a surface of the first body region between the JFET region and the second body region; A second gate that is isolated from the second body region, the second gate having a second channel region between the first source and the JFET region. A second gate overlying each of the first source and JFET regions may be further included so as to be formed along the surface of the first body region.

  A second semiconductor region of the same conductivity type as the first semiconductor region, the first semiconductor region being on and in contact with the second semiconductor region; May further include a second semiconductor region forming a drain contact region.

  The first trench region may be filled with an insulating material.

  The first semiconductor region may have a conductivity type opposite to that of the first plurality of regions.

  The first plurality of regions may be discontinuous floating regions.

  A second trench region extending from the first surface to the first semiconductor region, the second trench region laterally extending from the first trench region to form a drift region therebetween And the first and second trench regions are substantially filled with an insulating material, along a second trench region and an outer sidewall of the second trench region. It may further include a second plurality of regions.

  Each volume of the first and second trench regions may be greater than a quarter of the volume of the drift region.

  The combined width of the trench region and one of the first plurality of regions may be greater than a quarter of the distance between adjacent regions of the first and second plurality of regions.

  A MOSFET further including a termination structure, wherein the termination structure is a termination trench region extending from the first surface to the first semiconductor region, the termination trench being filled with a semi-insulating material; The semi-insulating material may include a termination trench region that is insulated from the first semiconductor region.

  The termination trench region includes a first trench region such that a substantially uniform electric field is obtained in a region between the termination trench region and the first trench region during an operation mode of the MOSFET. May be spaced along the lateral direction.

  The semi-insulating material is such that the electric field of the semiconductor region under the portion of the semi-insulating material extending over the first surface is substantially reduced during the mode of operation of the MOSFET. It may extend on the first surface in a direction away from the first trench region.

  The MOSFET further including a termination structure, the termination structure being a termination trench region filled with an insulator extending from the first surface to the first semiconductor region, wherein the termination trench region is , Laterally from the first trench region, such that a substantially uniform electric field is obtained in a region between the termination trench region and the first trench region during the MOSFET operating mode. It may include termination trench regions that are spaced along.

  A plurality of floating regions along the sidewall of the termination trench region may be further included.

  A MOSFET according to the present invention comprises a first semiconductor region having a first surface and a trench region filled with first and second insulators extending from the first surface to the first semiconductor region, respectively. And the trench regions filled with the first and second insulators each have first and second layers of silicon having a conductivity type opposite to that of the first semiconductor region. A trench region filled with an insulator, the trench region filled with the first and second insulators being spaced apart to form a drift region therebetween in the first semiconductor region; The volume of each of the first and second trench regions is greater than a quarter of the volume of the drift region, thereby achieving the above objective.

  The outer layer of silicon is such that a depletion region formed in the first semiconductor region during the operation mode of the MOSFET extends to the first semiconductor region away from the first surface. Lightly doped silicon may be used.

  A body region extending from the first surface to the first semiconductor region, the body region having a conductivity type opposite to a conductivity type of the first semiconductor region; and the body region A source region having the same conductivity type as the first semiconductor region, and a second trench region extending from the first surface to the first semiconductor region. A gate of the second trench region extending between a portion of the body region, wherein the gate has a channel region extending perpendicular to the first surface between the source and the first semiconductor region. And a gate overlying the source and the first semiconductor region so as to be formed in the body region therebetween.

  First and second body regions each extending from the first surface to the first semiconductor region, wherein the first body region forms a JFET region therebetween. First and second body regions spaced laterally from the region, the first and second body regions having a conductivity type opposite to that of the first semiconductor region; First and second source regions in the first and second body regions, respectively, wherein the first and second source regions have the same conductivity type as the first semiconductor region, And a second source region.

  A gate extending over the JFET region and a portion of the first and second body regions, but insulated from the JFET region and a portion of the first and second body regions, the gate comprising: The first and second sources such that a channel region is formed along the respective body surface of the first and second body regions between the corresponding source and the JFET region. A gate may be further included overlying the region.

  A gate extending over each of the first and second body regions but insulated from the first and second body regions, wherein the channel region is between the corresponding source and the JFET region And the gate is discontinuous across the surface of the JFET region between the first body region and the second body region. A certain gate may be further included.

  The MOSFET according to the present invention is a first semiconductor region on a substrate, the first semiconductor region having a first surface, and the first semiconductor region and the first surface, respectively, from the first surface A trench region filled with first and second insulators extending to a predetermined depth in the first semiconductor region, wherein each of the trench regions filled with the first and second insulators is provided with the insulating material. By having an outer layer of doped silicon material that becomes discontinuous along the bottom of the trench region filled with the body, the insulator material along the bottom of the trench region filled with the insulator A trench region filled with first and second insulators in direct contact with one semiconductor region, wherein the outer layer of silicon material is of a conductivity type opposite to that of the first semiconductor region; To achieve the above objectives That.

  The trench regions filled with the first and second insulators are spaced apart to form a drift region therebetween in the first semiconductor region, and are filled with the first and second insulators. The volume of each trench region may be greater than a quarter of the volume of the drift region.

  Each of the doped silicon outer layers of the trench region filled with the first and second insulators has a depletion region formed in the first semiconductor region during the operation mode of the MOSFET. It may be lightly doped silicon so as to extend further to the first semiconductor region away from the surface of one.

  A body region extending from the first surface to the first semiconductor region, the body region having a conductivity type opposite to a conductivity type of the first semiconductor region; and the body region A source region having the same conductivity type as the first semiconductor region, and a second trench region extending from the first surface to the first semiconductor region. A gate of the second trench region extending between a portion of the body region, wherein the gate has a channel region extending perpendicular to the first surface between the source and the first semiconductor region. And a gate overlying the source and the first semiconductor region so as to be formed in the body region therebetween.

  First and second body regions each extending from the first surface to the first semiconductor region, wherein the first body region forms a JFET region therebetween. First and second body regions spaced laterally from the region, the first and second body regions having a conductivity type opposite to that of the first semiconductor region; First and second source regions in the first and second body regions, respectively, wherein the first and second source regions have the same conductivity type as the first semiconductor region, And a second source region.

  A gate extending over the JFET region and a portion of the first and second body regions, but insulated from the JFET region and a portion of the first and second body regions, the gate comprising: The first and second sources such that a channel region is formed along the respective body surface of the first and second body regions between the corresponding source and the JFET region. A gate may be further included overlying the region.

  A gate extending over each of the first and second body regions but insulated from the first and second body regions, wherein the channel region is between the corresponding source and the JFET region And the gate is discontinuous across the surface of the JFET region between the first body region and the second body region. A certain gate may be further included.

  The MOSFET described above further comprising a termination structure, wherein the termination structure is a termination trench region extending from the first surface to the first semiconductor region, the termination trench being made of a semi-insulating material. The filled and semi-insulating material may include a termination trench region that is insulated from the first semiconductor region.

  The termination trench region is configured to provide a substantially uniform electric field in a region between the termination trench region and the first and second trench regions during the operation mode of the MOSFET. And may be spaced laterally from the second trench region.

  The semi-insulating material is such that the electric field in the first semiconductor region under the portion of the semi-insulating material extending on the first surface is substantially reduced during the MOSFET operating mode. On the first surface, it may extend in a direction away from the first and second trench regions.

  The MOSFET further including a termination structure, the termination structure being a termination trench region filled with an insulator extending from the first surface to the first semiconductor region, wherein the termination trench region is , Laterally spaced from the first and second trench regions, and substantially uniform in a region between the termination trench region and the first and second trench regions during an operation mode of the MOSFET. A simple electric field may be obtained.

  A MOSFET according to the present invention includes a first semiconductor region having a first surface, a first insulator-filled trench region extending from the first surface to the first semiconductor region, and the first insulator. A strip of semi-insulating material along the sidewall of the filled trench region, wherein the strip of semi-insulating material is insulated from the first semiconductor region.

  A MOSFET further including a second insulator-filled trench region extending from the first surface to a predetermined depth in the first semiconductor region, the second insulator-filled trench region extending along a sidewall thereof And having a strip of semi-insulating material, the strip of semi-insulating material being insulated from the first semiconductor region, wherein the first and second insulator-filled trench regions are in the first semiconductor region , Spaced to form a drift region therebetween, wherein each of the first and second insulator filled trench regions may have a volume greater than one quarter of the volume of the drift region.

  A body region extending from the first surface to the first semiconductor region and having a conductivity type opposite to the first semiconductor region; and being in the body region and having the same conductivity as the first semiconductor region A first source region, a second trench region extending from the first surface to the first semiconductor region, and a body region between the source and the first semiconductor region, A gate in a second trench region extending over a portion of the body region and overlying the source and the first semiconductor region so as to form a channel region extending perpendicularly to the surface of May further be included.

  First and second body regions respectively extending from the first surface to the first semiconductor region, the first body region being laterally spaced from the second body region. First and second body regions formed in a JFET region in between, wherein the conductivity type of the first and second body regions is opposite to the conductivity type of the first semiconductor region, and The semiconductor device may further include first and second source regions that are in the first and second body regions and have the same conductivity type as the first semiconductor region.

  Extending over the JFET region and a portion of the first and second body regions and insulated from the JFET region and the and second body regions, the first between the corresponding source and the JFET region And a gate overlying the first and second source regions, such that a channel region is formed along a body surface of each of the second body regions.

  Extending over each of the first and second body regions such that a channel region is formed along the respective surface of the first and second body regions between the corresponding source and the JFET region. A MOSFET further comprising a gate isolated from each of the first and second body regions, the gate being discontinuous across the surface of the JFET region between the first and second body regions. There may be.

  The strip of semi-insulating material may be formed from an oxygen doped polysilicon material.

  A MOSFET further comprising a source region, wherein the strip of semi-insulating material may be electrically connected to the source region.

  Each of the strips of semi-insulating material may be insulated from the surrounding area.

  Each of the strips of semiconductor material may be floating.

  A MOSFET further comprising a drain and a source, wherein each of the strips of semi-insulating material may be electrically connected between the drain and the source.

  A MOSFET further comprising a drain and a source, each of the strips of semi-insulating material being electrically connected between the drain and the source, and during operation of the MOSFET, of the semi-insulating material. Each of the strips may achieve a linear voltage gradient from one end of the strip to the opposite end of the strip.

  The first semiconductor region is on and in contact with a second semiconductor region having the same conductivity type as the first semiconductor region, and the second semiconductor region is in contact with the first semiconductor region. The strip of semi-insulating material may extend through the first semiconductor region and terminate at the second semiconductor region.

  The first semiconductor region is on and in contact with a second semiconductor region having the same conductivity type as the first semiconductor region, and the second semiconductor region is in contact with the first semiconductor region. The first insulator-filled trench may extend through the first semiconductor region and terminate at the second semiconductor region.

  The method according to the present invention is a method of forming a MOSFET, comprising: forming a first epitaxial layer on a substrate; and forming a first doped region in the first epitaxial layer, The first doped region has a conductivity type opposite to the conductivity type of the first epitaxial layer; and forming a second epitaxial layer over the first doped region and the first epitaxial region From the surface of the second epitaxial layer, so that the first doped region is divided into two floating discontinuous regions along the sidewalls of the first trench region, Forming said first and second epitaxial layers and a first trench region extending through said first doped region, thereby To achieve.

  The method may further include filling the first trench region with a dielectric material.

  Forming a body region in the second epitaxial layer, the body region having a conductivity type opposite to the second epitaxial layer, and forming a source region in the body region. The source region is of the same conductivity type as the epitaxial layer, and forming a second trench region extending at least to the second epitaxial layer, the second trench region comprising: A channel laterally spaced from the first trench region, and forming a gate in the second trench region, the channel extending perpendicular to the surface of the second epitaxial layer The gate is formed in the body region such that a region is formed in the body region between the source and the second epitaxial layer. Extends over part overlies the source region and the second epitaxial layer may further include the steps.

  The second trench may be shallower than the first trench.

  The method according to the present invention is a method of forming a MOSFET, comprising: forming a first epitaxial layer on a substrate; and forming first and second doped regions in the first epitaxial layer, The first and second doped regions have opposite conductivity types to the first epitaxial layer; and forming a second epitaxial layer on the first and second doped regions and the first epitaxial layer; Forming first and second trench regions, the first trench region extending through the first and second epitaxial layers and the first doped region, wherein the first doped region is the first Divided into two floating discontinuous regions along the sidewalls of the trench region, and the second trench region is the first and second epitaxial layers; Extending through the second doped region, the second doped region being divided into two floating discontinuous regions along the sidewalls of the second trench region, thereby achieving the above objective To do.

  Forming first and second body regions each extending from a surface to the second epitaxial layer, wherein the first body region is laterally spaced from the second body region with a JFET region therebetween Forming the first and second body regions having opposite conductivity types to the second epitaxial layer, forming first and second source regions in the first and second body regions, respectively; The first and second source regions may further include a step having the same conductivity type as the second epitaxial layer.

  Forming a gate extending over the JFET region and a portion of the first and second body regions, overlying the first and second source regions, and a channel region being the first and second A step may be further included that is formed between the corresponding source region and the JFET region along each body surface of the body region.

  Forming a gate extending above and insulated from each of the first and second body regions, and having a channel region between the corresponding source region and the JFET region along the respective surfaces of the first and second body regions; The method may further include a step formed between and wherein the gate is discontinuous on the surface of the JFET region between the first and second body regions.

  Forming a first gate extending above and insulated from the first body region, overlying the first source region and the JFET region, and a first channel region extending along a surface of the first body region; Forming a step formed between the first source region and the JFET region, and a second gate extending above the step while being insulated from the second body region, and the second source region and the JFET region And a second channel region is formed between the first source region and the JFET region along the surface of the first body region.

  The first doped region is spaced laterally from the second doped region by a first distance, and each of the first and second trench regions may have a width greater than ¼ of the first distance. Good.

  The method according to the present invention is a method of forming a MOSFET, comprising: forming a first trench in a first semiconductor region; forming a first doped region along a bottom of the first trench; Extending a first trench deeper in the first semiconductor region, leaving two floating discontinuous regions of the first doped region along the sidewalls of the first trench, thereby Achieve the goal.

  A method according to the present invention is a method of forming a MOSFET, the method comprising: forming a first semiconductor region on a substrate, the first semiconductor region having a first surface; and from the first surface Forming a first trench extending into the first semiconductor region by a predetermined depth, and forming a layer of doped silicon material along the sidewalls of the trench, the doped silicon material layer comprising: And having a conductivity type opposite to that of the first semiconductor region, thereby achieving the above object.

  The method may further include filling the trench with an insulating material, wherein the insulating material along a bottom surface of the insulating filled trench region directly contacts the first semiconductor region.

  Forming a second trench extending into the first semiconductor region by a predetermined depth from the first surface, and forming a layer of doped silicon material along the sidewall of the second trench, The doped silicon material layer has a conductivity type opposite to that of the first semiconductor region, and the first trench and the second trench are spaced apart in the first semiconductor region and form a drift region therebetween. And a step in which each volume of the first and second trenches is greater than ¼ of the drift volume.

  Since the doped silicon layer of each of the first and second trenches is lightly doped, a depletion region formed in the first semiconductor region during the operation mode of the MOSFET leaves the first surface and the first silicon layer is lightly doped. It may further extend into one semiconductor region.

  Forming first and second body regions each extending from the first surface to the first semiconductor region, the first body region being laterally spaced from the second body region and between them A JFET region is formed, the first and second body regions have a conductivity type opposite to the first semiconductor region, and a first and second source regions in the first and second body regions, respectively And forming the first and second source regions having the same conductivity type as the first semiconductor region.

  A gate region is formed which extends from the JFET region and the first and second body regions while being insulated from the first and second body regions, and a channel region overlaps the first and second source regions. A step may be further included that is formed between the corresponding source region and the JFET region along each body surface of the body region.

  Forming a gate extending above and insulated from each of the first and second body regions, and having a channel region between the corresponding source region and the JFET region along the respective surfaces of the first and second body regions; The method may further include a step formed between and wherein the gate is discontinuous on the surface of the JFET region between the first and second body regions.

  Forming a body region extending from the first surface to the first semiconductor region, the body region having a conductivity type opposite to the first semiconductor region, and forming a source region in the body region The source region has the same conductivity type as the first semiconductor region, forming a second trench extending from the first surface to the first semiconductor region, and the second trench Forming a gate extending in a region over a portion of the body region, and overlying the source region and the first semiconductor region, a channel region extending perpendicular to the first surface is formed between the source region and the first semiconductor region And a step formed in the body region between.

  MOSFET cell structures, edge termination structures, and methods of manufacturing them are described in accordance with the present invention. In other features and advantages, the cell and termination structures, and methods of manufacturing them, exhibit substantially reduced output capacity, high breakdown voltage, and improved temperature performance.

  FIG. 2 shows a cross-sectional view of a power MOSFET cell array according to an embodiment of the present invention. As shown, both the gate terminal 205 and the source terminal 207 are disposed along the top surface of the device, and the drain terminal 203 is disposed along the bottom surface. The drain terminal 203 is connected to the lightly doped epitaxial region 202 through a highly doped region 200 that functions as a drain contact. The oxide-filled trench regions 204 a and 204 b extend from the upper surface by a predetermined depth of the epitaxial region 202. Discontinuous floating p-type regions 206a, 206b are spaced along the outer sidewalls of trench regions 204a, b. P-type body regions 208a, 208b extend from the top surface into an epitaxial region adjacent to trench regions 204a, b. As shown, body regions 208a, b include highly doped p + regions 210a, b, but these p + regions may be removed if desired. Source regions 212a, b are formed in body regions 208a, b as shown.

  Polysilicon gate 216 covers source regions 212a, b and extends with the surface area of body regions 208a, b and the surface area of epitaxial region 202 between body regions 208a and 208b. Gate 216 is insulated from the underlying region by gate oxide 214. The surface area of the body regions 208a, b immediately below the gate 216 forms a channel region. Metal layer 218 covers the top surface of the structure and forms a common source-body contact.

  The area of the epitaxial region between trenches 204a and 204b is hereinafter referred to as drift region 209. When the gate, drain, and source terminals are appropriately biased to turn on the device, the drain contact region 200, drift region 209, channel region, source diffusion region 212a, b, and finally through the metal layer 218. Thus, a current flows between the drain terminal 203 and the source terminal 207.

  Comparing FIG. 1 and FIG. 2, polysilicon 106a, b (FIG. 1) in the trench replaces the insulating material and removes what contributes significantly to the output capacitance (ie, Cox) of the structure of FIG. It is understood that By replacing the polysilicon with an insulator such as silicon dioxide, it appears that a larger portion of the spacing charge region is through the insulator rather than silicon. Since the dielectric constant of the insulator is lower than the dielectric constant of silicon (less than about one third for silicon dioxide), the area of the spaced charge region along its boundary is (particularly when the applied voltage is low) The output capacity is greatly reduced (at least a third).

  As noted above, the trench polysilicon in the prior art FIG. 1 structure helps to improve the cell breakdown voltage by pushing the depletion region deeper into the drift region. By removing the polysilicon, the breakdown voltage is reduced if no other means of reducing the electric field is used. The floating p regions 206a, 206b serve to reduce the electric field. In FIG. 2, the electric field rises as the drain voltage increases, so that the floating p regions 206a, b get a corresponding potential determined by their position in the spacing charge region. Due to the floating potential of these p regions, the electric field diffuses deeper into the drift region, producing a more uniform electric field throughout the depth of the drift region, resulting in a higher breakdown voltage. Accordingly, a breakdown voltage characteristic similar to that of the structure of FIG. 1 is achieved, but the output capacitance is lower.

  The floating p regions 206a, b have the opposite effect of reducing the width of the drift region 209, and as a result, current flows through those drift regions 209 when the device is on, resulting in on resistance. (On-resistance) rises. However, the adverse effect of the floating p region on on-resistance causes an optimal balance between the charge density of the drift region and such characteristics of the floating p region (eg, size, doping density, spacing Lp between them). Can be reduced by obtaining. For example, a higher charge density drift region requires a smaller spacing Lp. The reverse is also true. Furthermore, because the floating p region reduces the electric field near the surface in the channel, its channel length can be reduced to improve the on-resistance and general performance of the device as a high frequency amplifier.

In one embodiment where a breakdown voltage of 80-100V is desired, the epitaxial region 202 has a doping density in the region of 5 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ and the floating p regions 206a, b Has a doping density of 5 to 10 times the doping density of the epitaxial region. 3 (1a) to 3 (1e) are cross-sectional views illustrating an exemplary set of process steps for forming the structure of FIG. In FIG. 3 (1 a), a first n epitaxial layer 302 is deposited on the highly doped substrate 300 using conventional methods. The p regions 306 and 308 are formed by implanting p-type impurities (eg, boron) through the mask 304. The size of the opening in mask 304 depends on the desired width of the trench and the desired width of the floating p region, which are affected by the device performance target. In one embodiment, the target width of the trench is in the range of 1-5 μm, and the width of the p-regions 306, 308 is at least 1 μm wider than the width of the trench, and between the adjacent p-regions 306 and 308 The lateral spacing between is at least 1 μm, and the n epitaxial layer 302 has a doping density of about 2 × 10 ¹⁶ cm ⁻³ and a thickness in the range of 2-5 μm.

  In FIG. 3 (1 b), steps similar to those in FIG. 3 (1 a) are performed to form a second n epitaxial layer 316 and p regions 310, 312. These steps can be repeated depending on the desired number of floating p regions. Alternatively, the step of FIG. 3 (1b) may be removed to form only one floating p region along the sidewall of each trench.

  In FIG. 3 (1c), a final epitaxial layer 320 is deposited that receives the device body and source regions. Although the deposition techniques used in forming the epitaxial regions 302, 316 and 320 are the same, the doping density of each epitaxial region can be varied depending on the desired characteristics of the drift region. Similarly, the p regions 306, 308 may be implanted to have a different doping density than the p regions 310, 312 if desired.

  In FIG. 3 (1 d), the mask 330 and conventional silicon trench etching techniques are used to etch through the center of the three epitaxial layers 302, 316, 320 and p regions 306, 308, 310, 312, Trenches 322a, 322b and corresponding floating p regions 306a, b, 308a, b, 310a, b and 312a, b are formed. The width of the opening in mask 330 determines the width of the oxide trench relative to the width of the floating p region.

  After preparing the trench surface, a relatively thin insulator (e.g., about 300-500 thermal oxide) is grown on the trench surface. The trenches 322a, b are then filled with a dielectric material such as silicon dioxide using conventional conformal coating methods and / or spin-on-glass (SOG) methods. A low-k dielectric may be used to fill the trenches 322a, b to reduce the output capacitance. The conventional process steps used to form a self-aligned gate DMOS structure are then performed to form the gate structure shown in FIG. 3e.

  Another method of manufacturing the structure of FIG. 2 will now be described using the simplified cross-sectional views of FIGS. 3 (2a) -3 (2c). In FIG. 3 (2a), an initial n epitaxial layer 342 is deposited on the highly doped substrate 340, after which a trench 344a is formed in the n epitaxial layer 342, and then an implant step forms a p region 346 at the bottom of the trench 344a. Followed by a diffusion step that further diffuses the p-dopant into the epitaxial region 342. In FIG. 3 (2b), the trench 344a passes through the p region 346 and is further etched into the epitaxial region 342 to form a deeper trench 344b, and an implant and diffusion step similar to the step of FIG. Performed to form p region 348 at the bottom of trench 344b. In FIG. 3 (2c), the trench 344b is etched through the p region 348 into the epitaxial region 342 to form a deeper trench 344c, after which the trench 344c is filled with a suitable insulator. Thus, insulator filled trench 344c, floating p regions 346a, b and 348a, b are formed. The remaining process steps are similar to those described in conjunction with FIG. 3 (1e).

  With further reference to FIG. 2, the vertical charge control enabled by the floating p region allows the cells to be laterally spaced without affecting the electrical characteristics of the device. Further, by spacing the cells, the heat generated by each cell diffuses over a wider area and less thermal interaction occurs between adjacent cells. Thus, lower device temperatures are achieved.

In order to achieve efficient vertical charge control, the spacing Lp (FIG. 2) between adjacent floating p-regions 206a and 206b needs to be carefully designed. In one embodiment, the distance Lp is determined according to the following definition (the product of the doping density of the drift region and the distance Lp is in the range of 2 × 10 ¹² to 4 × 10 ¹² cm ⁻² ). Thus, for example, for a drift region doping density of 5 × 10 ¹⁵ cm ⁻³ , the spacing Lp needs to be about 4 μm. Once the optimal spacing Lp is determined, the spacing Lc between the central axes of adjacent trenches 204a, b can be increased independently without affecting the electrical characteristics of the device.

  Two ways to increase the Lc interval and keep the Lp interval constant are shown in FIGS. In FIG. 4, discontinuous floating p regions 406a, b along the source and body regions are extended through a larger portion of the region between adjacent trenches to achieve a wider Lc spacing. . In one embodiment, the combined width of one trench (eg, 404b) and one of the first plurality of floating regions (eg, 406b) is greater than a quarter of the spacing Lp. This embodiment of FIG. 4 is particularly effective in a technique where a trench having a width of Wt is strictly limited to the maximum size. If the trench width is not tightly limited, as shown in FIG. 5, the trench width can be increased to obtain a wider Lc spacing, but the spacing Lp remains constant.

  The advantage of the structure of FIG. 5 over that of FIG. 4 is that the output capacitance is lower. The reason is that the floating p region is smaller and a larger part of the depletion region occurs in a wider insulator filled trench. Thus, by designing the cell structure to increase the ratio of the trench insulator volume to the drift region volume, the reduction in output capacitance due to the larger size trench can be facilitated. Also, wider trenches result in improved temperature performance. In one embodiment, the volume of the trench insulator is at least one quarter of the volume of the drift region. Thus, the larger the trench volume, the lower the output capacitance and the better the temperature performance of the device. However, there is little increase when the trench is made wider than the die thickness (eg, 100 μm).

  Although FIGS. 2-5 show a plurality of floating p regions along the sidewalls of the trench, the present invention is not so limited. Depending on device performance requirements and design goals, only one floating p-region can be formed along each sidewall of the trench.

  FIG. 6 shows a cross-sectional view of a power MOSFET cell array according to another embodiment of the present invention. The structure of FIG. 6 is similar to the structure of FIG. However, the floating p regions 206a, b (FIG. 2) are removed, except that p layers (p liners) 606a, b are introduced along the outer peripheries of the trenches 604a and 604b. Similar to the floating p regions 206a, b, it helps to extend the depletion region deeper into the drift region, thus improving the breakdown voltage. Since the P liners 606a, b are in electrical contact with the body regions 608a, b, they are biased to the same potential as the body regions 608a, b.

  In FIG. 7, similar to FIG. 5, the width Wt of the oxide trench is increased to achieve improved temperature performance, while the Lp spacing is maintained at the same optimal value. The disadvantage of the structure of FIG. 7 is that due to the p-liner 706a, b, the spacing charge region follows the entire contour of the trench, so that the p-liner 706a, b results in a higher output capacitance. It is. One approach to reducing the contribution of the p-liner to the output capacitance is to remove a portion of the p-liner that extends through the bottom of the trench, as shown in FIG. In this manner, the output capacitance is reduced and the same breakdown voltage is maintained. This is because the p strips 806a, b (FIG. 8) extend the depletion region deeper into the drift region.

  An exemplary set of process steps that form the structure of FIG. 8 is shown in FIGS. In FIG. 9a, a hard mask 906 by conventional silicon trench etching is used to etch the epitaxial region 902 to form wide trenches 904a, 904b. Using the same mask, p-liner 908 is formed by implanting p-type impurities into the sidewalls and bottom of the trench at an angle of about 45 degrees using conventional methods. In FIG. 9b, a conventional silicon etch process is performed to remove a portion of the p-liner along the bottom of the trench, leaving p-strips 908a, b along the trench sidewalls. In FIG. 9c, temperature grown oxide layers 910a, b are formed along the inner sidewalls and bottom of each trench. The p-type dopant in strips 908a, b is then activated using conventional methods. A conventional oxide volume step (eg, SOG method) is performed to fill the trench with oxide and then planarize the oxide surface. Conventional process steps used in forming the gate structure of the self-aligned gate DMOS structure are then performed to form the complete structure shown in FIG. 9c. 7 and 8, there is a temperature grown oxide liner similar to the temperature grown oxide liner of FIG. 9c, but is omitted for simplicity. The temperature grown oxide layer is included to provide a cleaner interface between the trench insulator and the p strip.

  From the above, the structure of FIG. 8 is easier to manufacture than the structure of FIG. 5 because additional steps are required in forming the floating p region in the structure of FIG. .

The p-liner / strip doping density of FIGS. 6-8 affects the output capacitance of each of these structures. Since a higher reverse bias potential is required to fully deplete the p region, the higher the output capacitance is due to the higher doping of the p region. Therefore, a low doping density (eg, about 1 × 10 ¹⁷ cm ⁻³ ) is desirable for these p regions. Note that these p regions do not significantly affect the output capacitance at high operating voltages.

  FIGS. 10a-10c show cross-sectional views of three power MOSFET cell arrays, each including a strip of semi-insulating material (eg, oxygen-doped polysilicon SiPOS) along the trench sidewalls. In all three drawings, similar to the previous embodiment, wide insulation filled trenches 1004a, b are used to improve thermal performance. Also, the semi-insulating strips in these structures function in the same manner as the prior art polysilicons 106a, b in FIG. 1 in that they push the depletion region into the deeper drift region, thereby improving breakdown voltage. Let

  In FIG. 10a, strips 1006a, b of semi-insulating material extend along the trench sidewalls and are insulated from epitaxial region 1002 and body regions 1008a, b by a layer of insulating material 1010a, b. The strips 1006a, b are in electrical contact with the upper metal layer 1018 and are thereby biased to the same potential as the source and body regions.

  In FIG. 10b, the strip 1020a, b of semi-insulating material is similar to the strip of FIG. 10a, except that the strip 1020a, b is insulated from the upper metal layer 1018 and is thereby floating. Embedded in the cell array. During operation, the potential in the spacing charge region is connected to the semi-insulating stop via the insulating layers 1010a, b to bias the strip to a corresponding substantially uniform potential.

  In FIG. 10 c, the insulation filled trenches 1024 a, b extend widely through the epitaxial region 1002 and terminate in the substrate 1000. The semi-insulating strips 1022a, b extend along the sidewalls of the trench and are in electrical contact with the source terminal via the upper metal layer 1018 and the drain terminal via the substrate region 1000. This strip thus forms a resistive connection between the drain and source terminals. During operation, the strip acquires a linear voltage gradient from the highest potential at its bottom (ie, drain potential) to the lowest potential at its top (ie, source potential). Strips 1022a, b are insulated from epitaxial region 1002 by insulating layers 1026a, b. The gate structure in FIGS. 10a and 10b as well as in FIG. 10c is similar to the previous embodiment.

The semi-insulating strip in the structure of FIGS. 10a-10c serves as an additional tool that can optimize the electrical properties of the device. Depending on the application and design objectives, certain structures may be preferred over others. In each of the structures of FIGS. 10a, 10b, and 10c, the resistivity of the strip of semi-insulating material can be adjusted to allow shaping of the spacing charge region formation depending on the applied drain-source voltage _VDS. Thus, the potential can be varied from the top to the bottom.

  An exemplary set of process steps for forming the structure in FIG. 10a is as follows. Using a hard mask, the silicon is etched back to form a wide trench, as in the previous embodiment with a wide trench. A thermally grown oxide layer having a thickness in the range of 200-1000 mm is then formed along the inner wall and bottom of the trench. Then about 4000 コ ン of conformal oxide is deposited on the thermally grown oxide layer. Oxygen doped polysilicon (SiPOS) is then deposited in the trench region and etched to form strips 1008a, b along the sidewalls. The trench is then filled with an insulator using conventional methods (eg, SOG method), followed by planarization of the oxide surface. The conventional steps used to form the self-aligned gate DMOS structure are then performed to form a full cell structure as shown in FIG. 10a.

  The depth of the trenches of the various embodiments described above can be varied depending on the desired device performance and the intended use of the device. For example, for a high breakdown voltage (eg, higher than 70V), the trench may extend deeper (eg, to a depth of about 5 μm) into the epitaxial region. As another example, the trench may extend widely through the epitaxial region to reach the substrate region (as in FIG. 10c). For lower voltage applications, the p region (eg, the floating p region of FIG. 2 and the p strip of FIG. 8) need not extend deep into the epitaxial region. This is because the device is not required to meet a high breakdown voltage and also to minimize its contribution to the p-region-output capacitance.

  Although the trench structures of the various embodiments described above are shown in combination with the gate structure of a conventional DMOS cell, the present invention is not limited thereto. Two examples of other gate structures that can be combined with these trench structures are shown in FIGS. These two cell structures have the advantage of low gate-drain capacitance, and when combined with the low output capacitance of the trench structure yields a power device that is particularly suitable for high frequency applications.

  The structure of FIG. 11 is similar to FIG. 8 except that a substantial portion of the gate extending on the surface of the drift region has been deleted. Thus, the gate-drain capacitance is reduced by an amount corresponding to the removed portion of the gate. In the structure of FIG. 12, the trench structure of FIG. 8 is combined with the gate structure of a conventional UMOS cell. Thus, the advantages of UMOS cells (eg, low on-resistance) are obtained while retaining the low output capacity and improved thermal performance of the trench structure according to the present invention. In certain embodiments where the structure of FIG. 12 is intended for lower voltage applications (eg, in the range of 30-40V), the depth of p-strips 1208a, b is relatively shallow (eg, 1.5 μm to 3 μm). range).

  It will be apparent to those skilled in the art, upon reviewing this disclosure, that the gate structure of FIGS. 11 and 12 or any other gate structure may be combined with the various trench structures described above.

  In the above embodiment, the vertical charge control enabled by the resistive elements disposed along the insulation-filled trenches allows the cells to be spaced apart laterally without affecting the electrical characteristics of the device. It becomes possible. Furthermore, the distant cells dissipate the heat generated by each cell over a large area, making it difficult for heat to interact between adjacent cells. Thereby, the temperature of the device is lower.

  Although the above embodiments have shown the drain to be placed along the lower side of the die, the present invention is not so limited. Each of the above cell structures is modified to be a pseudo vertical conductive structure by including a highly doped n-type buried layer extending along the interface between the epitaxial region and the underlying highly doped substrate region. Can be done. In a convenient location, the buried layer extends vertically to the top surface that can be contacted to form the drain terminal of the device. In these embodiments, the substrate region may be n-type or p-type depending on the application of the MOSFET.

  As described above, an edge termination structure with a breakdown voltage equal to or higher than the breakdown voltage of individual cells is required to obtain a high device breakdown voltage. In the case of the structure of FIG. 8, the simulation results terminate at the outer edge of a device having a trench structure similar to the trench 804b, resulting in a higher electric field due to field transitions to the top surface outside the outer trench. It shows that. An edge termination structure that obtains the same or higher breakdown voltage as the cell structure of FIG. 8 is shown in FIG.

  In FIG. 13, the active gate on the drift region between the outer two trenches 1306b and 1306c is removed, and the drift region spacing Lt between these two outer trenches is the drift region spacing Lc in the cell structure. Can be reduced to less than. However, the active gate may remain if obtaining an interval of Lt is not required for its removal. The outer p-strip 1308d is not biased (ie, floated) and may be removed if desired. A conventional field plate structure 1310 is optionally included in FIG. The termination structure of FIG. 13 results in (a) a depletion region terminated in the outer trench 1306c, thereby reducing the electric field outside the trench 1306c, and (b) the electric field inside the outer trench 1306c is reduced to the depletion region. Is reduced due to the short Lt interval that pushes into the drift region.

  In another embodiment, a gate structure is included between trenches 1306b and 1306c with spacing Lt and spacing Lc equal. In this embodiment, the p-strip immediately to the right of the gate structure between trench 1306b and trench 1306c (ie, the p-strip corresponding to the strip along the left side of trench 1306c) is not connected to the source, and thus Floating.

  Other modifications of the embodiment of FIG. 13 are possible. For example, a floating guard ring can be used outside the trench 1306c with or without the field plate structure 1310. Although the cell trenches 1306a, b and the termination trench 1306c are shown to be narrower than the cell trench of FIG. 8, the trenches 1306a, b, c may extend as shown in FIG. Further, the width Wt of the termination trench 1306c may be designed to be different from the cells of the trenches 1306a, b if desired.

  14 is a cross-sectional view showing another termination structure combined with the cell structure shown in FIG. As shown, the termination structure includes a termination trench 1408 covering the inside of the insulating layer 1410 along its sidewalls and bottom. A field plate 1406 (eg, from doped polysilicon) is provided on the insulating layer 1410 in the trench 1408 and extends laterally on its surface away from the active region.

  Although the termination structure described above is shown in combination with the cell structure of FIG. 8, these and other known termination structures may be combined with any of the cell structures described above.

  While the above is a complete description of embodiments of the invention, various alternatives, modifications, and equivalents may be used. For example, the various embodiments described above are n-channel power MOSFETs. Equivalent p-channel MOSFET designs will be apparent to those skilled in the art in view of the above teachings. In addition, p + regions similar to the p + regions 210a and 210b of the structure of FIG. 2 are added to the body regions of other structures described herein to reduce body resistance and prevent source penetration. Also good. Also, the cross-sectional views are intended to show various regions in different structures and do not necessarily limit the layout of the cell array or other structural aspects. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention.

(wrap up)
According to an embodiment of the present invention, a MOSFET comprises a trench region filled with at least two insulators spaced laterally in a first semiconductor region to form a drift region therebetween, And at least one resistive element disposed along the outer periphery of each of the trench regions filled with the insulator. The ratio of the width of each trench region filled with insulator to the width of the drift region is adjusted so that the output capacitance of the MOSFET is minimized.

FIG. 1 shows a cross-sectional view of a known n-channel DMOS transistor cell array. FIG. 2 illustrates a cross-sectional view of a cell array having a floating p region according to one embodiment of the present invention. FIG. 3 (1a) is a cross-sectional view illustrating an exemplary set of processing steps to form the structure of FIG. FIG. 3 (1b) is a cross-sectional view illustrating an exemplary set of processing steps to form the structure of FIG. FIG. 3 (1c) is a cross-sectional view illustrating an exemplary set of processing steps to form the structure of FIG. FIG. 3 (1d) is a cross-sectional view illustrating an exemplary set of processing steps to form the structure of FIG. FIG. 3 (1e) is a cross-sectional view illustrating an exemplary set of processing steps to form the structure of FIG. FIG. 3 (2a) is a cross-sectional view illustrating another exemplary process step for forming the structure of FIG. FIG. 3 (2b) is a cross-sectional view illustrating another exemplary process step for forming the structure of FIG. FIG. 3 (2c) is a cross-sectional view illustrating another exemplary process step for forming the structure of FIG. FIG. 4 shows a cross-sectional view of a cell array having an elongated floating p-region according to another embodiment of the present invention. FIG. 5 illustrates a cross-sectional view of a cell array having a wide insulator filled trench according to yet another embodiment of the present invention. FIG. 6 shows a cross-sectional view of a cell array having an insulator filled trench with a thin p layer along the periphery, according to another embodiment of the present invention. FIG. 7 shows a cross-sectional view of a cell array having a wide trench. FIG. 8 illustrates a cross-sectional view of a cell array having p strips along the sidewalls of the trench, according to another embodiment of the present invention. FIG. 9a is a cross-sectional view illustrating an exemplary set of process steps to form the structure of FIG. FIG. 9b is a cross-sectional view illustrating an exemplary set of process steps to form the structure of FIG. FIG. 9c is a cross-sectional view illustrating an exemplary set of process steps to form the structure of FIG. FIG. 10a shows a cross-sectional view of a cell array with a strip of semi-insulating material along the sidewalls of the trench according to a third embodiment of the present invention. FIG. 10b shows a cross-sectional view of a cell array with a strip of semi-insulating material along the trench sidewalls according to a third embodiment of the present invention. FIG. 10c shows a cross-sectional view of a cell array having a strip of semi-insulating material along the sidewalls of the trench according to a third embodiment of the present invention. FIG. 11 shows a cross-sectional view of the cell array. In this cross-sectional view, the trench structure shown in FIG. 8 is coupled to a gate structure different from the trench structure shown in FIG. FIG. 12 shows a cross-sectional view of the cell array. In this cross-sectional view, the trench structure shown in FIG. 8 is combined with yet another gate structure. FIG. 13 illustrates a cross-sectional view of an edge termination structure according to one embodiment of the present invention. FIG. 14 shows a cross-sectional view of another edge termination structure according to another embodiment of the present invention.

Explanation of symbols

200 Highly doped region 202 Epitaxial region 203 Drain terminal 204a, b Trench region 205 Gate terminal 206a, b Floating p region 207 Source terminal 208a, b Body region 209 Drift region 210 p + region 212a, b Source region 214 Gate oxide 216 Gate 218 Metal layer

Claims (71)

MOSFET,
A trench region filled with at least two insulators spaced laterally of the first semiconductor region to form a drift region therebetween;
And at least one resistive element disposed along the outer periphery of each of the two insulator filled trench regions;
The ratio of the width of each trench region filled with the insulator to the width of the drift region is adjusted so that the output capacitance of the MOSFET is minimized. MOSFET,
A first semiconductor region having a first surface;
A first trench region extending from the first surface to the first semiconductor region;
And at least one floating discontinuous region along the sidewall of the first trench region. MOSFET,
A first semiconductor region having a first surface;
A first trench region extending from the first surface to the first semiconductor region;
A first plurality of regions along a sidewall of the first trench region. The first plurality of regions are such that a depletion region formed in the first semiconductor region during the operation mode of the MOSFET extends to the first semiconductor region away from the first surface. The MOSFET of claim 3, wherein the MOSFET is spaced along an outer wall of the first trench region. A body region extending from the first surface to the first semiconductor region, the body region having a conductivity type opposite to a conductivity type of the first semiconductor region;
A source region of the body region, the source region having the same conductivity type as the first semiconductor region;
A second trench region extending from the first surface to the first semiconductor region;
A gate of the second trench region extending between a portion of the body region, the gate having a channel region extending perpendicular to the first surface between the source and the first semiconductor region; The MOSFET of claim 3, further comprising: a gate overlying the source and the first semiconductor region so as to be formed in the body region. First and second body regions each extending from the first surface to the first semiconductor region, wherein the first body region forms a JFET region therebetween. First and second body regions spaced laterally from the region, the first and second body regions having a conductivity type opposite to that of the first semiconductor region;
First and second source regions in the first and second body regions, respectively, wherein the first and second source regions have the same conductivity type as the first semiconductor region, The MOSFET according to claim 3, further comprising: a second source region. A gate extending over the JFET region and a portion of the first and second body regions, but insulated from the JFET region and a portion of the first and second body regions, the gate comprising: The first and second sources such that a channel region is formed along the respective body surface of the first and second body regions between the corresponding source and the JFET region. The MOSFET of claim 6 further comprising a gate overlying the region. A gate extending over each of the first and second body regions but insulated from the first and second body regions, wherein the channel region is between the corresponding source and the JFET region And the gate is discontinuous across the surface of the JFET region between the first body region and the second body region. The MOSFET of claim 6 further comprising a gate. A first gate extending over the first body region but insulated from the first body region, the first gate having a first channel region and the first source; A first gate overlying each of the first source and JFET regions, so as to be formed along the surface of the first body region between the JFET regions;
A second gate extending over the second body region but insulated from the second body region, wherein the second gate has a second channel region and the first source; And a second gate overlying each of the first source and JFET regions so as to be formed along a surface of the first body region between the JFET regions. MOSFET. A second semiconductor region of the same conductivity type as the first semiconductor region, the first semiconductor region being on and in contact with the second semiconductor region; The MOSFET of claim 6 further comprising a second semiconductor region forming a drain contact region. The MOSFET of claim 3, wherein the first trench region is filled with an insulating material. 4. The MOSFET according to claim 3, wherein the first semiconductor region has a conductivity type opposite to a conductivity type of the first plurality of regions. The MOSFET of claim 3, wherein the first plurality of regions are discontinuous floating regions. A second trench region extending from the first surface to the first semiconductor region, the second trench region laterally extending from the first trench region to form a drift region therebetween A second trench region spaced apart along and wherein the first and second trench regions are substantially filled with an insulating material;
The MOSFET according to claim 3, further comprising: a second plurality of regions along a side wall outside the second trench region. The MOSFET of claim 14, wherein the volume of each of the first and second trench regions is greater than a quarter of the volume of the drift region. The combined width of the trench region and one of the first plurality of regions is greater than a quarter of the distance between adjacent regions of the first and second regions. The MOSFET described. The MOSFET of claim 3, further comprising a termination structure, wherein the termination structure comprises:
A termination trench region extending from the first surface to the first semiconductor region, wherein the termination trench is filled with a semi-insulating material, and the semi-insulating material is insulated from the first semiconductor region. A MOSFET including a termination trench region. The termination trench region includes a first trench region such that a substantially uniform electric field is obtained in a region between the termination trench region and the first trench region during an operation mode of the MOSFET. The MOSFET of claim 17, wherein the MOSFET is spaced laterally from the side. The semi-insulating material is such that the electric field of the semiconductor region under the portion of the semi-insulating material extending over the first surface is substantially reduced during the mode of operation of the MOSFET. The MOSFET of claim 17 extending over the first surface in a direction away from the first trench region. The MOSFET of claim 3, further comprising a termination structure, wherein the termination structure comprises:
A termination trench region filled with an insulator extending from the first surface to the first semiconductor region, wherein the termination trench region and the termination trench region and the first trench region during an operation mode of the MOSFET; A MOSFET comprising a termination trench region spaced laterally from the first trench region so that a substantially uniform electric field is obtained in a region between the first trench region and the first trench region. The MOSFET of claim 20 further comprising a plurality of floating regions along a sidewall of the termination trench region. A first semiconductor region having a first surface;
Trench regions filled with first and second insulators respectively extending from the first surface to the first semiconductor region, the trench regions filled with the first and second insulators, A trench region filled with first and second insulators each having an outer layer of silicon of a conductivity type opposite to the conductivity type of the first semiconductor region;
Trench regions filled with the first and second insulators are spaced apart to form a drift region therebetween in the first semiconductor region, and each of the first and second trench regions MOSFET whose volume is greater than one quarter of the volume of the drift region. The outer layer of silicon is such that a depletion region formed in the first semiconductor region during the operation mode of the MOSFET extends to the first semiconductor region away from the first surface. 23. The MOSFET of claim 22 that is lightly doped silicon. A body region extending from the first surface to the first semiconductor region, the body region having a conductivity type opposite to a conductivity type of the first semiconductor region;
A source region of the body region, the source region having the same conductivity type as the first semiconductor region;
A second trench region extending from the first surface to the first semiconductor region;
A gate of the second trench region extending between a portion of the body region, the gate having a channel region extending perpendicular to the first surface between the source and the first semiconductor region; 23. The MOSFET of claim 22 further comprising: a gate overlying the source and the first semiconductor region as formed in the body region of the gate. First and second body regions each extending from the first surface to the first semiconductor region, wherein the first body region forms a JFET region therebetween. First and second body regions spaced laterally from the region, the first and second body regions having a conductivity type opposite to that of the first semiconductor region;
First and second source regions in the first and second body regions, respectively, wherein the first and second source regions have the same conductivity type as the first semiconductor region, The MOSFET of claim 22 further comprising: a second source region. A gate extending over the JFET region and a portion of the first and second body regions, but insulated from the JFET region and a portion of the first and second body regions, the gate comprising: The first and second sources such that a channel region is formed along the respective body surface of the first and second body regions between the corresponding source and the JFET region. 26. The MOSFET of claim 25 further comprising a gate overlying the region. A gate extending over each of the first and second body regions but insulated from the first and second body regions, wherein the channel region is between the corresponding source and the JFET region And the gate is discontinuous across the surface of the JFET region between the first body region and the second body region. 26. The MOSFET of claim 25 further comprising a gate. A first semiconductor region on a substrate, the first semiconductor region having a first surface; and
Trench regions filled with first and second insulators each extending from the first surface to a predetermined depth within the first semiconductor region, the trench regions being filled with the first and second insulators Each trench region has an outer layer of doped silicon material that is discontinuous along the bottom surface of the trench region filled with the insulator, thereby providing a bottom surface of the trench region filled with the insulator. The insulator material is in direct contact with the first semiconductor region and the outer layer of the silicon material is of a conductivity type opposite to that of the first semiconductor region. And a trench region filled with a body. The trench regions filled with the first and second insulators are spaced apart to form a drift region therebetween in the first semiconductor region, and are filled with the first and second insulators. 29. The MOSFET of claim 28, wherein the volume of each trench region is greater than one quarter of the volume of the drift region. Each of the doped silicon outer layers of the trench region filled with the first and second insulators has a depletion region formed in the first semiconductor region during the operation mode of the MOSFET. 29. The MOSFET of claim 28, wherein the MOSFET is lightly doped silicon so as to extend further to the first semiconductor region away from the surface of the first. A body region extending from the first surface to the first semiconductor region, the body region having a conductivity type opposite to a conductivity type of the first semiconductor region;
A source region of the body region, the source region having the same conductivity type as the first semiconductor region;
A second trench region extending from the first surface to the first semiconductor region;
A gate of the second trench region extending between a portion of the body region, the gate having a channel region extending perpendicular to the first surface between the source and the first semiconductor region; 30. The MOSFET of claim 28, further comprising: a gate overlying the source and the first semiconductor region so as to be formed in the body region. First and second body regions each extending from the first surface to the first semiconductor region, wherein the first body region forms a JFET region therebetween. First and second body regions spaced laterally from the region, the first and second body regions having a conductivity type opposite to that of the first semiconductor region;
First and second source regions in the first and second body regions, respectively, wherein the first and second source regions have the same conductivity type as the first semiconductor region, The MOSFET of claim 28, further comprising: a second source region. A gate extending over the JFET region and a portion of the first and second body regions, but insulated from the JFET region and a portion of the first and second body regions, the gate comprising: The first and second sources such that a channel region is formed along the respective body surface of the first and second body regions between the corresponding source and the JFET region. The MOSFET of claim 32 further comprising a gate overlying the region. A gate extending over each of the first and second body regions but insulated from the first and second body regions, wherein the channel region is between the corresponding source and the JFET region And the gate is discontinuous across the surface of the JFET region between the first body region and the second body region. The MOSFET of claim 32 further comprising a gate. 30. The MOSFET of claim 28 further comprising a termination structure, the termination structure comprising:
A termination trench region extending from the first surface to the first semiconductor region, wherein the termination trench is filled with a semi-insulating material, and the semi-insulating material is insulated from the first semiconductor region. A MOSFET including a termination trench region. The termination trench region is configured to provide a substantially uniform electric field in a region between the termination trench region and the first and second trench regions during the operation mode of the MOSFET. 36. The MOSFET of claim 35, wherein the MOSFET is spaced laterally from the second trench region.   The semi-insulating material is such that the electric field in the first semiconductor region under the portion of the semi-insulating material extending on the first surface is substantially reduced during the mode of operation of the MOSFET. 36. The MOSFET of claim 35 extending on a first surface in a direction away from the first and second trench regions. The MOSFET of claim 28 further comprising a termination structure,
The termination structure is a termination trench region that is filled with an insulator that extends from the first surface to the first semiconductor region, the termination trench region extending laterally from the first and second trench regions. A MOSFET that is spaced in a direction and provides a substantially uniform electric field in a region between the termination trench region and the first and second trench regions during the mode of operation of the MOSFET. A first semiconductor region having a first surface;
A first insulator-filled trench region extending from the first surface to the first semiconductor region;
A strip of semi-insulating material along a sidewall of the first insulator-filled trench region, wherein the strip of semi-insulating material is insulated from the first semiconductor region. A MOSFET further comprising a second insulator-filled trench region extending from the first surface to a predetermined depth in the first semiconductor region,
The second insulator-filled trench region has a strip of semi-insulating material along its sidewalls, the strip of semi-insulating material being insulated from the first semiconductor region;
The first and second insulator-filled trench regions are spaced apart in the first semiconductor region to form a drift region therebetween, each of the first and second insulator-filled trench regions. 40. The MOSFET of claim 39, wherein the volume of is greater than one quarter of the volume of the drift region. A body region extending from the first surface to the first semiconductor region and having a conductivity type opposite to the first semiconductor region;
A source region in the body region and having the same conductivity type as the first semiconductor region;
A second trench region extending from the first surface to the first semiconductor region;
Extending over a portion of the body region such that a channel region extending perpendicularly to the first surface is formed in a body region between the source and the first semiconductor region, the source and 40. The MOSFET of claim 39, further comprising: a gate in a second trench region overlying the first semiconductor region. First and second body regions respectively extending from the first surface to the first semiconductor region, the first body region being laterally spaced from the second body region. First and second body regions formed in a JFET region in between, wherein the conductivity type of the first and second body regions is opposite to the conductivity type of the first semiconductor region;
40. The MOSFET of claim 39, further comprising: first and second source regions, each in the first and second body regions and having the same conductivity type as the first semiconductor region.   Extending over the JFET region and a portion of the first and second body regions and insulated from the JFET region and the and second body regions, the first between the corresponding source and the JFET region 43. The MOSFET of claim 42, further comprising a gate overlying the first and second source regions such that a channel region is formed along a body surface of each of the second body region and the second body region.   Extending over each of the first and second body regions such that a channel region is formed along the respective surface of the first and second body regions between the corresponding source and the JFET region. A MOSFET further comprising a gate isolated from each of the first and second body regions, the gate being discontinuous across the surface of the JFET region between the first and second body regions. 43. The MOSFET of claim 42, wherein:   40. The MOSFET of claim 39, wherein the strip of semi-insulating material is formed from an oxygen doped polysilicon material.   40. The MOSFET of claim 39, further comprising a source region, wherein the strip of semi-insulating material is electrically connected to the source region.   40. The MOSFET of claim 39, wherein each of the strips of semi-insulating material is insulated from surrounding regions.   40. The MOSFET of claim 39, wherein each of the strips of semiconductor material is floating.   40. The MOSFET of claim 39 further comprising a drain and a source, wherein each of the strips of semi-insulating material is electrically connected between the drain and the source.   A MOSFET further comprising a drain and a source, each of the strips of semi-insulating material being electrically connected between the drain and the source, and during operation of the MOSFET, of the semi-insulating material. 40. The MOSFET of claim 39, wherein each of the strips achieves a linear voltage gradient from one end of the strip to the opposite end of the strip. The first semiconductor region is on and in contact with a second semiconductor region having the same conductivity type as the first semiconductor region, and the second semiconductor region is in contact with the first semiconductor region. Having a higher doping concentration,
40. The MOSFET of claim 39, wherein the strip of semi-insulating material extends through the first semiconductor region and terminates at the second semiconductor region. The first semiconductor region is on and in contact with a second semiconductor region having the same conductivity type as the first semiconductor region, and the second semiconductor region is in contact with the first semiconductor region. Having a higher doping concentration,
40. The MOSFET of claim 39, wherein the first insulator filled trench extends through the first semiconductor region and terminates in the second semiconductor region. A method of forming a MOSFET comprising:
Forming a first epitaxial layer on a substrate;
Forming a first doped region in the first epitaxial layer, wherein the first doped region has a conductivity type opposite to that of the first epitaxial layer;
Forming a second epitaxial layer over the first doped region and the first epitaxial region;
From the surface of the second epitaxial layer, the first doped region is divided into two floating discontinuous regions along the sidewalls of the first trench region. Forming a second epitaxial layer and a first trench region extending through the first doped region.   54. The method of claim 53, further comprising filling the first trench region with a dielectric material. Forming a body region in the second epitaxial layer, the body region having a conductivity type opposite to the second epitaxial layer;
Forming a source region in the body region, the source region having the same conductivity type as the epitaxial layer; and
Forming a second trench region extending at least into the second epitaxial layer, wherein the second trench region is laterally spaced from the first trench region;
Forming a gate in the second trench region, wherein a channel region extending perpendicular to the surface of the second epitaxial layer is located in the body region between the source and the second epitaxial layer; The gate of claim 53, further comprising: the gate extending over a portion of the body region and overlying the source region and the second epitaxial layer. Method.   56. The method of claim 55, wherein the second trench is shallower than the first trench. A method of forming a MOSFET comprising:
Forming a first epitaxial layer on a substrate;
Forming first and second doped regions in the first epitaxial layer, wherein the first and second doped regions have opposite conductivity types to the first epitaxial layer;
Forming a second epitaxial layer on the first and second doped regions and the first epitaxial layer;
Forming first and second trench regions, the first trench region extending through the first and second epitaxial layers and the first doped region, wherein the first doped region is the first trench; And is divided into two floating discontinuous regions along the sidewalls of the region, and the second trench region extends through the first and second epitaxial layers and the second doped region, and the second doped region is the second doped region. Splitting into two floating discontinuous regions along the sidewalls of the two trench regions. Forming first and second body regions each extending from a surface to the second epitaxial layer, wherein the first body region is laterally spaced from the second body region with a JFET region therebetween Formed, and wherein the first and second body regions have a conductivity type opposite to the second epitaxial layer;
Forming first and second source regions in the first and second body regions, respectively, wherein the first and second source regions have the same conductivity type as the second epitaxial layer; 58. The method of claim 57. Forming a gate extending over the JFET region and a portion of the first and second body regions, overlying the first and second source regions, and a channel region being the first and second 59. The method of claim 58, further comprising: forming between a corresponding source region and a JFET region along each body surface of the body region. Forming a gate extending above and insulated from each of the first and second body regions, and having a channel region between the corresponding source region and the JFET region along the respective surfaces of the first and second body regions; 59. The method of claim 58, further comprising: formed between and wherein the gate is discontinuous on the surface of the JFET region between the first and second body regions. Forming a first gate extending above and insulated from the first body region, overlying the first source region and the JFET region, and a first channel region extending along a surface of the first body region; A step formed between the first source region and the JFET region;
Forming a second gate extending above and insulated from the second body region, overlying the second source region and the JFET region, and a second channel region extending along the surface of the first body region; 59. The method of claim 58, further comprising: forming between the first source region and the JFET region. The first doped region is spaced laterally from the second doped region by a first distance, and each width of the first and second trench regions is greater than ¼ of the first distance. 58. The method according to Item 57. A method of forming a MOSFET comprising:
Forming a first trench in the first semiconductor region;
Forming a first doped region along the bottom of the first trench;
Extending the first trench to a deeper depth in the first semiconductor region, and leaving two floating discontinuous regions of the first doped region along the sidewalls of the first trench. A method of forming a MOSFET comprising:
Forming a first semiconductor region on a substrate, the first semiconductor region having a first surface;
Forming a first trench extending into the first semiconductor region by a predetermined depth from the first surface;
Forming a layer of doped silicon material along the sidewalls of the trench, the doped silicon material layer having a conductivity type opposite to the first semiconductor region. 65. The method of claim 64, further comprising filling the trench with an insulating material, wherein the insulating material along a bottom surface of the insulating filled trench region is in direct contact with the first semiconductor region. . Forming a second trench extending into the first semiconductor region by a predetermined depth from the first surface;
Forming a layer of doped silicon material along the sidewalls of the second trench, the doped silicon material layer having a conductivity type opposite to the first semiconductor region; Two trenches are spaced apart in the first semiconductor region to form a drift region therebetween, each volume of the first and second trenches being greater than ¼ of the drift volume, and 68. The method of claim 64, further comprising. Since the doped silicon layer of each of the first and second trenches is lightly doped, a depletion region formed in the first semiconductor region during the operation mode of the MOSFET leaves the first surface and the first 68. The method of claim 66, further extending into one semiconductor region. Forming first and second body regions each extending from the first surface to the first semiconductor region, the first body region being laterally spaced from the second body region and between them A JFET region is formed, and the first and second body regions have a conductivity type opposite to the first semiconductor region;
Forming first and second source regions in the first and second body regions, respectively, wherein the first and second source regions have the same conductivity type as the first semiconductor region; 68. The method of claim 66. A gate region is formed which extends from the JFET region and the first and second body regions while being insulated from the first and second body regions, and a channel region overlaps the first and second source regions. 69. The method of claim 68, further comprising: forming between a corresponding source region and a JFET region along each body surface of the body region. Forming a gate extending above and insulated from each of the first and second body regions, and having a channel region between the corresponding source region and the JFET region along the respective surfaces of the first and second body regions; 69. The method of claim 68, further comprising: formed between and wherein the gate is discontinuous on the surface of the JFET region between the first and second body regions. Forming a body region extending from the first surface to the first semiconductor region, the body region having a conductivity type opposite to the first semiconductor region;
Forming a source region in the body region, the source region having the same conductivity type as the first semiconductor region;
Forming a second trench extending from the first surface to the first semiconductor region;
Forming a gate extending over a portion of the body region in the second trench region, and overlying the source region and the first semiconductor region, a channel region extending perpendicular to the first surface and the source region and the 65. The method of claim 64, further comprising: forming in the body region between the first semiconductor region.

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