JP2006040940A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which has good electrical characteristic and improves a yield. <P>SOLUTION: The method of manufacturing the semiconductor device includes a first step of depositing a first insulating film 15 on a semiconductor substrate 10 having an electron supply layer 13 and a cap layer 14, a second step of forming a resist film 16 on the semiconductor substrate 10, a third step of forming an opening 16a in the resist film 16, a fourth step of forming an opening 15a by etching the first insulating film 15 through the opening 16a, a fifth step of releasing the resist film 16, a sixth step of forming an opening 14a by etching the electron supply layer 13 and selectively the cap layer 14 through the opening 15a of the first insulating film 15, a seventh step of depositing a thick second insulating film 17 without blocking the opening 14a of the cap layer 14, an eighth step of exposing the electron supply layer 13 by etch-back processing the second insulating film 17, a ninth step of etching the electron supply layer 13 to a predetermined depth with the second insulating film 17 as a mask, and a tenth step of forming a gate metal 20 on the electron supply layer 13. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device that improves the characteristics of a semiconductor device using a compound semiconductor.

  A semiconductor device using a compound semiconductor such as GaAs, for example, a field effect transistor (hereinafter referred to as an FET) is excellent in high frequency characteristics and widely used as a semiconductor device operating in a microwave band.

  Here, a conventional method for manufacturing a semiconductor device will be described with reference to FIG.

  As shown in FIG. 2A, the semiconductor substrate 30 has a channel layer 32, an electron supply layer 33, and a cap layer 34 formed in order on a GaAs substrate 31. The channel layer 32, the electron supply layer 33, and the cap layer 34 are formed of high purity GaAs, n-AlGaAs, and n-GaAs semiconductor layers, respectively. A first resist film 35 is formed on the cap layer 34. The first resist film 35 is patterned and an opening 35a is formed in a part thereof.

  Next, as shown in FIG. 2B, a part of the cap layer 34 is removed by selective dry etching using the opening 35a of the first resist film 35 to form a so-called 1st recess.

  Next, the first resist film 35 is removed, and as shown in FIG. 2C, a second resist film 36 is formed on the cap layer 34 provided with the opening 34a, and is further patterned to form an opening in a part thereof. 36a is formed.

  Next, as shown in FIG. 2D, the electron supply layer 33 is etched to a certain depth using the opening 36 a to form a recess 33 a in a part of the electron supply layer 33.

  Next, as shown in FIG. 2E, a gate metal 37 is deposited on the entire surface.

  Next, as shown in FIG. 2F, the gate electrode G is formed by lift-off.

  Next, as shown in FIG. 2G, a top passivation 38, for example, a SiN film is formed on the entire surface by plasma CVD.

A method for manufacturing a semiconductor device as described above is disclosed in Patent Document 1, Patent Document 2, and the like.
Japanese Patent Laid-Open No. 11-176839 JP 2001-185558 A

  In the conventional method for manufacturing a semiconductor device, the cap layer 34 is etched using the pattern of the first resist film 35 as a mask to form an opening 34 a (1st recess) in a part of the cap layer 34. In this case, the first resist film 35 is made of an organic material containing, for example, carbon (C), hydrogen (H), oxygen (O), etc., and the cap layer 34 is etched by, for example, SiCl4 / SF6 gas or BCl3. / SF6 gas or the like is used.

  In the conventional method described above, when the size of the opening 34a is 0.3 μm or less, an etching redeposit is formed on the side wall region facing the opening 34a of the cap layer 34 and the bottom surface region of the opening 34a when performing selective dry etching. May generate. For this reason, side etching of the side wall region does not proceed, or etching residue is generated in the bottom surface region of the opening 34a, and the reproducibility of the opening 34a is lowered. As a result, the yield decreases, for example, a good breakdown voltage characteristic cannot be obtained.

  Although the reason why the etching redeposit is generated is not clear, for example, oxygen (O) contained in the first resist film 35 reacts with Si contained in the etching gas to generate an oxygen-based compound such as SiO2. It is presumed that. At this time, it is considered that a carbon-based compound is also generated as an etching redeposit.

  In the conventional method, the patterned first resist film 35 is used as a mask for forming the opening 34a of the cap layer 34. On the other hand, the gate metal pattern is formed separately from the first resist film 35, and the patterned second resist film 36 is used as a mask. For this reason, misalignment may occur between the pattern of the first resist film 35 and the pattern of the second resist film 36. As a result, for example, variations in the source and gate resistance occur, and uniform electrical characteristics cannot be obtained, resulting in a decrease in yield.

  An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-described drawbacks, has good characteristics, and improves yield.

  The method for manufacturing a semiconductor device according to the present invention includes a first step of depositing a mask layer that does not contain at least one of oxygen and carbon on a semiconductor substrate provided with first and second semiconductor layers each having a junction. A second step of forming a resist film on the semiconductor substrate on which the mask layer is deposited; a third step of forming an opening at a predetermined position of the resist film; and etching the mask layer through the opening to form the mask layer A fourth step of forming an opening in the substrate, a fifth step of removing the resist film, and a sixth step of selectively etching the first semiconductor layer with the second semiconductor layer through the opening of the mask layer. It is characterized by becoming.

  According to the present invention, the mask layer not containing at least one of oxygen and carbon is patterned, and the first semiconductor layer is selectively etched from the second semiconductor layer using the mask layer as a mask. In this case, since the mask layer does not contain at least one of oxygen and carbon, deposition of an etching redeposit, for example, an oxygen-based compound or a carbon-based compound when the first semiconductor layer is etched is reduced. Therefore, a method for manufacturing a semiconductor device with improved reproducibility of etching, good characteristics, and improved yield is realized.

  The embodiment of the present invention will be described with reference to the process cross-sectional view of FIG. 1 in which the vicinity of the gate is extracted by taking an FET using a compound semiconductor as an example.

  As shown in FIG. 1A, a semiconductor substrate 10 has a plurality of semiconductor layers such as a channel layer 12, an electron supply layer 13, a cap layer 14 and the like formed in this order on a semi-insulating GaAs substrate 11, for example. . The channel layer 12, the electron supply layer 13, and the cap layer 14 are formed of, for example, high-purity GaAs, n-AlGaAs, and n-GaAs, respectively, and the electron supply layer 13 and the cap layer 14 are in a heterojunction. Then, a mask layer made of a material not containing at least one of oxygen and carbon, for example, a first insulating film 15 made of a material not containing oxygen, for example, a SiN film (hereinafter referred to as P-SiN) formed by a plasma CVD method on the cap layer 14. A film) is formed. Further, a first resist film 16 is formed on the first insulating film 15 and further patterned, and an opening 16a is formed in a part thereof.

  Although not shown, for example, a drain electrode is provided on the cap layer 14 on the right side of the opening 16a, and a source electrode is provided on the cap layer 14 on the left side of the opening 16a.

  Next, using the opening 16a of the resist film 16, as shown in FIG. 1B, the first insulating film 15 is etched to form the opening 15a. Thereafter, the resist film 16 is removed.

  Next, as shown in FIG. 1C, the cap layer 14 is selectively dry-etched with the electron supply layer 13 using the opening 15a of the first insulating film 15 to form the opening 14a, a so-called 1st recess. To do. At this time, the opening 14a of the cap layer 14 is wider in the horizontal direction in the drawing than the opening 15a of the first insulating film 15, and side etching is performed until a desired 1st recess width is obtained. In addition, the electron supply layer 13 is exposed on the bottom surface of the opening 14a by this dry etching.

  Next, as shown in FIG. 1D, a second insulating film 17 such as a P-SiN film is formed on the entire surface. At this time, the second insulating film 17 is formed on the upper surface of the first insulating film 15 and the side wall facing the opening 15 a, the lower surface of the first insulating film 15 facing the opening 14 a, and the opening 14 a of the cap layer 14. It is formed on the facing side wall and on the electron supply layer 13 exposed at the bottom of the opening 14a.

  The second insulating film 17 is formed to a thickness that does not block the opening 15 a of the first insulating film 15, and the opening 17 a of the second insulating film 17 is formed inside the opening 15 a of the first insulating film 15. The second insulating film 17 is formed on the side wall facing the opening 14a of the cap layer 14 and forms a so-called side wall.

  Next, as shown in FIG. 1E, a part of the second insulating film 17 is removed by etch back, and a part of the electron supply layer 13 located at the bottom part of the opening 14a is exposed. At this time, the region where the electron supply layer 13 is exposed is located, for example, below the opening 17a of the second insulating film 17 described in the step of FIG. 1D, and its size and shape correspond to the opening 17a. .

  Next, as shown in FIG. 1F, the second insulating film 17 is used as a mask and a phosphoric acid-based etchant is used to etch the electron supply layer 13 exposed in the opening 14a portion to a certain depth. 13a is formed, thereby adjusting the current value, for example.

  Next, as shown in FIG. 1G, a second resist film 18 and a third resist film 19 are sequentially formed on the first insulating film 15, and each of them is patterned to form openings 18a and 19a.

  The opening 18a of the second resist film 18 extends, for example, to the outside of the opening 15a of the first insulating film 15 in the left-right direction of the drawing. The opening 19a of the third resist film 19 is formed narrower than the opening 18a of the second resist film 18 and wider than the opening 15a of the first insulating film 15 in the horizontal direction of the drawing.

  Next, as shown in FIG. 1H, a gate metal 20, for example, Au / Pt / Ti, is deposited using the third resist film 19 as a mask. At this time, the gate metal 20 includes the upper surface of the third resist film 19 and the upper region of the concave groove 13a including the inside of the concave groove 13a, for example, a partial region of the opening 14a portion of the cap layer 14, the second insulating film 17. A region that fills the opening 17a, a partial region of the opening 18a of the second resist film 18, for example, a region below the opening 19a.

  Next, as shown in FIG. 1I, the second resist film 18 and the third resist film 19 are removed by a lift-off method to form a gate electrode G having a T-shaped cross section.

  Next, as shown in FIG. 1 (j), a top passivation 21 such as a P-SiN film is formed on the entire surface.

  In the above embodiment, the second semiconductor layer, for example, the electron supply layer 33 is etched to a predetermined depth, and the gate electrode is formed in the concave groove 33a. In this case, the current can be adjusted by the shape of the concave groove 33a, for example, the depth thereof. In addition, it is possible to reduce the influence of damage to the second semiconductor layer surface that occurs when the first semiconductor layer, for example, the cap layer is etched.

  According to the method described above, the cap layer is etched using an insulating film not containing oxygen, for example, a P-SiN film as a mask. For this reason, when the cap layer is etched, even if SiCl4 / SF6 gas or the like is used, an oxygen-based compound such as SiO2 is not generated. Therefore, etching redeposition on the side wall of the cap layer is reduced, and side etching can be performed reliably. Therefore, the opening of the insulating film can be reduced, and the adoption of the self-alignment technique is facilitated.

  In addition, since the etching residue is small, the reproducibility when the cap layer is etched is improved, and even when the gate length is as small as 0.3 μm or less, the electrical characteristics are uniformed and the yield is improved.

  Further, the cap layer is side-etched to the 1st recess width with reference to the opening provided in one insulating film, and a gate metal is formed. Therefore, there is no misalignment between the first recess end and the gate metal, and variations in gate-source resistance can be suppressed. In addition, a decrease in breakdown voltage can be prevented and yield is improved.

  Further, the side wall of the cap layer is covered with an insulating film, and gate metal is deposited. For this reason, the contact between the gate metal and the side wall portion of the cap layer is eliminated, and deterioration of the breakdown voltage can be prevented.

  In the above embodiment, the first insulating film 15 made of a material not containing oxygen, for example, a P-SiN film, is used as a mask layer formed on the cap layer 14. However, a mask layer made of a material that does not contain carbon, such as a metal mask, may be used instead of the P-SiN film. In this case, when the cap layer 14 is etched, the deposition of the carbon-based compound can be prevented, and the same effect as that obtained when the P-SiN film is used can be obtained.

  Further, if the mask layer is formed of a material that does not contain both oxygen and carbon, deposition of oxygen-based compounds and carbon-based compounds can be prevented, and etching with good reproducibility can be performed.

  When manufacturing a FET or the like, if a metal mask is used, the metal mask has conductivity, which may hinder subsequent processes. In such a case, for example, if the metal mask is removed after etching the cap layer, or if an insulating film or the like is provided after removing the metal mask, the above problem can be solved.

It is process drawing for demonstrating embodiment of this invention. It is process drawing for demonstrating a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 11 ... GaAs substrate 12 ... Channel layer 13 ... Electron supply layer 14 ... Cap layer 15 ... 1st insulating film 16 ... 1st resist film 17 ... 2nd insulating film 18 ... 2nd resist film 19 ... 3rd resist Film 20 ... Gate metal 21 ... Top passivation G ... Gate

Claims (3)

  A first step of depositing a mask layer that does not contain at least one of oxygen and carbon on a semiconductor substrate provided with first and second semiconductor layers having a heterojunction, and the semiconductor substrate on which the mask layer is deposited A second step of forming a resist film thereon; a third step of forming an opening at a predetermined position of the resist film; a fourth step of etching the mask layer through the opening to form an opening in the mask layer; 5. A semiconductor device manufacturing method comprising: a fifth step of removing the resist film; and a sixth step of selectively etching the first semiconductor layer with the second semiconductor layer through the opening of the mask layer. Method.   A first step of depositing a first insulating film on the semiconductor substrate provided with the first and second semiconductor layers having a spout junction, and forming a resist film on the semiconductor substrate on which the first insulating film is deposited A second step, a third step of forming an opening at a predetermined position of the resist film, a fourth step of etching the first insulating film through the opening to form an opening in the first green film, A fifth step of stripping the resist film, a sixth step of selectively etching the first semiconductor layer through the opening of the first insulating film, and closing the opening of the first insulating film. A seventh step of depositing a second insulating film having a thickness that does not have a thickness; an eighth step of performing an etch-back process on the second insulating film to expose the second semiconductor layer; and a gate metal on the second semiconductor layer. And a ninth step of forming Method of manufacturing a conductor arrangement.   A first step of depositing a first insulating film on the semiconductor substrate provided with the first and second semiconductor layers having a spout junction, and forming a resist film on the semiconductor substrate on which the first insulating film is deposited A second step, a third step of forming an opening at a predetermined position of the resist film, a fourth step of etching the first insulating film through the opening to form an opening in the first green film, A fifth step of stripping the resist film, a sixth step of selectively etching the first semiconductor layer through the opening of the first insulating film, and closing the opening of the first insulating film. A seventh step of depositing a second insulating film having a thickness that does not include, an eighth step of performing an etch-back process on the second insulating film to expose the second semiconductor layer, and using the second insulating film as a mask Etching the second semiconductor layer to a predetermined depth; Process and method of manufacturing a semiconductor device characterized by comprising a tenth step of forming a gate metal on the second semiconductor layer.

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