JP2006040318A - Memory device control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a malfunction in fetching data at the time of signal transition to a HiZ state when a bidirectional data strobe signal is fetched as a clock. <P>SOLUTION: The memory device control circuit controls a memory device having the data strove signal for fetching the data, and comprises two kinds of delay circuits for delaying the data strobe signal, handling the data strobe signal delayed by one delay circuit as a clock for fetching read data, and handling the data strobe signal delayed by the other delay circuit as an enable signal for fetching the read data. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory device control circuit, and more particularly to a control circuit for a memory device having a data strobe signal.

  In recent years, as the degree of semiconductor integration has improved, the speed of LSI internal processing has increased significantly. Therefore, high-speed data transfer is also required for external storage elements used as main memory, and DDR (double data rate) SDRAM is used. It has become.

  DDRSDRAM can input and output data at a data rate twice that of the clock signal in synchronization with both edges of the clock.

  For data (DQ) transfer of DDRSDRAM, a data strobe signal called a DQS signal is used, and data is captured at the rising edge and falling edge of the DQS signal.

  FIGS. 1A and 1B are timing charts showing a relationship among a clock signal, a DQ signal, and a DQS signal related to DDRSDRAM data transfer.

  FIG. 1A is a timing chart when a write operation from the controller to the memory device is performed. The controller outputs so that the edge of the DQS signal comes to the center of the window of the DQ signal. When a DQS signal is output from the controller, a period in which a Low called a preamble is first output and a period in which a Low called a postamble is output after the DQS signal is output are required.

  FIG. 1B is a timing chart when read data is output from the memory device to the controller. The memory device aligns and outputs the change points of the DQ signal and DQS signal. Even during reading, the memory device has a low period called a preamble and a low period called a postamble before outputting data. When reading, the DQ signal and DQS signal are aligned and input to the controller, so the controller generates a DQSDLY signal with a delay applied to the input DQS signal, and captures data at the rising and falling edges of the DQSDLY signal I do. Data captured at both edges of the DQSDLY signal needs to be synchronized with the clock signal inside the controller, and the DQSDLY signal and the internal clock are transferred.

  FIG. 2 shows an example of a circuit configuration of a controller for fetching read data, and FIG. 3 shows a timing chart thereof. When the DQS signal (202) is input into the LSI, a delay is added using a delay circuit (203) such as a DLL, and the DQSDLY signal (204) to which the delay is added is a flip-flop that takes in the DQ signal (201). Connected to the clock terminal. There are flip-flops (205) that fetch DQ signals at the rise of the DQSDLY signal and flip-flops (206) that fetch at the fall of the DQSDLY signal.The flip-flop that fetches at the rise of DQSDLY signal is the first beat data of DQ. The flip-flop fetched downstream is the next beat data. In this configuration, the flip-flop (207) that takes in the output of the flip-flop fetched at the rising edge receives the data again at the falling edge of the DQSDLY signal.

  The DQ signal (201) and DQS signal (202) are output at the same frequency as the clock that operates the DDRSDRAM, and in order to bring the edge of the DQSDLY signal (204) to the center of the window of the DQ signal (201) It is necessary to delay by 1/4 phase. In many cases, a DLL is used to delay the DQS signal (202).

  Data captured by the DQSDLY signal (204) is transferred to the flip-flop of the internal clock of the controller for processing inside the controller.

The DQS signal (202) input and the internal clock signal are out of phase because of delay on the PCB board.
JP 2001-189078 A

  The DQ signal (201) and the DQS signal (202) are bidirectional signals because they are output from both the controller and the memory device. Accordingly, during the controller write operation, except for the read operation from the memory device, the DQ signal line and DQS signal line are not driven at all, that is, are in the Hi-Z level and terminated at the reference potential.

  Therefore, when read data is returned from the memory device to the controller, it is driven from the Hi-Z level to the preamble low, and after the desired read data is transferred from the memory device to the controller, the postamble low is driven. After a period of time, the DQS signal transitions to the Hi-Z state.

  However, as shown in FIG. 2, since the DQS signal is connected to the data terminal of the flip-flop through the delay circuit inside the controller, the level of the DQS signal is over at the Hi-Z transition as shown in FIG. When a phenomenon occurs in which the reference potential is increased or decreased due to shooting or the influence of noise or the like, rising edges and falling edges are generated.

  If these rising edges and falling edges occur between transfers to the internal clock, data corruption may occur and malfunction may occur.

  Similarly in memory devices, malfunctions may occur due to overshoot or noise of the DQS signal, and countermeasures are required.

  This measure includes means for counting valid DQS edges or determining the DQS period during which valid DQS is issued to generate an enable signal and a mask signal and gating other than valid DQS. However, if the memory device side can generate the clock signal, command, and data system signal enable signal and mask signal determined according to the AC specifications, the read data, that is, the controller side outputs the data from the memory device. Since the PCB board delay until the read data is returned is added, the internal clock system and the input phase of the DQS signal are out of phase, so it is very difficult to generate the determined enable signal and mask signal. Further, in the case of LSI, there is a possibility that it is mounted on a plurality of types of PCB boards, and board delays are different for each board, so it is very difficult to guarantee an enable signal and a mask signal at a certain timing.

  The present invention has been made in view of the above, and an object of the present invention is to realize a mechanism for preventing malfunction due to the influence of noise or the like on the DQS signal even when the phase relationship between the internal clock and the DQS signal is uncertain. And

  A memory device control circuit according to the present invention is a control circuit for a memory device having a data strobe signal for taking in data, and has two types of delay circuits for adding a delay to the data strobe signal. The circuit has a larger delay amount than the other delay circuit, handles a data strobe signal with a small delay amount as a clock for fetching data read from a memory device, and a data strobe signal with a large delay amount Is a memory device control circuit that enables data capture when capturing data read from the memory device.

  According to the present invention, the controller that controls the memory device uses the postamble period during which the DQS signal is guaranteed to be at a low level as an enable signal that captures the DQ signal. It is possible to prevent malfunction due to the influence of overshoot and noise at the time of transition to, and the configuration of the present invention can be realized without depending on the configuration of the PCB board and the delay amount.

<Embodiment 1>
An embodiment of the present invention is shown in FIG.

  The delay circuit 2 (401) for adding a delay to the DQS signal (202) is added to the read data capturing circuit shown in FIG. 2 to generate the data enable signal (402), and the falling edge of the DQSDLY signal This is realized by connecting to the enable terminal (403) of the flip-flop fetched in (1).

  An equivalent result can also be obtained by connecting the AND gate of the DQSDLY signal (204) to the clock terminal of the flip-flop by inverting the data enable signal (402).

  In this configuration, the delay amount of the delay circuit 1 (203) for generating the DQSDLY signal (204) is set to the 1/4 phase delay of the clock, and the delay amount of the delay circuit 2 (401) for generating the data enable signal. Is described as a 2/5 phase delay of the clock, but the present invention is not limited to this combination.

  FIG. 5 shows a timing chart according to the realization of the configuration shown in FIG.

  The DQ signal (201) and DQS signal (202) from the memory device are input to the LSI in phase, and the DQS signal is delayed by 1/4 phase by the delay circuit 1 (203) to generate the DQSDLY signal (204). Is done. By delaying by 1/4 phase, the generated DQSDLY signal (204) is controlled so that the edge comes to the center of the window of the DQ signal (201).

  Further, the DQS signal input to the LSI is delayed by 2/5 phase by the delay circuit 2 (401) to generate the DQEN signal (402).

  The rising edge and falling edge of the DQSDLY signal (204) generated by the delay circuit 1 (203) are connected to the clock terminal of the flip-flop (205, 206, 207) that takes in the DQ signal, and the delay circuit 2 (401) The generated DQEN signal (402) is connected to the enable terminal (403) of the flip-flop captured at the falling edge (206, 207) of the DQSDLY signal (204). In this embodiment, it is assumed that the DQ signal is captured as Enable when the input signal of the enable terminal (403) is High. The DQEN signal (402) must also be inverted when using flip-flops with reversed polarity.

  In this configuration, the flip-flop (205) that captures at the rising edge of the DQSDLY signal (204) always captures the DQ signal (201) at the rising edge and captures at the falling edge of the DQSDLY signal (204). The DQ signal (201) is taken in only when the DQEN signal (402) is High at the falling edge of the DQSDLY signal (204).

  In the example of FIG. 5, the rising edge and falling edge are generated when the DQS signal (202) transitions to Hi-Z at the end of reading, and this is a signal transition that should not be judged as an edge. The signal delayed by the delay circuit 2 (401) during the low period of the postamble signal is the DQEN signal. At the falling edge of the DQSDLY signal, the DQEN signal is low, so the DQ signal is captured. Will not cause malfunction.

  FIG. 6 shows a circuit configuration for generating timing equivalent to the circuit configuration shown in FIG.

  In this configuration, the same timing as the timing of the DQEN signal shown in FIG. 5 is realized by adding a delay circuit 3 (601) that delays the DQSDLY signal generated by the delay circuit 1 (203).

It is an example of a timing chart showing a relationship between clock, data, and data strobe signals of DDRSDRAM. It is an example of a fetch circuit configuration for fetching read data of DDRSDRAM. It is a timing chart figure at the time of taking in reading data of DDRSDRAM. It is a circuit block diagram in the Example of this invention. It is a timing chart figure at the time of reading data reading in the example of the present invention. It is a circuit block diagram in the Example of this invention.

Explanation of symbols

101 DQS signal noise example 201 DQ signal 202 DQS signal 203 DQS signal delay circuit 204 DQSDLY signal 205 DQSDLY signal rise flip-flop 206, 207 DQSDLY signal fall flip-flop 401 DQS signal delay circuit 402 Data capture enable signal 403 Flip-flop enable terminal 601 DQSDLY signal delay circuit

Claims (18)

A memory device control circuit for controlling a memory device having a data strobe signal for capturing data,
At least two delay circuits for adding a delay to the data strobe signal;
A flip-flop or latch for capturing data,
Connect the data strobe signal to the input terminals of both delay circuits,
Connect the output of the first delay circuit to the clock terminal of the flip-flop or latch,
A memory device control circuit, wherein the output of the other delay circuit is connected to the enable terminal of the flip-flop or latch.   2. The memory device control circuit according to claim 1, wherein the delay amount of one of the two types of delay circuits is small.   3. The memory device control circuit according to claim 1, wherein the delay circuit is realized by a delay lock loop (DLL).   The memory device control circuit according to claim 1, wherein a delay amount by the delay circuit can be set by software or the like.   5. The memory device control circuit according to claim 4, wherein the delay circuit is realized by a delay lock loop (DLL). A memory device control circuit for controlling a memory device having a data strobe signal for capturing data,
At least two delay circuits for adding a delay to the data strobe signal;
A flip-flop or latch that captures the data;
A gate circuit for masking signals,
Connect the data strobe signal to the input terminals of both delay circuits,
Connecting the output of the first delay circuit to the clock terminal of the flip-flop or latch and one terminal of the gate circuit;
Connect the output of the other delay circuit to the other terminal of the gate circuit,
A memory device control circuit, wherein an output of the gate circuit is connected to a data terminal of the flip-flop or latch.   2. The memory device control circuit according to claim 1, wherein the delay amount of one of the two types of delay circuits is small.   3. The memory device control circuit according to claim 1, wherein the delay circuit is realized by a delay lock loop (DLL).   The memory device control circuit according to claim 1, wherein a delay amount by the delay circuit can be set by software or the like.   5. The memory device control circuit according to claim 4, wherein the delay circuit is realized by a delay lock loop (DLL). A memory device control circuit for controlling a memory device having a data strobe signal for capturing data,
At least two delay circuits that add a delay to the input signal; and
Have flip-flops or latches to capture data,
Connect the data strobe signal to the input terminal of the first delay circuit,
Connecting the data strobe signal to which the delay is added in the first delay circuit to the clock terminal of the flip-flop or the latch and the input terminal of the other delay circuit;
A memory device control circuit, wherein the output of the other delay circuit is connected to the enable terminal of the flip-flop or latch.   12. The memory device control circuit according to claim 11, wherein the delay circuit is realized by a delay lock loop (DLL).   12. The memory device control circuit according to claim 11, wherein a delay amount by the delay circuit can be set by software or the like.   14. The memory device control circuit according to claim 13, wherein the delay circuit is realized by a delay lock loop (DLL). A memory device control circuit for controlling a memory device having a data strobe signal for capturing data,
At least two delay circuits that add a delay to the input signal; and
A flip-flop or latch that captures data and a gate circuit that masks the signal;
Connect the data strobe signal to the input terminal of the first delay circuit,
Connecting the data strobe signal to which the delay is added by the first delay circuit to the clock terminal of the flip-flop or latch, the input terminal of the other delay circuit, and one input terminal of the gate circuit;
Connect the output of the other delay circuit to the other gate circuit of the gate circuit,
A memory device control circuit, wherein an output of the gate circuit is connected to a data terminal of the flip-flop or latch.   The memory device control circuit according to claim 15, wherein the delay circuit is realized by a delay lock loop (DLL).   16. The memory device control circuit according to claim 15, wherein a delay amount by the delay circuit can be set by software or the like.   The memory device control circuit according to claim 17, wherein the delay circuit is realized by a delay lock loop (DLL).

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