JP2006039821A - Method for controlling multiprocessor-equipped system lsi - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generalize and perform the optimization and high speed operation of the multi-task control of a multiprocessor. <P>SOLUTION: This system LSI is constituted of a processor group having a data cache inside the system LSI and a high-capacity external shared memory as hard configuration. The combined candidates of tasks are generated, and the same task is redundantly and speculatively executed by a plurality processors. Inter-processor communication is used as penalty, and the result of the combination of the processor and the task for preventing penalty most is adopted so that it is possible to realize the consistency of the whole system between the data cache and the shared memory while using the most efficient processing procedure. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an LSI configuration method called a system LSI or system-on-chip (SOC), which includes a plurality of CPUs, that is, multiprocessors, and is incorporated in one LSI together with a dedicated hardware circuit. It is related with the method of performing what is called multitasking which performs different programs simultaneously and independently and communicates and controls between programs.

  In recent years, with the advancement of semiconductor manufacturing processes and integration, LSIs called so-called system LSIs or system-on-chip (SOC), which are configured by incorporating a CPU with a dedicated hardware circuit into a single LSI, are used extensively. It has come to be. Furthermore, with the increase in the degree of integration of semiconductors, it is relatively easy to mount a plurality of CPUs in terms of the area occupied by a CPU in an LSI, and a multi-CPU including a plurality of CPUs is mounted to improve performance. The SOC by the processor is gradually being used. In the future, due to further improvements in the degree of integration of semiconductors, the impact on the price of LSI will be more limited by the number of pins connected to the outside, and mounting of a very large number of CPUs, such as tens to hundreds, From the viewpoint of area, it is expected that an era will be possible on the SOC at a very low cost.

  On the other hand, software used in digital devices has become relatively complex, and an operating system (OS) that can be used in so-called multitasking that executes programs simultaneously and independently and communicates and controls between programs is provided. Use is increasing.

On the other hand, it is considered difficult to continue to increase the operating frequency at a conventional pace from the viewpoint of the physical properties of semiconductors, power consumption, and heat generation. In the past, application software by multiprocessors and multitasking OS for multiprocessors have been developed and used for high-speed processing. Thousands of processors are used for large-scale parallel numerical calculations, or two. A multitasking multitasking OS using four processors is used.
JP-A-9-185593

  However, the conventional method has the following problems.

  1) Application software with a large number of multiprocessors is effective in cases where specific parallel operations can be performed, for example, image processing, numerical calculations for solving field equations, etc., but control system processing that cannot be easily divided in parallel However, it is difficult to automatically parallelize algorithms. For example, the dependency of individual tasks in a multitasking application is different for each specific application. There is no general solution for generating parallel algorithms in such control system processing, and automation is difficult.

  2) When using a shared memory that simultaneously accesses memory in one area by a multiprocessor, the bus traffic to the shared memory increases and the access speed decreases as the number of processors increases. For this reason, it is necessary to increase the speed by using a copy to a local high-speed memory that can be accessed for each processor such as a cache mechanism. In this case, the consistency between the cache and the shared memory for each processor must be taken. Becomes difficult. Although it is possible to arrange only the distributed memory close to each processor, in this case, it is difficult to exchange data between the distributed memories, and the consistency of the contents of the distributed memory should be ensured in a general control algorithm. Is difficult.

  3) It is difficult to select an appropriate method for improving the data processing efficiency of the entire system when a plurality of tasks are assigned to a plurality of processors.

  As an example, when tasks Ta, Tb, and Tc are operated by processors Px and Py, a certain task Ta is assigned to one processor and Px: (Ta), Py: (Tb, Tc) In addition, there is a method in which a plurality of tasks Ta and Tb are assigned to one processor and Px: (Ta, Tb) and Py: (Tc) are set. Here, with respect to the task Ta, the task Ta clearly operates at a high speed from the viewpoint that the former method has no task transition in the processor and does not require register data exchange (context switch) in the processor. On the other hand, when operations are performed by communicating messages between tasks Ta and Tb, communication must be performed between different processors, and when the overhead for that is large, the former method is speedy. Is a factor that decreases. The synchronization overhead between processors varies depending on the hardware system configuration such as multiprocessor and memory, and the control configuration of the multitasking software program. As a result, the configuration of complex tasks and processors In this case, it can be said that it is a case-by-case whether the former method or the latter method can process data more efficiently. As described above, it is difficult to select a method for assigning tasks to multiprocessors.

  In such an environment that can solve the above problems and can use a huge number of processors at low cost, the data transfer speed to the shared memory does not become a bottleneck, and the consistency of the data in a large number of distributed memories is achieved. The architecture and algorithm to execute this software at high speed were desired.

  In order to solve the above-mentioned problems, the present invention has the following configuration.

  A multiprocessor, a high-speed distributed memory directly connected to each of the processors P1, P2, P3,..., A bus connected in a shared manner so as to be accessible from all processors, and a bus connected to the above-mentioned bus A high-speed internal shared memory that can be referenced by providing an address offset for each area, a memory controller that can be connected to the shared memory externally through the bus, and the same data from the shared memory to each distributed memory simultaneously by copying data from the bus A system LSI having at least an internal DMA controller capable of transfer, and in the execution of multitasking, candidates for allocation methods to each processor of tasks T1, T2, T3,. Each of the means for preparing a plurality of types as D2, D3,. A means for allocating a processor, a high-speed distributed memory, and a divided area of a high-speed internal shared memory; and a means for performing the same task on a plurality of processors by assigning a processor to a task using the table. Means for detecting the progress of transition between tasks for each distribution method, and means for writing back the contents of the distributed memory of the processor used for the processing of the distribution method most advanced based on the detection means to the shared memory And a multitask control method for a multiprocessor-mounted system LSI.

  As described above, according to the present invention, when assigning a multitask to a multiprocessor, a plurality of distribution method candidates are raised and applied to the processor, and the most efficient task assignment result is left. Thus, the following effects can be obtained.

  1) Multitask allocation scheduling to multiprocessors that are difficult to predict is optimized.

  2) Since the subsequent optimal allocation is not predicted by taking a history (log), dynamic optimal allocation at that moment is performed even for state transitions that have poor reproducibility and are difficult to predict statistically.

  3) Even if the number of processors increases or the number of tasks increases, it can be scalable with the same algorithm.

  This is particularly effective when using a system LSI that requires a small number of package pins even if the number of processors is enormous. For example, even if a large number of processors are arranged so that the number of processors is sufficiently larger than the number of tasks, the number of processors It is effective when using a configuration with a high degree of integration that does not significantly affect the cost, or when using a small processor core.

<Embodiment 1>
Hereinafter, the principle of the present invention will be described with reference to an example of a preferred embodiment of the present invention. In the following, embodiments based on the principle of the present invention are illustrated and described for the purpose of facilitating understanding, and the scope of the present invention is not necessarily limited by the details of the embodiments.

  FIG. 1 is a diagram showing the basic concept of the present invention.

  FIG. 1A shows a hardware configuration of a system LSI, and FIG. 1B shows a control method showing how multitasks are allocated on the multiprocessor.

  As shown in FIG. 1A, high-speed distributed memories M1, M2, M3,... And processors P1, P2, P3,. Yes. A shared memory 200 is connected to the bus 100 via a memory controller (not shown). An arbitration processor 500 receives and controls a signal from each processor Pn. A DMA controller 400 is capable of transferring data between the shared memory and the high-speed distributed memory.

  Reference numeral 600 denotes a high-speed shared memory 600.

  Reference numeral 300 denotes a part constituted by a system LSI. On the other hand, T1, T2, T3,... Are prepared as tasks that are software programs executed on the processor. FIG. 1 (b) shows a part of it.

  Here, an example in which there are 10 or more processors and three tasks T1, T2, and T3 will be described. First, there are the following possibilities for task distribution. This is shown below as distribution method tables D1 to D5. Here, (task...) Indicates a task assigned to one processor. For example, (T1, T2) indicates that tasks T1 and T2 are assigned to one processor. {(Task...)...} Indicates a method of assigning all tasks to the processors by the above assignment.

  For example, D2 = {(T1, T2), (T3)} is a distribution method in which tasks T1 and T2 are assigned to one processor, and all tasks are executed by assigning a task T3 to another processor. D2 is shown.

D1 = {(T1), (T2), (T3)}
D2 = {(T1, T2), (T3)}
D3 = {(T2, T3), (T1)}
D4 = {(T3, T1), (T2)}
D5 = {(T1, T2, T3)}
In this example, for example, a task Tn is assigned to the processor Pn as follows.

P1: (T1)
P2: (T2)
P3: (T3)
P4: (T1, T2)
P5: (T2, T3)
P6: (T3, T1)
P7: (T1, T2, T3)
P8: (T3)
P9: (T1)
P10: (T2)
As described above, the same task is assigned to a plurality of processors.

  Accordingly, the processors are assigned to the distribution method table Dn as follows.

D1 = {P1, P2, P3}
D2 = {P4, P8}
D3 = {P5, P9}
D4 = {P6, P10}
D5 = {P7}
Here, as described above, the same processor Pn is not allocated to different distribution method tables Dn, but is exclusively allocated. Therefore, the processors are independent for each distribution method table.

  Here, high-speed distributed memories M1... M10 corresponding to the processors P1 to P10 are directly connected to each other. Each distributed memory and shared memory are mapped to different positions in the same physical address space, but the distributed memory corresponding to each processor is seen as the same address space. For example, the address range from P1 to M1 The address range from P2 to M2 can be the same. That is, when accessing the corresponding distributed memory from each CPU, an address offset setting mechanism is provided so that all the processors can see it as the same address space. Using this mechanism, a copy of the page data of the shared memory is stored in the high-speed distributed memory M1... M10, and from each processor as a cache area of the shared memory under the manual management of the user. Can be handled.

  First, as a processing start sequence, for each high-speed distributed memory, the data block used by the assigned task (stack area used within the assigned task, messages between assigned tasks, etc.) is transferred using the DMA controller. Load from shared memory.

  In addition, a partial block of a data area (such as an image data area) to be shared and processed between tasks on the shared memory is loaded into the shared high-speed memory 600.

  At this time, the shared high-speed memory 600 is divided into the number of the distribution method tables, and a processor for each distribution table is allocated to each partition of the divided high-speed shared memory. In the case of the above example, each partition of the high-speed shared memory divided into five is assigned to the distribution tables D1 to D5. Each partition has a different address offset, and is shared between processors allocated in the same distribution table, and the distribution table is used as an independent area exclusively between different processors. As this method, an address offset table is prepared in the shared high-speed memory 600 corresponding to the access from each processor ID.

  Of the processors, a processor to which two or more tasks are assigned repeats a transition between assigned tasks by the kernel being switched by a timer interrupt (not shown).

  While this state continues, each processor notifies the arbitration processor when an appropriate task cyclic stop condition is satisfied, and stops the operation (idle state). Here, an appropriate task cyclic stop condition is, for example, a case where a message from a task other than the task operating in the current processor is requested.

  The operation at this time will be described using an example in which tasks T1 and T2 are assigned to the processor P4. Since the OS of the processor P4 knows that the tasks assigned to it are T1 and T2 at the start of execution, when it is determined that the message requested by the task T1 is obtained from the task T3, P4 passes through the OS. The arbitration processor is notified of the stop state, and shifts to the idle state.

  In this way, each processor informs the arbitration processor and stops when information from a task other than the task operating inside itself becomes necessary. In this way, the processor stops one after another.

  Here, as described in the problem to be solved by the invention of the previous section, the data processing amount of each task until the stop is the highest in data processing efficiency without task transition when one task is assigned to one processor. Note that is not necessarily expensive. This is because, in this configuration, messages between tasks are held in the high-speed distributed memory, and if the messages in the high-speed distributed memory can be exchanged between tasks operating in one processor, different processors This is because the processing may be more efficient than the message communication between tasks operating in the.

  For example, it is assumed that the processor Pn and the task Tn are assigned as follows.

P1: (T1)
P2: (T2)
P4: (T1, T2)
At this time, although P1 and P2 are high-speed when there is no task transition, since the distributed memory directly connected to the processor is different, when message communication occurs between the tasks, data synchronization between the different processors and the distributed memory Must be taken and processing time is required. Furthermore, when the number of processors is enormous and the communication mechanism between tasks is complicated, it is complicated to synchronize the distributed memories. On the other hand, in P4, there are a plurality of tasks and task transitions occur. However, regarding communication between tasks in this processor, data consistency is ensured in the same distributed memory, so processing time required for data synchronization is necessary. Absent. Therefore, it can be said that which combination is more efficient is more case-by-case than the operation being executed.

  Here, the arbitration processor invalidates the table including the stopped processor every time the processor stops in the distribution method table Dn. Thus, the task group operating on the processor of the table that survives to the end and the contents of the distributed memory are validated. That is, at this time, the data related to task control in the distributed memory that has survived becomes valid. Thereafter, when the processor stops, the effective contents of the distributed memory are written back to the shared memory. When a plurality of tables are valid at the time of stopping, an arbitrary method, preferably a sorting table with a small number of processors may be selected.

  That is, the data block used in the assigned task (stack area used in the assigned task, message between assigned tasks, etc.) is written back.

  It should be noted that, during the operation, an instruction or arbitration processor that allows the task to specify a valid allocation table by itself and stop all processors by the arbitration processor and write back the distributed memory data and the high-speed internal shared memory. To have a flash instruction ,.

  After this, the process returns to the process start sequence again and the same process may be repeated. When processing data in a larger shared memory data area (image data area, etc.), stop any processor operation when one of the tasks finishes processing the data of the high-speed internal shared memory divided area size. Then, the processor of the distribution method including the task is enabled, and the effective contents of the distributed memory and the effective contents of the high-speed internal shared memory are written back to the shared memory.

  The arbitration processor flush instruction described above is used for this operation.

  Thereafter, the data at the position following the data written back on the shared memory is again loaded into the high-speed internal shared memory by the DMA controller by the size of the partial block. By repeating the above, data on a large distributed memory is processed.

  In the configuration example of the present invention, the input / output data uses a part of the shared memory as a ring buffer for the input / output data, and the ring buffer and the I / O controller are controlled by the arbitration processor to ensure data consistency. keep.

  In the above-described embodiment, the distribution method table for all multiprocessor combinations is generated in the case of three tasks. However, the number of tables may be limited to an appropriate number by combining the number of processors and the number of tasks. .

Hardware configuration and multitask control method

Explanation of symbols

100 bus 200 shared memory 400 DMA controller 500 arbitration processor 600 high-speed shared memory

Claims (1)

A multiprocessor, a high-speed distributed memory directly connected to each of the processors P1, P2, P3,..., A bus connected in a shared manner so as to be accessible from all processors,
A high-speed internal shared memory that is connected to the bus and can be referred to by providing an address offset for each divided area, a memory controller that can connect the shared memory to the outside through the bus, A system LSI having at least an internal DMA controller capable of simultaneously transferring the same data to the distributed memory,
In the execution of multitasking, means for preparing a plurality of types of allocation method candidates to the respective processors T1, T2, T3,... As allocation method tables D1, D2, D3,.
Means for exclusively assigning a processor, a high-speed distributed memory, and a high-speed internal shared memory divided area for each distribution method table;
Means for assigning a processor to a task using the above table and executing the same task on a plurality of processors in a speculative manner;
Means for detecting the progress of transition between tasks for each distribution method;
Multitask control of a multiprocessor-mounted system LSI, characterized by having means for writing back the contents of the distributed memory of the processor used for the processing of the distribution method that has been most advanced based on the detection means to the shared memory Method.

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