JP2006038782A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of reducing its size for analyzing defective cause of built-in memories, as well as shortening the analysis time for the cause of defective built-in memories. <P>SOLUTION: An address data generating section 5 writes test data in each object address of RAM 1 to 4. A verification section 7 reads out data actually stored in each object address of RAM 1 to 4, to compare each memorized datum with the test data as expected values. When a difference between stored data and the test data exists, a preserved data generating section 8 preserves the preserved data, which include the data indicating the content of difference, the data indicating which RAMs correspond to the RAM containing the occurred difference, and the data indicating object addresses, to a housing domain of the preserved data prepared in the RAM1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit (hereinafter referred to as an IC) such as an LSI (Large Scale Integration), and in particular, an IC having a BIST (Built In Self Test) circuit for inspecting a built-in memory such as a RAM (Random Access Memory). About.

  In an IC such as an SOC (System On a Chip) having a RAM having a relatively large storage capacity, a BIST circuit for inspecting the RAM is usually provided.

  FIG. 7 is a block diagram showing the configuration of an IC having a conventional BIST circuit. The IC 100 includes an address / data generation unit 101, a RAM 102, a collation unit 103, and a selector 104.

  At the time of the inspection of the RAM 102, a signal indicating “test of the RAM 102” is given from the outside to the selector 104, and the bus 121 connected to the address / data generation unit 101 is connected to the RAM 102. Then, the address / data generation unit 101 gives an address signal indicating an address (target address) to be inspected in the RAM 102, a signal indicating predetermined test data, and a write signal to the RAM 102 via the selector 104. Test data is written to the target address in the RAM 102.

  When the RAM 102 is not used for inspection but is normally used (during normal use), the bus 120 for transmitting an address signal / data signal from a CPU (Central Processing Unit; not shown) or the like is connected via the selector 104 to the RAM 102. These address signals / data signals are supplied to the RAM 102 (normal input). Data from the RAMs 1 to 4 is given to the CPU or the like.

  After that, the collation unit 103 reads the data (stored data) actually stored at the target address from the RAM 102, the actual storage data and the test data as the expected value given from the address / data generation unit 101, Is matched.

  The writing of test data by the address / data generation unit 101 and the collation by the collation unit 103 are repeated for all addresses in the RAM 102, and the collation unit 103 determines that the stored data matches the expected value at all addresses. A signal indicating that there is no defect in the RAM 102 is output to an external terminal (not shown) of the IC 100, while a signal indicating that the RAM 102 is defective is output if there is any mismatch.

  These signals indicating whether or not the RAM 102 is defective are given to an inspection device (general-purpose logic tester or the like; not shown) provided outside the IC 100. In this way, the quality of the RAM 102 built in the IC 100 is checked.

  In order to improve the IC manufacturing yield, it is necessary to analyze the cause of the defective IC (identify the defective part; that is, specify which bit of which address in the RAM 102 is the defective part). . For example, if analysis reveals that only a specific bit at a specific address is defective, information for yield improvement such as “Is there a scratch on a specific part of an IC pattern forming mask” is obtained. Because it is.

  In the IC 100 of FIG. 7, when specifying a defective part, the selector 104 is controlled so that the data stored in the RAM 102 can be read by an external inspection device (not shown), and the address bus, data bus, etc. (The address bus 122 is thereby connected to the RAM 102 via the selector 104). Then, an address signal is given from the outside to read out the stored contents of all addresses in the RAM 102 to identify which bit of which address in the RAM 102 is defective, that is, the defective part.

  Normally, the ratio of defective addresses (addresses including defective bits) to all addresses is very small (for example, 1 / tens of thousands). However, in the conventional configuration example of FIG. 7, in order to specify a defective portion of the RAM 102, that is, to specify which bit of which address is defective, the stored data of all addresses of the RAM 102 is read out to the outside. Need to be verified. For this reason, there is a problem that analysis time becomes long (hereinafter, sometimes referred to as “Problem 1”). This long analysis time leads to an increase in IC development and manufacturing costs.

  Further, no matter how fast the operation speed of the IC 100 (for example, the operation clock is 200 MHz), the reading speed of the stored data in the RAM 102 is the operation speed of the inspection device (for example, the operation clock is 40 MHz. It is often slower than the speed). Therefore, when the operation speed of the inspection device is low, the analysis time becomes very long.

  In many cases, an image processing IC used in a digital camera or the like has a plurality of RAMs (for example, several tens), and in that case, which bit of which address of which RAM is defective. It is necessary to specify whether it is. However, even if there are a plurality of RAMs included in the IC, there is usually only one set of external terminals connected to the data bus or address bus accessing each RAM (because each RAM has an external terminal). Therefore, it is necessary to perform the above analysis in order for each RAM. For example, if an analysis time of 0.1 second is required when there is only one RAM as shown in FIG. 7, an analysis time of 10 seconds is required in an IC provided with 100 RAMs. come. Therefore, in the IC having a plurality of RAMs, the above problem 1 becomes very remarkable.

  In addition, in order to specify a defective portion, it is necessary that an external inspection device can read out the data stored in the RAM 102 as described above, and a wiring area and a selector for the reading (the selector in FIG. 7). 104) is required, but when the IC includes a plurality of RAMs, selectors for the number of RAMs (selectors for switching three buses such as the selector 104) are required. The amount of wiring for connecting to the selector becomes enormous. That is, there is a problem that the circuit scale for analyzing the cause of the failure of the memory (RAM) becomes very large (hereinafter, sometimes referred to as “problem 2”).

An object of the present invention is to provide a semiconductor integrated circuit (IC) that can shorten the analysis time of a cause of a failure of a built-in memory. Another object of the present invention is to provide a semiconductor integrated circuit capable of reducing the circuit scale for analyzing the cause of failure of the built-in memory.

  In order to achieve the above object, a semiconductor integrated circuit according to the present invention includes a memory capable of reading and writing data, an address / data generation unit for writing predetermined data to a predetermined target address of the memory, and the address / data generation When the data actually stored at the target address by writing by the unit is read from the memory, and the actual stored data is different from the predetermined data, the data indicating the difference and the data indicating the target address are And a collation result storage control unit for storing the stored data in a storage data storage area provided in the memory.

  As a result, it is possible to identify a defective part (analysis of the cause of the defect), that is, to identify which bit of which address has a defect by simply reading out a small amount of stored data stored in the storage data storage area. Become. Therefore, the failure cause analysis time is greatly shortened, which contributes to the development of semiconductor integrated circuits and the reduction of manufacturing costs.

  A plurality of memories capable of reading and writing data, an address / data generation unit for writing predetermined data to a predetermined target address of each memory, and data actually stored at each target address by writing by the address / data generation unit Is read from each memory, it is determined for each memory whether the actual storage data of each target address is different from the predetermined data, and if any storage data is different from the predetermined data, the difference contents Stored data stored in any one of the plurality of memories is stored data including data indicating which memory is different from the data indicating the data and data indicating the target address. And a collation result storage control unit for storing in the area.

  As a result, it is possible to specify a defective portion, that is, which bit of which address of which memory is defective, by simply reading out a small amount of stored data stored in the storage data storage area. Therefore, the failure cause analysis time is greatly shortened, which contributes to the development of semiconductor integrated circuits and the reduction of manufacturing costs.

  In addition, since the cause of failure can be analyzed by accessing only one of a plurality of memories, a conventional selector (selector for switching three buses such as the selector 104) is provided for the number of memories. There is no need to prepare, and it is not necessary to secure as many wiring areas as the number of memories. That is, the circuit scale for failure analysis can be greatly reduced.

  Further, for example, before performing the process of storing the stored data in the stored data storage area, it is determined whether there is a defective area in the stored data storage area, and if there is a defective area, the verification result storage control unit May store the stored data while avoiding the defective area.

  Thereby, accurate storage data can be stored in the storage data storage area.

  Further, for example, the stored data may include information regarding an address where the defective area exists.

  Thereby, even if a defective area exists in the storage data storage area, an external inspection device or the like can accurately know at which address in the storage data storage area the storage data is stored.

  Specifically, the data representing the content of the difference includes data associated with the predetermined data or the predetermined data and the stored data.

  The memory provided with the storage data storage area may be a nonvolatile memory.

  As a result, the stored data can be used even after the semiconductor integrated circuit is incorporated into an electrical device. By referring to the stored data, it is possible to read and write data while avoiding the defective portion of the memory. Therefore, even if there are some defective portions in the memory, the memory operates normally. In other words, this improves the yield in manufacturing the semiconductor integrated circuit.

  As described above, according to the semiconductor integrated circuit of the present invention, it is possible to greatly reduce the analysis time of the cause of the built-in memory failure. Further, the circuit scale for analyzing the cause of failure of the memory can be reduced.

  Embodiments of a semiconductor integrated circuit (IC) according to the present invention will be described below with reference to the drawings. FIG. 1 is a configuration block diagram of an IC according to an embodiment of the present invention.

  The IC 10 gives address signals, data signals, and control signals (write signals, etc.) for inspecting the RAMs 1 to 4 to the RAMs 1, 2, 3, and 4 as the memories capable of reading and writing data, and the RAMs 1 to 4. The address / data generation unit 5 and the collation result storage control unit 6 are roughly configured. The collation result storage control unit 6 reads the stored data in each of the RAMs 1 to 4 and collates the stored data with the data written by the address / data generation unit 5 (determines matching / mismatching). When the collation result of the collation unit 7 is input and there is a defect in the RAMs 1 to 4 (when there is a difference between the stored data and the test data), data representing the content of the defect is generated and the data is stored as data The storage data generation unit 8 stored in the RAM 1 and selectors 31, 32, 33, and 34 for switching the buses connected to the RAMs 1, 2, 3, and 4, respectively.

  When the RAMs 1 to 4 are inspected, a signal indicating “tests for RAM 1 to 4” is given from the outside to the selectors 31, 32, 33, and 34, and the bus 21 (p ( p is an integer of 3 or more) (consisting of a number of signal lines) is connected to the RAM 1, 2, 3, 4. As a result, the address / data generation unit 5 can supply address signals, data signals, and control signals (write signals, etc.) for inspecting the RAMs 1 to 4 to the RAMs 1, 2, 3, and 4, respectively.

  When the RAMs 1, 2, 3, 4 are normally used (in normal use) instead of the inspection, the bus 20 (q (q is 3 or more) for transmitting an address signal / data signal from a CPU (not shown) or the like. Are connected to the RAMs 1, 2, 3, and 4 through the selectors 31, 32, 33, and 34, and their address / data signals are stored in the RAMs 1, 2, 3, and 4, respectively. (Usually input). Data from the RAMs 1 to 4 is given to the CPU or the like (normal output).

  Each of the RAMs 1 to 4 can store data (1 word) consisting of 16 bits for 4 kilowords (4096 words). The following explanation will be given by assuming that the lowest address of each of the RAMs 1 to 4 is 000h in hexadecimal notation and the highest address is FFFh in hexadecimal notation.

(Fig. 2: Flow chart of inspection operation)
In the IC 10 of FIG. 1, an operation for inspecting whether or not there is a defective bit (defective cell) in each of the RAMs 1 to 4 (operation during the inspection of the RAMs 1 to 4) will be described with reference to the flowchart of FIG.

  First, in step S1, the address / data generation unit 5 sets the address to be inspected (target address) to an initial value of 000h. In subsequent step S2, the address / data generation unit 5 writes predetermined test data (for example, 5555h) to each target address of the RAMs 1 to 4.

  In step S3, which is shifted to after finishing step S2, the collation unit 7 writes the data actually stored in the respective target addresses of the RAMs 1 to 4 by the writing by the address / data generation unit 5 (step S2). The process proceeds to step S4 described later.

  The collation unit 7 is provided with test data written to the target addresses of the RAMs 1 to 4 in step S2 from the address / data generation unit 5 as the expected value of the storage data read in step S3. In step S4, the collation unit 7 generates actual storage data (actually stored data) and address / data generation of each target address (respective target addresses in the RAMs 1 to 4) read in step S3. The test data as the expected value given from the unit 5 is collated for each RAM (determining whether or not they are different).

  If it is determined in step S4 that the stored data of each target address is consistent with the test data (OK in step S4), the process proceeds to step S5. In step S5, the collation unit 7 sends a signal (for example, a high level signal) indicating that there is no defect in each target address to an inspection device (general-purpose logic tester) connected to the outside of the saved data generation unit 8 and the IC 10. Etc .; not shown) and the process proceeds to step S9 described later.

  On the other hand, if it is determined in step S4 that at least one stored data of each target address is different from the test data (NG in step S4), the process proceeds to step S6. In step S <b> 6, the collation unit 7 checks that a signal (for example, a low level signal) indicating that there is a defect in any of the target addresses in the RAMs 1 to 4 is connected to the outside of the saved data generation unit 8 and the IC 10. To the device (not shown), and the process proceeds to step S7 to be described later.

  The stored data generation unit 8 is provided with an address signal indicating a target address (initial value is 000h) and a data signal indicating test data, which are subjected to collation in step S4, from the address / data generation unit 5. The storage data of each target address is also given from each of RAM1-4. In step S7, the saved data generation unit 8 generates saved data representing the failure contents of the RAMs 1 to 4 based on the given target address, test data, and storage data of each target address, and will be described later in step S8. Migrate to Details of the stored data will be described later.

  In step S <b> 8, the saved data generation unit 8 saves the saved data generated in step S <b> 7 in the saved data storage area 1 a provided in the RAM 1. At this time, the selector 31 is controlled so that the saved data generation unit 8 can store the saved data in the saved data storage area 1a. Here, the allocation of the storage area of the RAM 1 is shown in FIG. In the RAM 1, the area from F00h to FFFh among all the address areas 000h to FFFh is a saved data storage area 1a reserved for storing saved data. In step S8, the saved data is saved from the higher address side of the saved data storage area 1a. Of course, it may be stored from the lower address side.

  Further, as will be apparent from the following description, the inspection of whether or not there is a defective area (area where a defective bit exists) in the stored data storage area 1a (F00h to FFFh) is performed before the operation of FIG. The storage data generation unit 8 stores an address corresponding to the defective area in the storage data storage area 1a in its own internal register (not shown). In step S8, the saved data generation unit 8 saves the saved data by avoiding the defective area in the stored data storage area 1a (avoids the defective address). As a result, accurate saved data is stored in the saved data storage area 1a.

  In step S9, the process proceeds after step S5 described above or the process proceeds after step S8, it is determined whether the target address (initial value is 000h) matches the final address to be inspected. Since each of the RAMs 1 to 4 has addresses from 000h to FFFh, the final address to be inspected is FFFh.

  When the target address = FFFh is not established (No in step S9), the process proceeds to step S10, and the target address is updated. Specifically, the target address is incremented by 1 (increased by 1). At this time, the test data may be updated to different data (for example, updated from 555h to AAAh).

  When step S10 is completed, the process proceeds to step S2 described above, and the processes of steps S2 to S10 are performed again using the updated target address as the inspection target.

  When the processes of steps S2 to S10 are performed for all addresses, the target address = FFFh is established in step S9 (Yes in step S9), and the process proceeds to step 11 described later. Further, after the determination in step S9 becomes affirmative (Yes in step S9), the test data is updated (for example, updated from 555h to AAAh) before proceeding to step S11, and the process returns to step S1, and steps S2 to S2 are performed again. After the process of S10 is repeated, the process may move to step S11.

  Note that when the target address is F00h to FFFh, the processing of steps S2 to S8 is not performed for the RAM 1. This is because the area from F00h to FFFh in the RAM 1 is reserved as the saved data storage area 1a for storing the saved data, and therefore test data should not be written (step S2). Therefore, for RAM 1, addresses 000h to EFFh are inspection target areas in the operation of FIG. 2, and for RAMs 2 to 4, all addresses (000h to FFFh) are inspection target areas in the operation of FIG.

  For example, a three-state buffer (not shown) between a terminal (not shown) for outputting a write signal of the address / data generator 5 and a write input terminal (terminal for controlling a write operation; not shown) of the RAM 1 When the process of step S2 is performed when the target address is F00h to FFFh, the write signal (for example, a low level signal) from the address / data generation unit 5 is not applied to the write input terminal of the RAM 1. Control the three-state buffer.

  In step S11, it is determined whether or not there are defective addresses (addresses including defective bits) in the inspection target areas of the RAMs 1 to 4. When the process of step S6 has not been performed once before shifting to step S11 (No in step S11), the collation unit 7 indicates that all the inspection target areas are free of defects (for example, a high level signal). Is supplied to an inspection device connected to the outside (step S12), and if the process of step S6 is performed even once before moving to step S11, the collation unit 7 indicates that the inspection target area is defective. A signal (for example, a low level signal) is given to an inspection device connected to the outside (step S13). With these signals, it is possible to determine whether or not there is a defective area in the RAMs 1 to 4. When step S12 or step S13 is completed, the inspection operation in FIG. 2 ends.

(Fig. 4: Inspection of storage data storage area)
Next, the inspection of the storage data storage area 1a of the RAM 1 that is separately performed before the operation of FIG. 2 will be described with reference to the flowchart of FIG.

  First, in step S21, the address / data generation unit 5 sets an address to be inspected (target address) to an initial value F00h. In subsequent step S <b> 22, the address / data generator 5 writes predetermined test data (for example, 5555h) at the target address of the RAM 1.

  In step S23, which is shifted to after step S22, the collation unit 7 reads data actually stored in the target address of the RAM 1 from the RAM 1 by writing by the address / data generation unit 5 (step S22), and proceeds to step S24 described later. Transition.

  The collation unit 7 is given test data written in the target address of the RAM 1 in step S22 from the address / data generation unit 5 as an expected value of the data read in step S23. In step S24, the collation unit 7 tests the actual storage data (actually stored data) of the target address read in step S23 and the expected value given from the address / data generation unit 5. Match data.

  If it is determined in step S24 that the stored data at the target address matches the test data (OK in step S24), the process proceeds to step S26 described later.

  On the other hand, if it is determined in step S24 that the storage data of the target address is different from the test data (NG in step S24), the process proceeds to step S25, and the saved data generation unit 8 determines that the target address is defective. It is stored in its own internal register (not shown) as an address. Note that the stored data generation unit 8 is provided with an address signal indicating the target address (initial value is F00h) subjected to collation in step S24 from the address / data generation unit 5.

  In step S26 which moves after finishing step S24 or S25 described above, it is determined whether the target address (initial value is F00h) matches the final address to be inspected. Since the storage data storage area 1a of the RAM 1 is from addresses F00h to FFFh, the final address to be inspected is FFFh.

  When the target address = FFFh is not satisfied (No in step S26), the process proceeds to step S27, and the target address is updated. Specifically, the target address is incremented by 1. At this time, the test data may be updated to different data (for example, updated from 555h to AAAh).

  When step S27 is completed, the process proceeds to step S22 described above, and the processes of steps S22 to S27 are performed again using the updated target address as the inspection target.

  When the processing of steps S22 to S27 is performed for all addresses included in the saved data storage area 1a, the target address = FFFh is established in step S26 (Yes in step S26), and the process proceeds to step 28 described later. . In addition, after the determination in step S26 is affirmative (Yes in step S26), the test data is updated (for example, updated from 555h to AAAh) before the process proceeds to step S28, and the process returns to step S21, and again from steps S22 to S22. After the process of S27 is repeated, the process may move to step S28.

  In step S28, it is determined whether or not there is a defective address in the stored data storage area 1a of the RAM 1 (the inspection target area in the operation of FIG. 4). If the process of step S25 has never been performed before the process proceeds to step S28 (No in step S28), the collation unit 7 indicates that there is no defect in the stored data storage area 1a (for example, a high level signal). Is supplied to the inspection device connected to the outside (step S29), and if the process of step S25 is performed even once before moving to step S28, the collation unit 7 has a defect in the stored data storage area 1a. A signal indicating this (for example, a low level signal) is given to an inspection device connected to the outside (step S30). From these signals, it is possible to determine whether or not there is a defective area in the stored data storage area 1a. When step S29 or step S30 is finished, the inspection operation of FIG. 4 is finished.

(Figure 5: Contents of stored data)
FIG. 5 shows the contents of the stored data generated in the process of step S7 of FIG. One stored data is composed of three words (a word is 16 bits), a first word, a second word, and a third word. The first word stores a defective address (address where a defective bit exists), that is, a target address (12-bit data; ADD [11: 0]) at the time of reaching step S7.

  The third word stores the inspection program number (6-bit data; PROG [5: 0]). This inspection program number is associated with the test data that the address / data generator 5 writes to each of the RAMs 1 to 4 (step S2). If the inspection program number is specified, what is the test data for the inspection device? Can be determined. Of course, instead of the inspection program number, the test data may be directly stored in the stored data (in this case, 4 words are required for one stored data).

  In the third word, a RAM number (2-bit data: RAMID [1: 0]) indicating which of the RAMs 1 to 4 is determined as having a defective bit in step S4 is stored. Is done. RAMID [1: 0] = “00” (binary display) when the RAM determined to have a defective bit is RAM1, RAMID [1: 0] ] Are “01”, “10”, and “11” (binary number display), respectively. Further, actual storage data (16-bit data: DATA [15: 0]) of the target address determined to have a defective bit is stored from the second word to the third word.

  For example, the address / data generation unit 5 writes the test data 5555h corresponding to the program number 1 to each target address A00h in step S2 of FIG. 2, and the RAM 1, 2, 3 read to the collation unit 7 in step S3. Suppose that the stored data of 4 are 5555h, 5555h, 5554h, and 5555h, respectively. In the saved data created in that case, the defective address (ADD [11: 0]) is A00h, the storage data DATA [15: 0] is 5554h, the inspection program number PROG [5: 0] is 01h, and there is a defective bit. The RAM number RAMID [1: 0] determined to be “10” is “10” (binary display).

  As described above, in step S4 of FIG. 2, when it is determined even once that there is a defect in the inspection target address (the test data and the actual storage data are different), the process proceeds to step S13 and the defect is detected. Existence is notified to an external inspection device (not shown). An inspection device (not shown) that knows the existence of a defect sends an address signal to the RAM 1 via an address input terminal and a control signal input terminal (both not shown) provided in the IC 10 and a selector (not shown). Then, a control signal (read signal) is given, and the stored data stored in the stored data storage area 1a is read out via a data output terminal (not shown) provided in the IC 10.

  As described above, in the stored data, it is determined that the test data (or the inspection program number associated with the test data) and the defective address (in step S4 in FIG. 2), the actual stored data is different from the test data. In addition to the data representing the difference between the test data and the stored data composed of the stored data at the address), the inspection device stores the defective address and the RAM number where the defect exists. By simply reading a small amount of stored data stored in the data storage area 1a, the identification of the defective part (analysis of the cause of the defect), that is, the identification of which bit of which address of which RAM is defective is completed. Thereby, the analysis time of the cause of failure (time for specifying the defective portion) is greatly shortened (the “problem 1” which has been a problem in the past is solved).

  In addition, in a conventional IC incorporating a plurality of RAMs, it is necessary to read out the stored data of all the RAMs, and therefore it is necessary to secure a selector corresponding to the number of RAMs and a wiring area corresponding to the number of RAMs. On the other hand, in the IC 10 of FIG. 1, since an external inspection device can specify a defective portion by accessing only the RAM 1, a selector as in the conventional example (switching three buses such as the selector 104 of FIG. 7) is switched. Therefore, it is not necessary to prepare selectors for the number of memories, and it is not necessary to secure wiring areas for the number of RAMs. That is, the circuit scale for failure analysis can be greatly reduced (the above “problem 2” which has been a problem is solved).

  Further, data (6-bit data; INC [5: 0) indicating in which address in the stored data storage area 1a the defective area in the stored data storage area 1a exists from the first word to the third word of the stored data. ]) Is stored. When it is determined in step S11 in FIG. 2 that the inspection target area is defective (Yes in step S11), the external inspection device reads data stored in the saved data storage area 1a. However, by referring to the data INC [5: 0], the inspection device can know at which address in the storage data storage area 1a the storage data is stored.

  FIG. 6 shows an example of the data INC [5: 0] after the operations of FIG. 2 and FIG. In this example, it is determined that the addresses FF2h, FF3h, FF4h, FF5h, and FF9h in the stored data storage area 1a are defective addresses in the operation of FIG. Then, after the operation of inspecting the stored data storage area 1a shown in FIG. 4, it is assumed that there are four defective addresses in any of the RAMs 1 to 4 by the operation shown in FIG.

  In this case, the first saved data A is stored in the addresses FFDh to FFFh of the RAM 1. The addresses FFFh, FFEh, and FFDh correspond to the first word, the second word, and the third word of the stored data A, respectively (see FIG. 5). Similarly, the stored data B, C, and D are stored in the addresses FFAh to FFCh, addresses FF6h to FF8h, and addresses FEFh to FF1h of the RAM 1, respectively, while avoiding defective addresses in the stored data storage area 1a.

  INC [5: 0] of the stored data A is “000000” in binary number display (“0” in decimal number display), and the next stored data B is stored in the lower address side of the stored data A without any gap. It has been shown. INC [5: 0] of the stored data B is “000001” in binary number display (“1” in decimal number display), and the next stored data C is one address on the lower address side of the stored data B. Indicates that the file is saved. INC [5: 0] of the stored data C is “000100” in binary notation (“4” in decimal notation), and the next stored data D has four addresses on the lower address side of the stored data C. Indicates that the file is saved. INC [5: 0] of the stored data D is “000000” in binary number display (“0” in decimal number display), and the stored data to be stored next has a gap at the lower address side of the stored data D. (However, in this example, there is no saved data to be saved next to the saved data D).

  That is, INC [5: 0] functions as a pointer that indicates how many addresses are stored in the storage data to be stored next. By providing such data INC [5: 0] in each saved data, the external shipping inspection device saves the saved data A, B, C and D in any address of the saved data storage area 1a. You can know what is being done.

  Note that error detection data (2-bit data: CRC) is provided in each of the first word, the second word, and the third word of the stored data (see FIG. 5).

<< Other, deformation, etc. >>
In the above-described embodiment, the number of RAMs built in the IC is four, but the present invention can be applied to any number of RAMs. The present invention can be applied even if the number of built-in RAMs is one, but the effect of applying the present invention increases as the number of built-in RAMs increases. When the number of built-in RAMs is one, the RAM number (RAMID [1: 0]; see FIG. 5) indicating which RAM is the RAM that is determined to have a defective bit in the stored data. Is unnecessary.

  Further, since the storage data storage area 1a of the RAM 1 is used to identify defective portions of the RAMs 1 to 4, when the RAMs 1 to 4 are normally used by being incorporated in an electric device, the storage data storage area 1a is basically used. It is not necessary to. Therefore, when the RAMs 1 to 4 are incorporated in an electric device and used normally, the storage data storage area 1a is also an area that is normally read and written.

  However, the RAM 1 may be a non-volatile memory, and the storage data stored in the storage data storage area 1a at the time of inspection may be continuously stored in the storage data storage area 1a even after being incorporated in an electrical device. In this way, a CPU or the like (memory use unit) that reads / writes data from / to the RAMs 1 to 4 refers to the stored data stored in the stored data storage area 1a of the RAM 1, thereby causing defects in the RAMs 1 to 4. It is possible to read and write data while avoiding locations.

  Normally, if there is even one defective portion in the RAMs 1 to 4, the IC 10 cannot be incorporated into an electrical device. However, as described above, the RAM 1 is a non-volatile memory, and the defective portions of the RAMs 1 to 4 are avoided. If data is read and written, the RAMs 1 to 4 operate normally even if there are some defective parts in the RAMs 1 to 4. In other words, this improves the yield when the IC 10 is manufactured.

(Another expression of the present invention)
The present invention can also be expressed as follows.
Memory that can read and write data,
Address for writing the first data, the second data,..., The nth data to the first target address, the second target address,..., The nth target address (n; an integer of 2 or more), respectively. A data generator,
Reading the data actually stored in each of the first target address, the second target address,..., The nth target address by writing by the address / data generation unit from the memory,
When the first storage data is different from the actual storage data of the first target address, the storage data storage area provided in the memory includes storage data including data indicating the difference and data indicating the first target address Save to
When the actual data stored at the second target address is different from the second data, the storage data including the data indicating the difference and the data indicating the second target address is stored in the storage data storage area;・ ・,
When the actual data stored at the nth target address is different from the nth data, the collation result stores the stored data including the data indicating the difference and the data indicating the nth target address in the stored data storage area A storage control unit;
A semiconductor integrated circuit (hereinafter referred to as “another expression 1”).

Furthermore, the present invention can also be expressed as follows.
Multiple memories that can read and write data,
Address for writing first data, second data,..., N-th data to the first target address, second target address,..., N-th target address (n: integer of 2 or more) of each memory, respectively. A data generator,
The data actually stored in each of the first target address, the second target address,..., The nth target address of each memory by writing by the address / data generation unit is read from each memory,
When there is a difference between the actual storage data of the first target address of each memory and the first data, the data indicating the content of the difference and the data indicating which memory is different Storing storage data including data representing the first target address in a storage data storage area provided in any one of the plurality of memories;
When there is a difference between the actual storage data of the second target address of each memory and the second data, the data indicating the difference contents and the data indicating which memory is different Storing storage data including data representing the second target address in the storage data storage area;
When there is a difference between the actual storage data of the nth target address of each memory and the nth data, the data indicating the contents of the difference and the data indicating which memory is different A verification result storage control unit that stores storage data including data representing the nth target address in the storage data storage area;
A semiconductor integrated circuit (hereinafter referred to as “another expression 2”).

  The first data, the second data,..., The nth data in the “other expression 1” and “other expression 2” can take arbitrary values. Accordingly, the first data, the second data,..., The nth data may be different from each other, or a part thereof may be matched. Moreover, all may be in agreement.

  According to the present invention, it is possible to shorten the analysis time of the cause of failure of the memory and reduce the circuit scale for failure cause analysis. Therefore, the present invention is suitable for an SOC (System On a Chip) or the like as a semiconductor integrated circuit (IC) provided with a BIST circuit. Further, if the present invention is applied, cost reduction and miniaturization are realized. Therefore, representative examples of mobile communication devices such as mobile phones and PHS (Personal Handyphone System) and miniaturization and personal computers are desired. The present invention is suitable for various electric devices such as information processing devices. In particular, the effect of the present invention becomes more remarkable as the number of built-in memories increases. Therefore, the present invention is suitable for an image processing IC (used in a digital camera or the like) that often includes a large number of memories. is there.

1 is a configuration block diagram of an IC according to an embodiment of the present invention. 2 is a flowchart for explaining the operation of the IC of FIG. 1. It is a figure which shows allocation of the memory area of RAM of FIG. 2 is a flowchart for explaining the operation of the IC of FIG. 1. FIG. 3 shows the contents of stored data stored in the operation of FIG. 2. FIG. 3 shows the contents of stored data stored in the operation of FIG. 2. It is a block diagram of a conventional IC.

Explanation of symbols

1, 2, 3, 4 RAM
5 Address / Data Generation Unit 6 Verification Result Storage Control Unit 7 Verification Unit 8 Storage Data Generation Unit 31, 32, 33, 34 Selector 10 IC
1a Storage data storage area

Claims (7)

Memory that can read and write data,
An address / data generator for writing predetermined data to a predetermined target address of the memory;
When the data actually stored at the target address is read from the memory by writing by the address / data generation unit, and the actual storage data is different from the predetermined data, the data indicating the difference and the target address A collation result storage control unit that stores storage data including data representing data in a storage data storage area provided in the memory;
A semiconductor integrated circuit comprising: Multiple memories that can read and write data,
An address / data generator for writing predetermined data to a predetermined target address of each memory;
The data actually stored in each target address by writing by the address / data generation unit is read from each memory, and it is determined for each memory whether the actual storage data of each target address is different from the predetermined data, If any of the stored data is different from the predetermined data, the storage includes data indicating the content of the difference, data indicating the memory in which the difference occurs, and data indicating the target address A verification result storage control unit for storing data in a storage data storage area provided in any one of the plurality of memories;
A semiconductor integrated circuit comprising: Before performing the process of storing the stored data in the stored data storage area, it is determined whether or not there is a defective area in the stored data storage area. If there is a defective area, the verification result storage control unit 3. The semiconductor integrated circuit according to claim 1, wherein the storage data is stored while avoiding the above. 4. The semiconductor integrated circuit according to claim 3, wherein the stored data includes information regarding an address where the defective area exists. 5. The data representing the content of the difference includes data associated with the predetermined data or the predetermined data and the storage data. Semiconductor integrated circuit. 6. The semiconductor integrated circuit according to claim 1, wherein the memory in which the storage data storage area is provided is a nonvolatile memory.   An electrical apparatus comprising the semiconductor integrated circuit according to claim 1.

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