JP2006032734A - Ferroelectric memory and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for improving reliability of a ferroelectric memory. <P>SOLUTION: It is possible to restrain generation of troubles such as a seam and a void in a hydrogen protection film and excessive etching of the hydrogen protection film in a projection part when a capacity contact is opened. The necessity of preparation of a special device and the necessity of heat treatment at a high temperature are low. Therefore, generation of a leak path of hydrogen generated in the hydrogen protection film can be effectively restrained, and reduction deterioration can be restrained in a ferroelectric film due to hydrogen atmosphere exposure in post-process. Consequently, hydrogen barrier property of the hydrogen protection film 113 formed in the upper surface of the ferroelectric capacity element 132 for restraining hydrogen from entering the ferroelectric capacity element 132 can be fully shown. Consequently, yield of a ferroelectric memory 100 and data retention property can be improved effectively. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a ferroelectric memory and a method for manufacturing the same.

  In recent years, technological development of memory elements using polarization maintaining characteristics provided in a ferroelectric film has been actively conducted. In order to constitute this ferroelectric memory, it is usually necessary to form an interlayer film, a through hole, a wiring, a passivation and the like after forming the ferroelectric capacitor. However, it is known that the properties of the ferroelectric film are easily changed through these steps, thereby reducing the performance and reliability of the ferroelectric memory. Therefore, there is a demand for a memory element configuration and manufacturing method that minimizes changes in the characteristics of the ferroelectric film due to these steps after formation of the ferroelectric capacitor.

  Factors that cause changes in the characteristics of such ferroelectric films are generally reduction degradation of oxide ferroelectric films due to reducing atmospheres during semiconductor processes and changes in polarization characteristics due to lattice distortion of ferroelectric films caused by stress. Are known.

  An example of a ferroelectric memory device that solves such a problem is described in Patent Document 1.

JP-A-7-111318 JP 7-38003 A JP-A-10-229169 Japanese Patent Laid-Open No. 11-307735

  According to the technique described in Patent Document 1, a hydrogen protective film made of aluminum nitride (AlN) or titanium nitride (TiN) is formed on a ferroelectric capacitor obtained by sequentially laminating a lower electrode, a ferroelectric film, and an upper electrode. Is formed. Here, AlN and TiN have a property that the film density is relatively high and it is difficult for hydrogen to permeate. Therefore, there is an effect of suppressing hydrogen from reaching the ferroelectric film and causing a reduction reaction.

  Further, since AlN and TiN have conductivity, it is not necessary to remove this portion of the hydrogen protective film when opening the capacitor contact. Therefore, it is possible to open the capacitor contact without impairing the shielding effect of the hydrogen protective film.

  However, the prior art described in the above literature has room for improvement in the following points.

  In FIG. 1 of Patent Document 1, all surfaces of the ferroelectric film are described flat. However, in practice, the ferroelectric film is often used in a polycrystalline state, and there are irregularities on the surface. In particular, when the ferroelectric film has a columnar crystal structure, a crystal plane with a slow growth rate appears on the surface to form facets, and acute-angle irregularities occur at the boundary portions of the facets.

  FIG. 12 is a cross-sectional view illustrating a ferroelectric capacitor in consideration of irregularities on the surface of the ferroelectric film. The hydrogen protective film 13 is formed on the uneven upper electrode 11. For the formation of the hydrogen protective film 13, a sputtering method, which is a film forming method that does not release hydrogen, is used. However, it is difficult to uniformly grow on a rough surface by sputtering, and in particular, a seam 14 or a void 15 may be formed in the film of the hydrogen protective film 13 in the concave portion of the upper electrode 11. Here, since the film thickness of the hydrogen protective film 13 is locally thinned at the place where the seam 14 and the void 15 are formed, it is considered that a hydrogen leak path is likely to occur.

  FIG. 13 is a cross-sectional view showing a state in which the capacitor cover film 16 is formed on the ferroelectric capacitor and the capacitor contact 17 is opened. In order to ensure conduction between the upper electrode 11 and the hydrogen protective film 13, it is necessary to perform etching when opening the capacitor contact 17 until the concave portion of the hydrogen protective film 13 is exposed. Therefore, the etching time is excessive at the convex portion, and the hydrogen protective film 13 is locally thinned. In other locations, the surface of the hydrogen protective film 13 is etched when the capacitor contact 17 is opened, so that the opening of the seam 14 existing in the hydrogen protective film 13 is expanded or the void 15 is formed. It is considered that by exposing to the surface, the thickness of the hydrogen protective film 13 in each portion is further reduced, and hydrogen is more easily transmitted.

  As described above, in the conventional technique, the hydrogen protective film 13 is formed on the uneven upper electrode 11, so that a local hydrogen leak path is easily generated in the hydrogen protective film 13, and the There is room for improvement in that the ferroelectric film 10 is reduced by the hydrogen that has entered.

  Here, when the surface density of the hydrogen leak path existing in the hydrogen protective film 13 increases, the ratio of the ferroelectric capacitance containing this leak path increases, leading to a decrease in yield. Therefore, it is necessary to reduce the surface density of such a leak path.

  As one example of a method for solving the above-described problem, flattening of the surface of the ferroelectric film is considered, suppressing leakage current due to electric field concentration in the concave portion of the ferroelectric film, There is a technique for the purpose of suppressing variations in polarization characteristics due to microscopic film thickness variations. Among such conventional techniques, techniques aiming at flattening without impairing the polarization characteristics of the ferroelectric film include the techniques described in Patent Documents 2 to 4. However, all have room for improvement in that there are restrictions such as the necessity of heat treatment at a high temperature of 650 ° C. or higher or the need to prepare a device having a special mechanism for flattening. It was.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a technique for improving the reliability of a ferroelectric memory.

  According to the present invention, a semiconductor substrate, a ferroelectric capacitor provided on the semiconductor substrate, in which a lower electrode, a ferroelectric film, an upper electrode, and a hydrogen protective film are stacked in this order; There is provided a ferroelectric memory characterized in that the flatness of the surface of the upper electrode on the side in contact with the hydrogen protective film is larger than the flatness of the surface of the ferroelectric film on the side in contact with the upper electrode. .

  According to the present invention, the flatness of the surface of the upper electrode in contact with the hydrogen protective film is larger than the flatness of the surface of the ferroelectric film on the side in contact with the upper electrode. It is possible to improve the hydrogen barrier property of the hydrogen protective film formed for the purpose of suppressing the intrusion of. Therefore, the yield and characteristics of the ferroelectric memory can be improved. As a result, the reliability of the ferroelectric memory can be improved.

  According to the present invention, a step of preparing a semiconductor substrate, a step of forming a lower electrode on the semiconductor substrate, a step of forming a ferroelectric film on the lower electrode, and an upper electrode on the ferroelectric film And a step of forming a film on the upper electrode, and a step of forming a hydrogen protective film on the film, wherein the film embeds at least a part of the upper electrode. A manufacturing method is provided.

  According to the present invention, since the film embeds at least a part of the upper electrode, the upper surface of the upper electrode becomes flatter than the upper surface of the ferroelectric film, and the purpose is to suppress the intrusion of hydrogen into the ferroelectric capacitor. The hydrogen barrier property of the hydrogen protective film formed as can be improved. Therefore, the yield and characteristics of the ferroelectric memory can be improved efficiently. As a result, the reliability of the ferroelectric memory can be improved efficiently.

  According to the present invention, a step of preparing a semiconductor substrate, a step of forming a lower electrode on the semiconductor substrate, a step of forming a ferroelectric film on the lower electrode, and an upper electrode on the ferroelectric film And a step of flattening the upper electrode, and a step of forming a hydrogen protective film on the flattened upper electrode in the above step. The

  According to the present invention, since the upper electrode is flattened and the hydrogen protective film is formed on the flattened upper electrode, the upper surface of the upper electrode becomes flatter than the upper surface of the ferroelectric film. The hydrogen barrier property of the hydrogen protective film formed for the purpose of suppressing the intrusion of hydrogen can be improved. Therefore, the yield and characteristics of the ferroelectric memory can be improved efficiently. As a result, the reliability of the ferroelectric memory can be improved efficiently.

  According to the present invention, a technique for improving the reliability of a ferroelectric memory is provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

First Embodiment FIG. 1 is a sectional view of a memory cell portion of a ferroelectric memory 100 according to this embodiment. The memory cell is provided on a semiconductor substrate 101, a memory cell transistor 130 provided on the semiconductor substrate 101, including a diffusion layer 102 and a gate electrode 103, and an interlayer insulating film 107 formed of SiO ₂ or the like. a first metal wiring 105, the ferroelectric capacitive element 132 is a ferroelectric capacitor provided in the formed capacitor cover film 116 due to SiO _2, ferroelectric SiO ₂ provided on the capacitive element 132 And a second metal wiring 118 in the passivation film 119 made of Si ₃ N ₄ or the like. The diffusion layer 102 and the first metal wiring 105 are connected via the first plug 104, and the first metal wiring 105 and the ferroelectric capacitor element 132 are connected via the second plug 106, and the ferroelectric capacitor element 132 and the second metal wiring 118 are connected via a capacitor contact 117.

  FIG. 2 is an enlarged cross-sectional view of a portion of the ferroelectric capacitor element 132 of FIG. The ferroelectric capacitor 132 is electrically connected to the plug 106 in the interlayer insulating film 107 from below, and has a conductive lower barrier film 108, lower electrode 109, ferroelectric film 110, upper electrode 111, film. The second upper electrode 112 and the hydrogen protective film 113 are stacked in this order. Here, the second upper electrode 112 is formed so as to embed a part of the surface of the upper electrode 111, and is formed so as to bury mainly the bottom of the concave portion provided on the upper surface of the upper electrode 111. The surface of the film composed of the upper electrode 111 and the second upper electrode 112 has a greater flatness than the surface of the ferroelectric film 110.

  Here, the flatness flatness (v) is an index representing the degree of flatness of v from the distribution of the positions of points around v with respect to the point v, and can be defined as the following equation.

  flatness (v) = N (v) (1)

  Here, N (v) is a function (area, normal vector, number of points, etc.) representing the features of the plane.

  Further, the surface of the film composed of the upper electrode 111 and the second upper electrode 112 has a flatness greater than at least the surface of the ferroelectric film 110. May be defined as being larger than the average aspect ratio of the recesses present on the surface of the ferroelectric film 110. Here, the concave portion is, for example, a portion including a minimum value when the surface shape of the upper electrode 111 is formulated, an inflection point from the concave function to the convex function, and an inflection point from the convex function to the concave function. The average aspect ratio of the recess means the ratio of the horizontal length and the vertical length of the recess. Moreover, the bottom part of a recessed part means the vicinity of the part containing minimum value.

  Furthermore, the surface of the film composed of the upper electrode 111 and the second upper electrode 112 has a flatness greater than at least the surface of the ferroelectric film 110. May be defined as being smaller than the surface density of the recesses present on the surface of the ferroelectric film 110. Here, the surface density of the recesses is, for example, the number of recesses present on the surface of the upper electrode 111 divided by the surface area of the upper electrode 111.

  Furthermore, the fact that the surface of the film composed of the upper electrode 111 and the second upper electrode 112 has a flatness greater than at least the surface of the ferroelectric film 110 exists on the surface of the upper electrode 111. The average height of the convex portions may be defined as being smaller than the average height of the convex portions existing on the surface of the ferroelectric film 110. Here, for example, when the surface shape of the upper electrode 111 is mathematically expressed, the convex portion is a portion including the maximum value, an inflection point from the concave function to the convex function, and a change from the convex function to the concave function. The average height of the convex portion means, for example, the average height of the convex portions existing on the surface of the upper electrode 111.

  The lower barrier film 108 is composed of a laminated film of Ti and TiN, and has a function of suppressing the components constituting the lower electrode 109 from diffusing into the interlayer insulating film 107 when the lower electrode 109 is formed.

The lower electrode 109 is made of, for example, Ru, and the ferroelectric film 110 is made of a film having a polarization maintaining characteristic such as, for example, PZT (PbZr _x Ti _1-x O ₃ ). For example, it is made of Ru or the like.

  Since the ferroelectric film 110 is formed of a film having polarization maintaining characteristics, the ferroelectric memory 100 can be a nonvolatile memory element.

  The second upper electrode 112 is made of, for example, a conductive material such as TiN, AlN, etc., in order to make the upper surface of the upper electrode 111 flatter than the upper surface of the ferroelectric film 110. Provided. Here, when Ru is used as the material constituting the upper electrode 111, Ru is easily etched by using oxygen radicals, except for the platinum group element used as the electrode of the ferroelectric capacitor 132. However, in this case, since the etching proceeds isotropically, it is not easy to planarize the upper electrode 111 with good controllability. Therefore, it is preferable to use a material that can be processed more easily than the upper electrode 111 as the material constituting the second upper electrode 112 that is used for the purpose of planarization with good controllability. And Al are particularly preferably used because they easily react with Cl radicals to produce a product having a relatively high vapor pressure.

  As a material constituting the hydrogen protective film 113, a material having a high film density, not easily permeating hydrogen, chemically stable, and having conductivity, for example, TiN or AlN is used. . Further, as described above, as a material constituting the second upper electrode 112, a material having conductivity and a hydrogen barrier property may be used. Therefore, the second upper electrode 112 and the hydrogen protective film 113 may be made of the same material.

  Hereinafter, an example of a method for manufacturing the ferroelectric memory 100 according to the present embodiment will be described with reference to FIG.

  Through a normal semiconductor integrated circuit manufacturing process, a memory cell transistor 130, a first plug 104, and a first metal wiring 105, which are MOS transistors including a diffusion layer 102 and a gate electrode 103, are formed on a semiconductor substrate 101. On the first metal wiring 105, the second plug 106 is formed so as to reach the surface of the interlayer insulating film 107 (FIG. 3A). Subsequently, a ferroelectric capacitor element 132 is formed on the second plug 106 (FIG. 3B).

  A method for forming the ferroelectric capacitor 132 will be described in detail with reference to FIG. 5 which is a process cross-sectional view showing a method for manufacturing the ferroelectric capacitor 132.

As shown in FIG. 5A, on the interlayer insulating film 107, a lower barrier film 108 made of a laminated film of Ti and TiN, for example, a lower electrode 109 made of Ru or the like, PZT (Pb (Zr, Ti) O ₃ ) Etc., a ferroelectric film 110 made of Ru, etc., an upper electrode 111 made of Ru, etc., and a second upper electrode 112 made of TiN, etc. are formed in this order from the bottom using a sputtering method or the like.

Next, using a dry etching method or the like, the second upper electrode 112 is etched back with a gas not containing hydrogen atoms such as BCl ₃ and Cl ₂ (FIG. 5B). At the time of etch back, the etching amount of the second upper electrode 112 is adjusted so that a part of the upper electrode 111 is exposed on the surface. Next, a hydrogen protective film 113 made of, for example, TiN is formed on the second upper electrode 112 (FIG. 5C).

  Subsequently, the ferroelectric protective element 132 is formed by etching the hydrogen protective film 113, which is a laminated film formed by the above process, using a known technique (FIG. 5D).

The process after forming the ferroelectric capacitor 132 will be described with reference to FIG. 4 again. After a film such as a SiO ₂ film is deposited on the ferroelectric capacitor element 132, the capacitor cover film 116 is formed by planarizing the film. Further, a W plug is formed as a capacitor contact 117 on the ferroelectric capacitor 132 using a known technique (FIG. 4A).

  Next, a second metal wiring 118 and a passivation film 119 are formed on the capacitor cover film 116 and the capacitor contact 117, thereby completing the ferroelectric memory 100 (FIG. 4B).

  Hereinafter, effects of the ferroelectric memory 100 according to the present embodiment will be described.

  In the above-described conventional technique, the hydrogen protective film 13 is formed on the uneven upper electrode 11, so that a local hydrogen leak path is likely to occur in the hydrogen protective film 13, and the hydrogen protective film 13 has entered through the leak path. There was room for improvement in that the ferroelectric film 10 was reduced by hydrogen. Further, as a technique for suppressing the reduction of the ferroelectric film 10 and suppressing the generation of a hydrogen leak path, flattening of the upper surface of the ferroelectric film 10 can be cited, but it is necessary to prepare a special apparatus or perform heat treatment at a high temperature. There was room for improvement in terms of need. On the other hand, in the ferroelectric memory 100, the second upper electrode 112 formed on the upper electrode 111 etches back the second upper electrode 112, and the upper electrode 111 and the second upper electrode 112. It is formed for the purpose of obtaining the flatness of the surface constituted by. That is, since a chemically stable platinum group element is often used as a material constituting the upper electrode 111, the upper electrode 111 is difficult to process, and it is not easy to planarize the upper electrode 111 by etch back. Because there is no. The hydrogen protective film 113 is formed on a flattened surface constituted by the upper electrode 111 and the second upper electrode 112. Therefore, it is possible to suppress the occurrence of problems such as seams and voids in the hydrogen protective film, which is a room for improvement in the above-described prior art, and excessive etching of the convex hydrogen protective film when the capacitor contact 117 is opened. can do. In addition, it is less necessary to prepare a special apparatus or to perform heat treatment at a high temperature. Therefore, generation of a hydrogen leak path in the hydrogen protective film is effectively suppressed, and reduction degradation of the ferroelectric film 110 due to exposure to a hydrogen atmosphere in a subsequent process can be suppressed. Therefore, the hydrogen barrier property of the hydrogen protective film 113 formed on the ferroelectric capacitor element 132 can be sufficiently exerted for the purpose of suppressing the permeation of hydrogen into the ferroelectric capacitor element 132. As a result, the yield and data retention characteristics of the ferroelectric memory 100 can be improved efficiently.

  Further, since the second upper electrode 112 which is a film embeds the recess of the upper electrode 111, the recess of the upper electrode 111 is embedded by the second upper electrode 112, so that the upper electrode 111 and the second upper electrode 112 are configured. The flatness of the surface to be obtained can be further obtained. Therefore, excessive etching of the convex hydrogen protective film when opening the capacitor contact can be further suppressed. Therefore, the generation of a hydrogen leak path that has occurred in the hydrogen protective film is more efficiently suppressed, and reduction degradation of the ferroelectric film due to exposure to a hydrogen atmosphere in the subsequent process can be further suppressed. As a result, the hydrogen barrier property of the hydrogen protective film 113 formed on the ferroelectric capacitor element 132 can be further exerted for the purpose of suppressing entry of hydrogen into the ferroelectric capacitor element 132.

  Further, the optimum value of the etch back amount of the second upper electrode 112 is considered to largely depend on the shape of the irregularities on the upper surface of the ferroelectric film 110, the shape of the upper electrode 111, the shape of the second upper electrode 112, and the like. . Therefore, it is considered that a flatter surface can be obtained by setting the etching amount within a range in which a part of the upper surface of the upper electrode 111 is exposed.

Second Embodiment FIG. 6 shows a cross-sectional view of a ferroelectric capacitor element 132 of a ferroelectric memory 100 according to this embodiment. In the present embodiment, the definition that the flatness and the flatness are large is the same as that described in the first embodiment.

  In the first embodiment, as shown in FIG. 2, the second upper electrode 112 covers and embeds only a part of the upper electrode 111, whereas in the present embodiment, the second upper electrode The second embodiment is different from the first embodiment in that almost the entire surface 112 is covered.

  FIG. 7 is a process cross-sectional view illustrating a method of manufacturing a portion of the ferroelectric capacitor 132 that is a component of the ferroelectric memory 100 according to the present embodiment. The manufacturing process other than the ferroelectric capacitor 132 is the same as the manufacturing method described in the first embodiment.

  In the first embodiment, as shown in FIG. 5B, the etching amount when etching back the second upper electrode 112 is set so that a part of the upper electrode 111 is exposed on the surface. It was. On the other hand, in this embodiment, as shown in FIG. 7B, the etching amount for etching back the second upper electrode 112 is set by shortening the etching time, for example, and the upper electrode 111 The entire upper surface of the upper electrode 111 is covered with the second upper electrode 112 without being exposed.

  Here, the optimum value of the etching amount of the second upper electrode 112 is considered to largely depend on the uneven shape of the upper surface of the ferroelectric film 110, the covering shape of the upper electrode 111, the covering shape of the second upper electrode 112, and the like. Therefore, depending on the shape and state of the ferroelectric film 110, the upper electrode 111, and the second upper electrode 112, the entire upper surface of the upper electrode 112 is covered with the second upper electrode 112, whereby the upper electrode 111 and the second upper electrode are covered. The surface constituted by 112 can be further flattened. In this case, since the etch back film thickness may be set in a range where the upper electrode 111 is not exposed, the allowable range of the etch back film thickness is widened. Thereby, in the etch back process, the probability that the variation in the etch back film thickness falls within the allowable range is improved. Therefore, higher reproducibility of the etch back process can be obtained.

Third Embodiment FIG. 8 is a sectional view of a portion of a ferroelectric capacitor element 132 of a ferroelectric memory 100 according to this embodiment. The constituent elements of the ferroelectric capacitor 132 are the same as those in the first embodiment. The present embodiment is different from the first embodiment in that the second upper electrode 112 is not formed. In this embodiment, the definition of the flatness and the flatness being large is the same as that described in the first embodiment.

  The ferroelectric capacitive element 132 according to the present embodiment is configured by laminating a lower barrier film 108, a lower electrode 109, a ferroelectric film 110, an upper electrode 111, and a hydrogen protective film 113 in order from the bottom. The upper electrode 111 covers almost the entire upper surface of the ferroelectric film 110, and the upper surface of the upper electrode 111 is at least flatter than the upper surface of the ferroelectric film 110.

  FIG. 9 is a process cross-sectional view illustrating an example of a method of manufacturing a portion of the ferroelectric capacitor 132 that is a component of the ferroelectric memory 100 in the present embodiment. The manufacturing method other than the ferroelectric capacitor 132 is the same as that of the first embodiment.

As shown in FIG. 9A, a lower barrier film 108 made of TiN or the like, a lower electrode 109 made of Ru, or the like, PZT (PbZr _x Ti _1-x O ₃ ) on the interlayer insulating film 107 from below. A ferroelectric film 110 made of etc. and an upper electrode 111 made of Ru etc. are laminated in this order. Next, the upper electrode 111 is etched by a dry etching method or the like (FIG. 9B). The etching time of the upper electrode 111 is set in a range where the upper surface of the ferroelectric film 110 is not exposed.

  Here, since the convex portion on the surface of the upper electrode 111 is more likely to collide with the etching gas than the concave portion, the convex portion is preferentially etched, and the flatness of the surface is improved.

  Next, a hydrogen protective film 113 made of TiN is formed on the planarized upper electrode 111 (FIG. 9C). Subsequently, the ferroelectric protective element 132 is obtained by etching the hydrogen protective film 113, which is a laminated film, using a known technique (FIG. 9D).

  The etching time and etching conditions of the upper electrode 111 are in a range where the upper surface of the ferroelectric film 110 is not exposed, and the convexity of the upper surface of the upper electrode 111 is etched, so that the flatness of the upper surface of the upper electrode 111 is improved. By setting the range, the upper electrode 111 can be planarized without forming the second upper electrode. Therefore, the manufacturing process for forming the second upper electrode can be reduced. Therefore, the surface density of the hydrogen leak path can be reduced efficiently, and the yield and data retention characteristics of the ferroelectric memory 100 can be improved efficiently.

Fourth Embodiment FIG. 10 is a sectional view of a portion of a ferroelectric capacitor element 132 of a ferroelectric memory 100 according to this embodiment. In the ferroelectric capacitor 132 according to the present embodiment, a lower barrier film 108, a lower electrode 109, a ferroelectric film 110, an upper electrode 111, and a hydrogen protective film 113 are laminated in this order from the bottom. The upper electrode 111 covers the upper surface of the ferroelectric film 110, and the upper surface is flatter than at least the upper surface of the ferroelectric film 110. Here, the upper electrode 111 may be a laminated film or a single layer film. In the present embodiment, the definition of the flatness and the flatness being large is the same as that described in the first embodiment.

  FIG. 11 is a process sectional view showing an example of a manufacturing process of a portion of the ferroelectric capacitor 132 which is a component of the ferroelectric memory 100 in the present embodiment. The manufacturing process other than the portion of the ferroelectric capacitor 132 is the same as that of the first embodiment.

As shown in FIG. 11A, a lower barrier film 108 made of TiN or the like, a lower electrode 109 made of Ru, etc., PZT (PbZr _x Ti _1-x O ₃ ) or the like is formed on the interlayer insulating film 107. The ferroelectric film 110 and the upper electrode 111 made of Ru or the like are formed in this order from the bottom. Next, the upper surface of the upper electrode 111 is planarized using a chemical mechanical polishing (CMP) technique (FIG. 11B). Next, a hydrogen protective film 113 made of TiN or the like is formed on the planarized upper electrode 111 (FIG. 11C). Subsequently, the ferroelectric protective element 132 is obtained by etching the hydrogen protective film 113 using a known technique (FIG. 11D).

  In the present embodiment, a flat upper surface of the upper electrode 111 can be obtained by using a CMP technique for planarizing the upper electrode 111. Therefore, the microscopic film thickness uniformity of the hydrogen protective film 113 formed on the upper electrode 111 is further improved, and the hydrogen leak path is further reduced. Accordingly, the hydrogen barrier property of the hydrogen protective film 113 formed on the upper surface of the ferroelectric capacitor element 132 can be exhibited for the purpose of preventing hydrogen from entering the ferroelectric capacitor element 132. As a result, the yield and data retention characteristics of the ferroelectric memory 100 can be improved.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

  For example, in the above-described embodiment, the form using a conductive material such as AlN or TiN as the material constituting the hydrogen protective film 113 has been described. However, the material has a property that hardly permeates hydrogen, Any material that can open the capacitor contact 117 without impairing the shielding effect of the hydrogen protective film 113 may be used.

  In the above-described embodiment, the form using TiN, AlN, or the like as the material constituting the second upper electrode 112 has been described. However, it is a material that can be processed more easily than the upper electrode 111 and can be planarized with good controllability. Any material can be used.

  In the third and fourth embodiments, the etching or CMP process is used as the planarization method. However, any other method can be used as long as the upper electrode 111 can be planarized. Good.

1 is a cross-sectional view schematically showing a memory cell portion of a ferroelectric memory according to an embodiment. 1 is a cross-sectional view schematically showing a ferroelectric capacitor portion of a ferroelectric memory according to an embodiment. It is process sectional drawing which showed typically the manufacturing process of the ferroelectric memory which concerns on embodiment. It is process sectional drawing which showed typically the manufacturing process of the ferroelectric memory which concerns on embodiment. It is process sectional drawing which showed typically the manufacturing process of the ferroelectric capacitor which comprises the ferroelectric memory which concerns on embodiment. 1 is a cross-sectional view schematically showing a ferroelectric capacitor portion of a ferroelectric memory according to an embodiment. It is process sectional drawing which shows typically the manufacturing process of the ferroelectric capacitor which comprises the ferroelectric memory which concerns on embodiment. 1 is a cross-sectional view schematically showing a ferroelectric capacitor portion of a ferroelectric memory according to an embodiment. It is process sectional drawing which showed typically the manufacturing process of the ferroelectric capacitor which comprises the ferroelectric memory which comprises the ferroelectric memory which concerns on embodiment. 1 is a cross-sectional view schematically showing a ferroelectric capacitor portion of a ferroelectric memory according to an embodiment. 1 is a cross-sectional view schematically showing a ferroelectric capacitor portion of a ferroelectric memory according to an embodiment. It is sectional drawing which showed typically the ferroelectric capacitor which concerns on a prior art. It is sectional drawing which showed typically the state which opened the capacity | capacitance contact of the ferroelectric capacitor based on a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Ferroelectric memory 101 Semiconductor substrate 102 Diffusion layer 103 Gate electrode 104 Plug 105 Metal wiring 106 Plug 107 Interlayer insulating film 108 Lower barrier film 109 Lower electrode 110 Ferroelectric film 111 Upper electrode 112 Second upper electrode 113 Hydrogen protective film 116 Capacitor cover film 117 Capacitor contact 118 Metal wiring 119 Passivation film 130 Memory cell transistor 132 Ferroelectric capacitor

Claims (9)

A semiconductor substrate;
A ferroelectric capacitor provided on the semiconductor substrate, in which a lower electrode, a ferroelectric film, an upper electrode, and a hydrogen protective film are stacked in this order;
With
A ferroelectric memory characterized in that the flatness of the surface of the upper electrode in contact with the hydrogen protective film is larger than the flatness of the surface of the ferroelectric film on the side in contact with the upper electrode. The ferroelectric memory according to claim 1, wherein
A film is provided between the upper electrode and the hydrogen protective film,
A ferroelectric memory characterized in that at least a part of the upper surface of the upper electrode is buried with the film. The ferroelectric memory according to claim 2, wherein
2. A ferroelectric memory according to claim 1, wherein a bottom portion of a concave portion provided on the upper surface of the upper electrode is filled with the film. The ferroelectric memory according to claim 2 or 3,
A ferroelectric memory characterized in that the entire upper surface of the upper electrode is covered with the film. The ferroelectric memory according to any one of claims 1 to 4,
A ferroelectric memory characterized in that the upper electrode is flattened. The ferroelectric memory according to claim 5, wherein
A ferroelectric memory, wherein the upper electrode is planarized using a CMP method. The ferroelectric memory according to claim 5, wherein
A ferroelectric memory, wherein the upper electrode is planarized by etching. Preparing a semiconductor substrate; and
Forming a lower electrode on the semiconductor substrate;
Forming a ferroelectric film on the lower electrode;
Forming an upper electrode on the ferroelectric film;
Forming a film on the upper electrode;
Forming a hydrogen protective film on the film;
Including
A method of manufacturing a ferroelectric memory, wherein the film embeds at least a part of the upper electrode. Preparing a semiconductor substrate; and
Forming a lower electrode on the semiconductor substrate;
Forming a ferroelectric film on the lower electrode;
Forming an upper electrode on the ferroelectric film;
Planarizing the upper electrode;
Forming a hydrogen protective film on the upper electrode planarized in the step;
A method for manufacturing a ferroelectric memory, comprising:

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