JP2006031542A - Net list production device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate extraction of a parasitic RC, and to improve analysis accuracy of circuit simulation. <P>SOLUTION: The parasitic RC of a wiring line is extracted from layout data Z applied with an abstract showing a ground wiring and a power supply line inside a block of a top hierarchy, an extraction result thereof is applied to a net list C, coordinate information of a node of the parasitic RC on the layout data is specified, coordinate information of a terminal of a circuit element stored in a coordinate file F1 on the layout data and the coordinate information of the node of the parasitic RC on the layout data are compared, and connection relation of the parasitic RC and the circuit element in a net list E applied with the extraction result of the parasitic RC is made to be proper. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a net list creation device for creating a net list used when a circuit simulation is performed in consideration of parasitic resistance of power supply wiring and ground wiring.

A conventional netlist creation device extracts parasitic RC (parasitic resistance, parasitic capacitance) of wiring from layout data of the entire LSI that is hierarchically designed when performing circuit simulation considering parasitic resistance of power supply wiring and ground wiring. To do.
For this reason, it takes a lot of time to extract the parasitic RC, and if a net list of the entire LSI is created from the extraction result of the parasitic RC, the number of nodes and elements in the net list becomes enormous, and the practical time In some cases, circuit simulation cannot be performed within the network (for example, see Patent Document 1).

Therefore, if the method of extracting only the parasitic RC between a plurality of blocks is handled by treating the inside of the top layer block in the layout data of the entire LSI as a black box, a node in the net list obtained from the extraction result of the parasitic RC is used. Since the number and the number of elements are reduced, circuit simulation can be performed within a practical time.
However, when this method is used, since the parasitic RC of the power supply wiring and ground wiring inside the block is not extracted, the analysis accuracy of the circuit simulation may deteriorate.

In order to solve the problem of the above method, after extracting the parasitic resistance of the power wiring and ground wiring of the top hierarchy, if the method of extracting the parasitic resistance of the power wiring and ground wiring of the lower hierarchy sequentially is used, Analysis accuracy of circuit simulation can be increased.
However, when this method is used, the user needs to input a net name indicating the power supply wiring and ground wiring of each layer. Therefore, when the scale of the LSI increases, it takes a long time for input work, which is realistic. Not a way.

JP-A-10-283391 (paragraph number [0003], FIG. 8)

  Since the conventional netlist creation apparatus is configured as described above, if the inside of the top layer block in the layout data of the entire LSI is made a black box, only the parasitic RC between a plurality of blocks is extracted. Circuit simulation can be carried out within a practical time. However, since the parasitic RC of the power supply wiring and ground wiring inside the block is not extracted, there is a problem that the analysis accuracy of the circuit simulation may be deteriorated.

  The present invention has been made in order to solve the above-described problems. It is an object of the present invention to obtain a netlist creation device that can facilitate the extraction of parasitic RC and can improve the analysis accuracy of circuit simulation. Objective.

  The net list creation device according to the present invention extracts the parasitic resistance of the wiring from the layout data to which the abstract showing the power supply wiring and the ground wiring in the block of the top hierarchy is applied, and the extraction result is created by the data creation means In addition to applying to the net list, parasitic resistance application means for specifying the coordinate information on the layout data of the node of the parasitic resistance is provided, and the coordinate information on the layout data of the terminal of the circuit element specified by the coordinate information specifying means and the parasitic The coordinate information on the layout data of the parasitic resistance node specified by the resistance applying means is compared, and the connection relation between the circuit element and the parasitic resistance in the net list to which the extraction result of the parasitic resistance is applied is optimized. It is a thing.

  According to the present invention, the parasitic resistance of the wiring is extracted from the layout data to which the abstract indicating the power supply wiring and the ground wiring in the block of the top hierarchy is applied, and the extraction result is applied to the net list created by the data creation means. In addition, parasitic resistance application means for specifying the coordinate information on the layout data of the node of the parasitic resistance is provided, and the coordinate information on the layout data of the terminal of the circuit element specified by the coordinate information specification means and the parasitic resistance application means Since the coordinate information on the layout data of the specified parasitic resistance node is compared and the connection result between the circuit element and the parasitic resistance in the netlist to which the extraction result of the parasitic resistance is applied is configured, This makes it easy to extract parasitic resistance and improves the analysis accuracy of circuit simulation. There is an effect that can be Mel.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a net list creating apparatus according to Embodiment 1 of the present invention. In FIG. 1, a net list creating unit 1 creates a net list A from circuit diagram data of an LSI to be verified. The netlist creation unit 2 refers to the EXTRACT technology file in which element information and connection information extraction rules are described, and extracts circuit element element information and connection information from the layout data X corresponding to the circuit diagram data. Then, a netlist B is created based on the element information and connection information.

The coordinate file creation unit 3 refers to the COMPARE technology file in which the comparison conditions of the net list are described, and the net list A created by the net list creation unit 1 and the net list B created by the net list creation unit 2 are In comparison, the coordinate information on the layout data of the terminals of the circuit elements connected to the power supply wiring or the ground wiring is specified, and the coordinate information is stored in the coordinate file F1.
The net list creation unit 1, the net list creation unit 2, and the coordinate file creation unit 3 constitute coordinate information specifying means.

The black boxing unit 4 creates layout data Y by converting the top layer block in the layout data X into a black box. The net list creation unit 5 refers to the EXTRACT technology file, extracts the circuit element element information and connection information from the layout data Y created by the black boxing unit 4, and the net list based on the element information and connection information. Create C.
The black boxing unit 4 and the net list creation unit 5 constitute data creation means.

The net name input unit 6 accepts the input of the net name of the power wiring and ground wiring of the top layer and stores the net name in the net name file.
Based on the pin information connected to the power supply wiring and the ground wiring indicated by the net name stored in the net name file, the abstract creating unit 7 determines the power supply wiring and ground wiring (in the top layer block) from the layout data X and Y. Create an abstract showing contact / through-holes).
The abstract application unit 8 replaces the top layer block in the layout data Y with the abstract created by the abstract creation unit 7 and outputs the layout data Z which is the layout data after the replacement.
The net name input unit 6, the abstract creation unit 7, and the abstract application unit 8 constitute an abstract application unit.

The parasitic RC extraction unit 9 refers to the wiring parasitic RC extraction technology file in which the extraction rules of the parasitic RC (parasitic resistance, parasitic capacitance) are described, and the parasitic RC of the wiring from the layout data Z output from the abstract application unit 8. To extract.
The parasitic RC application unit 10 applies the parasitic RC extracted by the parasitic RC extraction unit 9 to the netlist C and outputs a netlist D.
The coordinate file creation unit 11 specifies coordinate information on the layout data of the parasitic RC node extracted by the parasitic RC extraction unit 9, and stores the coordinate information in the coordinate file F2.
The parasitic RC extraction unit 9, the parasitic RC application unit 10, and the coordinate file creation unit 11 constitute a parasitic resistance application unit.

The netlist application unit 12 applies the corresponding part in the netlist A to each block that remains in the black box in the netlist D output from the parasitic RC application unit 10, and the wiring parasitic RC A netlist E is created.
The connection relation optimizing unit 13 compares the coordinate information of the terminal of the circuit element stored in the coordinate file F1 with the coordinate information of the node of the parasitic RC stored in the coordinate file F2, and the wiring parasitic RC inclusion net The connection relationship between the circuit element and the parasitic resistance in the list E is optimized, and the optimized netlist is output as a circuit simulation netlist.
The netlist application unit 12 and the connection relation optimization unit 13 constitute optimization means.

The simulation execution unit 14 uses the circuit simulation netlist output from the connection relation optimization unit 13 of the netlist creation device to perform circuit simulation in consideration of parasitic resistance of power supply wiring and ground wiring.
2 and 3 are flowcharts showing the processing contents of the net list creation device according to the first embodiment of the present invention.

Next, the operation will be described.
First, when the netlist creation unit 1 inputs circuit diagram data of an LSI to be verified (for example, data indicating a circuit diagram of an LSI configured using circuit elements such as transistors, resistors, and capacitors), A netlist A is created from the circuit diagram data (step ST1). The creation process for creating the netlist A from the circuit diagram data will not be described because an existing technique may be employed.
The netlist A is data in which circuit element connection relationships and the like are described as character data.

When the netlist creation unit 2 receives the layout data X corresponding to the circuit diagram data, the netlist creation unit 2 refers to the EXTRACT technology file in which element information and connection information extraction rules are described, and from the layout data X Element information and connection information of circuit elements are extracted, and a netlist B is created based on the element information and connection information (step ST2).
The netlist B is data in which circuit element connection relationships and the like are described in character data.

The coordinate file creation unit 3 executes LVS (Layout Versus Schematic) of the netlist A created by the netlist creation unit 1 and the netlist B created by the netlist creation unit 2.
That is, referring to the COMPARE technology file in which the comparison conditions of the netlist are described, the netlist A and the netlist B are compared, and the layout data of the terminals of the circuit elements connected to the power supply wiring or the ground wiring Is specified (step ST3).
Then, the coordinate file creation unit 3 stores the coordinate information on the layout data of the terminals of the circuit elements in the coordinate file F1.

When the layout data X corresponding to the circuit diagram data is input, the black boxing unit 4 converts the top layer block in the layout data X into a black box and creates layout data Y (step ST4).
Here, FIG. 14 is an image diagram showing a layout in which the blocks in the top layer are made black boxes.
In the example of FIG. 14, there are five blocks in the top hierarchy, and the inside of these blocks is black boxed.

  When the black boxing unit 4 creates the layout data Y, the netlist creation unit 5 refers to the EXTRACT technology file and extracts the element information and connection information of the circuit elements from the layout data Y, and the element information and connection A netlist C is created based on the information (step ST5).

  When the user designates the net name of the power wiring or ground wiring in the top hierarchy, the net name input unit 6 accepts the input of the net name and stores the net name in the net name file (step ST6).

When the net name input unit 6 stores the net name in the net name file, the abstract creating unit 7 specifies a power supply wiring and a ground wiring having the net name.
Then, as shown in FIG. 15, the abstract creating unit 7 extracts pin information connected to the power supply wiring and the ground wiring from the layout data X and Y, and based on the pin information, the power supply wiring in the top layer block By tracking the ground wiring and the ground wiring, the power wiring and the ground wiring pattern (including the contact / through hole) in the block are extracted from the layout data X, and an abstract indicating the power wiring and the ground wiring pattern is created (step ST7). ).

  When the abstract creation unit 7 creates the abstract, the abstract application unit 8 replaces the top layer block in the layout data Y with the abstract created by the abstract creation unit 7 as shown in FIG. The layout data Z, which is data, is output (step ST8).

When the parasitic RC extraction unit 9 receives the layout data Z from the abstract application unit 8, the parasitic RC extraction unit 9 refers to the wiring parasitic RC extraction technology file in which the extraction rules of the parasitic RC are described, and calculates the parasitic RC of the wiring from the layout data Z. Extract (step ST9).
The parasitic RC extracted by the parasitic RC extraction unit 9 includes the parasitic RC from the top layer to the lowest layer related to the power supply wiring and the ground wiring having the net name stored in the net name file, as well as the top layer. Parasitic RC of inter-block wiring other than power supply wiring and ground wiring is also included.

When the parasitic RC extraction unit 9 extracts the parasitic RC of the wiring, the parasitic RC application unit 10 applies the parasitic RC to the netlist C created by the netlist creation unit 5 to generate the netlist D (parasitic RC of the wiring). (A net list including the above information) is output (step ST9).
When the parasitic RC extraction unit 9 extracts the parasitic RC of the wiring, the coordinate file creation unit 11 specifies coordinate information on the layout data of the node of the parasitic RC, and stores the coordinate information in the coordinate file F2 (step ST9). ).

When the netlist application unit 12 receives the netlist D from the parasitic RC application unit 10, the netlist application unit 12 applies the corresponding part in the netlist A to each block that remains in the black box in the netlist D. Then, the net list E including the wiring parasitic RC is created (step ST10).
FIG. 16 is a circuit diagram in which a net list E including wiring parasitic RC is expressed. As is clear from FIG. 16, at this stage, circuit elements connected to the power supply wiring and ground wiring in each block are shown. All terminals are connected to nodes of power supply terminals and ground terminals.
In the figure, PR1-17 are parasitic resistors, Q1-5 are circuit elements BJT (transistors), M1-2 are circuit elements MOS-Tr (transistors), and R1-6 are circuit elements (resistance elements) ), C1 is a capacitor (capacitance element) which is a circuit element.
In the example of FIG. 16, only the parasitic R (parasitic resistance) of the wiring is extracted, and the parasitic C (parasitic capacitance) is not extracted.

The connection relation optimization unit 13 compares the coordinate information of the terminal of the circuit element stored in the coordinate file F1 with the coordinate information of the node of the parasitic RC stored in the coordinate file F2, and includes the wiring parasitic RC. The connection relationship between the circuit element and the parasitic resistance in the netlist E is optimized (step ST11).
In other words, the connection relation optimization unit 13 compares the coordinate information of the terminal of the circuit element with the coordinate information of the node of the parasitic RC to identify the node of the parasitic RC corresponding to the terminal of the circuit element, and In the RC-incorporated netlist E, the process of replacing the terminal of the circuit element connected to the node of the power supply terminal or the ground terminal with the corresponding parasitic RC node as shown in FIG.
When the connection relationship optimization unit 13 optimizes the connection relationship between the circuit element and the parasitic resistance, the connection relationship optimization unit 13 outputs the optimized netlist as a circuit simulation netlist.

  When the simulation execution unit 14 receives the circuit simulation netlist from the connection relation optimization unit 13 of the netlist creation device, the simulation execution unit 14 uses the circuit simulation netlist to take into account the parasitic resistance of the power supply wiring and the ground wiring. A simulation is performed (step ST12).

  As apparent from the above, according to the first embodiment, the parasitic RC of the wiring is extracted from the layout data Z to which the abstract indicating the power supply wiring and the ground wiring in the top layer block is applied, and the extraction result is obtained. While being applied to the netlist C, the coordinate information on the layout data of the node of the parasitic RC is specified and stored in the coordinate file F2, while the coordinate information of the terminal of the circuit element stored in the coordinate file F1 and the coordinate file F2 Is compared with the coordinate information of the node of the parasitic RC stored in, and the connection relationship between the circuit element and the parasitic RC in the netlist E to which the extraction result of the parasitic RC is applied is optimized. It is possible to facilitate the extraction of RC and to increase the analysis accuracy of circuit simulation.

That is, since the parasitic RC of the power supply and ground wiring inside the block and the parasitic RC of the wiring between blocks are extracted, the analysis accuracy of the circuit simulation can be improved.
Further, since the user can automatically extract the parasitic RC simply by specifying the net name of the power wiring or ground wiring in the top layer, the work time required for extracting the parasitic RC can be greatly reduced. .

Embodiment 2. FIG.
In the first embodiment, the extraction of the parasitic RC of the power supply and ground wiring inside the block and the parasitic RC of the wiring between the blocks has been described. However, there is a practical problem from the circuit simulation netlist. The parasitic R may be deleted within a range in which an analysis accuracy of a certain level can be maintained.
In the second embodiment, the connection relation optimization unit 13 counts the number of circuit elements connected to one end of the parasitic R, and deletes the parasitic R having one number.

Specifically, it is as follows.
FIG. 4 is a flowchart showing the processing contents of the net list creating apparatus according to the second embodiment of the present invention.

  When the connection relation optimizing unit 13 creates a circuit simulation netlist in the same manner as in the first embodiment, a power source indicated by the net name stored in the net name file is selected from the circuit simulation netlist. The parasitic R of the wiring and the ground wiring is searched, and the parasitic R (the number of the parasitic R may be one or more) as a search result is stored in the parasitic R information file (step ST21).

The connection relation optimization unit 13 extracts the parasitic R in order from the parasitic R information file, counts the number of circuit elements connected to one end (node) of the parasitic R, and the number of parasitic elements is one. Delete R.
For example, since one end of the parasitic R of PR8 in FIG. 17 is connected to only one circuit element R6, the parasitic R of PR8 is deleted as shown in FIG.
However, since one end of the parasitic R of PR17 in FIG. 17 is connected to the two circuit elements Q2 and Q3, the parasitic R of PR17 is not deleted as shown in FIG.

When the connection relation optimizing unit 13 deletes the parasitic R as described above, a process of connecting the terminal of the circuit element connected to one end of the parasitic R to the other end (node) of the parasitic R is performed. The circuit simulation netlist is updated (step ST22).
When the connection relation optimization unit 13 executes the process of step ST22 for all the parasitic R stored in the parasitic R information file, the parasitic R of PR4, PR8, PR9, PR, 11, PR12, and PR14 in FIG. Deleted.

When the circuit simulation netlist is updated as described above, the connection relation optimization unit 13 repeatedly executes the processing of steps ST21 and ST22 (described as “processing 1” in FIG. 4) until there is no parasitic R to be deleted. To do.
In the second process, the parasitic R of PR7 and PR13 in FIG. 17 is deleted. The final result is as shown in FIG.

  In the second embodiment, as described above, the connection relation optimization unit 13 counts the number of circuit elements connected to one end of the parasitic R, and the number of the parasitic R is deleted. However, since the parasitic R that greatly affects the voltage drop of the power supply wiring and the ground wiring is the parasitic R of the power supply wiring and the main line of the ground wiring where the power / ground current is concentrated, the number of connected circuit elements is small. Even if one parasitic R is deleted, the influence on the analysis accuracy is small. In addition, since the number of parasitic R is reduced, the circuit simulation execution time is shortened.

In the second embodiment, the connection relation optimization unit 13 counts the number of circuit elements connected to one end of the parasitic R, and the number of the parasitic R is deleted. The parasitic R having a resistance value equal to or less than the specified value may be deleted, or the parasitic R connected in series or in parallel may be converted into one parasitic R. be able to.
When the parasitic R connected in series or in parallel is converted into one parasitic R, in the example of FIG. 17, the parasitic R of “PR2 and PR3” and the parasitic R of “PR16 and PR17” are each converted to one parasitic R. Can be converted.

Embodiment 3 FIG.
In the second embodiment, the connection relation optimizing unit 13 counts the number of circuit elements connected to one end of the parasitic R, and the number of the parasitic elements is deleted. The relationship optimization unit 13 may count the number of circuit elements connected to one end of the parasitic R, and delete the parasitic R whose number is equal to or less than the designated number. Similar effects can be achieved.

Specifically, it is as follows.
FIG. 5 is a flowchart showing the processing contents of the net list creating apparatus according to the third embodiment of the present invention.

First, the user sets an upper limit value M for the number of circuit elements connected to one end of the parasitic R (step ST31).
When the connection relation optimizing unit 13 creates a circuit simulation netlist in the same manner as in the first embodiment, a power source indicated by the net name stored in the net name file is selected from the circuit simulation netlist. The parasitic R of the wiring and the ground wiring is searched, and the parasitic R as the search result is stored in the parasitic R information file (step ST32).

The connection relation optimization unit 13 sequentially extracts the parasitic R from the parasitic R information file, counts the number of circuit elements connected to one end (node) of the parasitic R, and the number is equal to or less than M. The parasitic R is deleted.
When the connection relation optimizing unit 13 deletes the parasitic R as described above, a process of connecting the terminal of the circuit element connected to one end of the parasitic R to the other end (node) of the parasitic R is performed. The circuit simulation netlist is updated (step ST33).
The connection relation optimization unit 13 executes the process of step ST33 for all the parasitic R stored in the parasitic R information file.

When the circuit simulation netlist is updated as described above, the connection relation optimization unit 13 repeatedly performs the processing of steps ST32 and ST33 (described as “processing 2” in FIG. 5) until the parasitic R to be deleted is eliminated. To do.
For example, when M = 2 is set, as shown in FIG. 19, the parasitic R of PR6, PR10, PR16, and PR17 not deleted in the second embodiment is deleted.

Embodiment 4 FIG.
In the second embodiment, the connection relation optimization unit 13 counts the number of circuit elements connected to one end of the parasitic R, and the number of the parasitic elements is deleted. When the circuit element connected to one end of R is the capacitive element C, the connection relationship optimizing unit 13 may not be included in the number of circuit elements connected to one end of the circuit element. Good.

Specifically, it is as follows.
FIG. 6 is a flowchart showing the processing contents of the net list creating apparatus according to the fourth embodiment of the present invention.

  When the connection relation optimizing unit 13 creates a circuit simulation netlist in the same manner as in the first embodiment, a power source indicated by the net name stored in the net name file is selected from the circuit simulation netlist. The parasitic R of the wiring and the ground wiring is searched, and the parasitic R as the search result is stored in the parasitic R information file (step ST41).

The connection relation optimization unit 13 extracts the parasitic R in order from the parasitic R information file, and counts the number of circuit elements connected to one end (node) of the parasitic R. However, when the circuit element connected to one end of the parasitic R is the capacitive element C, the circuit element is not included in the number.
The connection relation optimizing unit 13 deletes the parasitic R having one count as described above.

When the connection relation optimizing unit 13 deletes the parasitic R as described above, a process of connecting the terminal of the circuit element connected to one end of the parasitic R to the other end (node) of the parasitic R is performed. Then, the circuit simulation netlist is updated (step ST42).
The connection relation optimization unit 13 executes the process of step ST42 for all the parasitic Rs stored in the parasitic R information file.

  When the circuit simulation netlist is updated as described above, the connection relation optimization unit 13 repeatedly executes the processing of steps ST41 and ST42 (described as “processing 3” in FIG. 6) until there is no parasitic R to be deleted. To do.

In the fourth embodiment, when the circuit element connected to one end of the parasitic R is the capacitive element C, the connection relationship optimizing unit 13 is connected to one end of the circuit element of the circuit element. Since it is not included in the number, the parasitic R of PR10 not deleted in the second embodiment is also deleted.
In general, the current flowing through the capacitive element is often smaller than the current in other parts. Therefore, even if the parasitic R is deleted without counting the capacitive element C, the analysis accuracy is maintained at a level where there is no practical problem. As a result, the execution time of the circuit simulation can be shortened.

  In the fourth embodiment, the technique of applying the technique that does not count the capacitive element C when performing the method for removing the parasitic R in the second embodiment is described. However, the parasitic R in the third embodiment is described. When performing this deletion method, a technique of not counting the capacitive element C may be applied.

Embodiment 5. FIG.
In the second embodiment, the connection relation optimizing unit 13 counts the number of circuit elements connected to one end of the parasitic R, and the number of the parasitic elements is deleted. When the terminal of the circuit element connected to one end of the parasitic R is a collector terminal or emitter terminal of a BJT having an emitter area larger than a specified value, the parasitic R may not be deleted.

Specifically, it is as follows.
FIG. 7 is a flowchart showing the processing contents of the net list creating apparatus according to the fifth embodiment of the present invention.

First, the user sets an upper limit value Ae-max of the emitter area Ae of BJT (step ST51).
When the connection relation optimizing unit 13 creates a circuit simulation netlist in the same manner as in the first embodiment, a power source indicated by the net name stored in the net name file is selected from the circuit simulation netlist. The parasitic R of the wiring or ground wiring is searched, and the parasitic R as the search result is stored in the parasitic R information file (step ST52).

The connection relation optimization unit 13 extracts the parasitic R in order from the parasitic R information file, counts the number of circuit elements connected to one end (node) of the parasitic R, and the number of parasitic elements is one. Delete R.
However, when one end of the parasitic R is connected to the collector terminal or emitter terminal of the BJT having an emitter area Ae larger than the upper limit value Ae-max, the connection relation optimization unit 13 determines the parasitic R as the parasitic R. Do not delete.
When applied to the case where the upper limit value M of the number of circuit elements is set as in the third embodiment, when one end of the parasitic R is connected to the collector terminals or emitter terminals of a plurality of BJTs, If the sum of the emitter areas Ae of the BJTs is larger than the upper limit Ae-max, the parasitic R is not deleted.
For example, when Ae-max = 80 μm ² is set, the sum of the emitter areas Ae of BJT Q2 and Q3 is 100 μm ² , which exceeds the upper limit value Ae-max. Therefore, the collector terminals of Q2 and Q3 Alternatively, the parasitic R of PR16 and PR17 connected to the emitter terminal is not deleted (see FIGS. 18 and 19).

When the connection relation optimizing unit 13 deletes the parasitic R as described above, a process of connecting the terminal of the circuit element connected to one end of the parasitic R to the other end (node) of the parasitic R is performed. The circuit simulation netlist is updated (step ST53).
The connection relationship optimization unit 13 executes the process of step ST53 for all the parasitic R stored in the parasitic R information file.

  When the circuit simulation netlist is updated as described above, the connection relation optimization unit 13 repeatedly executes the processing of steps ST52 and ST53 (described as “processing 4” in FIG. 7) until there is no parasitic R to be deleted. To do.

In the fifth embodiment, when one end of the parasitic R is connected to the collector terminal or emitter terminal of the BJT having an emitter area Ae larger than the upper limit value Ae-max, the parasitic R is not deleted. However, in general, a BJT having a large emitter area Ae has a large collector current and an emitter current, and the voltage drop of the parasitic R due to this current increases, so even the parasitic R at the end may not be ignored.
Therefore, according to the fifth embodiment, there is an effect that a higher level of analysis accuracy can be maintained than in the second embodiment.

Embodiment 6 FIG.
In the second embodiment, the connection relation optimizing unit 13 counts the number of circuit elements connected to one end of the parasitic R, and the number of the parasitic elements is deleted. When the circuit element connected to one end of the parasitic R is a resistance element R, and the other end of the resistance element R is connected to the collector terminal or emitter terminal of a BJT having an emitter area larger than a specified value, The parasitic R may not be deleted.

Specifically, it is as follows.
FIG. 8 is a flowchart showing the processing contents of the net list creating apparatus according to the sixth embodiment of the present invention.

First, the user sets an upper limit value Ae-max of the emitter area Ae of BJT (step ST61).
When the connection relation optimizing unit 13 creates a circuit simulation netlist in the same manner as in the first embodiment, a power source indicated by the net name stored in the net name file is selected from the circuit simulation netlist. The parasitic R of the wiring or ground wiring is searched, and the parasitic R as the search result is stored in the parasitic R information file (step ST62).

The connection relation optimization unit 13 extracts the parasitic R in order from the parasitic R information file, counts the number of circuit elements connected to one end (node) of the parasitic R, and the number of parasitic elements is one. Delete R.
However, in the connection relation optimization unit 13, the circuit element connected to one end of the parasitic R is the resistance element R, and the other end of the resistance element R has an emitter area Ae larger than the upper limit value Ae-max. If it is connected to the collector terminal or emitter terminal of the BJT, the parasitic R is not deleted.
For example, when Ae−max = 80 μm ² is set, the other end of the resistor element R5 is connected to the collector terminal of Q4, which is a BJT with an emitter area Ae of 100 μm ² , and thus connected to the resistor element R5. The parasitic R of PR9 is not deleted (see FIGS. 17 and 18).
When the other end of the resistance element R is connected to the collector terminals or emitter terminals of a plurality of BJTs, the parasitic R is deleted if the sum of the emitter areas Ae of the plurality of BJTs is larger than the upper limit value Ae-max. Do not.
When applied to a device in which the upper limit value M of the number of circuit elements is set as in the third embodiment, the collector terminal or the emitter terminal is connected to one end of the parasitic R in combination with the fifth embodiment. If the sum of the emitter areas Ae of all the BJTs connected directly or through the resistance elements is larger than the upper limit value Ae-max, the parasitic R is not deleted.

When the connection relation optimizing unit 13 deletes the parasitic R as described above, a process of connecting the terminal of the circuit element connected to one end of the parasitic R to the other end (node) of the parasitic R is performed. Then, the circuit simulation net list is updated (step ST63).
The connection relation optimization unit 13 executes the process of step ST63 for all the parasitic R stored in the parasitic R information file.

  When the circuit simulation netlist is updated as described above, the connection relation optimization unit 13 repeatedly executes the processing of steps ST62 and ST63 (described as “processing 5” in FIG. 8) until there is no parasitic R to be deleted. To do.

In the sixth embodiment, the circuit element connected to one end of the parasitic R is the resistance element R, and the other end of the resistance element R has a collector of BJT having an emitter area Ae larger than the upper limit value Ae-max. When connected to a terminal or an emitter terminal, the parasitic R is not deleted. Generally, a BJT having a large emitter area Ae has a large collector current and emitter current, and the voltage of the parasitic R due to this current is large. Since the drop is large, even the parasitic end R may not be ignored.
Therefore, according to the sixth embodiment, there is an effect that it is possible to maintain a higher level of analysis accuracy than in the second embodiment.

Embodiment 7 FIG.
In the second embodiment, the connection relation optimizing unit 13 counts the number of circuit elements connected to one end of the parasitic R, and the number of the parasitic elements is deleted. When the terminal of the circuit element connected to one end of the parasitic R is a drain terminal or a source terminal of a MOS-Tr having a gate width larger than a specified value, the parasitic R may not be deleted. .

Specifically, it is as follows.
FIG. 9 is a flowchart showing the processing contents of the net list creating apparatus according to the seventh embodiment of the present invention.

First, the user sets an upper limit value W-max of the gate width W of the MOS-Tr (step ST71).
When the connection relation optimizing unit 13 creates a circuit simulation netlist in the same manner as in the first embodiment, a power source indicated by the net name stored in the net name file is selected from the circuit simulation netlist. The parasitic R of the wiring or ground wiring is searched, and the parasitic R as the search result is stored in the parasitic R information file (step ST72).

The connection relation optimization unit 13 extracts the parasitic R in order from the parasitic R information file, counts the number of circuit elements connected to one end (node) of the parasitic R, and the number of parasitic elements is one. Delete R.
However, when one end of the parasitic R is connected to the drain terminal or the source terminal of the MOS-Tr having the gate width W larger than the upper limit value W-max, the connection relation optimization unit 13 is connected to the parasitic R. Do not delete R.
When applied to the case where the upper limit value M of the number of circuit elements is set as in the third embodiment, when one end of the parasitic R is connected to the drain terminals or source terminals of a plurality of MOS-Trs If the total gate width W of the plurality of MOS-Trs is larger than the upper limit value W-max, the parasitic R is not deleted.

When the connection relation optimizing unit 13 deletes the parasitic R as described above, a process of connecting the terminal of the circuit element connected to one end of the parasitic R to the other end (node) of the parasitic R is performed. The circuit simulation netlist is updated (step ST73).
The connection relation optimization unit 13 executes the process of step ST73 for all the parasitic R stored in the parasitic R information file.

  When the circuit simulation netlist is updated as described above, the connection relation optimization unit 13 repeatedly executes the processing of steps ST72 and ST73 (described as “processing 6” in FIG. 9) until there is no parasitic R to be deleted. To do.

In the seventh embodiment, when one end of the parasitic R is connected to the drain terminal or the source terminal of the MOS-Tr having the gate width W larger than the upper limit value W-max, the parasitic R is not deleted. However, in general, a MOS-Tr having a large gate width W has a large drain current and a large source current, and the voltage drop of the parasitic R due to this current becomes large. .
Therefore, according to the seventh embodiment, it is possible to maintain an analysis accuracy at a higher level than in the second embodiment.

Embodiment 8 FIG.
In the second embodiment, the connection relation optimizing unit 13 counts the number of circuit elements connected to one end of the parasitic R, and the number of the parasitic elements is deleted. When the circuit element connected to one end of the parasitic R is a resistance element R, and the other end of the resistance element R is connected to the drain terminal or the source terminal of a transistor having a gate width larger than a specified value, The parasitic R may not be deleted.

Specifically, it is as follows.
FIG. 10 is a flowchart showing the processing contents of the net list creating apparatus according to the eighth embodiment of the present invention.

First, the user sets an upper limit value W-max of the gate width W of the MOS-Tr (step ST81).
When the connection relation optimizing unit 13 creates a circuit simulation netlist in the same manner as in the first embodiment, a power source indicated by the net name stored in the net name file is selected from the circuit simulation netlist. The parasitic R of the wiring and the ground wiring is searched, and the parasitic R as the search result is stored in the parasitic R information file (step ST82).

The connection relation optimization unit 13 extracts the parasitic R in order from the parasitic R information file, counts the number of circuit elements connected to one end (node) of the parasitic R, and the number of parasitic elements is one. Delete R.
However, in the connection relationship optimization unit 13, the circuit element connected to one end of the parasitic R is the resistance element R, and the other end of the resistance element R has a gate width W greater than the upper limit value W-max. If it is connected to the drain terminal or the source terminal of the MOS-Tr having, the parasitic R is not deleted.
For example, when W-max = 50 μm is set, the other end of the resistance element R2 is connected to M2, which is a MOS-Tr having a gate width W of 100 μm, so that PR4 connected to the resistance element R2 Is not deleted (see FIGS. 17 and 18).
When the other end of the resistance element R is connected to the drain terminals or source terminals of the plurality of MOS-Trs, if the total gate width W of the plurality of MOS-Trs is larger than the upper limit value W-max, The parasitic R is not deleted.
When applied to the case where the upper limit value M of the number of circuit elements is set as in the third embodiment, the drain terminal or the source terminal is connected to one end of the parasitic R in combination with the seventh embodiment. If the sum of the gate widths W of all the MOS-Trs connected directly or via a resistance element is larger than the upper limit value W-max, the parasitic R is not deleted.

When the connection relation optimizing unit 13 deletes the parasitic R as described above, a process of connecting the terminal of the circuit element connected to one end of the parasitic R to the other end (node) of the parasitic R is performed. The circuit simulation net list is updated (step ST83).
The connection relation optimization unit 13 executes the process of step ST83 for all the parasitic R stored in the parasitic R information file.

  When the circuit simulation netlist is updated as described above, the connection relation optimization unit 13 repeatedly executes the processes of Steps ST82 and ST83 (described as “Process 7” in FIG. 10) until there is no parasitic R to be deleted. To do.

In the eighth embodiment, the circuit element connected to one end of the parasitic R is the resistance element R, and the other end of the resistance element R has the gate width W larger than the upper limit value W-max. However, the MOS-Tr having a large gate width W has a large drain current and a large source current, which is caused by this current. Since the voltage drop of the parasitic R becomes large, even the parasitic R at the end cannot be ignored.
Therefore, according to the eighth embodiment, there is an effect that it is possible to maintain a higher level of analysis accuracy than in the second embodiment.

Embodiment 9 FIG.
In the second embodiment, the connection relation optimizing unit 13 counts the number of circuit elements connected to one end of the parasitic R, and the number of the parasitic elements is deleted. When the direct current flowing through the terminal of the circuit element connected to one end of the parasitic R is larger than the specified value, the parasitic R may not be deleted.

Specifically, it is as follows.
FIG. 11 is a flowchart showing the processing contents of the net list creating apparatus according to the ninth embodiment of the present invention.

First, the simulation execution unit 14 performs a circuit simulation (DC analysis) on the netlist A, thereby calculating a DC current Idc flowing through the terminals of the circuit elements connected to the power supply wiring and the ground wiring, and the DC current Idc. Is stored in the DC current information file (step ST91).
Further, the user sets an upper limit value Idc-max of DC current Idc (step ST92).

  When the connection relation optimizing unit 13 creates a circuit simulation netlist in the same manner as in the first embodiment, a power source indicated by the net name stored in the net name file is selected from the circuit simulation netlist. The parasitic R of the wiring and the ground wiring is searched, and the parasitic R as the search result is stored in the parasitic R information file (step ST93).

The connection relation optimization unit 13 extracts the parasitic R in order from the parasitic R information file, counts the number of circuit elements connected to one end (node) of the parasitic R, and the number of parasitic elements is one. Delete R.
However, the connection relation optimizing unit 13 deletes the parasitic R when the DC current Idc flowing in the terminal of the circuit element connected to one end of the parasitic R is larger than the previously set upper limit value Idc-max. Do not.
When applied to the one where the upper limit value M of the number of circuit elements is set as in the third embodiment, when a plurality of circuit elements are connected to one end of the parasitic R, the terminals of the plurality of circuit elements If the sum total of the DC currents Idc flowing through is larger than the upper limit value Idc-max, the parasitic R is not deleted.

When the connection relation optimizing unit 13 deletes the parasitic R as described above, a process of connecting the terminal of the circuit element connected to one end of the parasitic R to the other end (node) of the parasitic R is performed. Then, the circuit simulation netlist is updated (step ST94).
The connection relation optimization unit 13 executes the process of step ST94 for all the parasitic R stored in the parasitic R information file.

  When the circuit simulation netlist is updated as described above, the connection relation optimization unit 13 repeatedly executes the processing of steps ST93 and ST94 (described as “processing 8” in FIG. 11) until there is no parasitic R to be deleted. To do.

  In the ninth embodiment, when the direct current Idc flowing through the terminal of the circuit element connected to one end of the parasitic R is larger than the upper limit value Idc-max, the parasitic R is not deleted. Since the determination of whether or not to delete is based on the circuit simulation result, the parasitic simulation R can be deleted as much as possible while maintaining a high level of analysis accuracy, and the circuit simulation execution time can be shortened Play.

Embodiment 10 FIG.
In the second embodiment, the connection relation optimizing unit 13 counts the number of circuit elements connected to one end of the parasitic R, and the number of the parasitic elements is deleted. When the maximum value of the alternating current flowing through the terminal of the circuit element connected to one end of the parasitic R is larger than the specified value, the parasitic R may not be deleted.

Specifically, it is as follows.
FIG. 12 is a flowchart showing the processing contents of the net list creating apparatus according to the tenth embodiment of the present invention.

First, the simulation execution unit 14 performs a circuit simulation (transient analysis) on the netlist A, thereby calculating an alternating current Iac flowing through the terminals of the circuit elements connected to the power supply wiring and the ground wiring, and the alternating current Iac. Are stored in an alternating current information file (step ST101).
Further, the user sets an upper limit value Iac-max of AC current Iac (step ST102).

  When the connection relation optimizing unit 13 creates a circuit simulation netlist in the same manner as in the first embodiment, a power source indicated by the net name stored in the net name file is selected from the circuit simulation netlist. The parasitic R of the wiring and the ground wiring is searched, and the parasitic R as the search result is stored in the parasitic R information file (step ST103).

The connection relation optimization unit 13 extracts the parasitic R in order from the parasitic R information file, counts the number of circuit elements connected to one end (node) of the parasitic R, and the number of parasitic elements is one. Delete R.
However, when the maximum value of the alternating current Iac flowing through the terminal of the circuit element connected to one end of the parasitic R is larger than the upper limit value Iac-max set in advance, the connection relation optimizing unit 13 Do not delete R.
When applied to the one where the upper limit value M of the number of circuit elements is set as in the third embodiment, when a plurality of circuit elements are connected to one end of the parasitic R, the terminals of the plurality of circuit elements If the maximum value of the total sum of the alternating currents Iac flowing through is larger than the upper limit value Iac-max, the parasitic R is not deleted.

When the connection relation optimizing unit 13 deletes the parasitic R as described above, a process of connecting the terminal of the circuit element connected to one end of the parasitic R to the other end (node) of the parasitic R is performed. The circuit simulation netlist is updated (step ST104).
The connection relation optimization unit 13 performs the process of step ST104 for all the parasitic R stored in the parasitic R information file.

  When the circuit simulation netlist is updated as described above, the connection relation optimization unit 13 repeatedly executes the processing of steps ST103 and ST104 (described as “processing 9” in FIG. 12) until there is no parasitic R to be deleted. To do.

  In the tenth embodiment, when the maximum value of the alternating current Iac flowing through the terminal of the circuit element connected to one end of the parasitic R is larger than the upper limit value Iac-max, the parasitic R is not deleted. Since the determination of whether or not to delete the parasitic R is based on the circuit simulation result, the parasitic R is deleted as much as possible while maintaining a high level of analysis accuracy to shorten the circuit simulation execution time. There is an effect that can.

Embodiment 11 FIG.
In the second embodiment, the connection relation optimization unit 13 counts the number of circuit elements connected to one end of the parasitic R, and the number of the parasitic elements is deleted. When the parasitic C is connected to one end of the target parasitic R, the node of the parasitic C connected to one end may be connected to the other end of the target parasitic R.

Specifically, it is as follows.
FIG. 13 is a flowchart showing the processing contents of the net list creating apparatus according to the eleventh embodiment of the present invention.

  In the first to tenth embodiments, as shown in FIG. 17, the parasitic RC extraction unit 9 extracts only the parasitic R and does not extract the parasitic C. However, in the eleventh embodiment, As shown in FIG. 20, it is assumed that the parasitic RC extraction unit 9 extracts the parasitic R and the parasitic C.

  When the connection relation optimizing unit 13 creates a circuit simulation netlist in the same manner as in the first embodiment, a power source indicated by the net name stored in the net name file is selected from the circuit simulation netlist. The parasitic R and the parasitic C of the wiring and the ground wiring are searched, and the parasitic R and the parasitic C that are the search results are stored in the parasitic RC information file (step ST111).

  The connection relation optimization unit 13 sequentially extracts the parasitic R from the parasitic RC information file, counts the number of circuit elements connected to one end (node) of the parasitic R, and the number of parasitic elements is one. The circuit simulation netlist is updated by deleting R and changing the terminal of the circuit element connected to one end of the parasitic R to the other end (node) of the parasitic R (see FIG. Step ST112).

In addition, when the parasitic C is connected to one end of the deleted parasitic R, the connection optimization unit 13 switches the node of the parasitic C connected to one end to the other end of the deleted parasitic R. The processing is performed to update the circuit simulation netlist (step ST113).
Thereby, the parasitic C of PC1 to PC5 in FIG. 20 is connected as shown in FIG.

The connection relation optimization unit 13 performs the processes of steps ST112 and ST113 for all the parasitic R stored in the parasitic R information file.
When the circuit simulation netlist is updated as described above, the connection relation optimization unit 13 repeatedly executes the processing of steps ST111 to ST113 (described as “processing 10” in FIG. 13) until there is no parasitic R to be deleted. To do.

In the eleventh embodiment, since the parasitic R is deleted while the information on the parasitic C is retained, even when the parasitic C is extracted, there is an effect that a high level of analysis accuracy can be maintained.
In the eleventh embodiment, the parasitic R information deleting method in the second embodiment has been described. However, the parasitic R deleting method in the third embodiment has been described. When performing the above, information on the parasitic C may be held.

It is a block diagram which shows the net list production apparatus by Embodiment 1 of this invention. It is a flowchart which shows the processing content of the net list production apparatus by Embodiment 1 of this invention. It is a flowchart which shows the processing content of the net list production apparatus by Embodiment 1 of this invention. It is a flowchart which shows the processing content of the net list production apparatus by Embodiment 2 of this invention. It is a flowchart which shows the processing content of the net list production apparatus by Embodiment 3 of this invention. It is a flowchart which shows the processing content of the net list production apparatus by Embodiment 4 of this invention. It is a flowchart which shows the processing content of the net list production apparatus by Embodiment 5 of this invention. It is a flowchart which shows the processing content of the net list production apparatus by Embodiment 6 of this invention. It is a flowchart which shows the processing content of the net list production apparatus by Embodiment 7 of this invention. It is a flowchart which shows the processing content of the net list production apparatus by Embodiment 8 of this invention. It is a flowchart which shows the processing content of the net list production apparatus by Embodiment 9 of this invention. It is a flowchart which shows the processing content of the net list production apparatus by Embodiment 10 of this invention. It is a flowchart which shows the processing content of the net list production apparatus by Embodiment 11 of this invention. It is an image figure which shows the layout by which the block of the top hierarchy is made into the black box. FIG. 15 is an image diagram in which pin information, abstracts, and the like are added to FIG. 14. It is a circuit diagram in which a net list E including wiring parasitic RC is expressed. FIG. 5 is a circuit diagram representing a netlist with a proper connection relationship. It is a circuit diagram expressing the net list after an update. It is a circuit diagram expressing the net list after an update. FIG. 5 is a circuit diagram representing a netlist with a proper connection relationship. It is a circuit diagram expressing the net list after an update.

Explanation of symbols

  1 Net list creation unit (coordinate information identification unit) 2 Net list creation unit (coordinate information identification unit) 3 Coordinate file creation unit (coordinate information identification unit) 4 Black box generation unit (data creation unit) 5 Net list Creation part (data creation means), 6 Net name input part (abstract application means), 7 Abstract creation part (abstract application means), 8 Abstract application part (abstract application means), 9 Parasitic RC extraction part (parasitic resistance application means) DESCRIPTION OF SYMBOLS 10 Parasitic RC application part (parasitic resistance application means), 11 Coordinate file creation part (parasitic resistance application means), 12 Net list application part (optimization means), 13 Connection relation optimization part (optimization means), 14 Simulation Execution part.

Claims (11)

  Coordinate information specifying means for comparing the layout data of the LSI and the circuit diagram data to specify the coordinate information on the layout data of the terminals of the circuit elements connected to the power supply wiring or the ground wiring, and the top in the layout data of the LSI Creates layout data in which the blocks in the hierarchy are black boxed, and also shows data creation means for creating a net list from the layout data, and power supply wiring and ground wiring in the top hierarchy block from the layout data of the LSI. Create an abstract, apply the abstract to the layout data created by the data creation means, and extract the parasitic resistance of the wiring from the layout data to which the abstract is applied by the abstract application means The extraction result is applied to the net list created by the data creating means, and the parasitic resistance applying means for specifying the coordinate information on the layout data of the node of the parasitic resistance, and the circuit specified by the coordinate information specifying means The coordinate information on the layout data of the terminal of the element is compared with the coordinate information on the layout data of the node of the parasitic resistance specified by the parasitic resistance applying means, and the parasitic resistance extraction result is applied by the parasitic resistance applying means. A netlist creation device comprising optimization means for optimizing the connection relationship between circuit elements and parasitic resistances in the netlist.   2. The net list creating apparatus according to claim 1, wherein the optimizing means counts the number of circuit elements connected to one end of the parasitic resistance and deletes one parasitic resistance.   2. The netlist creation according to claim 1, wherein the optimizing means counts the number of circuit elements connected to one end of the parasitic resistance, and deletes the parasitic resistance whose number is equal to or less than the specified number. apparatus.   When the circuit element connected to one end of the parasitic resistance is a capacitive element, the optimization means is not included in the number of circuit elements connected to one end of the circuit element. The net list creation device according to claim 2 or claim 3.   The optimization means deletes the parasitic resistance when the terminal of the circuit element connected to one end of the parasitic resistance to be deleted is the collector terminal or emitter terminal of a transistor having an emitter area larger than the specified value. 4. The net list creating apparatus according to claim 2, wherein the net list creating apparatus is not.   The optimization means is that the circuit element connected to one end of the parasitic resistance to be deleted is a resistance element, and the other end of the resistance element is connected to the collector terminal or emitter terminal of a transistor having an emitter area larger than a specified value. 4. The net list creating apparatus according to claim 2, wherein the parasitic resistance is not deleted if the resistance is set.   The optimization means deletes the parasitic resistance when the terminal of the circuit element connected to one end of the parasitic resistance to be deleted is the drain terminal or the source terminal of the transistor having a gate width larger than the specified value. 4. The net list creating apparatus according to claim 2, wherein the net list creating apparatus is not.   The optimization means is that the circuit element connected to one end of the parasitic resistance to be deleted is a resistance element, and the other end of the resistance element is connected to the drain terminal or source terminal of a transistor having a gate width larger than a specified value. 4. The net list creating apparatus according to claim 2, wherein the parasitic resistance is not deleted if the resistance is set.   The optimization means does not delete the parasitic resistance when the direct current flowing through the terminal of the circuit element connected to one end of the parasitic resistance to be deleted is larger than a specified value. The net list creation device according to claim 3.   The optimizing means does not delete the parasitic resistance when the maximum value of the alternating current flowing through the terminal of the circuit element connected to one end of the parasitic resistance to be deleted is larger than a specified value. The net list creation device according to claim 2 or claim 3.   When the parasitic capacitance is connected to one end of the parasitic resistance to be deleted, the optimizing means switches the parasitic capacitance node connected to one end of the parasitic resistance to the other end of the parasitic resistance. 4. The net list creation device according to claim 2 or 3, wherein:

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