JP2006031296A - Image processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus that utilizes hardware processing to implement a pixel-value correction process such as hole-filling interpolation or a blurring process. <P>SOLUTION: The image processing apparatus comprises a circuit that receives the input of the pixel values of pixels constituting image data and accompanying information corresponding to the pixels and that selects a plurality of data consisting of the pixel values corresponding to the different pixels and the corresponding accompanying information as data to be inputted to a correction process execution circuit; and the correction process execution circuit that calculates corrected pixel values for the pixels to be corrected on the basis of the data and executes a process for updating the accompanying information corresponding to the corrected pixels. This configuration enables a pixel-value correction process such as hole-filling interpolation or a blurring process to be executed through simple processing on hardware by outputting data in the order of raster scans without performing complex memory control. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image processing apparatus. More specifically, for example, pixel value correction such as interpolation processing is performed on a pixel in which an incorrect pixel value is set due to, for example, a false color due to lens aberration, or a pixel value is indefinite. The present invention relates to an image processing apparatus that generates image data.

  For example, an image photographed by a camera is composed of a large number of pixels, and pixel values corresponding to the respective pixels are set and displayed on a display or printed out. In such image data, some pixel values may be indefinite or corrected.

  For example, because the refractive index of light with respect to the lens material of the camera varies depending on the wavelength, a false color is generated on the imaging surface, and the value of the pixel at a specific position may be set to an unnatural value. This is a phenomenon based on chromatic aberration. Chromatic aberration includes axial chromatic aberration in which color blur occurs because the focal position on the optical axis differs depending on wavelength, and lateral chromatic aberration in which color shift occurs because image magnification varies depending on wavelength. As an erroneous pixel value setting phenomenon based on this chromatic aberration, for example, there is a purple false color that occurs in the vicinity of an overexposed pixel as a saturated state at a luminance level, which is known as purple fringe.

  In addition to these purple fringes, due to various troubles in image capturing conditions and data processing at the time of capturing, among the many pixels that make up image data, pixels with unspecified pixel values, or clearly incorrect There may occur a pixel in which a pixel value is set.

  For such a pixel value indefinite pixel or a pixel requiring correction, it is necessary to correct the pixel value. Many of the processes performed to determine the pixel values of these pixels are those of pixels having non-constant pixel values that exist in the vicinity of these pixels, or pixels that originally have correct pixel values without correction. Interpolation processing based on pixel values. That is, the pixel values of these pixels are determined based on the pixel values of correct pixels around the target pixel that needs to be corrected. Note that such a pixel value correction process is called a hole filling process.

In addition, it is rare that one pixel exists alone as a pixel value indefinite pixel or a pixel requiring correction, and there are many cases where a certain number of pixel value indefinite pixels or pixels that need correction exist in a group. When performing hole filling processing on such a pixel group,
a) Processed pixels and unprocessed pixels b) It is necessary to perform processing by distinguishing between applicable pixels and inapplicable pixels.

  Until now, such pixel filling correction processing has generally been performed as software processing, and a parameter (accompanying information) corresponding to each pixel is set to correspond to each pixel for each processing step. The configuration of changing the parameters of and proceeding with the process was taken. However, the hole filling process requires a large number of parameters corresponding to each pixel, and it is necessary to efficiently and reliably switch the parameters, and further, a large number of processes for determining the pixel value of each pixel are required. There is a problem that it is necessary, and a hole filling processing configuration using hardware has not been realized.

As an image processing apparatus configuration to which hardware is applied, for example, there is a configuration described in Patent Document 1. The configuration disclosed in this document uses, as area number information, processing contents that can be adaptively switched when a plurality of processes are sequentially performed on image data. Then, the region number information is also delayed by the delay time required for the processing of each pixel, the processing flow is made consistent, and the control is simplified. However, the area number information in this disclosed configuration cannot be rewritten, and smooth control cannot be performed in the case of processing that requires changing the pixel-corresponding parameters as appropriate, such as the above-described hole filling processing. .
JP-A-5-153386

  The present invention has been made in view of the above-described problems, and a hardware circuit performs pixel value correction such as interpolation processing on a pixel in which an incorrect pixel value is set, a pixel whose pixel value is indefinite, or the like. And an image processing apparatus capable of processing with a small circuit configuration.

The first aspect of the present invention is:
An image processing device,
The pixel value of each pixel constituting the image data and the accompanying information corresponding to the pixel are input, and a plurality of data consisting of the pixel value corresponding to the different pixel and the corresponding accompanying information are input to the correction processing execution circuit. A data selection circuit to select;
A correction process for calculating a correction pixel value of a pixel to be corrected based on a plurality of data including a pixel value input from the data selection circuit and accompanying information, and executing an updating process of the accompanying information corresponding to the correction pixel An execution circuit;
An image processing apparatus characterized by comprising:

  Furthermore, in one embodiment of the image processing apparatus of the present invention, the data selection circuit inputs data consisting of pixel values and associated associated information in the order of raster scanning, and includes pixel values included in n × m adjacent pixel regions. A configuration for executing processing for selecting the associated information as input data to the correction processing execution circuit, where n and m are integers of 1 or more.

  Furthermore, in an embodiment of the image processing apparatus of the present invention, the data selection circuit includes a line-corresponding data selection unit for selecting a pixel value of n pixels adjacent in the horizontal direction of the image data and corresponding associated information. There are stages, where n and m are integers of 1 or more, and a data delay corresponding to (image width (width) data length−n pixel corresponding data length) is executed between the line-corresponding data selection units of different stages. It has a delay circuit, and is configured to execute a process of selecting a pixel value included in an n × m adjacent pixel area and corresponding associated information as input data to the correction process execution circuit.

  Furthermore, in an embodiment of the image processing apparatus of the present invention, the image processing apparatus further includes a memory that stores the pixel value of each pixel constituting the image data in association with the associated information corresponding to the pixel. The data selection circuit is configured to input data composed of pixel values and corresponding incidental information in the raster scan order from the memory.

  Furthermore, in an embodiment of the image processing apparatus of the present invention, the correction processing execution circuit is configured to execute a pixel value correction process by a hole-filling interpolation process, and includes a pixel value input from the data selection circuit and accompanying information. Based on a plurality of data, the correction pixel value of the correction target pixel is calculated by the filling interpolation process, and the associated information update process corresponding to the correction pixel is executed.

  Furthermore, in one embodiment of the image processing apparatus of the present invention, the accompanying information is information that can determine whether the pixel is a correction target pixel or a pixel having a pixel value applicable to hole-filling interpolation, The correction processing execution circuit selects only a pixel value of a pixel indicating that the accompanying information is a pixel having a pixel value applicable to filling interpolation when the accompanying information indicates a correction target pixel. The correction pixel value of the correction target pixel is calculated.

  Furthermore, in an embodiment of the image processing apparatus of the present invention, the correction processing execution circuit is configured to execute pixel value correction processing by blurring processing, and includes a pixel value input from the input data selection circuit and accompanying information. The correction pixel value of the correction target pixel is calculated by blurring processing based on a plurality of data.

  Furthermore, in one embodiment of the image processing apparatus of the present invention, the accompanying information is information capable of distinguishing a correction target pixel or a corrected pixel from other pixels, and the correction processing execution circuit includes the accompanying information. Indicates that the pixel is a correction target pixel or a corrected pixel, the pixel is selected, and a new corrected pixel value of the selected pixel is calculated based on the pixel values of the surrounding pixels of the selected pixel. It is characterized by.

  Furthermore, in an embodiment of the image processing apparatus of the present invention, the correction processing execution circuit selects the pixel when the accompanying information indicates that the correction target pixel or the corrected pixel is selected, and surrounds the selected pixel. An average value of the pixel values of the pixels is calculated, and the process of setting the calculated value as a new corrected pixel value of the selected pixel is executed.

  Furthermore, in one embodiment of the image processing apparatus of the present invention, the correction processing execution circuit is configured to correct a correction pixel value of a pixel to be corrected based on a plurality of data including a pixel value input from the data selection circuit and accompanying information. Is calculated, the associated information corresponding to the correction pixel is updated, and the processed data is output in raster scan order.

  Furthermore, in one embodiment of the image processing apparatus of the present invention, the accompanying information can distinguish between overexposed pixels, correction target pixels, corrected pixels, and other pixels not corresponding to any of the pixels. The correction processing execution circuit is configured to identify the accompanying information and execute processing according to the identification result.

  Furthermore, in an embodiment of the image processing apparatus of the present invention, in the image processing apparatus, the data selection circuit and the correction processing execution circuit have a configuration capable of executing a plurality of repeated processes. .

  Other objects, features, and advantages of the present invention will become apparent from a more detailed description based on embodiments of the present invention described later and the accompanying drawings. In this specification, the system is a logical set configuration of a plurality of devices, and is not limited to one in which the devices of each configuration are in the same casing.

  According to the configuration of the present invention, a pixel value correction process in image data, for example, a pixel value correction such as an interpolation process for a pixel in which an incorrect pixel value is set or a pixel with an indefinite pixel value is performed by hardware. An image processing apparatus is realized that applies a circuit and enables processing with a small circuit configuration.

  In the configuration of the present invention, the pixel value of each pixel constituting the image data and the accompanying information corresponding to the pixel are input, and a plurality of pieces of data including the pixel value corresponding to the different pixel and the corresponding accompanying information are executed. Based on a data selection circuit to be selected as input data to the circuit, a plurality of data consisting of pixel values and accompanying information input from the data selection circuit, a correction pixel value of the pixel to be corrected is calculated, and Since the correction processing execution circuit that executes the update processing of the corresponding incident information is performed, the pixel data necessary for correction is sequentially selected by the data selection circuit, supplied to the correction processing execution circuit, and the correction is executed. By sequentially outputting data in raster scan order, simple hardware processing without complicated memory control, hole filling interpolation processing, Pixel value correction processing such processes can be executed.

  According to the configuration of the present invention, hole filling interpolation and blurring processing are executed by applying a circuit configured by hardware. In addition, the processing procedure can be executed by sequentially processing pixel values input from the memory in the raster scan order and the accompanying information, and it is not necessary to perform complicated memory input / output control. Since only pixel values are transferred between the circuits according to the progress of processing, no memory or control dedicated to the accompanying information is required, and hole filling interpolation and blurring processing can be executed by simple control.

  The details of the image processing apparatus of the present invention will be described below with reference to the drawings.

  As described in the Background Art section, for example, purple fringes due to chromatic aberration, and other various pixels constituting the image data due to various troubles in image capturing conditions and data processing during image capturing, A pixel whose pixel value cannot be specified or a pixel value that is clearly wrong may be set. As a process for determining an appropriate pixel value corresponding to such a pixel (a pixel of interest), the surrounding pixel values Based on this, processing for determining the pixel value of the pixel of interest is performed. This process is called a hole filling process or a hole filling interpolation process.

  As an example of the hole-filling interpolation process, an image data correction process example to which the hole-filling interpolation process for purple fringe due to chromatic aberration is applied will be described. FIG. 1 shows an example of image data in which purple fringes are generated due to chromatic aberration.

  As shown in FIG. 1A, the pixel is classified into one of “whiteout pixel 11”, “false color (purple fringe) pixel 12”, and “other pixel 13 that is neither whiteout nor purple fringe”. Is done. Among these, the pixel whose pixel value needs to be reset is a “false color (purple fringe) pixel 12”, and the pixel value of this pixel is based on “other pixels 13 that are neither whiteout nor purple fringe”. decide. This hole-filling interpolation process is executed in the direction of the arrow 15 in FIG. 1B, and the pixel value of each pixel is set as the sequentially interpolated pixel 14.

A processing procedure of image data correction processing to which this hole-filling interpolation processing is applied will be described. Hereinafter, the correction process of the image data to which the hole-filling interpolation process for the purple fringe is applied is executed by the following five steps, for example.
Step 1: Whiteout mask calculation Step 2: False color generation part search area setting (Dilate) processing (pixel setting of a portion inflated around whiteout)
Step 3: Purple pixel detection Step 4: Color interpolation processing Step 5: Color blur processing

  These five steps will be briefly described. First, since the violet-colored pixel with conspicuous chromatic aberration is a peripheral portion causing “whiteout” in the image, the “whiteout” pixel is detected in Step 1. The “white jump” pixel detection is executed as a process of selecting a pixel (high luminance pixel) whose pixel value is higher than a predetermined value.

Next, in step 2, an area in the image where there is a possibility that false fringes, that is, purple fringes, exist around “whiteout” is set as a false color generation part search area.
In step 3, the pixel value of each pixel included in the false color generation part search area set in step 2 is acquired, a purple-colored pixel is selected, and this is a false color (purple fringe) pixel, that is, an interpolation process target Select as a pixel.

Next, in step 4, the interpolation target pixel is interpolated from surrounding pixels. At this time, exceptionally, for pixels that should have been corrected but could not be corrected, a process of reducing the saturation is executed.
Then, in the final step 5, in order to make the difference between the pixel that has undergone the normal correction process in step 4 (a pixel interpolated from the surroundings) and the exception process pixel (a pixel with reduced saturation) inconspicuous Execute the blur process. The blurring process is executed by a process of resetting pixel values so as to show a gentle change in pixel values for a plurality of adjacent pixels.

  Note that, in the above-described processing, the processing in step 4, that is, the processing for interpolating the interpolation target pixel from the surrounding pixels is determined by applying the pixel value of the surrounding fixed pixel to the pixel value of the pixel that needs to be corrected. This process is called a hole-filling interpolation process.

  In the present invention, the above-described hole-filling interpolation process in step 4 and the blurring process in step 5 are executed by applying a circuit having a hardware configuration. The constituent pixels of the image data to be processed are “exposed pixels”, “purple pixels, pixels to be corrected”, or “other pixels” After detecting whether the pixel is “a pixel”, the pixel value for “a pixel having a purple color and a pixel to be corrected” is sequentially determined by the filling interpolation process.

  The processing in step 4 and step 5 will be described in detail. First, before entering step 4, for each pixel, it is “a pixel that is overexposed” or “a pixel that is purple and is a pixel to be corrected” or “ It is determined whether the pixel is a pixel other than. This discrimination process is performed by acquiring the pixel value of each constituent pixel.

Set “I” to “exposed pixels”
“H”, “purple pixel and pixel to be corrected (pixel that has not been corrected in the correction process)”
“M” is a “purple pixel and a pixel to be corrected (a pixel that has already been corrected in the correction process)”
Set “Other pixels” to “V”.
It will be expressed as

  That is, before entering Step 4, each pixel has “I” (overexposed pixel), “H” (correction target pixel), “ V ”(other pixels). Further, as will be described later, in the course of processing, the accompanying information of the pixel corresponding to “H” (correction target pixel) is changed to “M” (corrected pixel).

  Note that “I” is an acronym for effective, “H” is an acronym for Hole, “M” is an acronym for Modified, and “V” is an acronym for Valid.

Now, in step 4, after performing process A described below for a predetermined number of times (for example, 10 times), process B is performed.
Process A: For all “H” (correction target pixel) pixels (referred to as a target pixel), “M” (corrected pixel) out of the surrounding pixels (a total of 8 pixels in the front, back, left, and right directions). Alternatively, if there is a “V” (other pixel) pixel, the value of the pixel of interest is changed by the average value of the “M” (corrected pixel) or “V” (other pixel) pixel. The accompanying information of the target pixel is changed from “H” (correction target pixel) to “M” (corrected pixel).
Process B: The values of all “H” (correction target pixels) are set to zero.

  The reason why process B is necessary will be supplemented. Even if the process A is performed a predetermined number of times (10 times), there may still be a pixel in the state of “H” (correction target pixel). In other words, there is a possibility that “a pixel that has been corrected in the process of correction processing (predetermined number of times of processing A)” even though it is a “purple pixel and a pixel to be corrected”. is there. For such pixels, the interpolation from surrounding pixels is given up and the saturation is reduced (that is, the value of the pixel of interest is set to 0). That is process B.

Now, the boundary between the pixels that were “H” (correction target pixel) in Step 3 described above (that is, the boundary between the pixel changed in Process A and the pixel changed in Process B in Step 4). Since it is conspicuous, a process of blurring this conspicuous boundary is executed in step 5. In the blurring process, the following process C is executed a predetermined number of times (for example, 5 times).
Process C: Average of all “H” (correction target pixel) or “M” (corrected pixel) pixel values around the surrounding pixels (the pixel of interest and a total of nine pixels in the front, rear, left, and right directions) Change by value.

  Thus, the hole-filling interpolation process in step 4 and the blurring process in step 5 are completed, and a corrected image is output. Through these processes, the false color such as purple fringe based on chromatic aberration and other pixel values of indefinite pixels are corrected, and high-quality image data can be generated and output.

The hardware configuration of the image processing apparatus according to the present invention that executes the hole-filling interpolation process in step 4 and the blurring process in step 5 will be described below. First, the points of the present invention will be described. In the image processing apparatus of the present invention, each pixel is processed in the raster scan order. As a result, reading / writing from the memory can be performed in order. Furthermore, accompanying information corresponding to each pixel, ie,
"I" (whiteout pixel)
“H” (correction target pixel)
"V" (other pixels)
"M" (corrected pixel)
The associated information can be processed in the raster scan order at the same timing as the corresponding pixels. Input / output control of these accompanying information to the memory can be performed without securing a separate memory for holding the accompanying information. Is also unnecessary.

  The configuration of the image processing apparatus of the present invention will be described with reference to FIG. FIG. 2 is a block diagram illustrating an image processing apparatus that executes the above-described hole-filling interpolation process in step 4 and the blurring process in step 5 by applying a circuit having a hardware configuration.

  The image processing apparatus 20 illustrated in FIG. 2 includes an input / output port 21, a memory 22, a pixel discrimination processing unit 23, a hole filling interpolation processing unit 24, a blur processing unit 25, a bus 26, and a control unit 27.

  For example, an image having chromatic aberration, that is, image data including a pixel to be corrected is input from the input / output port 21, and after a series of processes described later is performed, an image in which chromatic aberration is corrected, that is, a filling interpolation process The image data after executing the blurring process is output from the input / output port 21.

The memory 22 is a memory that stores image data. The pixel discrimination processing unit performs the above-described processing from Step 1 to Step 3, that is,
Step 1: Whiteout mask calculation Step 2: False color generation part search area setting (Dilate) processing (pixel setting of a portion inflated around whiteout)
This is a circuit that executes step 3: purple pixel detection and executes a process of selecting a purple pixel as a correction target pixel of each pixel.

  The hole-filling interpolation processing unit 24 is a circuit that performs the hole-filling interpolation process in step 4 described above. The blur processing unit 25 is a circuit that performs the blur processing in step 5.

  The bus 26 is a data transfer bus between the components of the input / output port 21, the memory 22, the pixel discrimination processing unit 23, the hole-filling interpolation processing unit 24, and the blurring processing unit 25. Operation control and data transfer control of these components are executed by the control unit 27. Note that the output from the hole-filling interpolation processing unit 24 is directly input to the blurring processing unit 25.

  Details of the configuration and processing of the hole-filling interpolation processing unit 24 and the blur processing unit 25 will be described later with reference to FIGS. First, the flow of overall processing using the image processing apparatus 20 shown in FIG. 2 will be described.

  First, an image to be corrected, for example, “image data with chromatic aberration” is input from the input / output port 21 and stored in the memory 22 via the bus 26. The image data stored in the memory 22 is then input from the memory 22 to the pixel discrimination processing unit 23 via the bus 26.

In the pixel discrimination processing unit 23, the above-described processing from Step 1 to Step 3, that is,
Step 1: Whiteout mask calculation Step 2: False color generation part search area setting (Dilate) processing (pixel setting of a portion inflated around whiteout)
Step 3: Purple pixel detection is executed.

  As a result of this processing, the accompanying information of the accompanying information of each pixel (“H” (correction target pixel) “V” (other pixel) “I” (whiteout pixel)) is stored in the memory 22 for each pixel. Stored with value data.

  For example, if the pixel value of each pixel constituting the image data is 8 bits, the memory of the memory 22 is set as 10 bits per word, and the pixel value is set to the same address as the pixel value (8 bits) and the accompanying information (2 bits). And associated information are stored in association with each other.

  A data storage configuration in the memory 22 will be described in detail with reference to FIG. FIG. 3 shows data corresponding to a certain pixel stored at address XX of the memory 22. Since the memory 22 is 10 bits wide, the pixel value (8-bit data from 0 to 255) of the pixel is stored in the lower 8 bits (R7 to R0 in FIG. 3). . Further, the incidental information corresponding to this pixel determined by the circuit of the pixel discrimination processing unit 23 (two bits because all four states (H, V, I, M) are taken) is the same address (address XX). Are stored in the upper 2 bits (R9, R8 in FIG. 3).

Thus, the memory 22 stores the pixel values of the constituent pixels of the image data and the accompanying information, that is,
“H” (correction target pixel)
"V" (other pixels)
"I" (whiteout pixel)
Is stored in association with each other. Since it is before processing,
"M" (corrected pixel)
There is no pixel data in which the accompanying information is set.

  The stored data is output from the memory 22 storing the pixel values and the associated information in association with each other to the hole-filling interpolation processing unit 24 via the bus 26, and the hole-filling interpolation processing is executed. In 25, the blurring process is executed, and the processing result data is temporarily stored in the memory 22 via the bus 26 and then output via the input / output port 21 via the bus 26.

First, data corresponding to each pixel, that is, a pixel value and accompanying information are read from the memory 22 in the raster scan order. The “pixel value” and “accompanying information” are input to the hole-filling interpolation processing unit 24 via the bus 26 in the raster scan order. Details of the processing in the hole-filling interpolation processing unit 24 will be described later. In the hole-filling interpolation processing unit 24, the process B is executed after the above-described predetermined number (for example, 10 times) of the process A. That is,
Process A: For all “H” (correction target pixel) pixels (referred to as a target pixel), “M” (corrected pixel) out of the surrounding pixels (a total of 8 pixels in the front, back, left, and right directions). Alternatively, if there is a “V” (other pixel) pixel, the value of the pixel of interest is changed by the average value of the “M” (corrected pixel) or “V” (other pixel) pixel. The accompanying information of the target pixel is changed from “H” (correction target pixel) to “M” (corrected pixel).
Process B: The values of all “H” (correction target pixels) are set to zero.

  After these processes in the hole-filling interpolation processing unit 24, “pixel value” and “accompanying information” are output to the blurring processing unit 25 in the raster scan order.

Then, the “pixel value” and “accompanying information” output from the hole-filling interpolation processing unit 24 are input to the blurring processing unit 25 in the order of raster scanning, and the blurring processing unit 25 executes blurring processing. Although details of the configuration and processing of the blur processing unit 25 will be described later, here, the above-described processing C is executed a predetermined number of times (for example, five times). That is,
Process C: Average of all “H” (correction target pixel) or “M” (corrected pixel) pixel values around the surrounding pixels (the pixel of interest and a total of nine pixels in the front, rear, left, and right directions) Change by value.
This blurring process is executed, and “pixel value” and “accompanying information” are output in the raster scan order. Actually, the “accompanying information” is not used after this blurring process and may be discarded. However, in order to maintain consistency, here, the “accompanying information” is described as an example of outputting. To do.

  The “pixel value” and “accompanying information” output from the blur processing unit 25 are written in the memory 22 in the raster scan order via the bus 26. Finally, the images stored in the memory 22, that is, the process A and the process B for a predetermined number of times (for example, 10 times) in the hole-filling interpolation processing unit 14, and the process C for a predetermined number of times (for example, 5 times) in the blurring processing unit. The performed image data is output from the input / output port 21 via the bus 26, and the corrected image data is output.

  As described above, the order of image data read from the memory 22 and supplied to the hole-filling interpolation processing unit 24 is the raster scan order, and the order of output from the blur processing unit 25 and writing to the memory 22 is also the raster scan order.

That is, the read / write control of the memory 22 is a very simple process. For the control, for example, a memory read control and memory write control configuration shown in FIG. 4 is applied. In particular,
(A) Data read processing from the memory 22:
for (j = 0; j, height; ++ j) {
for (i = 0; i <width; ++ i) {
Read out the pixel at position (i, j) from the memory 22,
This is supplied to the hole-filling interpolation processing unit 24 via the bus 26.
}
}
(B) Data writing process to the memory 22:
for (j = 0; j, height; ++ j) {
for (i = 0; i <width; ++ i) {
Data output from the blur processing unit 25 is sent via the bus 26.
Then, it is stored in the memory 22 as a pixel at the position (i, j).
}
}

[Width] is the horizontal width of the image (or the width of the image of the part to be processed), and [height] is its height.
The above memory control, that is, when reading data from the memory,
The pixel correspondence data (pixel value and accompanying information) is acquired in the horizontal direction sequentially from the first scan line of j = 0 in order, and when the highest scan line reaches the end, the next lower scan The process moves to the line, sequentially extracts the pixel-corresponding data in the horizontal direction and reaches the lowest scan line, and the data write process to the memory is also executed along the scan line in the same order as the above read process It is shown that. As described above, data reading from the memory and data writing to the memory are executed along the scan line, and can be executed with simple control.

  Next, the configuration and processing details of the hole-filling interpolation processing unit 24 will be described with reference to FIGS. 5 to 8, and then the configuration and processing details of the blurring processing unit 25 will be described with reference to FIGS. 9 and 10. Will be described.

  First, the configuration and processing of the hole-filling interpolation processing unit 24 will be described with reference to FIGS. FIG. 5 is a diagram for explaining a specific configuration of the hole-filling interpolation processing unit 24 shown in FIG. As shown in FIG. 5, the hole-filling interpolation processing unit 24 includes filter processing circuits 50-1 and 50-2 to 50-10 and an exception processing unit 51.

The filter processing circuits 50-1 and 50-2 to 50-10 have the same configuration and perform the same processing, and repeatedly execute the above-described processing A 10 times. That is,
Process A: For all “H” (correction target pixel) pixels (target pixels), “M” (corrected pixels) or “V” of the surrounding pixels (a total of 8 pixels in the front, back, left, and right directions). If there is a pixel “” (other pixels), the value of the pixel of interest is changed by the average value of the pixels “M” (corrected pixels) or “V” (other pixels). The accompanying information of the target pixel is changed from “H” (correction target pixel) to “M” (corrected pixel).
The filters 50-1 and 50-2 to 50-10 repeatedly execute this process A ten times. In this example, an example in which the number of repetitions is set to 10 will be described, but the number of repetitions is not limited to 10.

The exception processing unit 51 performs the above-described process B, that is,
Process B: The values of all “H” (correction target pixels) are set to zero.
Execute the process. That is, the process of setting the value of the pixel “H” (correction target pixel) remaining in process A 10 times to 0 is executed.

  With reference to FIG. 5 and subsequent figures, the processing of the hole-filling interpolation processing unit 24 will be described. “Pixel value” and “accompanying information” input from the memory 22 to the hole-filling interpolation processing unit 24 via the bus 26 in the raster scan order are first input to the filter processing circuit 50-1. The output of the filter processing circuit 50-1 is input to the filter processing circuit 50-2. The output of the filter processing circuit 50-2 is input to the filter processing circuit 50-3. Thereafter, the same applies, and the output of the filter processing circuit 50-9 is input to the filter processing circuit 50-10. The output of the filter processing circuit 50-10 is input to the exception processing unit 51. The output 51 (“pixel” and “accompanying information”) is input to the blurring processing unit 25 as the output of the hole-filling interpolation processing unit 24.

  A specific circuit configuration of the filter processing circuit 50-h (h = 1 to 10) that executes the process A will be described with reference to FIG. The filter processing circuit 50-h (h = 1 to 10) includes a data selection circuit 600 and a filter calculation circuit 623 as a correction processing execution circuit.

  “Pixel value” data input from the memory 22 via the bus 26 in the raster scan order is input to a unit delay circuit (FF) 601 serving as a data selection unit included in the data selection circuit 600. The output of the unit delay circuit (FF) 601 is a unit delay circuit 602, a unit delay circuit 603, a delay circuit (the delay amount is width-3) 604, a unit delay circuit 605, a unit delay circuit 606, and a unit delay circuit 607. The delay circuit (the delay amount is width-3) 608, the unit delay circuit 609, the unit delay circuit 610, and the unit delay circuit 611 are sequentially sent.

  The amount of delay data in the delay circuit 604 and the delay circuit 608 is a scan line width (width) -3 pixels. In this example, 3 × 3 9 pixels are selected in the data selection circuit, and pixel values corresponding to these 9 pixels and accompanying information are input to the filter calculation circuit 623 serving as the correction processing execution circuit. The data selection circuit 600 can be configured to select arbitrary n × m pixel data (pixel value and accompanying information), and the delay circuit 604 and the delay circuit 608 are configured according to the configuration. The amount of delayed data varies.

  Explaining in general terms, the data selection circuit 600 is configured to have m stages of line-corresponding data selection units for selecting pixel values of n pixels adjacent in the horizontal direction of image data and corresponding incidental information (where n, m is an integer of 1 or more), and a delay circuit that executes a data delay corresponding to (image width (width) data length−n pixel corresponding data length) is configured between the line-corresponding data selection units at different stages. The With this configuration, pixel values included in n × m adjacent pixel regions and corresponding associated information are input to a filter calculation circuit 623 serving as a correction processing execution circuit.

  Similarly, the “accompanying information” data input in the raster scan order is input to a unit delay circuit 612 as a data selection unit constituting the data selection circuit 600. The output of the unit delay circuit (FF) 612 includes a unit delay circuit 613, a unit delay circuit 614, a delay circuit (delay amount is width-3) 615, a unit delay circuit 616, a unit delay circuit 617, and a unit delay circuit 618. , The delay circuit (the delay amount is width-3) 619, the unit delay circuit 620, the unit delay circuit 621, and the unit delay circuit 622 are sequentially transmitted.

  Since the bit length of the “pixel value” data is 8 bits, the unit delay circuits (FF) 601 to 611 are 8 bits wide. Further, since the bit length of the “accompanying information” is 2 bits, the unit delay circuits (FF) 612 to 622 are 2 bits wide. These 8-bit pixel value data and 2-bit associated information are selected for 3 × 3 pixels and input to the filter calculation circuit 623 serving as a correction processing execution circuit.

  As described above, the unit delay circuits (FF) 601, 602, 603, 605, 606, 607, 609, 610, 611 and 612, 613, 614, 616, 617, 618, 620, which are constituent elements of the data selection circuit 600, are provided. , 621 and 622 are input to a filter calculation circuit 623 serving as a correction processing execution circuit, and the processing shown in FIG. 7 is performed. As a result, “pixel (8 bits)” and “accompanying information (2 bits)” are obtained. Is output from the circuit shown in FIG. 6 and input to the subsequent filter processing circuit 50-k or the exception processing unit 51.

  Processing performed by the filter calculation circuit 623 serving as a correction processing execution circuit will be described with reference to FIG. In FIG. 7, the output value of the unit delay circuit (FF) 601 shown in FIG. 6 is D00, the output value of the unit delay circuit (FF) 602 is D10, the output value of the unit delay circuit (FF) 603 is D20, and the unit delay. The output value of the circuit (FF) 605 is D01, the output value of the unit delay circuit (FF) 606 is D11, the output value of the unit delay circuit (FF) 607 is D21, the output value of the unit delay circuit (FF) 609 is D02, The output value of the unit delay circuit (FF) 610 is D12, the output value of the unit delay circuit (FF) 611 is D22, the output value of the unit delay circuit (FF) 612 is F00, and the output value of the unit delay circuit (FF) 613 is The output value is F10, the output value of the unit delay circuit (FF) 614 is F20, the output value of 616 is F01, the output value of the unit delay circuit (FF) 617 is F11, and the output of the unit delay circuit (FF) 618 The F21, the output value of the unit delay circuit (FF) 620 F02, the output value of the unit delay circuit (FF) 621 F12, the output value of the unit delay circuit (FF) 622 is set to F22.

  Dxx is pixel data. If D11 is a pixel of interest, pixel value data of a pixel in a 3 × 3 portion around the pixel is input to the filter calculation circuit 623 as Dxx. Fxx is accompanying information and is any one of “H” (correction target pixel), “M” (corrected pixel), “V” (other pixels), and “I” (overexposed pixels), and 3 × The incidental information of part 3 is input to the filter calculation circuit 623 as Fxx.

  With reference to FIG. 8, data input to the filter calculation circuit 623 will be described. As shown in FIG. 8, the data input to the filter calculation circuit 623 is a pixel value (Dxx) corresponding to 3 × 3 pixels and accompanying information (Fxx) corresponding to the pixels. These are selected by the data selection circuit 600. Based on the pixel value (Dxx) corresponding to these 3 × 3 pixels and the accompanying information (Fxx) corresponding to the pixel, the filter calculation circuit 623 calculates the pixel value ( D11) and accompanying information (F11) are updated.

  The process of FIG. 7 will be described. The calculation process shown in FIG. 7 is as follows.

if (F11 == H) {
sum = 0;
num = 0;
if (F00 == VorM) {sum + = D00; ++ num;}
if (F01 == VorM) {sum + = D01; ++ num;}
if (F02 == VorM) {sum + = D02; ++ num;}
if (F10 == VorM) {sum + = D11; ++ num;}
if (F12 == VorM) {sum + = D12; ++ num;}
if (F20 == VorM) {sum + = D20; ++ num;}
if (F20 == VorM) {sum + = D21; ++ num;}
if (F22 == VorM) {sum + = D22; ++ num;}
if (num! = 0) {
Do = sum / num; Fo = M;
} else {
Do = D11; Fo = F11;
}
} else {
Do = D11; Fo = F11;
}

  The arithmetic processing will be described. First, it is checked whether the accompanying information F11 corresponding to the pixel of interest is “H” (correction target pixel). If it is “H” (correction target pixel), the output pixel value (Do) is obtained by the following processing. And output accompanying information (Fo) are determined. That is, only when the variable: sum and num are set to 0 and the value of the accompanying information: Fpq is either “M” (corrected pixel) or “V” (other pixels), the corresponding pixel value: Dpq is added to sum and num is incremented by 1 (p = 0-2, q = 0-2, p = 1 and q = 1 are excluded).

  Then, Do = sum / num is output as the value of “pixel” as the output of the filter calculation circuit 623, and Fo = “M” (corrected pixel) as the value of “accompanying information” as the output of the filter calculation circuit 623. Is output.

  In this process, when the center pixel of 3 × 3 pixels is “H” (correction target pixel), the accompanying information of “M” (corrected pixel) or “V” (other pixels) is obtained from the surrounding eight pixels. Only the set pixels are selected, the average (sum / num) of the pixel values of these pixels is set as the correction pixel value of the center pixel of 3 × 3 pixels, and the accompanying information is “M” (corrected pixel ).

  However, num is 0, that is, the center pixel of 3 × 3 pixels is “H” (correction target pixel), but “M” (corrected pixel) or “V” (other pixels) is included in the surrounding eight pixels. When there is no pixel for which the accompanying information is set, Do = D11 is output as the value of “pixel” as the output of the filter calculation circuit 623, and Fo = as the value of “accompanying information” as the output of the filter calculation circuit 623. F11 (that is, “H” (correction target pixel)) is output. That is, without correcting the pixel value, the input pixel value [D11] is left as it is, and the accompanying information is also output as F11 = “H” (correction target pixel).

  Further, when F11 is not “H” (correction target pixel), the value of “pixel” as the output of the filter calculation circuit 623 is output as the input pixel value, that is, Do = D11 is output, and the filter calculation circuit Fo = F11 is output without changing the value of “accompanying information” which is the output of 623.

  The processing of the filter calculation circuit 623 shown in FIG. 7 is realized by a hardware circuit composed of arithmetic circuits such as an addition processing circuit, an AND circuit, and a plurality of unit delay circuits (FF) shown in FIG. The pixel value and accompanying information are input, and the arithmetic processing shown in FIG. 7 is executed.

This processing is processing A for the target pixel, that is,
Process A: For all “H” (correction target pixel) pixels (target pixels), “M” (corrected pixels) or “V” of the surrounding pixels (a total of 8 pixels in the front, back, left, and right directions). If there is a pixel “” (other pixels), the value of the pixel of interest is changed by the average value of the pixels “M” (corrected pixels) or “V” (other pixels). The accompanying information of the target pixel is changed from “H” (correction target pixel) to “M” (corrected pixel).
It corresponds to performing the process.
This process A is repeated 10 times by 10 circuits of the filter processing circuits 50-1 to 50 shown in FIG. As a result, for the pixels for which “H” (correction target pixel) is set as the accompanying information, a new pixel value is sequentially set by hole-filling interpolation, and the accompanying information is also changed to “M” (corrected pixel). It will be.

Next, processing in the exception processing unit 51 shown in FIG. 5 will be described with reference to FIG. The processing in the exception processing unit 51 is the following processing.
if (Fin == H) {
Dout = const;
Fout = Fin;
} else {
Dout = Din;
Fout = Fin;
}

In the exception processing unit 51, the above-described process B, that is,
Process B: The values of all “H” (correction target pixels) are set to zero.
Execute the process. That is, the process of setting the value of the pixel “H” (correction target pixel) remaining in process A 10 times to 0 is executed.

  When Fin is “H” (correction target pixel) from the input pixel value (Din) and the input accompanying information (Fin) corresponding to the pixel, the exception processing unit 51 outputs “pixel value”. Do = “constant value (for example, 0)” is output. Further, the value of “accompanying information” corresponding to the pixel is output as Fo = Fin, that is, “H” (correction target pixel) without changing the input accompanying information as it is.

When the input incidental information (Fin) is not “H” (correction target pixel), the exception processing unit 51 outputs Do “Din” as it is without changing the input pixel value as the output “pixel value”. And “Fo = Fin” is output without changing the input incidental information as it is. Obviously, this is the process B for the pixel of interest (Din), ie,
Process B: The values of all “H” (correction target pixels) are set to zero.
Execute the process. That is, this is equivalent to executing the process of setting the value of the remaining “H” (correction target pixel) pixel to 0 after 10 processes A.

  The processing of the exception processing unit 51 shown in FIG. 9 is realized by a hardware circuit constituted by arithmetic circuits such as an addition processing circuit, an AND circuit, and the final stage filter processing circuit 50-10 shown in FIG. 9 is input and the process shown in FIG. 9 is executed.

  As described above, the hole-filling interpolation processing unit 24 shown in FIG. 2 executes the hole-filling interpolation process by the predetermined number (here, 10 times) of the process A and the process B once. These processes are executed according to the raster scan order input from the memory 22, and the processing result from the hole filling interpolation processing unit 24 is also input to the blurring processing unit 25 in the raster scan order.

Next, the configuration and processing of the blur processing unit 25 will be described with reference to FIGS. 10 and 11. As described above, the blurring processing unit 25 performs the blurring process on the pixel values of the image data having the pixel values interpolated by the hole-filling interpolation process. That is, the following process C is executed a predetermined number of times (for example, 5 times).
Process C: Average of all “H” (correction target pixel) or “M” (corrected pixel) pixel values around the surrounding pixels (the pixel of interest and a total of nine pixels in the front, rear, left, and right directions) Change by value.

  FIG. 10 is a block diagram showing a configuration of the blur processing unit 25 shown in FIG. In FIG. 10, filter processing circuits 90-1 and 90-2 to 90-5 are circuits that perform the same processing. The filter processing circuits 90-3 and 90-4 are not shown.

  The “pixel value” and the “accompanying information” are input from the hole-filling interpolation processing unit 24 to the blurring processing unit 25 in the raster scan order, and are first input to the filter processing circuit 90-1. The output of the filter processing circuit 90-1 is input to the filter processing circuit 90-2. The output of the filter processing circuit 90-2 is input to the filter processing circuit 90-3. Thereafter, the same applies, and the output of the filter processing circuit 90-4 is input to the filter processing circuit 90-5. The output (“pixel value” and “accompanying information”) of the filter processing circuit 90-5 is stored in the memory 22 through the bus 26 as the output of the blurring processing unit 25.

  The configuration of the filter processing circuit 90-h (h = 1 to 5) is shown in FIG. As shown in FIG. 11, the filter processing circuit 90-h (h = 1 to 5) has the same configuration as the circuit described above with reference to FIG. 6 as the constituent circuit of the hole-filling interpolation processing unit 24. That is, as described with reference to FIG. 8, the data selection circuit 900 for inputting the pixel value (Dxx) of 3 × 3 pixels and the accompanying information (Fxx) to the filter calculation circuit 923, and the correction processing execution circuit The filter calculation circuit 923 of FIG.

  The data selection circuit 900 includes unit delay circuits (FF) 901 to 903, 905 to 907, 909 to 911, 912 to 914, 916 to 918, 920 to 922, and delay circuits 904, 908, 915 and 919. In the blurring processing unit, the data processing for these 3 × 3 pixel data, that is, the processing of the filter calculation circuit 923 as the correction processing execution circuit shown in FIG. 11 is the correction processing (FIG. 7) in the hole-filling interpolation processing unit 24. Are executed as different processes.

With reference to FIG. 12, the process performed by the filter calculation circuit 923 (see FIG. 11) of the blur processing unit 25 will be described. The filter calculation circuit 923 of the blur processing unit 25 executes the following processing.
if (F11 == HorM) {
Do = (D00 + D01 + D02
+ D10 + D11 + D12
+ D20 + D21 + D22) / 9;
Fo = F11;
} else {
Do = D11;
Fo = F11;
}

  First, it is checked whether the accompanying information F11 of the pixel of interest, that is, the center pixel of 3 × 3 pixels is “H” (correction target pixel) or “M” (corrected pixel), and “H” (correction target pixel). ) Or “M” (corrected pixel), the output pixel value (Do) and the output associated information (Fo) are determined by the following processing. That is, an average value of pixel values: Dpq (p = 0 to 2, q = 0 to 2) of 3 × 3 = 9 pixels to be input is calculated, and this average value is calculated for the pixel of interest, that is, 3 × 3 pixels. The output pixel value (Do) of the center pixel is assumed. Further, Fo = F11 is output as the value of “accompanying information” without changing the input accompanying information.

If the accompanying information of the pixel of interest: F11 is not “H” (correction target pixel) and is not “M” (corrected pixel), the filter calculation circuit 923 of the blurring processing unit 25 outputs the output “ Do = D11 as the “pixel value”, that is, the output pixel value is output without changing the input pixel value, and Fo = F11 is output without changing the value of the “accompanying information”. This is processing C for the target pixel, that is,
Process C: Average of all “H” (correction target pixel) or “M” (corrected pixel) pixel values around the surrounding pixels (the pixel of interest and a total of nine pixels in the front, rear, left, and right directions) Processing to change by value,
It has been done.

  The processing of the filter calculation circuit 923 of the blur processing unit 25 shown in FIG. 12 is realized by a hardware circuit including arithmetic circuits such as an addition processing circuit, an AND circuit, and the hole-filling interpolation processing unit 24 shown in FIG. The pixel value and accompanying information from the exception processing unit 51 (see FIG. 5) are input, and the process shown in FIG. 12 is executed.

  The process C is performed five times by the five circuits of the filter processing circuits 90-1 to 90-5 shown in FIG.

As described above, the hole-filling interpolation processing unit 24 illustrated in FIG. 2 performs the processing described with reference to FIGS.
Multiple times of processing A: For all “H” (correction target pixel) pixels (target pixel), “M” (corrected pixel) of the surrounding pixels (a total of 8 pixels in the front, back, left, and right directions). Alternatively, if there is a “V” (other pixel) pixel, the value of the pixel of interest is changed by the average value of the “M” (corrected pixel) or “V” (other pixel) pixel. The accompanying information of the target pixel is changed from “H” (correction target pixel) to “M” (corrected pixel).
Process B: The values of all “H” (correction target pixels) are set to zero.
Is executed,
In the blurring processing unit 25 shown in FIG. 2, the processing described with reference to FIGS.
Multiple times of processing C: The values of all “H” (correction target pixel) or “M” (corrected pixel) pixels are set to the surrounding pixels (the pixel of interest and a total of nine pixels including the front, back, left, and right. ) The average value of the process to change,
Is executed.

  Thus, in the configuration of the present invention, the hole-filling interpolation and the blurring processing are executed by applying a circuit configured by hardware. In addition, the processing procedure can be executed by sequentially processing pixel values input from the memory in the raster scan order and the accompanying information, and it is not necessary to perform complicated memory input / output control. Since only pixel values are transferred between the circuits according to the progress of processing, no memory or control dedicated to the accompanying information is required, and hole filling interpolation and blurring processing can be executed by simple control.

  The present invention has been described in detail above with reference to specific embodiments. However, it is obvious that those skilled in the art can make modifications and substitutions of the embodiments without departing from the gist of the present invention. In other words, the present invention has been disclosed in the form of exemplification, and should not be interpreted in a limited manner. In order to determine the gist of the present invention, the claims should be taken into consideration.

  As described above, according to the configuration of the present invention, pixel value correction processing in image data, for example, interpolation processing for a pixel with an incorrect pixel value set, a pixel with an indefinite pixel value, etc. Thus, an image processing apparatus is realized that applies a hardware circuit to the pixel value correction and enables processing with a small circuit configuration.

  In the configuration of the present invention, the pixel value of each pixel constituting the image data and the accompanying information corresponding to the pixel are input, and a plurality of pieces of data including the pixel value corresponding to the different pixel and the corresponding accompanying information are executed. Based on a data selection circuit to be selected as input data to the circuit, a plurality of data consisting of pixel values and accompanying information input from the data selection circuit, a correction pixel value of the pixel to be corrected is calculated, and Since the correction processing execution circuit that executes the update processing of the corresponding incident information is performed, the pixel data necessary for correction is sequentially selected by the data selection circuit, supplied to the correction processing execution circuit, and the correction is executed. By sequentially outputting data in raster scan order, simple hardware processing without complicated memory control, hole filling interpolation processing, Pixel value correction processing such processes can be executed.

  According to the configuration of the present invention, hole filling interpolation and blurring processing are executed by applying a circuit configured by hardware. In addition, the processing procedure can be executed by sequentially processing pixel values input from the memory in the raster scan order and the accompanying information, and it is not necessary to perform complicated memory input / output control. Since only pixel values are transferred between the circuits according to the progress of processing, no memory or control dedicated to the accompanying information is required, and hole filling interpolation and blurring processing can be executed by simple control.

It is a figure explaining a hole-filling interpolation process. It is a figure which shows the structure of the image processing apparatus of this invention which performs the image process which applied the hole-filling interpolation process. It is a figure explaining the data storage structure of the memory in the image processing apparatus of this invention. It is a figure explaining the data input / output control structure of the memory in the image processing apparatus of this invention. It is a block diagram which shows the structure of the hole-filling interpolation process part in the image processing apparatus of this invention. It is a figure which shows the circuit structure of the filter process part of the hole-filling interpolation process part in the image processing apparatus of this invention. It is a figure explaining the process of the filter calculation circuit of the hole-filling interpolation process part in the image processing apparatus of this invention. It is a figure explaining the structure of the input data with respect to the filter calculation circuit of the hole-filling interpolation process part in the image processing apparatus of this invention. It is a figure explaining the process of the exception process part of the hole-filling interpolation process part in the image processing apparatus of this invention. It is a block diagram which shows the structure of the blurring process part in the image processing apparatus of this invention. It is a figure which shows the circuit structure of the filter process part of the blurring process part in the image processing apparatus of this invention. It is a figure explaining the process of the filter calculation circuit of the blurring process part in the image processing apparatus of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 White skip pixel 12 False color (purple fringe) pixel 13 Other pixels 14 Interpolated pixel 20 Image processing device 21 Input / output port 22 Memory 23 Pixel discrimination processing unit 24 Filling interpolation processing unit 25 Blur processing unit 26 Bus 27 Control unit 50 -1 to 10 Filter processing circuit 51 Exception processing unit 600 Data selection circuit 601 to 603 Unit delay circuit (FF)
604 delay circuit 605-607 unit delay circuit (FF)
608 Delay circuit 609 to 614 Unit delay circuit (FF)
615 Delay circuit 616 to 618 Unit delay circuit (FF)
619 Delay circuit 620-622 Unit delay circuit (FF)
623 Filter calculation circuit 90-1-5 Filter processing circuit 900 Data selection circuit 901-903 Unit delay circuit (FF)
904 delay circuit 905 to 907 unit delay circuit (FF)
908 Delay circuit 909 to 914 Unit delay circuit (FF)
915 delay circuit 916 to 918 unit delay circuit (FF)
919 delay circuit 920 to 922 unit delay circuit (FF)
923 filter calculation circuit

Claims (12)

An image processing device,
The pixel value of each pixel constituting the image data and the accompanying information corresponding to the pixel are input, and a plurality of data consisting of the pixel value corresponding to the different pixel and the corresponding accompanying information are input to the correction processing execution circuit. A data selection circuit to select;
A correction process for calculating a correction pixel value of a pixel to be corrected based on a plurality of data including a pixel value input from the data selection circuit and accompanying information, and executing an updating process of the accompanying information corresponding to the correction pixel An execution circuit;
An image processing apparatus comprising: The data selection circuit includes:
In the raster scan order, input data consisting of pixel values and associated information,
A configuration for executing a process of selecting a pixel value and corresponding associated information included in an n × m adjacent pixel area as input data to the correction process execution circuit, where n and m are integers of 1 or more,
The image processing apparatus according to claim 1, wherein: The data selection circuit includes:
There are m stages of line-corresponding data selection units for selecting pixel values of n pixels adjacent in the horizontal direction of the image data and corresponding incidental information, where n and m are integers of 1 or more,
A delay circuit that executes a data delay corresponding to (image width (width) data length−n pixel corresponding data length) between the line-corresponding data selection units at different stages;
The image processing apparatus according to claim 2, wherein the image processing apparatus is configured to execute a process of selecting a pixel value included in an n × m adjacent pixel area and corresponding associated information as input data to a correction process execution circuit. The image processing apparatus further includes:
A memory for storing the pixel value of each pixel constituting the image data in association with the associated information corresponding to the pixel;
The data selection circuit includes:
The image processing apparatus according to claim 1, wherein the image processing apparatus is configured to input data including pixel values and corresponding incidental information in the raster scan order from the memory. The correction processing execution circuit includes:
It is a configuration that performs pixel value correction processing by hole filling interpolation processing,
Based on a plurality of data consisting of pixel values and accompanying information input from the data selection circuit, the correction pixel value of the pixel to be corrected is calculated by filling interpolation processing, and the accompanying information updating process corresponding to the correction pixel is updated. The image processing apparatus according to claim 1, wherein the image processing apparatus is configured to execute. The accompanying information is
Whether it is a pixel to be corrected,
Whether the pixel has a pixel value applicable to the filling interpolation,
Is information that can be determined,
The correction processing execution circuit includes:
When the accompanying information indicates a correction target pixel,
The correction pixel value of the correction target pixel is calculated by selecting only the pixel value of the pixel indicating that the accompanying information is a pixel having a pixel value applicable to the filling interpolation. Item 6. The image processing apparatus according to Item 5. The correction processing execution circuit includes:
It is a configuration that performs pixel value correction processing by blur processing,
2. The configuration according to claim 1, wherein a correction pixel value of a correction target pixel is calculated by a blurring process based on a plurality of data including a pixel value input from the input data selection circuit and accompanying information. Image processing device. The accompanying information is
It is information that can distinguish the correction target pixel or corrected pixel from other pixels,
The correction processing execution circuit includes:
A configuration in which, when the accompanying information indicates a correction target pixel or a corrected pixel, the pixel is selected, and a new correction pixel value of the selected pixel is calculated based on the pixel values of surrounding pixels of the selected pixel The image processing apparatus according to claim 7, wherein: The correction processing execution circuit includes:
When the accompanying information indicates a correction target pixel or a corrected pixel, the pixel is selected, an average value of pixel values of surrounding pixels of the selected pixel is calculated, and the calculated value is newly corrected for the selected pixel. The image processing apparatus according to claim 8, wherein the image processing apparatus is configured to execute a process of setting a pixel value. The correction processing execution circuit includes:
Based on a plurality of data composed of pixel values and accompanying information input from the data selection circuit, the correction pixel value of the pixel to be corrected is calculated, and the accompanying information corresponding to the correction pixel is updated, The image processing apparatus according to claim 1, wherein the processed data is output in raster scan order. The accompanying information is
It is information that enables discrimination between overexposed pixels, correction target pixels, corrected pixels, and other pixels that do not fall under any of the above pixels,
The correction processing execution circuit includes:
The image processing apparatus according to claim 1, wherein the image processing apparatus is configured to identify the accompanying information and execute processing according to the identification result. In the image processing apparatus,
The image processing apparatus according to claim 1, wherein the data selection circuit and the correction process execution circuit have a configuration capable of executing a plurality of repetitive processes.

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